CHA1077a RoHS COMPLIANT W-band Low Noise Amplifier GaAs Monolithic Microwave IC Description The CHA1077a is a W-band monolithic 3stages low noise amplifier. All the active devices are internally self-biased. This chip is compatible with automatic equipment for assembly. The circuit is manufactured on pHEMT process: 0.15µm gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is available in chip form. IN OUT +V -V W-band amplifier block-diagram Main Features W-band low noise amplifier High gain Wide operating frequency range High temperature range On-chip self biasing Additional external resistor allows to choose getting more gain instead of a minimum noise factor Automatic assembly oriented Low DC power consumption BCB layer protection Chip size: 2.6 x 1.32 x 0.1mm Small signal gain Main Characteristics Tamb = +25°C Symbol Parameter Min Typ Unit 77 GHz F_op Operating frequency G_lin Small signal gain 15 dB Noise figure 4.5 dB 9 dBm NF P_1dB 76 Max Output power at 1dB gain compression ESD Protections: Electrostatic discharge sensitive device observe handling precautions ! Ref. DSCHA1077a8266 - 22 Oct 2008 1/6 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 W-band LNA CHA1077a Electrical Characteristics Full operating temperature range, used according to section “Typical assembly and bias configuration”. Symbol F_op G_lin G_fl NF P_out_1dB Is VSWR_in VSWR_out +V +I -V -I Top Parameter Operating frequency Small signal gain Small signal gain flatness Noise figure Output power at 1dB gain compression Reverse isolation VSWR at input port (50Ω) VSWR at output port (50Ω) Positive supply voltage (1) Positive supply current Negative supply voltage (1) Negative supply current Operating temperature range Min 76 11 6 20 4.4 -4.6 -10 -40 Typ 15 0.5 4.5 9 30 2:1 2:1 4.5 40 -4.5 -6 Max 77 19 1 6.5 Unit GHz dB dB dB dBm dB 2.5:1 2.5:1 4.6 70 -4.4 0 100 V mA V mA °C (1) Negative supply voltage must be applied at least 1us before positive supply voltage. Absolute Maximum Ratings (1) Symbol P_in +V -V +I -I Tstg (1) (2) Parameter Maximum input power (2) Positive supply voltage Negative supply voltage Positive supply current Negative supply current Storage temperature range Values 3 5 -5 80 -13 -55 to +155 Unit dBm V V mA mA °C Operation of this device above anyone of these parameters may cause permanent damage. CW mode Ref. DSCHA1077a8266 - 22 Oct 2008 2/6 Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice W-band LNA CHA1077a Chip Mechanical Data and Pin References 55 2475 10991 9 6 8 5 405 405 7 0 1 2 3 4 70 645 945 1245 1845 Origin 0,0 Layout 2530X1250 Unit = µm External chip size (layout size + dicing streets) = 2600X1320 +/-35 Chip thickness = 100 +/- 10 HF Pads (5,8) = 105 X 86 (BCB opening) DC/IF Pads = 86 x 83 (BCB opening) Pin number Pin name 4, 6, 7, 9 3 5 OUT 8 IN 0 +V 1 -V1 2 -V23 Ref. DSCHA1077a8266 - 22 Oct 2008 Description Ground: should not be bonded. If required, please ask for more information. Ground (optional) RF output port RF input port Positive supply voltage Negative supply voltage for the first stage Negative supply voltage for the second and third stage 3/6 Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice W-band LNA CHA1077a Typical Assembly and Bias Configuration to get minimum noise figure 10991 L_in 9 6 8 5 L_out µ- strip line µ- strip line 7 0 2 4 3 >= 120pF +V -V DC lines This drawing shows an example of assembly and bias configuration. All the transistors are internally self-biased. An external capacitor is recommended for the positive and negative supply voltages. For the RF pads the equivalent wire bonding inductance (diameter=25µm) have to be according to the following recommendation. Port Equivalent inductance (nH) Wire length (mm) (1) IN OUT L_in = 0.25 L_out = 0.25 0.34 0.34 (1) This value is the total length including the necessary loop from pad to pad. For a micro-strip configuration a hole in the substrate is necessary for chip assembly. Ref. DSCHA1077a8266 - 22 Oct 2008 4/6 Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice W-band LNA CHA1077a Typical Assembly and Bias Configuration to increase the gain 10991 L_in 9 6 8 5 µ- strip line L_out µ- strip line 7 0 1 2 4 >= 120pF +V DC lines R -V Let’s tune the value of the external resistor R to control the biasing point of the first stage and then getting a higher gain for the LNA (trade-off ability between the gain and the noise factor). Typical value of the external resistor R R (kΩ Ω) 0 2 Ref. DSCHA1077a8266 - 22 Oct 2008 Description Low-noise configuration Maximum gain configuration 5/6 Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice W-band LNA CHA1077a As the connections at 77GHz (between MMIC and MMIC or between MMIC and external substrate) are critical, the transition matching network is split into two parts: one on MMIC and one on the external substrate. This choice allows doing also a direct connection between MMICs. For a connection to an external substrate a network is proposed on soft substrate for IN and OUT ports. The following drawings give the dimensions for a RO3003 substrate (thickness=0.127mm, εr=3). 500 um Bonding area 865 um 300 um 235 um Wire length : 340 µm 225 um Proposed matching network for a 50Ω transition between IN port and a µ-strip line on RO3003 substrate. 500 um 370 um Bonding area 225 um 100 um 300 um 235 um Wire length : 340 µm Proposed matching network for a 50Ω transition between OUT port and a µ-strip line on RO3003 substrate. Ordering Information Chip form : CHA1077a98F/00 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorized for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. DSCHA1077a8266 - 22 Oct 2008 6/6 Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice