ACE ACE93C66DP+UH Three-wire serial eeprom Datasheet

ACE93C46.56.66
Three-wire Serial EEPROM
Description
The ACE93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory
(EEPROM) organized as 64/128/256 words of 16 bits each, when the ORG pin is connected to VCC and 128/256/512
words of 8 bits each when it is tied to ground. The ACE93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
TSSOP and 8-lead JEDEC SOIC packages. The ACE93C46/56/66 is enabled through the Chip Select pin (CS), and
accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon
receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO.
The WRITE cycle is completely self-timed and no separate erase cycle is required before write. The Write cycle is only
enabled when it is in the Erase/Write Enable state. When CS is brought “high” following the initiation of a write cycle, the
DO pin outputs the Ready/Busy status.
Features





Low-voltage operation – 1.8 (VCC=1.8V to 5.5V)
Three-wire serial Interface
2MHz clock rate(5V) compatibility
Self-timed write cycle (5 ms max)
High-reliability – Endurance: 1 Million write cycles
Data retention: 100 Years
Packaging Type
DIP-8
SOP-8
TSSOP-8
Pin Configurations
Pin Name
Function
CS
Chip select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
Vcc
Power Supply
ORG
Internal Organization
DC
Don’t Connect
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ACE93C46.56.66
Three-wire Serial EEPROM
Block Diagram
ACE93C46
Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8”
organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability
of the internal 1 Meg ohm pullup, then the “x 16” organization is selected.
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ACE93C46.56.66
Three-wire Serial EEPROM
ACE93C56/66
Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8”
organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability
of the internal 1 Meg ohm pullup, then the “x 16” organization is selected.
Absolute Maximum Ratings
DC Supply Voltage
-0.3 to 6.5V
Input / Output Voltage
GND -0.3 to Vcc 0.3V
Operating Ambient Temperature
-40 to 85℃
Storage Temperature
-65 to 150℃
*Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are
stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the
operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.
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ACE93C46.56.66
Three-wire Serial EEPROM
Ordering information
ACE93C46/56/66 XX
+
X
H
Halogen-free
U : Tube
T : Tape and Reel
Pb - free
DP : DIP-8
FM : SOP-8
TM : TSSOP-8
Pin Capacitance
Applicable over recommended operating range from TA=25℃, f=1.0MHz,VCC=+1.8V (unless otherwise noted)
Test Conditions
Symbol Max Unit Conditions
Output Capacitance (DO)
COUT
5
pF
VOUT=0V
Input Capacitance (CS, SK, DI)
CIN
5
pF
VIN=0V
DC Characteristics
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
VCC3
Test Condition
Min
Typ
Max
Units
1.8
5.5
V
Supply Voltage
2.7
5.5
V
Supply Voltage
4.5
5.5
V
mA
VCC = 5.0V,
ICC1
Supply Current
Read at 1.0MHz
0.2
2.0
Write at 1.0MHz
0.9
3.0
ISB1
Standby Current
VCC = 1.8V, CS=0V
1.0
µA
ISB2
Standby Current
VCC = 2.7V, CS=0V
1.0
µA
ISB3
Standby Current
VCC = 5.0V, CS=0V
1.0
µA
ILI(1)
Input Leakage
VIN = 0 to VCC
0.1
1.0
µA
ILI(2)
Input Leakage
VIN = 0 to VCC
2.0
3.0
µA
IOL
Output Leakage
VIN = 0 to VCC
0.1
1.0
µA
VIL1(3)
Input Low Voltage
2.7V≦Vcc≦5.5V
-0.3
0.8
V
VIH1(3)
Input High Voltage
2.7V≦Vcc≦5.5V
2.0
Vcc+0.3
V
VIL2(3)
Input Low Voltage
1.8V≦Vcc≦2.7V
-0.3
Vcc+0.3
V
VIH2(3)
Input High Voltage
1.8V≦Vcc≦2.7V
Vcc*0.7
Vcc+0.3
V
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ACE93C46.56.66
Three-wire Serial EEPROM
Symbol
Parameter
Test Condition
VOL1
Output Low Voltage
2.7V≦Vcc≦5.5V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Min
Typ
IOL=2.1mA
IOH=-0.4mA
Max
Units
0.4
V
0.2
V
2.4
1.8V≦Vcc≦2.7V
IOL=0.15mA
IOH=-100uA
Vcc-0.2
Note: 1. DI.CS. SK input pin
2. ORG input pin
3. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, CL=1TTL Gate and 100pF
(unless otherwise noted).
Symbol
fsx
tskh
tskl
tcs
tcss
tdis
tcsh
tdih
Parameter
Test Condition
Min
4.5≦Vcc≦5.5v
0
2
2.7≦Vcc≦5.5V
0
1
1.8V≦Vcc≦5.5V
0
0.25
4.5≦Vcc≦5.5v
250
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
4.5≦Vcc≦5.5v
250
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
4.5≦Vcc≦5.5v
250
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
Relative to
SK
Relative to
SK
CS Hold Time
DI Hold Time
4.5≦Vcc≦5.5v
50
2.7≦Vcc≦5.5V
50
1.8V≦Vcc≦5.5V
200
4.5≦Vcc≦5.5v
100
2.7≦Vcc≦5.5V
100
1.8V≦Vcc≦5.5V
400
Relative to SK
Relative to
SK
0
4.5≦Vcc≦5.5v
100
2.7≦Vcc≦5.5V
100
1.8V≦Vcc≦5.5V
400
Typ Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
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ACE93C46.56.66
Three-wire Serial EEPROM
Symbol
Parameter
Test Condition
Output Delay to “1”
tpd1
Output Delay to “0”
tpd0
tsv
CS to Status Valid
tdf
CS=VIL
Write Cycle Time
Endurance(1)
5.0V, 25℃
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
4.5≦Vcc≦5.5v
250
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
4.5≦Vcc≦5.5v
250
2.7≦Vcc≦5.5V
250
1.8V≦Vcc≦5.5V
1000
4.5≦Vcc≦5.5v
100
2.7≦Vcc≦5.5V
100
1.8V≦Vcc≦5.5V
400
AC Test
Impedance
twp
250
AC Test
AC Test
Typ Max
4.5≦Vcc≦5.5v
AC Test
CS to DO in High
Min
1.5
Units
ns
ns
ns
ns
5
ms
Write
1M
Cycle
Note: 1. This parameter is characterized and is not 100% tested.
Functional Description
The ACE93C46/56/66 is accessed via a simple and versatile three-wire serial communication interface. Device
operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of
CS and consists of a start bit (logic“1”) followed by the appropriate op code and the desired memory address location.
Instruction Set for the ACE93C46
Instruction SB
Address
OP
Code
*8
*16
Data
*8
*16
Comments
Read data stored in memory, at
specified address
Write enable must precede all
programming modes
READ
1
10
A6-A0
A5-A0
EWEN
1
00
11XXXXX
11XXXX
REASE
1
11
A6-A0
A5-A0
WRITE
1
01
A6-A0
A5-A0
ERAL
1
00
10XXXXX 10XXXX
WRAL
1
00
01XXXXX 01XXXX D7-D0 D15-D0
EWDS
1
00
00XXXXX 00XXXX
Erase memory location An-A0
D7-D0 D15-D0
Writes memory location An-A0
Erases all memory locations. Valid
only at VCC=4.5V to 5.5V
Writes all memory locations. Valid
only at VCC=4.5V to 5.5V
Disables all programming
instructions
Notes: The X’s in the address field represent don’t care values and must be clocked.
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ACE93C46.56.66
Three-wire Serial EEPROM
Instruction Set for the ACE93C56/66
Instruction SB
Address
Data
OP
Code
*8
*16
*8
*16
READ
1
10
A8-A0
A7-A0
EWEN
1
00
11XXXXXX
11XXXXXX
REASE
1
11
A8-A0
A7-A0
WRITE
1
01
A8-A0
A7-A0
ERAL
1
00
10XXXXXXX 10XXXXXX
WRAL
1
00
01XXXXXXX 01XXXXXX D7-D0 D15-D0
EWDS
1
00
00XXXXXXX 00XXXXXX
D7-D0 D15-D0
Comments
Read data stored in memory,
at specified address
Write enable must precede all
programming modes
Erase memory location
An-A0
Writes memory location
An-A0
Erases all memory locations.
Valid only at VCC=4.5V to
5.5V
Writes all memory locations.
Valid only at VCC=4.5V to
5.5V
Disables all programming
instructions
Notes: The X’s in the address field represent don’t care values and must be clocked.
READ (READ):
The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and
address are decoded, data from the selected memory location is available at the serial output pin DO. Output data
changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”)
precedes the 8- or 16-bit data output string. The ACE93C56/66 supports sequential read operations. The device will
automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high .In this case ,the dummy bit (logic “0”)will not be clocked out between memory locations, thus allowing for a
continuous steam of data to be read.
ERASE/WRITE (EWEN):
To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first
applied. An Erase/Write Enable(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is
executed or VCC power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “1” at pin
DO indicates that the selected memory location has been erased, and the part is ready for another instruction.
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ACE93C46.56.66
Three-wire Serial EEPROM
WRITE (WRITE):
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The
self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A
logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part is ready for further
instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed
programming cycle, TWP.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for
testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (TCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction.
The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250ns
(TCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming
modes and should be executed after all programming operations. The operation of the Read instruction is independent
of both the EWEN and EWDS instructions and can be executed at any time.
Timing Diagrams
Note: This is the minimum SK period.
Figure 1: Synchronous Data Timing
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ACE93C46.56.66
Three-wire Serial EEPROM
Organization Key for Timing Diagrams
I/O
ACE93C46 (1K)
*16
*8
AN
A5
A6
DN
D15
D7
ACE93C56 (2K)
*8
(1)
A8
D7
ACE93C66 (4K)
*16
*8
*16
(2)
A7
A8
A7
D15
D7
D15
Note : 1. A8 is a DON’T CARE value ,but the extra clock is required.
2. A7 is a DON’T CARE value ,but the extra clock is required.
Figure 2: Read Timing
Figure 3: EWEN Timing
Figure 4: EWDS Timing
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ACE93C46.56.66
Three-wire Serial EEPROM
Figure 5: WRITE Timing
Note: Valid only at VCC=4.5V to 5.5V
Figure 6: WRAL Timing (1)
Figure 7: ERASE Timing
Note: Valid only at VCC=4.5V to 5.5V
Figure 8: ERAL Timing (1)
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ACE93C46.56.66
Three-wire Serial EEPROM
Packaging information
DIP-8
Note: Dimensions in Millimeters.
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ACE93C46.56.66
Three-wire Serial EEPROM
Packaging information
SOP-8
Note: Dimensions in Millimeters.
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ACE93C46.56.66
Three-wire Serial EEPROM
Packaging information
TSSOP-8
Note: Dimensions in Millimeters.
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ACE93C46.56.66
Three-wire Serial EEPROM
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.5
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