CY2CC810 1:10 Clock Fanout Buffer Features • • • • • • • • • • • • Description Low-voltage operation VDD range from 2.5V to 3.3V 1:10 fanout Over voltage tolerant input hot swappable Drives either a 50-Ohm or 75-Ohm transmission line Low-input capacitance 250 ps typical output-to-output skew 19 ps typical DJ jitter Typical propagation delay < 3.5 ns High-speed operation > 500 MHz Industrial versions available Available packages include: SOIC, SSOP The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic and buffers. The Cypress CY2CC810 fanout buffer features one input and ten outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. AVCMOS-type outputs dynamically adjust for variable impedance matching and reduce noise overall. . Block Diagram Pin Configuration Q1 GND Q3 VD D Q1 VDD Q2 Q4 IN INPUT Q5 GND Q6 Q3 VDD Q4 Q7 GND 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 20 pin SOIC/SSOP Q8 GND 1 2 3 4 5 6 7 8 9 10 CY2CC810 IN Q2 Q9 Q 10 OUTPUT (AVCMOS) Pin Description Pin Number Pin Name 1 Description IN Input LVCMOS 2, 6, 10, 13, 17 GND Ground Power 4, 8, 15, 20 VDD Power Supply Power Q1... Q10 Output AVCMOS 3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Cypress Semiconductor Corporation Document #: 38-07056 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 5, 2006 CY2CC810 Absolute Maximum Conditions[1, 2] Parameter Description Min. Max. Unit VDD VDD Ground Supply voltage –0.5 4.6 V VIN Input Supply Voltage to Ground Potential –0.5 5.8 V VOUT Output Supply Voltage to Ground Potential –0.5 VDD +1 V TS Temperature, Storage –65 150 °C TA Temperature, Operating Ambient –40 85 °C Power Dissipation 0.75 W DC Electrical Characteristics @ 3.3V (see Figure 5) Parameter Description VOH Output High Voltage Conditions VDD = Min., VIN = VIH or VIL IOH = –12 mA IOL = 12 mA Min. Typ. 2.3 3.3 Max. Unit V VOL Output Low Voltage VDD = Min., VIN = VIH or VIL VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. VIN = 2.7V IIL Input Low Current VDD = Max. VIN = 0.5V II Input High Current VDD = Max., VIN = VDD(Max.) VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA –1.2 V IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA OOFF Power down Disable VDD = GND, VOUT = < 4.5V 100 µA VH Input Hysteresis VDD = Min., VIN = VIH or VIL 0.2 2 –0.7 0.5 V 5.8 V 0.8 V 1 µA –1 µA 20 µA 80 mV DC Electrical Characteristics @ 2.5V (see Figure 1) Parameter Description Conditions Min. VOH Output High Voltage VDD = Min., VIN = VIH or VIL IOH = –7 mA 1.8 IOH = 12 mA 1.6 VOL Output Low Voltage VDD = Min., VIN = VIH or VIL IOL = 12 mA VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level Typ. Max. Unit V V 0.65 1.6 V 5.0 V 0.8 V IIH Input High Current VDD = Max. VIN = 2.4V 1 µA IIL Input Low Current VDD = Max. VIN = 0.5V –1 µA II Input High Current VDD = Max., VIN = VDD(Max.) 20 µA VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA IOK Continuous Clamp Current VDD = Max., VOUT = GND OOFF Power-down Disable VDD = GND, VOUT = < 4.5V VH Input Hysteresis –0.7 –1.2 V –50 mA 100 80 µA mV Capacitance Parameter Description Test Conditions Min. Typ. Max. Unit Cin Input Capacitance VIN = 0V 2.5 pF Cout Output Capacitance VOUT = 0V 6.5 pF Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07056 Rev. *E Page 2 of 9 CY2CC810 Power Supply Characteristics (see Figure 5) Parameter Description Test Conditions Min. ∆ICC Delta ICC Quiescent Power Supply Current (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD = Max. and VIN = VDD – 0.6V) ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ tPU Power-up time for all VDDs Power-up to reach minimum specified voltage (power ramp must be monotonic) Typ. 0.05 Max. Unit 50 µA 0.63 mA/ MHz 25 mA 500 ms High-frequency Parametrics Parameter DJ Fmax(3.3V) Description Jitter, Deterministic Maximum frequency VDD = 3.3V Typ. Max. Unit 50% duty cycle tW(50–50) The “point to point load circuit” Output Jitter – Input Jitter Test Conditions 2.5V Min. 23 35 ps 3.3V 19 30 ps 50% duty cycle tW(50–50) Standard Load Circuit. See Figure 5 160 MHz 50% duty cycle tW(50–50) The “point to point load circuit” See Figure 7 650 Fmax(2.5V Maximum frequency VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 7 200 MHz Fmax(20) Maximum frequency VDD = 3.3 V 20% duty cycle tW(20–80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V See Figure 7 250 MHz Maximum frequency VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 3 200 MHz Minimum pulse VDD = 3.3 V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V See Figure 7 1 Minimum pulse VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 3 1 tW ns AC Switching Characteristics @ 3.3V, VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter Description tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low See Figure 4 Min. Typ. Max. Unit 1.5 2.7 3.5 ns 1.5 2.7 3.5 ns tR Output Rise Time 0.8 V/ns tF Output Fall Time 0.8 V/ns tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.25 0.38 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output See Figure 9 (tPHL – tPLH). 0.2 ns tSK(t) Package Skew: Skew between outputs of different packages at the See Figure 11 same power supply voltage, temperature and package type. 0.42 ns Document #: 38-07056 Rev. *E Page 3 of 9 CY2CC810 AC Switching Characteristics @ 2.5V, VDD = 2.5V ±5%, Temperature = –40°C to +85°C Parameter Description tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low See Figure 4 Min. Typ. Max. Unit 1.5 2.0 3.5 ns 1.5 2.0 3.5 ns tR Output Rise Time 0.8 V/ns tF Output Fall Time 0.8 V/ns tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.25 0.38 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output See Figure 9 (tPHL – tPLH). 0.4 ns tSK(t) Package Skew: Skew between outputs of different packages at the See Figure 11 same power supply voltage, temperature and package type. 0.65 ns Parameter Measurement Information: VDD @ 2.5V Figure 1. Load Circuit [3,4,5] f F r o m O u tp u t U nder T est C L = 50 pF 500 ohm Figure 2. Voltage Waveforms Pulse Duration[6] t w(50-50) Input 2.0 V 1.25 V 1.25 V 0V t w(20-80) Input 2.0 V 1.25 V 0V Figure 3. Point to Point Load Circuit[3,4,5] F ro m O u tp u t U nder T est C L = 3 pF 500 ohm Notes 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50W, tR < 2.5 nS, tF < 2.5 nS. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd.. Document #: 38-07056 Rev. *E Page 4 of 9 CY2CC810 Figure 4. Voltage WaveformsPropagation Delay Times[4] 1.25 V Input 2.0 V 1.25 V 0V tPHL tPLH VOH 1.25 V VOL 1.25 V Output Parameter Measurement Information: VDD @ 3.3V Figure 5. Load Circuit [3,4,5] From Output Under Test C L = 50 pF 500 ohm Figure 6. Voltage Waveforms–Pulse Duration[6] tw(50-50) Input 2.7V 1.5V 1.5V 0V t w(20-80) Input 2.7V 1.5V 0V Figure 7. Point to Point Load Circuit[3,4,5] From Output Under Test CL = 3 pF 500 ohm Figure 8. Voltage Waveforms Propagation Delay Times[4] 1.5V Input tPLH Output Document #: 38-07056 Rev. *E 2.7V 1.5V 0V tPHL 1.5V 1.5V VOH VOL Page 5 of 9 CY2CC810 Figure 9. Pulse Skew–tsk(p) 3V 1.5V INPUT 0V t PHL t PLH VOH 1.5V OUTPUT VOL tsk (P) = l tPHL - tPLH l Figure 10. Output Skew–tsk(0) 3V 1 .5 V IN P U T 0V tP H L 1 tP LH 1 VOH 1 .5 V OUTPUT 1 VOL ts k ( O ) ts k ( O ) VOH 1 .5 V OUTPUT 2 VOL tP L H ts k ( P ) = tP L H 2 2 l tP LH 2 - tP LH 1 l o r tP H L2 - tP H L1 l Figure 11. Package Skew–tsk(t) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V PACKAGE 1 OUTPUT tsk (t) tsk (t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tsk (t) = Document #: 38-07056 Rev. *E tPLH 2 l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Page 6 of 9 CY2CC810 Ordering Information Part Number CY2CC810OI CY2CC810OIT CY2CC810OC CY2CC810OCT Lead-free CY2CC810OXC CY2CC810OXCT CY2CC810OXI CY2CC810OXIT Package Type 20-pin SSOP 20-pin SSOP–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel Product Flow Industrial, –40°C to 85°C Industrial, –40°C to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C 20-pin SSOP 20-pin SSOP–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Package Drawing and Dimensions Figure 12. 20-Lead (300-Mil) SOIC S20.3/SZ20.3 NOTE : PIN 1 ID 10 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT 1 DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.391] 0.300[7.620] MIN. MAX. 4. PACKAGE WEIGHT 0.55gms * 0.394[10.007] 0.419[10.642] 11 20 0.026[0.660] 0.032[0.812] PART # S20.3 STANDARD PKG. SZ20.3 LEAD FREE PKG. SEATING PLANE 0.497[12.623] 0.513[13.030] 0.092[2.336] 0.105[2.667] * 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] Document #: 38-07056 Rev. *E 0.004[0.101] 0.0118[0.299] * 0.004[0.101] 0.015[0.381] 0.050[1.270] 0.0091[0.231] 0.0125[0.317] 51-85024-*C Page 7 of 9 CY2CC810 Figure 13. 20-lead (5.3-mm) Shrunk Small Outline Package O20 51-85077-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07056 Rev. *E Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2CC810 Document History Page Document Title: CY2CC810 1:10 Clock Fanout Buffer Document #: 38-07056 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107081 06/07/01 IKA Convert from IMI to Cypress *A 114315 05/09/02 TSM ∆ IDD Validation *B 119117 10/07/02 RGL Added 5.8 as the Max. value of VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 1.8 to 5.0 in the DC Electrical Characteristics @2.5V table. *C 122743 12/14/02 RBI Added power up requirements to maximum ratings information. *D 387761 See ECN RGL Added typical values Updated jitter and skew specs. Removed devices with SOIC package Added Lead-free SSOP package *E 499991 See ECN RGL Added tpu parameter in the Power Supply Characteristics table Document #: 38-07056 Rev. *E Page 9 of 9