Allegro A6280 3 bit constant current led driver with pwm control Datasheet

A6280
3 Bit Constant Current LED Driver with PWM Control
Features and Benefits
Description
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The A6280 is a 3 bit constant current LED driver that has a wide
range of output currents. The A6280 controls LED luminance
with a pulse width modulation (PWM) scheme that gives the
application the capability of displaying a billion colors. The
overall maximum current is set by an external resistor.
5 to 17 V operation
Wide output current range (10 to 150 mA per output)
3 × 7 bit Dot Correction current settings
31 bit shift register
3 ×10 bit PWM luminance settings
Buffered output control pins
Up to 5 MHz serial / PWM clock frequency
Thermal Shutdown / UVLO
Packages: 16 pin DIP (suffix A), and
16 pin QFN/MLP (suffix ES)
The LED luminance is controlled by performing PWM control
on the outputs. The luminance data of the PWM signal for each
LED is stored in three 10 bit registers. Each LED can be dot
corrected by a 7 bit scalar register that scales the maximum
current from 100% down to 36.5%. All the internal latched
registers are loaded by a 31 bit serial shift register. One bit is used
to control the type of data loaded into the registers, either dot
correction / clock divider ratio or luminance data. The remaining
30 bits are used for the data. This helps reduce the pin count
of the A6280. To further lower the A6280 pin count, the PWM
clock and the serial bus clock share the same pin and work
concurrently to control LED luminance and to load data.
The A6280 is designed to minimize the number of components
needed to drive LEDs with large pixel spacing. Several A6280s
can be daisy chained together and controlled by just four control
signals (Clock, Serial Data, Latch, and Output Enable). Each
of these inputs has buffered outputs on chip. Also, the VIN pin
ES, approximate scale 1:1
Continued on the next page…
Application Diagram
Power Supply Bus
VLED
Clock
Data
Strobe
Output Enable
Microprocessor
Control Board
Cat5 UTP
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Strobe In
Strobe Out
OE In
OE Out
VREG A6280 REXT
Pixel Board #1
VLED
Cat5 UTP
VIN OutR OutG OutB
Clock In
Clock Out
Data In
Data Out
Strobe In
Strobe Out
OE In
OE Out
VREG A6280 REXT
Cat5 UTP
Pixel Board #2
Figure 1. Functional drawing of daisy chained display application. Additional pixel boards
with A6280 ICs can be applied.
A6280-DS, Rev. 1
Pixel Board #N
A6280
3 Bit Constant Current LED Driver with PWM Control
Description (continued)
can be tied to the LED voltage supply bus, thus eliminating the need
for a separate chip supply bus or an external linear regulator.
The A6280 is supplied in a 16 pin dual in line (DIP) package (suffix
‘A’) package and in a 16 lead QFN/MLP (suffix ‘ES’) package. The
packages are lead (Pb) free with 100% matte-tin leadframe plating.
Selection Guide
Part Number
Packing*
Mounting
A6280EA-T
25 pieces/tube
16 pin DIP
A6280EESTR-T
1500 pieces/reel
16 pin QFN/MLP
*Contact Allegro for additional packing options.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Supply Voltage
VIN
17
V
Output Voltage
VO
–0.5 to 17
V
Output Current
IO
170
mA
Ground Current
IGND
600
mA
Logic Input Voltage Range
VI
Operating Ambient Temperature
TA
Maximum Junction Temperature
–0.3 to 7
V
–40 to 85
ºC
TJ(max)
150
ºC
Tstg
–40 to 150
ºC
Storage Temperature
Range E
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
RθJA
Package Thermal Resistance
Rating Units
Package A, 4 layer PCB
38
ºC/W
Package ES, 4 layer PCB
40
ºC/W
Package ES, 1 layer PCB with 1 in2. Cu area
70
ºC/W
*For additional information, refer to the Allegro website.
Power Dissipation versus Ambient Temperature
3500
3250
3000
Pa
(R cka
Power Dissipation, PD (mW)
2750
g
QJ
A = e
38 A, 4
Pa
ºC lay
c
(R ka
/W er
g
QJ
)
PC
A = eE
40 S,
B
ºC 4 la
/W ye
)
rP
CB
Pa
c
(R kage
QJA
= 7 ES, 1
0º
C/W layer
PC
)
B
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
25
50
75
100
125
150
Temperature (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A6280
3 Bit Constant Current LED Driver with PWM Control
Functional Block Diagram
LI
LO
SDI
Shift Registers
SDO
CI
CO
OEI
Latched Registers
OEO
REXT
Current
Regulator 0
Current
Regulator 1
Current
Regulator 2
REXT
VIN
Regulator
VREG
OUT0
OUT1
OUT2
PGND
LGND
10 VIN
VREG 8
9 LGND
13 SDO
14 LO
15 OEO
11 OUT1
LGND
3
10 PGND
VIN
4
9
Package A
12 OUT0
8
REXT 7
2
SDI
11 CI
CO 6
1
7
12 OEI
OEO 5
REXT
VREG
LI
13 LI
6
14 SDI
LO 4
5
15 OUT2
SDO 3
CI
16 PGND
OUT0 2
OEI
OUT1 1
16 CO
Pin-out Drawings
OUT2
Package ES
Terminal List Table
Name
OUT1
OUT0
SDO
LO
OEO
CO
REXT
VREG
LGND
VIN
CI
Number
A Package ES Package
1
11
2
12
3
13
4
14
5
15
6
16
7
1
8
2
9
3
10
4
11
5
OEI
12
6
LI
SDI
OUT2
PGND
13
14
15
16
7
8
9
10
Description
Sinking output terminal
Sinking output terminal
Buffered serial data output after shift registers
Buffered latch output
Buffered output enable output
Buffered clock output
An external resistor at this terminal establishes overall output current
Regulator decoupling
Logic ground
Chip power supply voltage
Serial and PWM clock input
Output enable input; when low (active), the output drivers are enabled;
when high (inactive), all output drivers are turned off (blanked)
Latch input terminal; serial data is latched with high-level input
Serial data input to shift registers
Sinking output terminal
Power ground
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A6280
3 Bit Constant Current LED Driver with PWM Control
OPERATING CHARACTERISTICS, valid at TA = 25°C, VIN = 4.75 to 17.0 V, unless otherwise noted
Characteristic
ELECTRICAL CHARACTERISTICS
Quiescent Supply Current
Operating Supply Current
Symbol
Test Conditions
Min.
Typ.
Max.
Units
IDD
IDD
fCLKIN = 0.0 Hz
fCLKIN = 5 Mhz
VIN rising
VIN falling
IO =15 mA, VIN = 17 V
IO =15 mA, VIN = 4.75 V
REXT = 5 kΩ, scalar = 100%
REXT = 15 kΩ
Output to output variation—all outputs on, REXT = 5 kΩ
–
–
3.5
3.0
4.6
–
135
44
7
1.0
–
–
2.0
–
–
–20
–
3.8
150
100
–
–
–
–
–
–
–
–
200
150.0
–
–
–
±1
–
–
–
150
–
–
–
300
200
±1
165
15
5.0
15.0
4.5
4.0
5.4
600
165
54
7
3.0
±3
1.0
–
0.8
–
20
0.4
–
600
400
–
–
–
mA
mA
V
V
V
mV
mA
mA
%
V
%
μA
V
V
mV
μA
V
V
kΩ
kΩ
bit
°C
°C
tH(CLK)
tSU(D)
tH(D)
tSU(LE)
tH(LE)
tSU(OE)
20
20
20
20
20
40
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tP(OE)2
–
200
–
ns
–
–
–
–
–
–
–
200
50
30
10
10
50
100
–
100
60
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
tP(SDO)
–
50
100
ns
tP(OE)
–
50
100
ns
tP(LE)
tP(CLK)
tw(CLK)
fCLKIN
–
–
70
–
50
50
100
–
100
100
130
6
ns
ns
ns
MHz
Undervoltage Lockout
VIN(UV)
VREG Voltage Range
VREG Dropout Voltage
VREG
VDO
Output Current (any single output)
IO
Output to Output Matching Error*
Output Voltage Range
Load Regulation
Output Leakage Current
Err
VDS(min)
Logic Input Voltage
Logic Input Voltage Hysteresis
Logic Input Current
Logic Output Voltage
Input Resistance
Output Dot Correction Error
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
SWITCHING CHARACTERISTICS
Clock Hold Time
Data Setup Time
Data Hold Time
Latch Setup Time
Latch Hold Time
Output Enable Set Up Time
Output Enable Falling to Outputs Turning ON
Propagation Delay Time
Clock to Output Propagation Delay Time
Logic Output Fall Time
Logic Output Rise Time
IDSX
VIH
VIL
IIN
VOL
VOH
RI
TJTSD
TJhys
tP(OUT)
tBF
tBR
Output Fall Time (Turn Off)
tf
Output Rise Time (Turn On)
tr
Clock Falling Edge to Serial Data Out
Propagation Delay Time
Output Enable In to Output Enable Out
Propagation Delay
Latch In to Latch Out Propagation Delay
Clock In to Clock Out Propagation Delay
Clock Out Pulse Duration
Maximum CLKIN Frequency
*Err = [IO (min or max) – IO(av)] / IO(av).
I%Diff / VDS
VOH = 17 V
All digital inputs
VIN = 0 to 5 V
VIN ≥ 5.0 V, IO = ±2 mA
OEI pin, pull-up
LI pin, pull-down
REXT = 5 kΩ; LSB
Temperature increasing
VDS = 1.0 V, IO = 150 mA
COB = 50 pF, 4.5 to 0.5 V
COB = 50 pF, 0.5 to 4.5 V
CO = 10 pF, 90% to 10% of IO = 10 mA
CO = 10 pF, 90% to 10% of IO = 10 mA
CO = 10 pF, 90% to 10% of IO = 10 mA
CO = 10 pF, 90% to 10% of IO = 10 mA
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A6280
3 Bit Constant Current LED Driver with PWM Control
Timing Diagram
0
Clock
tSU (D )
1
2
3
4
5
6
7
15
8
tw(C L K)
tH( D)
D30 D29 D28 D27 D26 D25 D24 D23 D22
Serial Data In
16
30
D8 D7
D0
tP(SD O)
Don’t Care
Serial Data Out
D30
tSU (L E )
Latch Enable In
tH (L E )
tP( LE)
Latch Enable Out
Figure 2. Shift Register Timing
t0
T1
T2
1
2
TN
Clock IN
PWM Counter
OUT0
Luminance Data= 0
0
1023
0
1
2
X
0
tP (OU T)
tP( OU T)
tP (OU T)
OUT1
Luminance Data= 2
tP (OU T)
OUT2
Luminance Data= 1023
t w (OE)
Output Enable In
tP(OE )
Output Enable Out
Figure 3. PWM Counter and Output Timing
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A6280
3 Bit Constant Current LED Driver with PWM Control
Functional Description
Shift Registers
Output Buffers
The A6280 has a 31 bit shift register that loads data through the
Serial Data In (SDI) pin. The shift registers operate by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 30)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of
the Clock In (CI) pin. The Serial Data Out (SDO) pin is updated
to the state of bit 30 on the falling edge of the CI pin. This will
prevent any race conditions and erroneous data that might occur
while propagating information through multiple A6280 that are
daisy chained together. The contents of the shift registers will
continue to propagate on every rising edge of the CI pin. The
information in the shift registers is latched on a rising edge of the
Latch In (LI) pin. The latched data remains latched on a rising
Output Enable In (OEI) signal.
The A6280 is designed to allow daisy chaining many A6280s
together. It has the ability to pass the clock, data, latch, and output enable signals from one A6820 to the next without any loss of
data due to duty cycle skewing or signal degradation.
The A6820 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6280s
without the need for extra driving hardware. The A6280 drives
these signals to TTL levels. Each of the A6280 inputs have a corresponding buffered output:
• Clock In (CI) pin to Clock Out (CO) pin
• Latch In (LI) pin to Latch Out (LO) pin
• Output Enable In (OEI) pin to Output Enable Out (OEO) pin
• Serial Data In (SDI) pin to Serial Data Out (SDO) pin
Latch In
Latch Out
Shift Registers
Serial
Data In
0
……..
9
10
……..
19
20
……..
29
30
Serial
Data Out
Latched Registers
Clock In
Current
Scalar 0
7 bits
Output
Enable In
Clock
Divider
2 bits
Unused
1 bit
Current
Scalar 1
7 bits
Unused
3 bit
Current
Scalar 2
7 bits
Unused Test
Bit
1 bit 1 bit
PWM Counter 0
10 bits
PWM Counter 1
10 bits
PWM Counter 2
10 bits
Cur
Reg0
Cur
Reg1
Cur
Reg2
Test
Bit
1 bit
Bit 30
“1”
Clock Out
“0”
Output
Enable Out
Regulator
Vin
Vreg
Rext
Out0
Out1
Out2
GND
GND
Figure 4. Functional Diagram
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A6280
3 Bit Constant Current LED Driver with PWM Control
PWM Luminance Control
The A6280 controls the intensity of each LED by PWMing the
current of each output. The A6280 has three 10 bit luminance
registers, one for each output. These luminance registers set the
PWM count value at which the outputs switch off during each
PWM cycle. Each 10 bit luminance register gives 1023 levels of
light intensity. The duty cycle, DC (%), can be determined by the
following equation:
DC = [(PWMn + 1) / 1024] ×100 ,
where PWMn is the PWM value greater than zero that is stored
in the luminance register. When the luminance register is set to
zero, the outputs remain off for the duration of the PWM cycle
for a 0% DC. When a luminance register is set to 1023, the LED
for that output remains on (100% DC) when OEI is active and
begins the PWM cycle. The output remains on when the PWM
counter rolls over and begins a new count.
The PWM counter begins counting at zero and increments only
when the OEI pin is held low. When the PWM counter reaches
the count of 1023, the counter resets to zero and continues
incrementing. The counter resets back to zero either on a rising
edge of OEI, upon recovery from UVLO, or when powering up.
Latching new data into the luminance registers will not reset the
PWM counter.
There is a programmable clock divider that attenuates the
clock input of the CI pin. See table 1 for bit assignments of the
programmable clock divider. The PWM counter is incremented
on every rising edge of the CI pin divided by the clock divider
count value when the OEI pin is low. For example, if the clock
divider is programmed to divide the CI by 2, then the PWM
counter will increment once every 2 CI cycles. Given a 5 MHz
CI frequency, the clock period would be 200 ns.
The total number of possible colors of an RGB pixel is over
1 billion. Refer to figure 6 for the mapping of shift register bits
to latches.
Output Current Selection
The overall maximum current is set by the external resistor,
REXT , connected between REXT and LGND. Once set, the
maximum current remains constant regardless of the LED voltage variation, supply voltage variation, temperature, or other
circuit parameters that could otherwise affect LED current. The
maximum output current can be calculated using the following
equation:
IO(max) = 753.12 / REXT.
The relationship of the value selected for REXT and IO is shown
in figure 5.
Internal Linear Regulator
The A6280 has a built-in linear regulator. The regulator operates from 5 to 17 V, and is intended to allow the VIN pin of the
A6280 to connect to the same supply as the LEDs. This will
simplify board design by eliminating the need for a chip supply
bus and external voltage regulators.
The VREG pin is used by the internal liner regulator as an
energy reservoir. This pin is for internal use only and is not
intended as an external power source. The VREG pin should
have a 1.0 μF, 10 V ceramic capacitor connected between the
VREG pin and LGND. The capacitor should be located as close
to the VREG pin as possible.
Bits
7
0
1
0
1
8
0
0
1
1
Divide By Count
×1 (no division)
×2
×4
×8
The clock divider data in the shift registers is latched on a rising
edge of the Latch In (LI) pin. The latched clock divider data
remains latched on a rising OEI signal.
IO (mA)
Table 1. Clock Divider Configurations
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
5
15
25
35
45
REXT (kΩ)
55
65
75
Figure 5. Output Current versus External Resistor, REXT
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A6280
3 Bit Constant Current LED Driver with PWM Control
Dot Correction Control
Thermal Shutdown (TSD)
The A6280 can further control the maximum output current for
each output by setting the three 7 bit dot correction registers with
scale data that ranges from 36.5% to 100% of the overall maximum output current that is set by the REXT resistor. This feature
is useful because not every type of LED (red, green, or blue, for
example) has the same level of brightness or intensity for any
given current, and the brightness could be different even from
LED to LED of the same type. By scaling the output currents so
that all the LEDs have matched intensities, the application will
have full color depth when using the PWM counters. The dot
correction current can be calculated by the following equation:
When the junction temperature of the A6280 reaches the thermal
shutdown temperature threshold, TJTSD (165°C typical), the
outputs will shut off until the junction temperature cools down
below the recovery threshold, –TJTSD –∆TJ ( 15°C typical). The
shift registers and output latches will remain active during the
TSD event. Therefore there is no need to reset the data in the
output latches.
Undervoltage Lockout
The A6280 includes an internal undervoltage lockout (UVLO)
circuit that disables the driver outputs in the event of the logic
supply voltage dropping below a minimum acceptable level.
This prevents the display of erroneous information, a necessary
function for some critical applications. The shift registers will
not shift any data in a UVLO condition. Upon recovery of the
logic supply voltage and on power up, all internal shift registers
and latches will be set to zero.
IOn = IOn(max) × (Scalen / 2 + 36.5)
Refer to figure 6 for the bit configurations for the scalar registers.
The dot correction data in the shift registers is latched on a rising
edge of the Latch In (LI) pin. The latched dot correction data
remains latched on a rising OEI signal. The default output current when the A6280 is powered up or recovers from a UVLO is
36.5% of the current set by the REXT resistor.
Package Power Dissipation
Ballast Resistors
The maximum allowable package power dissipation is determined as:
The voltage on the outputs should be kept in the range 1 to 3 V.
If the voltage goes below 1V, the current will begin to rolloff
as the driver runs out of headroom. At VO above 3 V, the power
dissipation may become a problem, as each output contributes
VO × ILED of power loss in the output sink driver. Typically the
power supply nominal voltage is chosen to keep the output voltage in this range. Alternatively, series resistors can be added to
dissipate the extra power and keep the output voltage within the
recommended range.
PD(max) = (150 – TA) / RθJA .
The actual package power dissipation is:
PD(act) = DC0 × VDS0 × IOUT0
+ DC1 × VDS1 × IOUT1
+ DC2 × VDS2 × IOUT2 + VIN × IIN .
When calculating power dissipation, the total number of available device outputs is usually used for the worst-case situation
(i.e., displaying all 3 LEDs at 100% DC).
Bits
0 1 2 3 4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PWM Counter 0
Dot Correction
Register 0
Clock
0
Divider
PWM Counter 1
Dot Correction
Register 1
0 0 0
PWM Counter 2
Dot Correction
Register 2
29 30
0
0 ATB* ATB* 1
*Allegro Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application.
Figure 6. Register Configuration
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A6280
3 Bit Constant Current LED Driver with PWM Control
Applications Drawings
Tie LGND and PGND
to PAD externally
PAD
16
CO
15
OEO
14
LO
13
SDO
OUT0
REXT
1
A6280
ES
OUT2
Output Enable
VREG
5
CI
6
OEI
7
LI
8
SDI
Clock
Data
Strobe
2
9
OUT1
System Logic
3
10 kΩ
PGND
VIN
4
LGND
1 μF
X5R
10 11
12
VOn
1 to 3 V
+
8.5 V
Blue
LEDs
10 μF
A6280
ES
Maximum of
250 LEDs
Green Red
LEDs LEDs
–
Figure 7. Application Driving 3 RGB LEDs at 75 mA Peak
Tie LGND and PGND
to PAD externally
9
OUT0
REXT
PAD
10 11
10 μF
75 V
A6280
ES
12
VOn
1 to 3 V
+
10 V
1
16
CO
15
OEO
14
LO
13
SDO
A6280
ES
OUT2
Output Enable
VREG
5
CI
6
OEI
7
LI
8
SDI
Clock
Data
Strobe
2
OUT1
System Logic
3
5 kΩ
PGND
VIN
4
LGND
1 μF
10 V
Maximum of
250 LEDs
2Ω
0.5 W
–
Figure 8. Application Driving High Power LED at 450 mA
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A6280
3 Bit Constant Current LED Driver with PWM Control
A Package, 16 Pin DIP
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 BB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
.775 19.69
.735 18.67
A
.014 0.36
.008 0.20
B
16
.280 7.11
.240 6.10
.430 10.92
MAX
.300 .7.62
A
1
2
.195 4.95
.115 2.92
.210 5.33
MAX
SEATING
PLANE
C
.015 0.38
MIN
.005 0.13
MIN
.070 1.78
.045 1.14
.100 .2.54
16X
.150 3.81
.115 2.92
.022 .056
.014 .036
.010 [0.25] M C
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6280
3 Bit Constant Current LED Driver with PWM Control
ES Package, 16 Pin QFN/MLP
3.15 .124
2.85 .112
A
B
16
1
Preliminary dimensions, for reference only
(reference JEDEC MO-220WEED-4)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
A
2
3.15 .124
2.85 .112
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M); adjust as necessary to
meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
16X
SEATING
PLANE
0.08 [.003] C
16X
0.30 .012
0.18 .007
0.80 .031
0.70 .028
0.10 [.004] M C A B
0.05 [.002] M C
0.50 .020
0.20 .008
REF
0.30 .012
NOM
0.90 .035
NOM
0.05 .002
0.00 .000
0.50 .020
NOM
16
C
1.70 .067
NOM
C
1
1.70 .067
NOM
12X 0.20 .008
MIN
4X 0.20 .008
MIN
3.10 .122
NOM
2
B
1.70 .067
NOM
.067
1
16
16X 0.20 .008
MIN
1.70
NOM
0.23 x 0.23 .009 x .009
REF
0.50 .020
0.30 .012
3.10 .122
NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright©2006 AllegroMicrosystems, Inc.
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com