AD ADA4937-1YCPZ-R7 Ultralow distortion, differential adc driver Datasheet

Ultralow Distortion,
Differential ADC Driver
ADA4937-1
–FB 1
14 –VS
13 –VS
FUNCTIONAL BLOCK DIAGRAM
ADA4937-1
12 PD
06591-001
+VS 8
9 VOCM
+VS 7
10 +OUT
+FB 4
+VS 6
11 –OUT
–IN 3
+VS 5
+IN 2
Figure 1.
–55
HD2,
HD3,
HD2,
HD3,
–60
–65
VS = 5.0V
VS = 5.0V
VS = 3.3V
VS = 3.3V
–70
DISTORTION (dBc)
Extremely low harmonic distortion
−112 dBc HD2 @ 10 MHz
−79 dBc HD2 @ 70 MHz
−70 dBc HD2 @ 100 MHz
−102 dBc HD3 @ 10 MHz
−91 dBc HD3 @ 70 MHz
−84 dBc HD3 @ 100 MHz
Low input voltage noise: 2.2 nV/√Hz
High speed
−3 dB bandwidth of 1.9 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
0.1 dB gain flatness to 200 MHz
Fast overdrive recovery of 1 ns
1 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
Pb-free, 3 mm × 3 mm 16-lead LFCSP
16 –VS
15 –VS
FEATURES
–75
–80
–85
–90
–95
–100
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
–105
–110
–115
1
10
100
FREQUENCY (MHz)
06591-002
APPLICATIONS
Figure 2. Harmonic Distortion vs. Frequency
GENERAL DESCRIPTION
The ADA4937-1 is a low noise, ultralow distortion, high speed
differential amplifier. It is an ideal choice for driving high
performance ADCs with resolutions up to 16 bits from dc to
100 MHz. The adjustable level of the output common mode
allows the ADA4937-1 to match the input of the ADC. The
internal common-mode feedback loop also provides exceptional
output balance as well as suppression of even-order harmonic
distortion products.
With the ADA4937-1, differential gain configurations are easily
realized with a simple external feedback network of four
resistors determining the closed-loop gain of the amplifier.
The ADA4937-1 is fabricated using Analog Devices, Inc.
proprietary silicon-germanium (SiGe), complementary bipolar
process, enabling it to achieve very low levels of distortion with
an input voltage noise of only 2.2 nV/√Hz. The low dc offset
and excellent dynamic performance of the ADA4937-1 make it
well suited for a wide variety of data acquisition and signal
processing applications.
The ADA4937-1 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP. The pinout has been optimized to facilitate PCB layout
and minimize distortion. The part is specified to operate over
the −40°C to +105°C temperature range for 3.3 V supplies and
the −40°C to +85°C temperature range for 5 V supplies.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADA4937-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 18
Applications....................................................................................... 1
Analyzing an Application Circuit ............................................ 18
Functional Block Diagram .............................................................. 1
Setting the Closed-Loop Gain .................................................. 18
General Description ......................................................................... 1
Estimating the Output Noise Voltage ...................................... 18
Revision History ............................................................................... 2
The Impact of Mismatches in the Feedback Networks ......... 19
Specifications..................................................................................... 3
Calculating the Input Impedance of an Application Circuit 19
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 19
Absolute Maximum Ratings............................................................ 7
Setting the Output Common-Mode Voltage .......................... 19
Thermal Resistance ...................................................................... 7
Layout, Grounding, and Bypassing.............................................. 21
ESD Caution.................................................................................. 7
High Performance ADC Driving ................................................. 22
Pin Configuration and Function Descriptions............................. 8
3.3 V Operation .......................................................................... 24
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 25
Test Circuits..................................................................................... 16
Ordering Guide .......................................................................... 25
Operational Description................................................................ 17
Definition of Terms.................................................................... 17
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADA4937-1
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS /2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1. ±DIN to ±OUT Performance
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
INPUT CHARACTERISTICS
Offset Voltage
Conditions
Min
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VIN = 0 V to 1.5 V step; G = 3.16
See Figure 45 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p;, 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 2.5 V
TMIN to TMAX variation
Input Bias Current
−2.5
−30
TMIN to TMAX variation
Input Offset Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
−2
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V
−67
Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ
0.8
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; 10 MHz;
see Figure 44 for test circuit
Rev. 0 | Page 3 of 28
Typ
Max
Unit
1900
200
1700
6000
<1
MHz
MHz
MHz
V/μs
ns
−112
−79
−70
−102
−91
−84
−91
2.2
3
15
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
+0.5
±1
−20
0.01
+0.5
6
3
1
0.3 to 3.0
−80
+2.5
−10
+2
4.2
>100
−61
mV
μV/°C
μA
μA/°C
μA
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4937-1
Table 2. VOCM to ±OUT Performance
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
POWER DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
Disabled
Conditions
Min
1.2
8
VOS, cm = VOUT, cm; VDIN+ = VDIN– = +VS/2
0.97
3.0
38.5
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS; ΔVS = 1 V
Max
440
1150
7.5
VIN = 1.5 V to 3.5 V; 25% to 75%
f = 100 kHz
ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V
ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V
Typ
0.02
−70
Powered down
Enabled
10
2
0.5
−75
0.98
39.5
17
0.3
−90
MHz
V/μs
nV/√Hz
3.8
12
6.1
1.00
5.25
41.0
0.4
≤1
≥2
1
200
10
−300
PD = 5 V
PD = 0 V
OPERATING TEMPERATURE RANGE
−40
Rev. 0 | Page 4 of 28
40
−200
Unit
V
kΩ
mV
μA
dB
V/V
V
mA
μA/°C
mA
dB
V
V
μs
ns
50
−150
μA
μA
+85
°C
ADA4937-1
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS /2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 3. ±DIN to ±OUT Performance
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
INPUT CHARACTERISTICS
Offset Voltage
Conditions
Min
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm= 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VIN = 0 V to 1.0 V step; G = 3.16
See Figure 45 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = +VS/2
TMIN to TMAX variation
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
−2.5
−50
TMIN to TMAX variation
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1.0 V
−67
Maximum ∆VOUT; single-ended output
0.8
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 44 for test circuit
Rev. 0 | Page 5 of 28
Typ
Max
Unit
1900
200
1300
4000
<1
MHz
MHz
MHz
V/μs
ns
−106
−88
−81
−93
−80
−71
−87
2.2
3
15
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
+0.5
±1
−20
0.01
6
3
1
0.3 to 1.2
−80
+2.5
−10
2.5
95
−61
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4937-1
Table 4. VOCM to ±OUT Performance
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
POWER DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
Disabled
Conditions
Min
Typ
440
900
7.5
VIN = 0.9 V to 2.4 V; 25% to 75%
f = 100 kHz
1.2
VOS, cm = VOUT, cm; VDIN+ = VDIN− = 1.67 V
∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V
0.97
3.0
36
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS; ∆VS = 1 V
Max
0.02
−70
Powered down
Enabled
MHz
V/μs
nV/√Hz
2.1
10
2
0.5
−75
0.98
38
17
0.2
−90
6.1
1.00
5.25
39
0.3
≤1
≥2
1
200
10
−200
PD = 3.3 V
PD = 0 V
OPERATING TEMPERATURE RANGE
−40
Rev. 0 | Page 6 of 28
20
−120
Unit
V
kΩ
mV
μA
dB
V/V
V
mA
μA/°C
mA
dB
V
V
μs
ns
30
−100
μA
μA
+105
°C
ADA4937-1
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad)
soldered to a high thermal conductivity 2s2p circuit board,
as described in EIA/JESD 51-7.
Table 6. Thermal Resistance
Package Type
16-Lead LFCSP (Exposed Pad)
θJA
95
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4937-1
package is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the ADA4937-1. Exceeding a junction
temperature of 150°C for an extended period can result in
changes in the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP
(95°C/W) on a JEDEC standard 4-layer board.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
06591-003
Rating
5.5 V
See Figure 3
−65°C to +125°C
−40°C to +105°C
300°C
150°C
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 7 of 28
ADA4937-1
13 –VS
12 PD
11 –OUT
–IN 3
TOP VIEW
(Not to Scale)
10 +OUT
+VS 5
+FB 4
+VS 7
ADA4937-1
+VS 6
+IN 2
06591-400
PIN 1
INDICATOR
+VS 8
–FB 1
15 –VS
14 –VS
16 –VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
9 VOCM
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5 to 8
9
10
11
12
13 to 16
Mnemonic
−FB
+IN
−IN
+FB
+VS
VOCM
+OUT
−OUT
PD
−VS
Description
Negative Output for Feedback Component Connection.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output for Feedback Component Connection.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
Negative Supply Voltage.
Rev. 0 | Page 8 of 28
ADA4937-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOUT, dm = 2 V p-p, VOCM = +VS /2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted.
Refer to Figure 43 for test setup.
6
0
–3
–6
–9
–12
1
10
100
1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
1
10
100
1000
VS = 3.3V
VS = 5.0V
–6
–9
0
–3
–6
–9
–12
10
100
1000
FREQUENCY (MHz)
–15
06591-005
1
100
1000
Figure 9. Large Signal Frequency Response for Various Supplies
6
+105°C
+25°C
–40°C
+105°C
+25°C
–40°C
3
CLOSED-LOOP GAIN (dB)
3
10
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Supplies,
VOUT, dm = 100 mV p-p
6
1
06591-008
CLOSED-LOOP GAIN (dB)
–12
Figure 8. Large Signal Frequency Response for Various Gains
–12
CLOSED-LOOP GAIN (dB)
–9
3
–3
0
–3
–6
–9
0
–3
–6
–9
1
10
100
FREQUENCY (MHz)
1000
–12
06591-006
–12
–6
6
0
–15
–3
FREQUENCY (MHz)
VS = 3.3V
VS = 5.0V
3
0
–15
Figure 5. Small Signal Frequency Response for Various Gains, VOUT, dm = 100 mV p-p
6
3
1
10
100
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Temperatures,
VOUT, dm = 100 mV p-p
1000
06591-009
–15
G = +1
G = +2
G = +5
06591-007
3
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1
G = +2
G = +5
06591-004
NORMALIZED CLOSED-LOOP GAIN (dB)
6
Figure 10. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 9 of 28
ADA4937-1
6
6
RL = 1kΩ
RL = 100Ω
RL = 200Ω
3
CLOSED-LOOP GAIN (dB)
0
–3
–6
10
100
1000
FREQUENCY (MHz)
–9
NORMALIZED CLOSED-LOOP GAIN (dB)
–3
–6
–9
–12
1
10
100
1000
FREQUENCY (MHz)
Figure 12. Small Signal Frequency Response for Various Gains,
VS = 3.3 V and VOUT, dm = 100 mV p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
–3
–6
–9
–12
1
–6
–9
–12
1
6
0
–15
–3
10
100
1000
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p, RF = 348 Ω
10
100
1000
Figure 15. Large Signal Frequency Response for Various Gains, VS = 3.3 V
G = +1
G = +2
G = +5
3
0
FREQUENCY (MHz)
G = +1
G = +2
G = +5
3
0
–3
–6
–9
–12
–15
06591-012
NORMALIZED CLOSED-LOOP GAIN (dB)
6
1000
VS = 3.3V, G = +1
VS = 3.3V, G = +2
VS = 3.3V, G = +5
3
–15
06591-011
NORMALIZED CLOSED-LOOP GAIN (dB)
6
0
–15
100
Figure 14. Large Signal Frequency Response for Various Loads
VS = 3.3V, G = +1
VS = 3.3V, G = +2
VS = 3.3V, G = +5
3
10
FREQUENCY (MHz)
Figure 11. Small Signal Frequency Response for Various Loads,
VOUT, dm = 100 mV p-p
6
1
06591-014
1
06591-010
–9
–3
06591-013
–6
0
1
10
100
FREQUENCY (MHz)
1000
06591-015
CLOSED-LOOP GAIN (dB)
3
RL = 1kΩ
RL = 100Ω
RL = 200Ω
Figure 16. Large Signal Frequency Response for Various Gains, RF = 348 Ω
Rev. 0 | Page 10 of 28
ADA4937-1
VOCM CLOSED-LOOP GAIN (dB)
3
–50
VOCM = 1.0V
VOCM = 2.5V
VOCM = 3.9V
0
HD2,
HD3,
HD2,
HD3,
–60
G
G
G
G
= +1,
= +1,
= +2,
= +2,
RF = 200Ω
RF = 200Ω
RF = 402Ω
RF = 402Ω
DISTORTION (dBc)
–70
–3
–6
–80
–90
–100
–9
1
10
100
1000
FREQUENCY (MHz)
–120
06591-017
Figure 20. Harmonic Distortion vs. Frequency and Gain
RL = 1kΩ
RL = 100Ω
RL = 200Ω
0.4
–50
HD2,
HD3,
HD2,
HD3,
–60
0.2
RL = 1kΩ
RL = 1kΩ
RL = 200Ω
RL = 200Ω
–70
DISTORTION (dBc)
CLOSED-LOOP GAIN (dB)
0.3
0.1
0
–0.1
–0.2
–80
–90
–100
–0.3
–0.4
–110
1
10
06591-018
–0.5
100
10
FREQUENCY (MHz)
Figure 17. Small Signal Frequency Response for Various VOCM
0.5
1
100
FREQUENCY (MHz)
–120
1
06591-022
–12
06591-021
–110
100
10
FREQUENCY (MHz)
Figure 18. 0.1 dB Flatness Response for Various Loads
Figure 21. Harmonic Distortion vs. Frequency and Load
–55
HD2,
HD3,
HD2,
HD3,
–60
–65
VS = 5.0V
VS = 5.0V
VS = 3.3V
VS = 3.3V
–50
–60
–80
–85
–90
–95
–100
–80
–90
–100
–110
–105
–110
1
10
100
FREQUENCY (MHz)
–130
–1
0
1
2
3
4
5
6
VOUT (V)
Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage
Figure 22. Harmonic Distortion vs. VOUT and Supply Voltage
Rev. 0 | Page 11 of 28
7
06591-023
–120
06591-020
–115
VS = 3.3V
VS = 3.3V
VS = 5.0V
VS = 5.0V
–70
–75
DISTORTION (dBc)
DISTORTION (dBc)
–70
HD2,
HD3,
HD2,
HD3,
ADA4937-1
–30
HD2,
HD3,
HD2,
HD3,
–40
–50
0
f = 10MHz
f = 10MHz
f = 75MHz
f = 75MHz
–20
DISTORTION (dBc)
DISTORTION (dBc)
–60
–70
–80
–90
–40
–60
–80
–100
–100
1.5
2.0
2.5
3.0
3.5
4.0
VOCM (V)
–120
69.4
06591-025
–120
1.0
HD2,
HD3,
HD2,
HD3,
–50
69.8
70.0
70.2
70.4
70.6
FREQUENCY (MHz)
Figure 26. 70 MHz Intermodulation Distortion
Figure 23. Harmonic Distortion vs. VOCM and Frequency
–40
69.6
06591-027
–110
–30
f = 30MHz
f = 30MHz
f = 75MHz
f = 75MHz
RL = 200Ω
–40
CMRR (dB)
DISTORTION (dBc)
–60
–70
–50
–80
–60
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOCM (V)
–70
06591-045
–100
1.1
1
10
HD2,
HD3,
HD2,
HD3,
–60
–10
1V p-p
1V p-p
2V p-p
2V p-p
RL = 200Ω
–20
OUTPUT BALANCE (dB)
–70
–80
–90
–100
–110
–30
–60
–70
–130
1
10
100
FREQUENCY (MHz)
–60
1
10
100
FREQUENCY (MHz)
Figure 28. Output Balance vs. Frequency
Figure 25. Harmonic Distortion vs. Frequency and VOUT, VS = 3.3 V
Rev. 0 | Page 12 of 28
1000
06591-029
–120
06591-044
DISTORTION (dBc)
1k
Figure 27. CMRR vs. Frequency
Figure 24. Harmonic Distortion vs. VOCM and Frequency, VS = 3.3 V
–50
100
FREQUENCY (MHz)
06591-059
–90
ADA4937-1
–30
28
VOUT, dm PSRR, VS = 3.3V
VOUT, dm PSRR, VS = 5.0V
–40
G = +1
G = +2
G = +4
26
24
NOISE FIGURE (dB)
PSRR (dB)
–50
–60
–70
–80
22
20
18
16
14
–90
10
100
1000
FREQUENCY (MHz)
10
10
0
Figure 32. Noise Figure vs. Frequency
S11
S22
3
–10
2
VOUT DIFFERENTIAL (V)
–15
S-PARAMETERS (dB)
100
FREQUENCY (MHz)
Figure 29. PSRR vs. Frequency, RL = 200 Ω
–5
06591-033
1
06591-030
–100
12
–20
–25
–30
–35
–40
–45
1
0
–1
–2
–50
–55
1
10
100
1000
FREQUENCY (MHz)
TIME (2ns/DIV)
06591-031
Figure 30. Return Loss (S11, S22) vs. Frequency
–55
Figure 33. Overdrive Recovery Time (Pulse Input)
5
SFDR, RL = 1kΩ
SFDR, RL = 200Ω
–60
4
–65
3
–75
SIGNAL LEVEL (V)
DISTORTION (dBc)
–70
–80
–85
–90
–95
–100
2
1
0
–1
–2
–3
–105
–4
–115
–5
1
10
100
FREQUENCY (MHz)
Figure 31. Spurious-Free Dynamic Range vs. Frequency and Load
06591-032
–110
VIN × 3
VOUT DIFF
0
100
200
300
TIME (ns)
400
500
600
06591-034
–65
06591-060
–3
–60
Figure 34. Overdrive Amplitude Characteristics (Triangle Wave Input)
Rev. 0 | Page 13 of 28
60
60
55
55
50
50
45
45
SUPPLY CURRENT (mA)
40
35
+105°C
30
+25°C
25
20
+55°C
0°C
15
–40°C
10
35
+25°C
30
+105°C
25
0°C
20
15
+55°C
–40°C
10
5
5
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
POWER-DOWN VOLTAGE (V)
2.0
0
1.0
06591-036
0
1.0
40
Figure 35. Supply Current vs. PD for Various Temperatures
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
POWER-DOWN VOLTAGE (V)
1.9
2.0
06591-037
SUPPLY CURRENT (mA)
ADA4937-1
Figure 38. Supply Current vs. PD for Various Temperatures, VS = 3.3 V
0.20
5
4
0.15
3
0.10
VOUT, dm = 4V p-p
0.05
VOLTAGE (V)
VOLTAGE (V)
2
0
–0.05
1
VOUT, dm = 2V p-p
0
–1
–2
–0.10
–3
–0.15
–5
TIME (1ns/DIV)
06591-040
TIME (1ns/DIV)
06591-039
–0.20
–4
Figure 39. Large Signal Pulse Response
Figure 36. Small Signal Pulse Response
2.60
4.00
2.58
3.75
3.50
2.56
3.25
VOLTAGE (V)
3.00
2.52
2.50
2.48
2.75
2.50
2.25
2.00
2.46
1.75
2.44
1.50
2.42
1.25
TIME (2ns/DIV)
1.00
TIME (2ns/DIV)
Figure 40. Large Signal VOCM Pulse Response
Figure 37. Small Signal VOCM Pulse Response
Rev. 0 | Page 14 of 28
06591-041
2.40
06591-042
VOLTAGE (V)
2.54
ADA4937-1
100
2.4
2.2
PD INPUT
INPUT VOLTAGE NOISE (nV/ Hz)
1.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
SINGLE OUTPUT
TIME (150ns/DIV)
06591-038
VOLTAGE (V)
1.6
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 41. PD Response vs. Time
Figure 42. Voltage Spectral Noise Density, RTI
Rev. 0 | Page 15 of 28
10M
06591-061
2.0
ADA4937-1
TEST CIRCUITS
200Ω
5V
50Ω
VIN
200Ω
VOCM
61.9Ω
ADA4937-1
1kΩ
200Ω
06591-046
27.5Ω
200Ω
Figure 43. Equivalent Basic Test Circuit
200Ω
5V
50Ω
VIN
200Ω
50Ω
VOCM
61.9Ω
ADA4937-1
200Ω
50Ω
06591-047
27.5Ω
200Ω
Figure 44. Test Circuit for Output Balance
200Ω
5V
VIN
FILTER
61.9Ω
0.1µF
200Ω
VOCM
412Ω
FILTER
ADA4937-1
0.1µF
200Ω
412Ω
27.5Ω
200Ω
Figure 45. Test Circuit for Distortion Measurements
Rev. 0 | Page 16 of 28
06591-048
50Ω
ADA4937-1
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
–FB
RG
+IN
–OUT
VOCM
–DIN
This refers to the average of two node voltages. The output
common-mode voltage is defined as
ADA4937-1
VOUT, cm = (V+OUT + V−OUT)/2
RL, dm VOUT, dm
RG
RF
–IN
+OUT
+FB
Balance
06591-051
+DIN
RF
Figure 46. Circuit Definitions
Differential Voltage
This refers to the difference between two node voltages. For
example, the output differential voltage (or equivalently, output
differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Balance is a measure of how well differential signals are
matched in amplitude and are exactly 180° apart in phase.
Balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider’s midpoint
with the magnitude of the differential signal (see Figure 44). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
Rev. 0 | Page 17 of 28
Output Balance Error =
VOUT , cm
VOUT , dm
ADA4937-1
THEORY OF OPERATION
The ADA4937-1 differs from conventional op amps in that it
has two outputs whose voltages move in opposite directions.
Like an op amp, it relies on open-loop gain and negative
feedback to force these outputs to the desired voltages. The
ADA4937-1 behaves much like a standard voltage feedback op
amp and makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Also like an op amp, the ADA4937-1 has
high input impedance and low output impedance.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output
voltage. The common-mode feedback controls only the commonmode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The ADA4937-1 architecture results in outputs that are highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output commonmode voltage to zero. This results in nearly perfectly balanced
differential outputs that are identical in amplitude and are
exactly 180° apart in phase.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 46 can be
determined by
VOUT , dm
VIN , dm
=
RF
RG
This assumes the input resistors (RG) and feedback resistors (RF)
on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4937-1 can be
estimated using the noise model in Figure 47. The inputreferred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The noise currents are assumed to be
equal and produce a voltage across the parallel combination of
the gain and feedback resistances. vnCM is the noise voltage
density at the VOCM pin. Each of the four resistors contributes
(4kTRx)1/2. Table 8 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density terms.
VnRG1
RG1
VnRF1
RF1
inIN+
+
inIN–
VnIN
ADA4937-1
VnOD
ANALYZING AN APPLICATION CIRCUIT
VOCM
VnRG2
RG2
RF2
VnCM
VnRF2
06591-067
The ADA4937-1 uses open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN (see
Figure 46). For most purposes, this voltage can be assumed to
be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
Figure 47. ADA4937-1 Noise Model
Table 8. Output Noise Voltage Density Calculations
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN−
inIN+
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
Input Noise
Voltage Density
vnIN
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Rev. 0 | Page 18 of 28
Output
Multiplication Factor
GN
GN
GN
GN(β1 − β2)
GN(1 − β2)
GN(1 − β1)
1
1
Output Noise
Voltage Density Term
vnO1 = GN(vnIN)
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
vnO4 = GN(β1 − β2)(vnCM)
vnO5 = GN(1 − β2)(4kTRG1)1/2
vnO6 = GN(1 − β1)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
ADA4937-1
RF
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by the appropriate output factor,
ADA4937-1
+VS
where:
2
is the circuit noise gain.
GN =
(β1 + β2 )
RG1
RG2
and β2 =
are the feedback factors.
β1 =
RF1 + RG1
RF2 + RG2
–DIN
VOCM
RG
VOUT, dm
–IN
Figure 48. ADA4937-1 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 49),
the input impedance is
R
1
=1+ F
β
RG
RIN , cm
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms.
⎛
⎞
⎜
⎟
R
G
⎟
=⎜
RF
⎜1−
⎟
⎜
⎟
(
)
2
R
R
×
+
F
G
⎝
⎠
RF
+VS
8
RG
RS
2
∑ vnOi
i =1
VOCM
RT
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio
matching errors in the external resistors result in a degradation
of the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = 1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worstcase input CMRR of about 40 dB, a worst-case differentialmode output offset of 25 mV due to 2.5 V level-shift, and no
significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 48, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
ADA4937-1
VOUT, dm
RG
RS
RT
RF
06591-063
vnOD =
+IN
RF
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
GN =
RG
06591-062
+DIN
Figure 49. ADA4937-1 Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4937-1 is optimized for level-shifting, ground-referenced
input signals. As such, the center of the input common-mode
range is shifted approximately 1 V down from midsupply. For
5 V single-supply operation, the input common-mode range at
the summing nodes of the amplifier is 0.3 V to 3.0 V, and 0.3 V
to 1.9 V with a 3.3 V supply. To avoid clipping at the outputs,
the voltage swing at the +IN and –IN terminals must be confined
to these ranges.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4937-1 is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 100 mV of
the expected value.
In cases where more accurate control of the output commonmode level is required, it is recommended that an external
source, or resistor divider (10 kΩ or greater resistors), be used.
The output common-mode offset listed in the Specifications
section assumes that the VOCM input is driven by a low impedance
voltage source.
Rev. 0 | Page 19 of 28
ADA4937-1
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
assure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4937-1 devices share one reference output, it is
recommended that a buffer be used.
Note that some gain configurations at 3.3 V cause the input
common-mode voltage to exceed the specified range and should be
avoided. If larger gains are required, other alternatives should be
considered, such as an input common-mode offset, ac coupling,
or a bipolar power supply.
Table 9 and Table 10 list several common gain settings,
associated resistor values, input impedance, output noise
density, and approximate large signal bandwidth for both balanced
and unbalanced input configurations. Also shown are the input
common-mode voltage swings under the given conditions for
different VOCM settings with single 5 V and 3.3 V supplies.
Table 9. Differential Ground-Referenced Input, DC-Coupled; See Figure 48
Nominal
Gain (dB)
0
3
6
10
12
14
RF (Ω)
200
348
280
348
200
348
316
348
402
348
499
348
RG (Ω)
200
348
200
249
100
174
100
110
100
86.6
100
69.8
RIN, dm(Ω)
400
696
400
498
200
348
200
220
200
173
200
140
Differential
Output
Noise Density
(nV/√Hz)
5.8
6.7
7.2
7.6
8.0
9.0
11
12
14
13
17
16
Common-Mode Swing at +IN, −IN (V)
Approximate
Large-Signal
Bandwidth (MHz)
+VS = 5 V/3.3 V
1500/1100
+VS = 5 V
VOUT, dm = 2.0 V p-p
VOCM = 2.5 V VOCM = 3.2 V
0.75 to 1.75
1.10 to 2.10
+VS = 3.3 V
VOUT, dm = 1.6 V p-p
VOCM = 1.6 V
VOCM = 1.8 V
0.40 to 1.20
0.50 to 1.30
1500/1100
0.69 to 1.40
0.98 to 1.69
0.39 to 1.04
0.46 to 1.04
1400/1100
0.58 to 1.08
0.82 to 1.32
0.33 to 0.73
0.40 to 0.80
800/700
0.44 to 0.76
0.61 to 0.92
Out of range
0.31 to 0.56
500/500
0.37 to 0.62
0.51 to 0.76
Out of range
Out of range
300/300
0.32 to 0.52
0.43 to 0.63
Out of range
Out of range
Table 10. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω; See Figure 49
Nominal
Gain (dB)
0
3
6
10
12
14
1
RF
(Ω)
200
348
280
348
200
348
316
348
402
348
499
348
RG1
(Ω)
200
348
200
249
100
174
100
110
100
86.6
100
69.8
RT
(Ω)
61.9
56.2
60.4
59.0
75.0
61.9
73.2
69.8
71.5
76.8
71.5
86.6
RIN,cm
(Ω)
267
464
282
351
150
261
161
177
167
144
171
120
RG2
(Ω) 1
226
374
226
274
130
200
130
140
130
118
130
100
Differential
Output
Noise
Density
(nV/√Hz)
5.5
6.5
6.8
7.3
7.0
8.4
9.7
10
12
11
14
12
Approximate
Large-Signal
Bandwidth
(MHz)
+VS = 5 V/3.3 V
1500/1100
VOCM = 2.5 V
0.75 to 1.75
VOCM = 3.2 V
1.13 to 2.26
VOCM = 1.6 V
0.40 to 1.30
VOCM = 1.8 V
Out of range
1500/1100
0.71 to 1.52
1.03 to 1.83
0.39 to 1.04
0.48 to 1.13
1400/1100
0.66 to 1.31
0.94 to 1.59
0.37 to 0.89
0.45 to 0.97
800/700
0.52 to 0.93
0.73 to 1.14
0.30 to 0.63
0.36 to 0.69
500/500
0.45 to 0.77
0.62 to 0.94
Out of range
0.31 to 0.57
300/300
0.39 to 0.65
0.53 to 0.79
Out of range
Out of range
RG2 = RG1 + (RS||RT)
Rev. 0 | Page 20 of 28
Common-Mode Swing at +IN, -IN (V)
+VS = 3.3 V
+VS = 5 V
VOUT,dm = 2.0 V p-p
VOUT,dm = 1.6 V p-p
ADA4937-1
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4937-1 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. This
reduces radiated energy and makes the circuit less susceptible
to interference.
06591-052
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4937-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) should be
cleared of all ground and power planes (see Figure 50). This
minimizes any stray capacitance at these nodes and prevents
peaking of the response of the amplifier at high frequencies.
The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 μF tantalum capacitors from each supply
to ground.
Figure 50. Ground and Power Plane Voiding in Vicinity of RF and RG
Rev. 0 | Page 21 of 28
ADA4937-1
HIGH PERFORMANCE ADC DRIVING
The ADA4937-1 is ideally suited for broadband IF applications.
The circuit in Figure 51 shows a front-end connection for an
ADA4937-1 driving an AD9445, 14-bit, 105 MSPS ADC. The
AD9445 achieves its optimum performance when driven
differentially. The ADA4937-1 eliminates the need for a
transformer to drive the ADC and performs a single-endedto-differential conversion and buffering of the driving signal.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4937-1 is left floating,
allowing the internal divider to set the output common-mode
voltage at midsupply. One-half of the common-mode voltage is fed
back to the summing nodes, biasing –IN and + IN at 1.25 V. For a
common-mode voltage of 2.5 V, each ADA4937-1 output swings
between 2.0 V and 3.0 V, providing a 2 V p-p differential output.
The ADA4937-1 is configured with a single 5 V supply and
unity gain for a single-ended input to differential output. The
61.9 Ω termination resistor, in parallel with the single-ended
input impedance of 267 Ω, provides a 50 Ω termination for the
source. The additional 26 Ω (226 Ω total) at the inverting input
balances the parallel impedance of the 50 Ω source and the
termination resistor driving the noninverting input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 51.
5V (A) 3.3V (A) 3.3V (D)
200Ω
5V
200Ω
50Ω
61.9Ω
AVDD2 AVDD1 DRVDD
AD9445
VIN–
BUFFER T/H
24.3Ω
ADA4937-1
226Ω
30nH
47pF
ADC
24.3Ω
0.1µF
30nH
14
VIN+
CLOCK/
TIMING
200Ω
REF
AGND
SENSE
06591-064
SIGNAL
GENERATOR
VOCM
0.1µF
+
Figure 51. ADA4937-1 Driving an AD9445, 14-Bit, 105 MSPS ADC
Rev. 0 | Page 22 of 28
ADA4937-1
The circuit in Figure 53 shows a simplified front-end connection
for an ADA4937-1 driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves its optimum performance when driven
differentially. The ADA4937-1 performs the single-ended-todifferential conversion, eliminating the need for a transformer
to drive the ADC.
the SENSE pin to AGND. The inputs of the AD9246 are biased
at 1 V by connecting the CML output, as shown in Figure 53.
The circuit was tested with a −1 dBFS signal at various
frequencies. Figure 52 shows a plot of the second and third
harmonic distortion (HD2/HD3) vs. frequency.
–75
G = +2
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4937-1 is left
unconnected; therefore, the internal pull-ups set the output
common-mode voltage to midsupply. A portion of this is fed
back to the summing nodes, biasing –IN and + IN at 0.55 V. For
a common-mode voltage of 2.5 V, each ADA4937-1 output swings
between 2.0 V and 3.0 V, providing a 2 V p-p differential output.
–80
HD3
–85
HD2
–90
–95
–100
0
20
40
60
200Ω
50Ω
10µF
90Ω
90Ω
10µF
+
ADA4937-1
200Ω
10pF
200Ω
10µF
76.8Ω
33Ω
AVDD
DRVDD
VIN–
AD9246
VIN+
33Ω
D11 TO
D0
AGND SENSE CML
06591-058
VIN
1.8V
5V
76.8Ω
10µF
100
120
Figure 52. HD2/HD3 for Combination of ADA4937-1 and AD9246 ADC
The output is ac-coupled to a single-pole, low-pass filter. This
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting
50Ω
80
FREQUENCY (MHz)
06591-065
HARMONIC DISTORTION (dBc)
The ADA4937-1 is configured with a single 5 V supply and a
gain of ~2 V/V for a single-ended input to differential output.
The 76.8 Ω termination resistor, in parallel with the singleended input impedance of 137 Ω, provides a 50 Ω ac termination
for the source. The additional 30 Ω (120 Ω total) at the inverting
input balances the parallel ac impedance of the 50 Ω source and
the termination resistor driving the noninverting input.
200Ω
Figure 53. ADA4937-1 Driving an AD9246, a 14-Bit, 125 MSPS ADC
Rev. 0 | Page 23 of 28
ADA4937-1
453Ω
1.8V
3.3V
50Ω
VIN
200Ω
59Ω
VOCM
33Ω
+
ADA4937-1
10pF
56nH
AVDD
VIN–
DRVDD
AD9230
30pF
VIN+
33Ω
56nH
AGND
CML
06591-066
226Ω
D11 TO
D0
453Ω
Figure 54. ADA4937-1 Driving an AD9230, a 12-Bit, 250 MSPS ADC
3.3 V OPERATION
The ADA4937-1 provides excellent performance in 3.3 V
single-supply applications. Significant power savings can be
realized when the ADA4937-1 is used in combination with a
low voltage ADC.
The circuit in Figure 54 is an example of the ADA4937-1
driving an AD9230, 12-bit, 250 MSPS ADC that is specified to
operate with a single 1.8 V supply. The performance of the
ADC is optimized when it is driven differentially, making the
best use of the signal swing available within the 1.8 V supply.
The ADA4937-1 performs the single-ended-to-differential
conversion, common-mode level-shifting, and buffering of the
driving signal.
The ADA4937-1 is configured with a single 3.3 V supply and a
gain of 2 V/V for a single-ended input to differential output. The
59 Ω termination resistor, in parallel with the single-ended input
impedance of 306 Ω, provides a 50 Ω termination for the source.
The additional 26 Ω (226 Ω total) at the inverting input balances
the parallel impedance of the 50 Ω source and termination
resistor driving the noninverting input.
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin is connected to the CML output of the
AD9230, and sets the output common mode of the ADA4937-1 at
1.4 V. One-third of the output common-mode voltage of the
amplifier is fed back to the summing nodes, biasing –IN and + IN
at ~ 0.5 V. For a common-mode voltage of 1.4 V, each ADA4937-1
output swings between 1.09 V and 1.71 V, providing a 1.25 V p-p
differential output.
A third-order, 125 MHz, low-pass filter between the ADA4937-1
and the AD9230 reduces the noise bandwidth of the amplifier
and isolates the driver outputs from the ADC inputs.
Rev. 0 | Page 24 of 28
ADA4937-1
OUTLINE DIMENSIONS
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
TOP
VIEW
13
12
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
16
1
EXPOSED
PAD
0.50
BSC
1.00
0.85
0.80
0.50
0.40
0.30
9
PIN 1
INDICATOR
*1.45
1.30 SQ
1.15
(BOTTOM VIEW) 4
8
5
0.25 MIN
1.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADA4937-1YCPZ-R2 1
ADA4937-1YCPZ-RL1
ADA4937-1YCPZ-R71
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
Package Option
CP-16-2
CP-16-2
CP-16-2
Ordering Quantity
5,000
1,500
250
Branding
H1S
H1S
H1S
ADA4937-1
NOTES
Rev. 0 | Page 26 of 28
ADA4937-1
NOTES
Rev. 0 | Page 27 of 28
ADA4937-1
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06591-0-5/07(0)
Rev. 0 | Page 28 of 28