APL5332 CMOS LDO with Source-Sink & Output Selection Functions Features General Description • LDO with Source and Sink capabilities • Single Input Voltage • Input Voltage Range from 2.5V to 5.0V • Use One Pin to Select Fixed Output Voltage • Use One Pin to Choose Output Voltage by The APL5332 is a precise CMOS LDO with source sink and output selection functions. The APL5332 offers 2% output accuracy. The APL5332 integrates with two power mosfets to source and sink current as well as current and thermal limit into a single chip. The output voltage can be 1.225V or 1.45V by BS pin selection, and also can be adjusted by an external resistor divider connected to FB pin. The APL5332 also works with low-ESR output capacitors, reducing the amount of board space necessary for power applications. The APL5332 key features include current-limit, thermal shutdown, and fast transient response. A compact package TO-252-5 for power consumption purpose, and SOP-8 and SOP-8-P for space saving purpose. External Resistors • Thermal Shutdown Protection • Fast Transient Response • Stability with low-ESR capacitors • TO-252-5, SOP-8 and SOP-8-P Packages Applications Desktop computers TAB is GND VOUT FB GND BS VIN 1 • Pin Configuration 5 Current Limit Protection 4 • 3 Output Voltage Accuracy : ±2% 2 • TO-252-5 (Top View) VIN 1 8 NC BS 2 7 NC FB 3 6 GND 4 5 NC VOUT V IN BS FB VOUT 1 2 3 4 8 7 6 5 GND GND GND GND SO-8 (Top View) SOP-8-P (Top View) NC = No internal connection = Thermal Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 1 www.anpec.com.tw APL5332 Ordering and Marking Information Package Code U 5 : T O -2 5 2 -5 K : S O -8 K A : S O P -8 -P Tem p. Range C : 0 to 7 0 C H a n d lin g C ° ode TR : Tape & Reel L e a d F re e C o d e L : L e a d F re e D e v ic e B la n k : O rg in a l D e v ic e APL5332 L e a d F re e C o d e H a n d lin g C o d e Tem p. Range Package Code AP L5332 XXXXX A P L 5 3 3 2 K /K A : AP L5332 U : X X X X X - D a te C o d e X X X X X - D a te C o d e AP L5332 XXXXX Pin Function Description No. 1 2 3 4 5 PIN Name VIN BS GND FB VOUT I/O Description I I O I O Input supply voltage. Fixed output voltage selection by this pin. Ground pin for signal ground and power ground. Adjust output voltage by this pin Regulator output voltage. Block Diagram VI N FB Control Circuit VOUT BS Current Limit Thermal Control GND Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 2 www.anpec.com.tw APL5332 Absolute Maximum Ratings S ym bo l V IN V OUT PD P a ra m e te r R a tin g U n it V IN S u p p ly Vo lta g e , V IN to G N D -0 .2 ~ 5 .5 V B S , F B to G N D -0 .2 ~ V IN V V O U T O u tp u t Vo lta g e , V O U T to G N D -0 .2 ~ V IN V P o w e r D is s ip a tio n In te rn a lly L im ite d W TJ J u n c tio n Te m p e ra tu re 150 o T STG S to ra g e Te m p e ra tu re -6 5 ~ 1 5 0 o C 300 o C T SDR S o ld e rin g Te m p e ra tu re , 1 0 S e c o n d s V ESD M in im u m E S D R a tin g (H u m a n B o d y M o d e ) ±3 C kV Thermal Characteristics Symbol Parameter Value θJA Junction-to-Ambient Thermal Resistance in Free Air TO-252-5 SOP-8-P SOP-8 80 80 150 Unit o C/W Recommended Operating Conditions Symbol Parameter VIN VIN Supply Voltage IOUT VOUT Output Current (Note 1,2) TJ Junction Temperature Range Unit 2.4 ~ 3.5 V -1 ~ +2 A 0 ~ 125 o C Note 1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to GND. Note 2 : The max. IOUT varies with the TJ. Please refer to the typical characteristics. Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 3 www.anpec.com.tw APL5332 Electrical Characteristics Refer to the typical application circuit. These specifications apply over VIN=2.5~3.3V, and TJ= 0 to 125oC, unless otherwise specified. Typical values refer to TJ =25oC. P a ra m e te r S ym b o l APL5332 Te s t C o n d itio n s M in Typ M ax U n it O U T P U T V O LTA G E V REF R e fe re n c e Vo lta g e V OUT V O U T O u tp u t Vo lta g e FB=VO U T B S = V IN , F B = V IN 1 .2 2 5 B S = G N D , F B = V IN 1 .4 5 o A c c u ra c y V 0 .8 IO U T = 0 A , T J= 2 5 C o I O U T = -1 ~ + 2 A , T J = 0 ~ 1 2 5 C V -1 +1 -2 +2 % IO U T = 0 A ~ + 2 A V IN = 2 .5 V V IN = 3 .3 V L o a d R e g u la tio n 0 .5 1 I O U T = 0 ~ -1 A L in e R e g u la tio n % 0 .7 V IN = 2 .5 V o r 3 .3 V I O U T = 0 A , V IN = 2 .5 V ~ 3 .3 V 0 .0 5 0 .2 % P R O T E C T IO N S o u rc in g C u rre n t (V IN = 3 .3 V ) o T J= 2 5 C o I L IM C u rre n t L im it S in k in g C u rre n t T J= 2 5 C o (V IN = 2 .5 V o r 3 .3 V ) T J = 1 2 5 C S o u rc in g C u rre n t (V IN = 2 .5 V ) T SD T h e rm a l S h u td o w n T e m p e ra tu re T h e rm a l S h u td o w n H ys te re s is B S AN D FB T H R E SH O LD VO LT AG ES B S L o g ic H ig h T h re s h o ld Vo lta g e 2 .0 o T J= 1 2 5 C o T J= 2 5 C 1 .2 A 1 .7 1 .3 1 .7 o T J= 1 2 5 C 2 .0 A 1 .5 R is in g T J V B S R is in g 2 .3 1 .7 0 .6 B S H ys te re s is 150 o C 25 o C 1 .0 0 .8 B S In p u t B ia s C u rre n t V IN = 3 .3 V , B S = G N D F B L o g ic H ig h T h re s h o ld Vo lta g e V F B R is in g (V F B - V IN ) F B H ys te re s is F B In p u t B ia s C u rre n t V IN = 3 .3 V , F B = 0 .8 V Q u ie s c e n t V IN S u p p ly C u rre n t V IN P o w e r-O n -R e s e t T h re s h o ld Vo lta g e S o ft-S ta rt In te rva l IO U T = 0 A -0 .3 V mV 35 -0 .1 7 -0 .3 µA -0 .4 6 -0 .8 V mV 35 -0 .1 7 -0 .3 µA 4 8 14 mA 1 .4 2 .1 2 .4 V OTHER IQ V POR T SS 1 mS Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 4 www.anpec.com.tw APL5332 Typical Application Circuit V IN +3.3V or +2.5V U1 5 V OUT C1 47uF V OU T 4 FB C2 470uF 3 GND C3 1uF 2 BS 1 V IN BS A PL5332 B S = H, V OU T = 1.225V B S = L, V OU T = 1.45V Typical Application For Processor MCH Power Selection Schematic V IN +3.3V or +2.5V U1 V OUT C1 47uF FB GND BS V IN 5 V OU T 4 3 C2 470uF R1 850 2 1 Q1 A PM2300A R3 A PL5332 C3 1uF 3.02K R2 1.6K B S (Inv)= H, V OU T = 1.45V B S (Inv)= L, V OU T = 1.225V R4 +5V 10K BS(Inv ) Use External Resistors to Select the Desired Output Voltage Schematic Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 5 www.anpec.com.tw APL5332 Typical Operating Characteristics VREF Shutdown Threshold vs Junction Temperature 0.816 2.6 2.5 2.4 Reference Voltage, VREF (V) Power-On-Reset Threshold Voltage (V) Power-On-Reset Threshold Voltage vs Junction Temperature 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 100 125 -50 Junction Temperature (oC) 25 50 75 100 125 Sinking Current-Limit vs Junction Temperature 3.5 -0.5 3.0 -1.0 Current-Limit, ILIM (A) Current-Limit, ILIM (A) 0 Junction Temperature (oC) Sourcing Current-Limit vs Junction Temperature VIN = 3.3V 2.5 -25 2.0 VIN = 2.5V 1.5 1.0 -1.5 VIN = 2.5V or 3.3V -2.0 -2.5 -3.0 -50 -25 0 25 50 75 100 125 -50 0 25 50 75 100 125 o Junction Temperature ( C) Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 -25 6 www.anpec.com.tw APL5332 Typical Operating Characteristics Cont. FB Threshold Voltage vs Junction Temperature 1.1 -0.2 1.0 -0.3 0.9 FB Threshold Voltage (V) BS Pin Threshold Voltage (V) BS Pin Threshold Voltage vs Junction Temperature Rising 0.8 0.7 Falling 0.6 Rising -0.4 -0.5 Falling -0.6 -0.7 -0.8 0.5 -50 -25 0 25 50 75 -50 100 125 Junction Temperature (oC) -25 0 25 50 75 100 125 Junction Temperature (oC) Quiescent VIN Current vs Junction Temperature 10.0 Quiescent VIN Current (mA) 9.5 IOUT = 0A 9.0 8.5 VIN = 3.3V 8.0 7.5 7.0 VIN = 2.5V 6.5 6.0 5.5 5.0 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 7 www.anpec.com.tw APL5332 Functional Description General APL5332 is a source-sink linear regulator designed for motherboard front side bus. The device can supply loads from -1A to 2A in either fixed or adjustable voltage mode. APL5332 has a 0.8V reference, an error amplifier, two pass transistors, fixed voltage selection, an internal feedback resistor-divider, soft-start control and fault protections(current-limit and thermal shutdown). The output voltage is either 1.225V or 1. 45V selected by the BS pin when fixed voltage mode is active by setting FB=VIN. When the FB is connected with a feedback resistor-divider, the IC operates in adjustable voltage mode and the voltage of FB is regulated to 0.8V. In the mode, the input of BS pin is ignored. APL5332 is available in the SOP, SOP-8P, and TO-252-5 packages to meet different power dissipation applications. Current Limit The APL5332 monitors the sourcing or sinking currents and limits the maximum output current to prevent damages during overload or short-circuit conditions. Power-On-Reset and Soft-Start A Power-On-Reset circuit monitors input voltage of the VIN pin and prevents wrong logic controls. When the input voltage rises up more than the Power-OnReset threshold voltage, the device starts to output current. Therefore, a soft-start circuit which controls the reference voltage to rise up is required, limiting surge input currents. The typical soft-start interval is about 1mS. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of the APL5332. When the junction temperature exceeds +150oC, a thermal sensor turns off the Output Voltage Regulation The error amplifier working with the temperature-compensated 0.8V reference and the two pass transistors (high-side and low-side) regulates the output to the preset voltage. The error amplifier compares the reference with the feedback voltage and amplifies the difference to drive one of the pass transistors. The highside pass transistor provides current from VIN to VOUT and increases the output voltage when the feedback voltage is lower than the reference. The low-side pass both pass transistors, allowing the device to cool down. The regulator starts to regulate again after the junction temperature cools by 25oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed with a 25oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of APL5332. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125oC. transistor provides current from VOUT to GND and decreases the output voltage when the feedback voltage is higher than the reference. The two pass transistors are well controlled by the error amplifier and prevented shortthrough conditions. An internal output voltage sense pad is bonded to the VOUT pin for perfect load regulation in fixed voltage mode. Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 8 www.anpec.com.tw APL5332 Application Information Internal Parasitic Diode Do not apply a voltage to VOUT when the voltage applied at VIN is not present. The reason is the internal parasitic diodes from VOUT to VIN will conduct due to the forward-voltage applied at VOUT. 100 ESR (mΩ) 80 Stable Region 60 40 20 0 10 Output Voltage Selection The APL5332 allows operation in either fixed voltage or adjustable mode. Connecting FB to VIN selects fixed output voltage which is either 1.225V or 1.45V by setting the BS pin to be logic “High” or “Low”. The output voltage may also be adjusted by connecting a resistor-divider from VOUT to FB to GND (See the Typical Application Circuit). Selecting R2 in the 100Ω to 5kΩ range ignors the voltage offset caused by the internal pull-up current of FB. Calculate R1 with the following equation: R1 = R2 [(VOUT / VREF) - 1] The output capacitors are also used to reduce the slew rate of load current and help the APL5332 to minimize variations of the output voltage, improving transient response. For this purpose, the low-ESR capacitors are recommended. BS FB L H 1.225V 1.45V L Adjustable Adjustable Input Capacitor The VIN input capacitor is not required for stability but for supplying surge currents during large load transients, preventing the input rail from dropping and improving performance of APL5332. The parasitic inductors from the voltage sources or other bulk capacitors to the VIN pins will limit the slew rate of the surge currents during large load transients, resulting in voltage drop at VIN pin. An aluminum electrolytic capacitor (>47µF) is recommended for VIN pin, and It is not necessary to use low-ESR capacitors. Output Capacitor The APL5332 requires a proper output capacitor to maintain stability and improve transient response. The output capacitor selection is dependent upon the ESR (equivalent series resistance) and capacitance over temperature and current ranges. The following chart shows a stable region to select output capacitor for APL5332. This region above the curve indicates minimum required ESR and capacitance to maintain stability. However, the output capacitor should have an ESR less than1Ω. Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 1000 Ultra-low-ESR capacitors, such as ceramic chip capacitors, may promote unstable or under-damped transient response, but proper ceramic chip capacitors placed near loads can be used as decoupling capacitors. A low-ESR solid tantalum and aluminum electrolytic capacitor (ESR<1Ω) works extremely well and provides good transient response and stability over temperature. where VREF = 0.8V. The output voltage selection table is : H 100 Capacitance(µF) 9 www.anpec.com.tw APL5332 Application Information Layout and Thermal Consideration The input capacitors are normally placed near VIN for good performances. Ceramic decoupling capacitors for load must be placed as close to the load to reduce the parasitic inductors of traces. It is also recommended that the APL5332 and output capacitors are placed near the load for good load regulation and transient response. The negative pins of the input and output capacitors and the GND pin of the APL5332 are connected to analog ground plane of the load. See Figure 1. The SOP-8-P is a cost-effective package featuring a small size as a standard SOP-8 and a bottom thermal pad to minimize the thermal resistance of the package, being applicable to high current applications. The thermal pad of SOP-8-P or TO252-5 is soldered to the top ground pad which is connected to the internal or bottom ground plane by several vias. The printed circuit board (PCB) forms a heat sink and dissipates major heat into ambient air. 102 mil S O P -8-P 118 mil D ie Therm al pad Top ground pad Ambient Air Vias Internal ground plane Printed circuit board Figure 1 Figure 2 shows a recommended board layout using the SOP-8-P package. An area of 140mil*110mil on the top layer (250mil*250mil) is used as a thermal pad for APL5332 and is connected to the internal or bottom ground plane by vias. The vias shold have proper hole size to retain solder, and help heat conduction. More area of the internal or bottom plane reduces θJA and is better for dissipating power. The recommended area is without limit. Therefore the PCB and all components form a heat sink. Thermal resistance consists of two main elements, θ JC (junction-to-case thermal resistance) and θCA (caseto-ambient thermal resistance). θJC is specified from the IC junction to the bottom of the thermal pad directly below the die. θCA is the resistance from the bottom of thermal pad to the ambient air and it includes θCS (case-to-sink thermal resistance) and (sink- Internal or bottom Ground plane Top layer ground plane Pad to-ambient thermal resistance). The specified path for heat flow is the lowest resistance path and it dissipates 250m il major heat to the ambient air. Normally θCA is major reground plane reduces the resistance θCA . The relation- 8 7 6 5 1 2 3 4 110mil 250mil sistance in the path. Enlarging the internal or bottom ship between power dissipation and temperatures is PD = (TJ - TA) / θJA where, PD : power dissipation TJ : Junction Temperature TA : Ambient Temperature θ JA : Junction-to-Ambient Thermal Resistance Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 140m il Vias Soldering area for bottom pad Figure 2 10 www.anpec.com.tw APL5332 Application Information Figure 3 shows a board layout using the SOP-8-P package. The demoboard is made of FR-4 material and is a two-layer PCB. The board size and thickness are 65mm* 65mm and 1.6mm. The copper thickness of top and bottom layers is 2 oz. The partial layout around APL5332 is as the details above and shown in the figure 2. It uses 15mil vias to connect the top and bottom ground plane. The θJA of the APL5332 (SOP-8P) mounted on the demodoard is about 41.3oC/W in free air. Assuming the TA=25oC and the maximum TJ=150oC (typical thermal limit temperature), the maximum power dissipation is calculated as : PD(max) = (150 - 25) / 41.3 = 3.03W APL5332 Figure 3(b) Top layer If the TJ is designed to be below 125oC, the calculated power dissipation should be less than : PD = (125 - 25) / 41.3 = 2.42W APL5332 Figure 3(c) Bottom layer Figure 3(a) TopOver layer Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 11 www.anpec.com.tw APL5332 Packaging Information TO-252-5 H A J D M C B K L S Dim A B C D P S H J K L M P Millimeters Min. 6.40 5.20 6.80 2.20 Inches Max. 6.80 5.50 7.20 2.80 Min. 0.25 0.20 0.26 0.08 1.27 REF Max. 0.26 0.21 0.27 0.11 0.05 REF 0.50 2.20 0.45 0 0.90 5.40 0.80 2.40 0.55 0.15 1.50 5.80 Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 12 0.02 0.08 0.01 0 0.03 0.21 0.03 0.09 0.02 0.006 0.06 0.22 www.anpec.com.tw APL5332 Packaging Information E e1 0.015X45 SOP-8 pin ( Reference JEDEC Registration MS-012) H e2 D A1 A 1 L 0.004max. Dim M illimete rs Inches M in . M ax. M in. M ax. A 1.35 1.75 0.053 0.069 A1 D E 0.10 4.80 3.80 0.25 5.00 4.00 0.004 0.189 0.150 0.010 0.197 0.157 H L e1 e2 5.80 0.40 0.33 6.20 1.27 0.51 0.228 0.016 0.013 0.244 0.050 0.020 φ 1 Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 1.27BSC 0.50BSC 8° 8° 13 www.anpec.com.tw APL5332 Packaging Information E1 E 0.015X45 SOP-8-P pin ( Reference JEDEC Registration MS-012) H D1 e1 e2 D A1 A 1 L 0.004max. Dim A A1 D D1 E E1 H L e1 e2 M illimeter s Inc hes M in . M ax. M in . M ax. 1.3 5 0.1 0 4.8 0 1.7 5 0.2 5 5.0 0 0.0 53 0.0 04 0.1 89 0.0 69 0.0 10 0.1 97 3.0 0R EF 3.8 0 0.11 8REF 4.0 0 0.1 50 2.6 0R EF 5.8 0 0.4 0 0.3 3 φ 1 Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 0.1 57 0.1 02R EF 6.2 0 1.2 7 0.2 28 0.0 16 0.5 1 0.0 13 0.2 44 0.0 50 0.0 20 1.2 7BS C 0.5 0BS C 8° 8° 14 www.anpec.com.tw APL5332 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) temperature Reference JEDEC Standard J-STD-020A APRIL 1999 Peak temperature 183°C Pre-heat temperature Time Classification Reflow Profiles Convection or IR/ Convection Average ramp-up rate(183°C to Peak) 3°C/second max. 120 seconds max Preheat temperature 125 ± 25°C) 60 – 150 seconds Temperature maintained above 183°C Time within 5°C of actual peak temperature 10 –20 seconds Peak temperature range 220 +5/-0°C or 235 +5/-0°C Ramp-down rate 6 °C /second max. 6 minutes max. Time 25°C to peak temperature VPR 10 °C /second max. 60 seconds 215-219°C or 235 +5/-0°C 10 °C /second max. Package Reflow Conditions pkg. thickness ≥ 2.5mm and all bgas Convection 220 +5/-0 °C VPR 215-219 °C IR/Convection 220 +5/-0 °C pkg. thickness < 2.5mm and pkg. volume ≥ 350 mm³ Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 15 pkg. thickness < 2.5mm and pkg. volume < 350mm³ Convection 235 +5/-0 °C VPR 235 +5/-0 °C IR/Convection 235 +5/-0 °C www.anpec.com.tw APL5332 R e lia b ilit y te s t p r o g r a m Te s t ite m S O L D E R A B IL IT Y H O LT PCT TST ESD L a tc h -U p M e th o d M IL -S T D -8 8 3 D -2 0 0 3 M IL -S T D -8 8 3 D -1 0 0 5 .7 J E S D -2 2 - B , A 1 0 2 M IL -S T D -8 8 3 D -1 0 11 .9 M IL -S T D -8 8 3 D -3 0 1 5 .7 JESD 78 D e s c rip tio n 2 45 °C , 5 S E C 1 0 0 0 H rs B ia s @ 1 2 5 ° C 1 6 8 H rs , 1 0 0 % R H , 1 2 1 ° C -6 5 °C ~ 1 5 0 °C , 2 0 0 C y c le s V H B M > 2 K V, V M M > 2 0 0 V 1 0 m s , I tr > 1 0 0 m A Carrier Tape t D P Po E P1 Bo F W Ko Ao D1 T2 J C A B T1 Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 16 www.anpec.com.tw APL5332 Application TO-252 Application SOP- 8 A B C J 2 ± 0.5 T1 16.4 + 0.3 -0.2 330 ±3 100 ± 2 13 ± 0. 5 F D D1 Po 7.5 ± 0.1 1.5 +0.1 1.5± 0.25 A B 330 ± 1 62 +1.5 C 12.75+ 0.15 F D D1 5.5± 1 Application SOT-89 1.55 +0.1 1.55+ 0.25 T2 P E 2.5± 0.5 W 16+ 0.3 - 0.1 8 ± 0.1 1.75± 0.1 P1 Ao Bo Ko t 4.0 ± 0.1 2.0 ± 0.1 6.8 ± 0.1 10.4± 0.1 2.5± 0.1 0.3±0.05 J T1 T2 W P E 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 Po P1 Ao Bo Ko t 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013 P E 8 ± 0.1 1.75± 0.1 A B C J T1 T2 178 ±1 70 ± 2 13.5 ± 0.15 3 ± 0.15 14 ± 2 1.3 ± 0.3 W 12 + 0.3 12 - 0.1 F D D1 Po P1 Ao Bo Ko t 5.5 ± 0.05 1.5± 0.1 1.5± 0.1 4.0 ± 0.1 2.0 ± 0.1 4.8 ± 0.1 4.5± 0.1 1.80± 0.1 0.3±0.013 Cover Tape Dimensions Application TO- 252 SOP- 8 SOT- 89 Carrier Width 16 12 12 Cover Tape Width 13.3 9.3 9.3 Devices Per Reel 2500 2500 1000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 17 www.anpec.com.tw