MOTOROLA DSP56800FMD Preliminary technical data dsp56f826 16-bit digital signal processor Datasheet

DSP56F826/D
Rev. # 0, 3/2001
Semiconductor Products Sector
DSP56F826
Preliminary Technical Data
DSP56F826 16-bit Digital Signal Processor
•
Up to 64K × 16-bit words each of external
memory expansion for Program and Data
memory
Hardware DO and REP loops
•
One Serial Port Interface (SPI)
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
•
One additional SPI or two optional Serial
Communication Interfaces (SCI)
•
One Synchronous Serial Interface (SSI)
•
Up to 40 MIPS at 80MHz core frequency
•
DSP and MCU functionality in a unified,
C-efficient architecture
•
•
•
31.5K × 16-bit words Program Flash
•
One General Purpose Quad Timer
•
512 × 16-bit words Program RAM
•
JTAG/OnCE™ for debugging
•
2K × 16-bit words Data Flash
•
100-pin LQFP Package
•
4K × 16-bit words Data RAM
•
16 dedicated and 30 shared GPIO
•
2K × 16-bit words BootFLASH
•
One Time-of-Day module
EXTBOOT
RESET
IRQB
IRQA
VDD
6
3
IO
VDD
VSS
3
4
IO
VSS
Low Voltage Supervisor
JTAG/
OnCE
Port
VDDA
VSSA
4
Analog Reg
TOD
Timer
Program Controller
and
Hardware Looping Unit
Interrupt
Controller
4
Quad Timer
or
GPIO
6
SSI
or
GPIO
4
SCI0 & SCI1
or
SPI0
4
SPI1
or
GPIO
Dedicated
GPIO
Program Memory
32252 x 16 Flash
512 x 16 SRAM
PDB
Boot Flash
2048 x 16 Flash
XDB2
ApplicationSpecific
Memory &
Peripherals
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
CLKO
PLL
16-Bit
DSP56800
Core
XTAL
Clock Gen
.
EXTAL
CGDB
XAB1
XAB2
COP
RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
INTERRUPT
CONTROLS
16
IPBB
CONTROLS
16
IPBus Bridge
(IPBB)
DATA BUS [15:0]
16
Figure 1. DSP56F826 Block Diagram
© Motorola, Inc., 2001. All rights reserved.
Bit
Manipulation
Unit
PAB
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
Address
Generation
Unit
External
Bus
Interface
Unit
External
Address Bus
Switch
16
External
Data Bus
Switch
16
Bus
Control
A[00:15]
or
GPIO
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
Part 1 Overview
1.1 DSP56F826 Features
1.1.1
Digital Signal Processing Core
•
Efficient 16-bit DSP56800 Family DSP engine with dual Harvard architecture
•
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
•
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•
Two 36-bit accumulators, including extension bits
•
16-bit bidirectional barrel shifter
•
Parallel instruction set with unique DSP addressing modes
•
Hardware DO and REP loops
•
Three internal address buses and one external address bus
•
Four internal data buses and one external data bus
•
Instruction set supports both DSP and controller functions
•
Controller style addressing modes and instructions for compact code
•
Efficient C Compiler and local variable support
•
Software subroutine and interrupt stack with depth limited only by memory
•
JTAG/OnCE Debug Programming Interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
•
On-chip memory including a low cost, high volume flash solution
— 31.5K × 16-bit words of Program Flash
— 512 × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 4K × 16-bit words of Data RAM
— 2K × 16-bit words of BootFLASH
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64 K × 16-bit data memory
— As much as 64 K × 16-bit program memory
1.1.3
2
Peripheral Circuits for DSP56F826
•
One General Purpose Quad Timer totalling 7pins
•
One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)
•
One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling
4 pins
•
Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)
DSP56F826 Preliminary Technical Data
DSP56F826 Description
•
Sixteen (16) dedicated general purpose I/O (GPIO) pins
•
Thirty (30) shared general purpose I/O (GPIO) pins
•
Computer-Operating Properly (COP) Watchdog timer
•
Two external interrupt pins
•
External reset pin for hardware reset
•
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
•
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
•
Fabricated in high-density EMOS with 5V tolerant, TTL-compatible digital inputs
•
One Time of Day module
Energy Information
•
Dual power supply, 3.3V and 2.5V
•
Wait and Multiple Stop modes available
1.2 DSP56F826 Description
The DSP56F826 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications.
Because of its low cost, configuration flexibility, and compact program code, the DSP56F826 is wellsuited for many applications. The DSP56F826 includes many peripherals that are especially useful for
applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices,
remote metering, sonic alarms, POS terminals, feature phones.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.
The DSP56F826 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F826 also provides two
external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F826 DSP controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data
Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data
RAM. It also supports program execution from external memory.
The DSP56F826 incorporates a total of 2K words of BootFLASH for easy customer-inclusion of fieldprogrammable software routines that can be used to program the main Program and Data Flash memory
areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of
256 words. The BootFLASH memory can also be either bulk- or page-erased.
This DSP controller also provides a full set of standard programmable peripherals including one
Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI
or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and quad timer can be
used as General Purpose Input/Outputs (GPIOs) if a timer function is not required.
DSP56F826 Preliminary Technical Data
3
1.3 Best in Class Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete,
scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the
DSP56F826. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/.
Table 1. DSP56F826 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
Detailed description of the DSP56800 family architecture,
and 16-bit DSP core processor and the instruction set
DSP56800FM/D
DSP56824/F826/F827
User’s Manual
Detailed description of memory, peripherals, and interfaces
of the DSP56824, DSP56F826, DSP56F827
TBD
DSP56F826
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F826/D
DSP56F826
Product Brief
Summary description and block diagram of the DSP56F826
core, memory, peripherals and interfaces
DSP56F826PB/D
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when
low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
1.
4
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
DSP56F826 Preliminary Technical Data
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F826 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 describes the signal or signals present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Power (VDD , VDDIO or VDDA)
(3,4,1)
Ground (VSS , VSSIO or VSSA )
(3,4,1)
PLL and Clock
3
Address Bus1
16
Data Bus
16
Bus Control
4
Interrupt and Program Control
5
Dedicated General Purpose Input/Output
16
Synchronous Serial Interface (SSI) Port
6
Serial Peripheral Interface (SPI) Port1
4
Serial Communications Interface (SCI) Ports
4
Quad Timer Module Ports
4
JTAG/On-Chip Emulation (OnCE)
6
1.
Number of Pins
Alternately, GPIO pins
DSP56F826 Preliminary Technical Data
5
DSP56F826
VDD
VSS
VDDIO
VSSIO
3
3
2.5V Power Port
Ground Port
4
4
3.3V Power Port
Ground Port
Analog Power Port (3.3V)
Ground Port
VDDA
VSSA
EXTAL(CLOCKIN)
Dedicated
GPIO
SRCK (GPIOC2)
STD (GPIOC3)
STFS (GPIOC4)
STCK (GPIOC5)
16
GPIOA0–A7)
D0–D15
GPIOD0–7
SRFS (GPIOC1)
SSI Port or
GPIO
CLKO
A0-A15(GPIO/E0–E7,
GPIOB0–7
SRD (GPIOC0)
PLL and Clock
XTAL
8
8
16
External
Address
Bus or GPIO
External Data Bus
SCLK (GPIOF4)
SPI1 Port or
GPIO
MOSI (GPIOF5)
MISO (GPIOF6)
SS (GPIOF7)
PS
DS
External Bus Control
RD
WR
TA0 (GPIOF0)
TA1 (GPIOF1)
Quad Timer A
SCI0 Port or
SPI0 Port
TXD0 (SCLK0)
SCI1 Port or
SPI0 Port
TXD1 (MISO0)
RXD0 (MOSI0)
RXD1 (SS0)
TA2 (GPIOF2)
TA3 (GPIOF3)
Interrupt/
Program
Control
TCK
IRQA
IRQB
RESET
EXTBOOT
TMS
TDI
TDO
JTAG/OnCE
Port
TRST
DE
Figure 2. DSP56F826 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
6
DSP56F826 Preliminary Technical Data
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
A0
24
Output
A1
23
Output
A2
22
Output
A3
21
Output
A4
18
Output
A5
17
Output
A6
16
Output
A7
15
Output
GPIOE0–
GPIOE7
Type
Description
Address Bus—A0–A7 specify the address for external program or data
memory accesses.
Input/Output
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
A8
14
Output
A9
13
Output
A10
12
Output
A11
11
Output
A12
10
Output
A13
9
Output
A14
8
Output
A15
7
Output
GPIOA0–
GPIOA7
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
Input/Output
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
DSP56F826 Preliminary Technical Data
7
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
8
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
CLKO
65
Output
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKO Select Register (SLKOSR), the user can select between
outputting a version of the signal applied to XTAL and a version of the DSP
master clock at the output of the PLL. The clock frequency on this pin can be
disabled by programming the CLKO Select Register (CLKOSR).
D0
34
Input/Output
Data Bus— D0–D15 specify the data for external program or data memory
accesses. D0–D15 are tri-stated when the external bus is inactive.
D1
35
D2
36
D3
37
D4
38
D5
39
D6
40
D7
41
D8
42
D9
43
D10
44
D11
46
D12
47
D13
48
D14
49
D15
50
DE
98
Output
Debug Event—DE provides a low pulse on recognized debug events.
DS
28
Output
Data Memory Select—DS is asserted low for external data memory access.
Type
Description
DSP56F826 Preliminary Technical Data
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
EXTAL
61
CLOCKIN
Type
Description
Input
External Crystal Oscillator Input—This input can be connected to an
4MHz external crystal. If a 4MHz or less external clock source is used,
EXTAL can be used as the input and XTAL must not be connected. For
more information, please refer to Section 3.5.2.
Input
External Clock Input—This input can be connected to an external 8MHz
clock. For more information, please refer to Section 3.5.
The input clock can be selected to provide the clock directly to the DSP core.
This input clock can also be selected as input clock for the on-chip PLL.
EXTBOOT
25
Input
External Boot—This input is tied to VDD to force device to boot from offchip memory. Otherwise, it is tied to ground.
GPIOB0
66
Input or Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can
be individually programmed as input or output pins.
GPIOB1
67
GPIOB2
68
GPIOB3
69
GPIOB4
70
GPIOB5
71
GPIOB6
72
GPIOB7
73
GPIOD0
74
GPIOD1
75
GPIOD2
76
GPIOD3
77
GPIOD4
78
GPIOD5
79
GPIOD6
82
GPIOD7
83
After reset, the default state is GPIO input.
Input or Output
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
DSP56F826 Preliminary Technical Data
9
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
IRQA
32
Type
Input
Description
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge- triggered. If
level-sensitive triggering is selected, an external pull up resistor is required
for wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
IRQB
33
Input
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If levelsensitive triggering is selected, an external pull up resistor is required for
wired-OR operation.
MISO
86
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if the slave device is not
selected.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
GPIOF6
After reset, the default state is MISO.
MOSI
85
GPIOF5
10
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device
uses to latch the data.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
PS
29
Output
Program Memory Select—PS is asserted low for external program memory
access.
RD
26
Output
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the DSP data bus. When RD is deasserted high, the external
data is latched inside the DSP. When RD is asserted, it qualifies the A0–A15,
PS, and DS pins. RD can be connected directly to the OE pin of a Static
RAM or ROM.
DSP56F826 Preliminary Technical Data
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
RESET
45
Type
Input
Description
Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted,
the initial chip operating mode is latched from the external boot pin. The
internal reset signal will be deasserted synchronous with the internal clocks,
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware DSP reset is required and it is necessary not to reset the OnCE/
JTAG module. In this case, assert RESET, but do not assert TRST.
RXD0
96
MOSI0
Input
Receive Data (RXD0)— receive data input
Input/
Output
SPI Master Out/Slave In—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch
the data.
After reset, the default state is SCI input.
RXD1
92
SS0
Input
Receive Data (RXD1)— receive data input
Input
SPI Slave Select—In maste mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
SCLK
84
GPIOF4
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
SRCK
GPIOC2
53
Input/Output
SSI Serial Receive Clock (STCK)—This bidirectional pin provides the
serial bit rate clock for the Receive section of the SSI. The clock signal can
be continuous or gated and can be used by both the transmitter and receiver
in synchronous mode.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
DSP56F826 Preliminary Technical Data
11
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
SRD
51
GPIOC0
Type
Description
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers
the data to the SSI Receive Shift Receiver.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
SRFS
52
GPIOC1
Input/ Output
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by
the receive section of the SSI as frame sync I/O or flag I/O. The STFS can be
used only by the receiver. It is used to synchronize data transfer and can be
an input or an output.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
SS
87
GPIOF7
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
STCK
56
GPIOC5
Input/ Output
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the
serial bit rate clock for the transmit section of the SSI. The clock signal can
be continuous or gated. It can be used by both the transmitter and receiver in
synchronous mode.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
STD
GPIOC3
54
Output
SSI Transmit Data (STD)—This output pin transmits serial data from the
SSI Transmitter Shift Register.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
12
DSP56F826 Preliminary Technical Data
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
STFS
55
GPIOC4
Type
Description
Input
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used
by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS
can be used by both the transmitter and receiver in synchronous mode. It is
used to synchronize data transfer and can be an input or output pin.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
TA0-3
91
Input/Output
TA0–3—Timer F Channels 0, 1, 2, and 3
Input/Output
89
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
88
After reset, the default state is Quad Timer.
TCS
99
TCS—This pin is reserved for factory use. It must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
TCK
100
Input
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
TDI
2
Input
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an onchip pull-up resistor.
TDO
3
Output
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
TMS
1
Input
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
TRST
4
Input
Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset, TRST should
be asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST.
90
GPIOF0GPIOF3
DSP56F826 Preliminary Technical Data
13
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
TXD0
97
SCLK0
Type
Description
Output
Transmit Data (TXD0)—transmit data output
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
TXD1
93
MISO0
Output
Transmit Data (TXD1)—transmit data output
Input/Output
SPI Master In/Slave Out—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if hte slave device is not selected.
After reset, the default state is SCI output.
14
VDD
20
VDD
Power—These pins provide power to the internal structures of the chip, and
are generally connected to a 2.5V supply.
VDD
64
VDD
VDD
94
VDD
VDDA
59
VDDA
Analog Power—This pin supplies an analog power source (generally 2.5V).
VDDIO
5
VDDIO
Power—These pins provide power to the I/O structures of the chip, and are
generally connected to a 3.3V supply.
VDDIO
30
VDDIO
VDDIO
57
VDDIO
VDDIO
80
VDDIO
VSS
19
VSS
VSS
63
VSS
VSS
95
VSS
VSSA
60
VSSA
Analog Ground—This pin supplies an analog ground.
VSSIO
6
VSSIO
GND In/Out—These pins provide grounding for the I/O ring on the chip.
All should be attached to VSS.
VSSIO
31
VSSIO
VSSIO
58
VSSIO
VSSIO
81
VSSIO
GND—These pins provide grounding for the internal structures of the chip.
All should be attached to VSS.
DSP56F826 Preliminary Technical Data
Introduction
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1.
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2.
TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
WR
27
Output
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the DSP puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connected directly to the WE pin of a Static RAM.
XTAL
62
Output
Crystal Oscillator Output—This output connects the internal crystal
oscillator output to an external crystal. If an external clock source over
4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.5.2.
Type
Description
DSP56F826 Preliminary Technical Data
15
Part 3 Specifications
3.1 General Characteristics
The DSP56F826 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term 5-volt tolerant refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either or VDD or VSS).
Table 4. Absolute Maximum Ratings (VSS = 0 V)
Characteristic
Symbol
Min
Max
Unit
VDD
VSS – 0.3
3.0
V
VDDIO
VSS – 0.3
4.0
V
VIN
VSS – 0.3
VDDIO + 0.3
V
Current drain per pin excluding VDD, VSS
I
—
10
mA
Junction temperature
TJ
—
150
°C
TSTG
–55
150
°C
Supply voltage, core
Supply voltage, IO and analog
All other input voltages
Storage temperature range
16
DSP56F826 Preliminary Technical Data
DC Electrical Characteristics
Table 5. Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
VDD
2.25
2.75
V
Supply Voltage, IO and analog
VDDIO,VDDA
3.0
3.6
V
Ambient operating temperature
TA
–40
85
°C
Flash program/erase temperature
TF
0
85
°C
Supply voltage, core
Table 6. Thermal Characteristics1
100-pin LQFP
Characteristic
Symbol
Value
Unit
Thermal resistance junction-to-ambient
(estimated)
θJA
39.7
°C/W
I/O pin power dissipation
PI/O
User Determined
W
Power dissipation
PD
PD = (IDD x VDD) + PI/O
W
PDMAX
(TJ – TA) / θJA
°C
Maximum allowed PD
1.
See Section 5.1 for more detail.
3.2 DC Electrical Characteristics
Table 7. DC Electrical Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
VIHC
2.25
2.5
2.75
V
Input low voltage (XTAL/EXTAL)
VILC
-0.3
—
0.5
V
Input high voltage
VIH
2.0
—
5.5
V
Input low voltage
VIL
-0.3
—
0.8
V
Input current low (pullups disabled)
IIL
-1
—
1
µA
Input current high (pullups disabled)
IIH
-1
—
1
µA
IOZL
-10
—
10
µA
Output tri-state current low
DSP56F826 Preliminary Technical Data
17
Table 7. DC Electrical Characteristics (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Output tri-state current high
IOZH
-10
—
10
µA
Output High Voltage with IOH load
VOH
VDD – 0.7
—
—
V
Output Low Voltage with IOL load
VOL
—
—
0.4
V
Output High Current
IOH
-300
—
—
µA
Output Low Current
IOL
—
—
2
mA
Input capacitance
CIN
—
8
—
pF
Output capacitance
COUT
—
12
—
pF
VDD supply current
IDD
—
—
—
50
20
2
TBD
TBD
TBD
mA
mA
mA
VEI
—
2.7
TBD
V
Low Voltage Interrupt Recovery Hysteresis
VEIH
—
50
—
mV
Power on Reset4
POR
—
1.5
2.0
V
1
Run
Wait2
Stop
Low Voltage Interrupt3
1. Run (operating) IDD measured using external square external square clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled.
PLL set to 80MHz out.
2. Wait IDD measured using external square wave clock source (fosc = 8MHz); all inpuyts 0.2V from rail; no DC loads;
less than 50 pF on all outputs. CL= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait
IDD; measured with PLL and LVI enabled
3. When VDD drops below VEI max value, an interrupt is generated.
4. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power
is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the
ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached,
at which time it self regulates.
18
DSP56F826 Preliminary Technical Data
AC Electrical Characteristics
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in Section 3.2. In Figure 3 the levels of VIH and
VIL for an input signal are shown.
Pulse Width
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3. Input Signal Measurement References
Figure 4 shows the definitions of the following signal states:
•
Active state, when a bus or signal is driven, and enters a low impedance state.
•
Tri-stated, when a bus or signal is placed in a high impedance state.
•
Data Valid state, when a signal level has reached V OL or VOH.
•
Data Invalid state, when a signal level is in transition between VOL and VOH.
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4. Signal States
DSP56F826 Preliminary Technical Data
19
3.4 Flash Memory Characteristics
Table 8. Flash Memory Truth Table
Mode
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
1.
2.
3.
4.
5.
6.
7.
8.
X address enable, all rows are disabled when XE = 0
Y address enable, YMUX is disabled when YE = 0
Sense amplifier enable
Output enable, tri-state flash data out bus when OE = 0
Defines program cycle
Defines erase cycle
Defines mass erase cycle, erase whole block
Defines non-volatile store cycle
Table 9. IFREN Truth Table
20
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both block
Erase main memory block
DSP56F826 Preliminary Technical Data
Flash Memory Characteristics
Table 10. Timing Symbols
Characteristic
Symbol
See Figure(s)
X address access time
Txa
-
Y address access time
Tya
-
OE access time
Toa
-
PROG/ERASE to NVSTR set up time
Tnvs*
Figure 5, Figure 6, Figure 7
NVSTR hold time
Tnvh*
Figure 5, Figure 6
NVSTR hold time(mass erase)
Tnvh1*
Figure 7
NVSTR to program set up time
Tpgs*
Figure 5
Program hold time
Tpgh
Figure 5
Address/data set up time
Tads
Figure 5
Address/data hold time
Tadh
Figure 5
Recovery time
Trcv*
Figure 5, Figure 6, Figure 7
Cumulative program HV period
Thv
Figure 5
Program time
Tprog*
Figure 5
Erase time
Terase*
Figure 6
Mass erase time
Tme*
Figure 7
* The Flash interface unit provides registers for the control of these parameters.
DSP56F826 Preliminary Technical Data
21
Table 11. Flash Timing Parameters
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Program time1
Tprog
20
—
—
us
Erase time2
Terase
20
—
—
ms
Mass erase time3
Tme
100
—
—
ms
Endurance4
ECYC
10,000
—
—
cycles
Data Retention
DRET
10
—
—
years
The following parameters should only be used in the Manual Word Programming mode.
PROG/ERASE to NVSTR set up time
Tnvs
—
5
—
us
NVSTR hold time
Tnvh
—
5
—
us
NVSTR hold time(mass erase)
Tnvh1
—
100
—
us
NVSTR to program set up time
Tpgs
—
10
—
us
Recovery time
Trcv
—
1
—
us
Cumulative program HV period5
Thv
—
3
—
ms
1. Program specification guaranteed from TA = 0° C to 85° C.
2. Erase specification guaranteed from TA = 0° C to 85° C.
3. Mass erase specification guaranteed from TA = 0° C to 85° C.
4. One cycle is equal to an erase, program, and read.
5. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.
22
DSP56F826 Preliminary Technical Data
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
Tnvs
Tprog
Tpgh
NVSTR
Tpgs
Tnvh
Trcv
Thv
Figure 5. Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
Tnvs
NVSTR
Tnvh
Terase
Trcv
Figure 6. Flash Erase Cycle
DSP56F826 Preliminary Technical Data
23
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
Tnvs
NVSTR
Tnvh1
Tme
Trcv
Figure 7. Flash Mass Erase Cycle
3.5 External Clock Operation
The DSP56F826 system clock can be derived from a crystal or an external system clock signal. To generate
a reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 13. In Figure 8 a typical crystal oscillator circuit is shown.
Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The crystal
and associated components should be mounted as close as possible to the EXTAL and XTAL pins to
minimize output distortion and start-up stabilization time.
24
DSP56F826 Preliminary Technical Data
External Clock Operation
Crystal Frequency = 4MHz
EXTAL XTAL
Rz
Sample External Crystal
Parameters:
Rz = 20 MW
Figure 8. External Crystal Oscillator Circuit
3.5.2
External Clock Source
The recommended method of connecting an external clock is given in Figure 9. The external clock source
is connected to XTAL and the EXTAL pin is grounded.
DSP56F826
XTAL
EXTAL
External
Clock
VSS
Figure 9. Connecting an External Clock Signal using XTAL
It is possible to instead drive EXTAL with an external clock, though this is not the recommended method.
If you elect to drive EXTAL with an external clock source the following conditions must be met:
1. XTAL must be completely un-loaded,
2. the maximum frequency of the applied clock must be less than 6MHz.
Figure 10 illustrates how to connect an external clock circuit with a external clock source using EXTAL as
the input.
DSP56F826
XTAL
EXTAL
External
No
Connection Clock ( < 6MHz)
Figure 10. Connecting an External Clock Signal using EXTAL
DSP56F826 Preliminary Technical Data
25
Table 12. External Clock Operation Timing Requirements
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
fosc
0
—
80
MHz
Clock Pulse Width2, 5
tPW
6.25
—
—
ns
External clock input rise time3, 5
trise
—
—
3
ns
External clock input fall time4, 5
tfall
—
—
3
ns
1.
2.
3.
4.
5.
See Figure 9 for details on using the recommended connection of an external clock driver.
The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
Parameters shown are guaranteed by design.
VIH
External
Clock
90%
50%
10%
tPW
90%
50%
10%
tPW
tfall
VIL
trise
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 11. External Clock Timing
Table 13. PLL Timing
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
fosc
2
4
6
MHz
PLL output frequency
fop
40
—
80
MHz
PLL stabilization time 2
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation
26
DSP56F826 Preliminary Technical Data
External Bus Asynchronous Timing
3.6 External Bus Asynchronous Timing
Table 14. External Bus Asynchronous Timing1, 2
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
tAWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
tWRD
—
T + 4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
—
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
6.4
(T*WS) + 6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
tRDA
0
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
Input Data Hold to RD Deasserted
tDRD
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
—
18.7
(T*WS) + 18.7
Address Valid to RD Asserted
tARDA
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
ns
ns
0
—
ns
19
(T*WS) + 19
—
—
ns
ns
—
—
1
(T*WS) + 1
ns
ns
-4.4
—
ns
—
—
2.4
(T*WS) + 2.4
ns
ns
WR Deasserted to RD Asserted
tWRRD
6.8
—
ns
RD Deasserted to RD Asserted
tRDRD
0
—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
—
ns
RD Deasserted to WR Asserted
tRDWR
12.8
—
ns
DSP56F826 Preliminary Technical Data
27
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
tARDD
tRDA
tARDA
RD
tRDRD
tRD
tAWR
tWRWR
tWR
tWRRD
tRDWR
WR
tRDD
tAD
tWRD
tDRD
tDOS
D0–D15
tDOH
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 12. External Bus Asynchronous Timing
28
DSP56F826 Preliminary Technical Data
Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 15. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See
Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
21
ns
Figure 13
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Figure 13
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
Figure 14
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
—
15T
ns
Figure 15
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
—
16T
ns
Figure 15
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
—
13T
ns
Figure 16
IRQA Width Assertion to Recover from Stop State4
tIW
—
2T
ns
Figure 17
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 13
Figure 17
—
—
275,000T
12T
ns
ns
Figure 18
—
—
275,000T
12T
ns
ns
Figure 18
tII
—
—
275,000T
12T
ns
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5 ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two
cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the
Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
DSP56F826 Preliminary Technical Data
29
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
PS, DS,
RD, WR
First Fetch
Figure 13. Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 14. External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 15. External Level-Sensitive Interrupt Timing
30
DSP56F826 Preliminary Technical Data
Reset, Stop, Wait, Mode Select, and Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 16. Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 17. Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 18. Recovery from Stop State Using IRQA Interrupt Service
DSP56F826 Preliminary Technical Data
31
3.8 Serial Peripheral Interface (SPI) Timing
Table 16. SPI Timing1
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Cycle time
Master
Slave
Min
Max
Unit
50
50
—
—
ns
ns
—
25
—
—
ns
ns
—
100
—
—
ns
ns
17.6
25
—
—
24.1
25
—
—
ns
ns
20
0
—
—
ns
ns
0
2
—
—
ns
ns
4.8
15
ns
3.7
15.2
ns
—
—
4.5
20.4
ns
ns
0
0
—
—
ns
ns
—
—
11.5
10.0
ns
ns
—
—
9.7
9.0
ns
ns
tC
Enable lead time
Master
Slave
tELD
Enable lag time
Master
Slave
tELG
Clock (SCLK) high time
Master
Slave
tCH
Clock (SCLK) low time
Master
Slave
tCL
Data setup time required for inputs
Master
Slave
tDS
Data hold time required for inputs
Master
Slave
tDH
Access time (time to data active from high-impedance state)
Slave
tA
Disable time (hold time to high-impedance state)
Slave
tD
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Data invalid
Master
Slave
tDI
Rise time
Master
Slave
tR
Fall time
Master
Slave
tF
See Figure
Figures 19,
20, 21, 22
Figure 22
Figure 22
ns
ns
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
Figure 22
Figure 22
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
Figures 19,
20, 21, 22
1.Parameters listed are guaranteed by design.
32
DSP56F826 Preliminary Technical Data
Serial Peripheral Interface (SPI) Timing
SS
SS is held High on master
(Input)
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
LSB in
tDI
MOSI
(Output)
tDV
Master MSB out
Bits 14–1
tDI(ref)
Master LSB out
tR
tF
Figure 19. SPI Master Timing (CPHA = 0)
SS
SS is held High on master
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tDH
tR
MISO
(Input)
MSB in
tDI
tDV(ref)
MOSI
(Output)
Master MSB out
Bits 14–1
LSB in
tDV
Bits 14– 1
tF
Master LSB out
tR
Figure 20. SPI Master Timing (CPHA = 1)
DSP56F826 Preliminary Technical Data
33
SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tF
tR
tD
Bits 14–1
tDS
Slave LSB out
tDV
MOSI
(Input)
MSB in
tDI
tDI
tDH
Bits 14–1
LSB in
Figure 21. SPI Slave Timing (CPHA = 0)
SS
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELD
SCLK (CPOL = 1)
(Input)
tDV
tELG
tCL
tCH
tR
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
tDH
MOSI
(Input)
tD
tF
tA
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 22. SPI Slave Timing (CPHA = 1)
34
DSP56F826 Preliminary Technical Data
Quad Timer Timing
3.9 Quad Timer Timing
Table 17. Timer Timing1, 2
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Max
Unit
PIN
4T+6
—
ns
Timer input high/low period
PINHL
2T+3
—
ns
Timer output period
POUT
2T-3
—
ns
POUTHL
1T-3
—
ns
Timer input period
Timer output high/low period
1.
2.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.
Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 23. Quad Timer Timing
3.10 Serial Communication Interface (SCI) Timing
Table 18. SCI Timing4
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Max
Unit
BR
—
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
Baud Rate1
1.
2.
3.
4.
fMAX is the frequency of operation of the system clock in MHz.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
Parameters listed are guaranteed by design.
DSP56F826 Preliminary Technical Data
35
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 24. RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 25. TXD Pulse Width
3.11 JTAG Timing
Table 19. JTAG Timing1, 3
Operating Conditions: VSSIO=VSS = VSSA = 0 V, VDDIO=3.0 to 3.6V, VDD = VDDA = 2.25–2.75 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
fOP
DC
10
MHz
TCK cycle time
tCY
100
—
ns
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data setup time
tDS
0.4
—
ns
TMS, TDI data hold time
tDH
1.2
—
ns
TCK low to TDO data valid
tDV
—
26.6
ns
TCK low to TDO tri-state
tTS
—
23.5
ns
tTRST
50
—
ns
tDE
4T
—
ns
TRST assertion time
DE assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5 ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
36
DSP56F826 Preliminary Technical Data
JTAG Timing
tCY
tPW
tPW
VM
VM
VIH
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 27. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 28. TRST Timing Diagram
DE
tDE
Figure 29. OnCE—Debug Event
DSP56F826 Preliminary Technical Data
37
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F826
TCK
TCS
DE
TXD0
RXD0
VSS
VDD
TXD1
RXD1
TA0
TA1
TA2
TA3
SS
MISO
MOSI
SCLK
MPIOD7
MPIOD6
VSSIO
VDDIO
GPIOD5
GPIOD4
GPIOD3
GPIOD2
This section contains package and pin-out information for the 100-pin LQFP configuration of the
DSP56F826.
GPIOD1
GPIOD0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
CLKO
VDD
VSS
XTAL
EXTAL
VSSA
VDDA
VSSIO
VDDIO
STCK
STFS
STD
SRCK
SRFS
SRD
PIN 76
ORIENTATION
MARK
PIN 1
Motorola
DSP56F826
PIN 51
PIN 26
RD
WR
DS
PS
VDDIO
VSSIO
IREQA
IREQB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
RESET
D11
D12
D13
D14
D15
TMS
TDI
TDO
TRST
VDDIO
VSSIO
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
VSS
VDD
A3
A2
A1
A0
EXTBOOT
Figure 30. Top View, DSP56F826 100-pin LQFP Package
38
DSP56F826 Preliminary Technical Data
Package and Pin-Out Information DSP56F826
Table 20. DSP56F826 Pin Identification by Pin Number
Pin No.
Signal
Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
TMS
26
RD
51
SRD
76
GPIOD2
2
TDI
27
WR
52
SRFS
77
GPIOD3
3
TDO
28
DS
53
SRCK
78
GPIOD4
4
TRST
29
PS
54
STD
79
GPIOD5
5
VDDIO
30
VDDIO
55
STFS
80
VDDIO
6
VSSIO
31
VSSIO
56
STCK
81
VSSIO
7
A15
32
IRQA
57
VDDIO
82
GPIOD6
8
A14
33
IRQB
58
VSSIO
83
GPIOD7
9
A13
34
D0
59
VDDA
84
SCLK
10
A12
35
D1
60
VSSA
85
MOSI
11
A11
36
D2
61
EXTAL
86
MISO
12
A10
37
D3
62
XTAL
87
SS
13
A9
38
D4
63
VSS
88
TA3
14
A8
39
D5
64
VDD
89
TA2
15
A7
40
D6
65
CLKO
90
TA1
16
A6
41
D7
66
GPIOB0
91
TA0
17
A5
42
D8
67
GPIOB1
92
RXD1
18
A4
43
D9
68
GPIOB2
93
TXD1
19
VSS
44
D10
69
GPIOB3
94
VDD
20
VDD
45
RESET
70
GPIOB4
95
VSS
21
A3
46
D11
71
GPIOB5
96
RXD0
22
A2
47
D12
72
GPIOB6
97
TXD0
23
A1
48
D13
73
GPIOB7
98
DE
24
A0
49
D14
74
GPIOD0
99
TCS
25
EXTBOOT
50
D15
75
GPIOD1
100
TCK
DSP56F826 Preliminary Technical Data
39
S
0.15(0.006)
AC T-U
S
Z
S
S
-T-
0.15(0.006)
0.15(0.006) S
AC Z
B
-Z-
S
V
AC Z
S
S
T-U
T-U
S
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
-UA
9
0.15(0.006)
S
AB T-U
S
AE
Z
MILLIMETERS
DIM MIN MAX
A 13.950 14.050
B 13.950 14.050
C 1.400 1.600
D 0.170 0.270
E 1.350 1.450
F 0.170 0.230
G
0.500 BSC
H 0.050 0.150
J
0.090 0.200
K 0.500 0.700
M
12° REF
N 0.090 0.160
Q
1°
5°
R 0.150 0.250
S 15.950 16.050
V 15.950 16.050
W
0.200 REF
X
1.000 REF
S
AD
-AB-AC96X
G
SEATING
PLANE
(24X PER SIDE)
AE
0.100(0.004) AC
M°
C
R
0.25 (0.010)
E
GAUGE PLANE
D
F
J
N
H
INCHES
MIN MAX
0.549 0.553
0.549 0.553
0.055 0.063
0.007 0.011
0.053 0.057
0.007 0.009
0.020 BSC
0.002 0.006
0.004 0.008
0.020 0.028
12° REF
0.004 0.006
1°
5°
0.006 0.010
0.628 0.632
0.628 0.632
0.008 REF
0.039 REF
Q°
W
K
X
0.20(0.008) M AC T-U
S
Z
S
SECTION AE-AE
DETAIL AD
CASE 842F-01
Figure 31. 100-pin LQPF Mechanical Information
40
DSP56F826 Preliminary Technical Data
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
TJ = T A + ( P D × R θJA )
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
RθJA = RθJC + R θCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
DSP56F826 Preliminary Technical Data
41
Electrical Design Considerations
•
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package
case determined by a thermocouple.
The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition
on page 41. From a practical standpoint, that value is also suitable for determining the junction temperature
from a case thermocouple reading in forced convection environments. In natural convection, using the
junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the
case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal
metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives
a better estimate of the junction temperature in natural convection when using the surface temperature of
the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level
(e.g., either VSS or VDD).
Use the following list of considerations to assure correct DSP operation:
•
Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from
the board ground to each VSS (GND) pin.
•
The minimum bypass requirement is to place six 0.01–0.1 µF capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the eight VDD/VSS pairs, including VDDA/VSSA.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS (GND) pins are less than 0.5 inch per capacitor lead.
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS.
•
Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a highgrade capacitor such as a tantalum capacitor.
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
DSP56F826 Preliminary Technical Data
42
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VDD and VSS circuits.
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
•
Take special care to minimize noise levels on the VREF, V DDA and VSSA pins.
•
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pullup device.
•
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 21 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 21. DSP56F803 Ordering Information
Part
DSP56F826
43
Supply
Voltage
3.0–3.6 V
2.25-2.75 V
Package Type
Plastic Quad Flat Pack (LQFP)
Pin
Count
Frequency
(MHz)
Order Number
100
80
DSP56F803BU80
DSP56F826 Preliminary Technical Data
OnCE™ are trademarks of Motorola, Inc.
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
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specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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