BR24A01AFJ-WM
Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
No.09001ECT02
BR24A□□-WM series
●Description
BR24A□□-WM series is a serial EEPROM of I2C BUS interface method.
●Features
2
1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 2.5V~5.5V single power source action most suitable for battery use
4) Page write mode useful for initial value write at factory shipment
5) Highly reliable connection by Au pad and Au wire
6) Auto erase and auto end function at data rewrite
7) Low current consumption
*1
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) SOP8/SOP-J8/MSOP8 compact package *2
10) Data rewrite up to 100,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
*1 BR24A32-WM,BR24A64-WM : 1.5mA
*2 Refer to following list
●Page write
Number of Pages
Product
number
●BR24A series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
Bit format
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
8Byte
16Byte
32Byte
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
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© 2009 ROHM Co., Ltd. All rights reserved.
Power source Voltage
2.5～5.5V
2.5～5.5V
2.5～5.5V
2.5～5.5V
2.5～5.5V
2.5～5.5V
2.5～5.5V
1/17
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
MSOP8
●
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Absolute maximum ratings (Ta=25℃)
Parameter
Impressed voltage
symbol
VCC
Permissible dissipation
Limits
-0.3～+6.5
450 (SOP8) *1
450 (SOP-J8) *2
310 (MSOP8) *3
-65～+125
-40～+105
-0.3～VCC+1.0
Pd
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
-
Unit
V
mW
℃
℃
V
When using at Ta=25℃ or higher, 4.5mW(*1,*2) , 3.1mW(*3) to be reduced per 1℃
●Memory cell characteristics (VCC=2.5～5.5V)
Parameter
Number of data rewrite times
Data hold years *1
*1
Min.
100,000
40
Limits
Typ.
-
Max.
-
Unit
Test Condition
Times
Years
Ta=-40～105℃
Ta=25℃
○Shipment data all address FFh
*1 Not 100% TESTED
●Recommended operating conditions
Parameter
Power source voltage
Input voltage
Symbol
VCC
VIN
Limits
2.5～5.5
0～VCC
Unit
V
●Electrical characteristics (Unless otherwise specified, Ta=-40～+105℃, VCC=2.5～5.5V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
“HIGH” input voltage
VIH
0.7VCC
V
“LOW” input voltage
VIL
0.3 VCC
V
“LOW” output voltage 1
VOL
0.4
V
IOL=3.0mA (SDA)
Input leak current
ILI
-1
1
μA
VIN=0V～VCC
Output leak current
ILO
-1
1
μA
VOUT=0V～VCC, (SDA)
2.0 *1
VCC=5.5V,fSCL=400kHz, tWR=5ms,
ICC1
mA
Byte write, Page write
Current consumption
3.0 *2
at action
VCC=5.5V,fSCL=400kHz
ICC2
0.5
mA
Random read, current read, sequential read
VCC=5.5V, SDA・SCL=VCC
Standby current
ISB
2.0
μA
A0, A1, A2=GND, WP=GND
◎Radiation resistance design is not made.
*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
(Unless otherwise specified, Ta=-40～+105℃, VCC=2.5～5.5V)
FAST-MODE
STANDARD-MODE
2.5V≦VCC≦5.5V
2.5V≦VCC≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL frequency
fSCL
400
100
Data clock “HIGH“ time
tHIGH
0.6
4.0
Data clock “LOW“ time
tLOW
1.2
4.7
SDA, SCL rise time *1
tR
0.3
1.0
SDA, SCL fall time *1
tF
0.3
0.3
Start condition hold time
tHD:STA
0.6
4.0
Start condition setup time
tSU:STA
0.6
4.7
Input data hold time
tHD:DAT
0
0
Input data setup time
tSU:DAT
100
250
Output data delay time
tPD
0.1
0.9
0.2
3.5
Output data hold time
tDH
0.1
0.2
Stop condition setup time
tSU:STO
0.6
4.7
Bus release time before transfer start
tBUF
1.2
4.7
Internal write cycle time
tWR
5
5
Noise removal valid period (SDA, SCL terminal)
tI
0.1
0.1
WP hold time
tHD:WP
0
0
WP setup time
tSU:WP
0.1
0.1
WP valid time
tHIGH:WP
1.0
1.0
-
●Action timing characteristics
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1 Not 100% tested
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© 2009 ROHM Co., Ltd. All rights reserved.
2/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V～5.5V , 400kHz, namely, action is
made in FASTMODE. (Action is made also in STANDARD-MODE.)
●Sync data input / output timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
SDA
(入力)
(input)
tHD:STA
tSU:STO
SDA
tPD
tBUF
tDH
SDA
START BIT
(output)
(出力)
STOP BIT
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
SCL
SCL
DATA(1)
SDA
SDA
D0
D1
D0
ACK
ACK
ｔWR
ｔWR
Write data
(n-th address)
DATA(n)
ACK
Stop condition
Stop condition
ストップコンディション
WP
Start condition
tSU：WP
Fig.1-(c) Write cycle timing
ｔHD：WP
Fig.1-(d) WP timing at write execution
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancel
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© 2009 ROHM Co., Ltd. All rights reserved.
3/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Block diagram
*2
A0
1Kbit~64Kbit EEPROM array
1
8
Vcc
7
WP
6
SCL
5
SDA
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
*2
*2
A1
2
A2
3
8bit
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
Data
register
Slave - word
address register
START
STOP
Control circuit
ACK
GND
High voltage
generating circuit
4
＊1
7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
Power source
voltage detection
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
＊
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
: BR24A04-WM
: BR24A08-WM
: BR24A16-WM
Fig.2 Block diagram
●Pin assignment and description
A0
1
A1
2
A2
3
GND
4
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
8
Vcc
7
WP
6
SCL
5
SDA
Function
Terminal
name
Input /
output
A0
Input
A1
Input
A2
Input
GND
-
Reference voltage of all input / output, 0V
SDA
Input /
output
Slave and word address, Serial data input serial data output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
Vcc
-
Connect the power source.
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Slave address setting
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© 2009 ROHM Co., Ltd. All rights reserved.
Not connected
Slave address setting
Slave address setting
Not connected
Slave address setting
4/17
Not used
Slave address setting
Slave address setting
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
6
5
5
4
4
SPEC
3
2
Ta=105℃
Ta=-40℃
Ta=25℃
1
1
0.8
Ta=105℃
Ta=-40℃
Ta=25℃
3
2
1
0
Ta=-40℃
0
1
2
3
4
5
6
IOL1[mA]
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
1
2
3
4
5
6
Vcc[V]
Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
1.2
2.5
SPEC
[BR24A01/02/04/08/16 series]
SPEC
1
1
2
fSCL=400kHz
DATA=AAh
0.8
0.6
0.4
0.6
0.4
Ta=105℃
Ta=25℃
Ta=-40℃
0.2
Ta=105℃
Ta=25℃
Ta=-40℃
0.2
1
0
1
2
3
4
5
Vcc[V]
Fig.6 Input leak current ILI (SCL,WP)
0
0
6
1
2
3
Vcc[V]
4
5
6
0
3
4
5
6
Vcc[V]
Fig.8 Current consumption at WRITE action ICC1
(fscl=400kHz)
Fig.7 Output leak current ILO(SDA)
0.6
3.5
0.5
SPEC
ICC2[mA]
2.5
2
1.5
1
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
[BR24A01/02/04/08/16 series]
2
fSCL=400kHz
DATA=AAh
0.4
Ta=105℃
0.3
Ta=25℃
0.2
0.1
0
1
2
3
Vcc[V]
4
5
6
1
2
3
Vcc[V]
4
5
6
0
Fig.10 Current consumption at READ action ICC2
(fSCL=400kHz)
SPEC
2
1.5
1
0.5
1
2
3
Vcc[V]
4
5
Ta=105℃
0.2
1
Ta=25℃
Ta=-40℃
Ta=-40℃
3
4
5
6
Vcc[V]
Fig.13 Current consumption at READ action ICC2
(fSCL=100kHz)
1
2
0
1
SPEC2
10
3
2
Ta=-40℃
Ta=25℃
Ta=105℃
1
0
1
2
3
Vcc[V]
4
5
1
2
3
Vcc[V]
4
5
6
0
2
SPEC1
3
2
3
Vcc[V]
4
5
Fig.18 Start condition hold time tHD:STA
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© 2009 ROHM Co., Ltd. All rights reserved.
6
2
3
4
5
Vcc[V]
Fig.17 Data clock "L" time tLOW
6
0
Ta=-40℃
Ta=25℃
Ta=105℃
-50
-100
2
Ta=-40℃
Ta=25℃
Ta=105℃
-150
SPEC1
-200
0
1
1
SPEC1,2
4
1
0
SPEC1
50
tHD:DAT(HIGH)[ns]
tSU:STA[μs]
3
0
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC2
5
4
1
2
Fig.16 Data clock "H" time tHIGH
SPEC2
Ta=105℃
Ta=25℃
Ta=-40℃
3
1
6
5
6
0
0
6
Fig.15 SCL frequency fSCL
tHD:STA[μs]
SPEC1
0
1
5
SPEC2
tLOW[μs]
tHIGH [μs]
fSCL[kHz]
SPEC1
100
4
4
4
Ta=105℃
Ta=25℃
Ta=-40℃
3
Vcc[V]
5
SPEC2
1000
2
Fig.14 Standby current ISB
5
10000
Ta=25℃
0
0
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
Ta=105℃
0.5
0.1
6
6
1.5
0
0
5
SPEC
0.3
0
4
2
0.4
Ta=25℃
Ta=105℃
Ta=-40℃
3
Vcc[V]
fSCL=100kHz
DATA=AAh
ISB[μA]
SPEC
2
Fig.11 Current consumption at WRITE action ICC1
(fSCL=100kHz)
0.5
ICC2[mA]
2.5
1
2.5
[BR24A32/64 series]
3
fSCL=100kHz
DATA=AAh
Ta=25℃
Ta=105℃
Ta=-40℃
0
1
0.6
3.5
SPEC
0.5
Ta=-40℃
0
Fig.9 Current consumption at WRITE action ICC1
(fSCL=400kHz)
fSCL=100kHz
DATA=AAh
1.5
0
0
2
2.5
ICC1[mA]
fSCL=400kHz
DATA=AAh
1
SPEC
[BR24A32/64 series]
3
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
0
0
SPEC
1.5
ICC1[mA]
ILO[μA]
0.8
ILI[μA]
Ta=25℃
0
2
1.2
Ta=105℃
SPEC
3
4
5
6
Vcc[V]
Fig.3 H input voltage VIH1,2 (SCL,SDA,WP)
ICC1[mA]
SPEC
0.4
0
0
ICC1[mA]
0.6
0.2
1
0
VOL1[V]
6
VIL1,2[V]
VIH1,2[V]
●Characteristic data (The following values are Typ. ones.)
0
1
2
3
Vcc[V]
4
5
Fig.19 Start condition setup time tSU:STA
5/17
6
0
1
2
3
Vcc[V]
4
5
6
Fig.20 Input data hold time tHD:DAT(HIGH)
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Characteristic data (The following values are Typ. ones.)
50
300
300
SPEC1,2
-50
Ta=105℃
Ta=25℃
-100
-150
SPEC1
100
0
Ta=105℃
Ta=25℃
Ta=-40℃
-100
Ta=-40℃
-200
1
2
3
4
5
6
Vcc[V]
Fig.21 Input data hold time tHD:DAT(LOW)
SPEC1
100
Ta=105℃
0
-100
-200
0
SPEC2
200
tSU:DAT(LOW)[ns]
200
tSU:DAT(HIGH)[ns]
tHD:DAT(LOW)[ns]
0
SPEC2
-200
0
1
2
3
Vcc[V]
4
5
6
0
Fig.22 Input data setup time tSU:DAT(HIGH)
4
Ta=-40℃
Ta=25℃
1
2
3
Vcc[V]
4
5
6
Fig.23 Input data setup time tSU:DAT(LOW)
4
5
SPEC2
tPD1[μs]
tPD0[μs]
2
Ta=105℃
Ta=25℃
Ta=-40℃
1
SPEC1
2
Ta=-40℃
Ta=25℃
Ta=105℃
3
2
Ta=-40℃
Ta=25℃
Ta=105℃
1
SPEC2
SPEC1
SPEC1
SPEC1
0
0
1
SPEC1
1
SPEC2
0
4
SPEC2
3
tBUF[μs]
SPEC2
3
2
3
Vcc[V]
4
5
0
6
Fig.24 Output data delay time tPD0
1
2
3
Vcc[V]
4
5
0
6
0
Fig.25 Output data delay time tPD1
6
1
2
3
Vcc[V]
4
5
6
Fig.26 Bus release time before transfer start tBUF
0.6
0.6
SPEC1,2
5
0.5
0.5
3
tI(SCL H)[μs]
tWR[ms]
Ta=-40℃
Ta=105℃
2
1
0.4
Ta=-40℃
Ta=25℃
0.3
Ta=105℃
0.2
1
2
3
Vcc[V]
4
5
0.3
Ta=-40℃
0.2
Ta=25℃
Ta=105℃
0.1
6
SPEC1
0
0
0
0.4
SPEC1,2
0.1
0
0
Fig.27 Internal write cycle time tWR
1
2
3
Vcc[V]
4
5
0
6
Fig.28 Noise removal valid time tI(SCL H)
0.6
0.6
0.5
0.5
0.4
0.4
1
Ta=-40℃
Ta=25℃
Ta=105℃
0.2
SPEC1,2
Ta=-40℃
0.3
0.1
0
0
1
2
3
Vcc[V]
Ta=105℃
4
5
6
Fig.30 Noise removal valid time tI(SDA H)
5
6
SPEC1,2
Ta=105℃
Ta=25℃
-0.4
SPEC1
0
4
-0.2
Ta=25℃
0.2
0.1
3
Vcc[V]
0.2
tSU:WP[μs]
0.3
2
Fig.29 Noise removal valid time tI(SCL L)
0
tI(SDA L)[μs]
tI(SDA H)[μs]
tI(SCL L)[μs]
Ta=25℃
4
Ta=-40℃
-0.6
0
1
2
3
4
5
6
Vcc[V]
Fig.31 Noise removal valid time tI(SDA L)
0
1
2
3
Vcc[V]
4
5
6
Fig.32 WP setup time tSU:WP
1.2
1
tHIGH:WP[μs]
SPEC1,2
0.8
0.6
0.4
Ta=-40℃
Ta=25℃
Ta=105℃
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Fig.33 WP valid time tHIGH:WP
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© 2009 ROHM Co., Ltd. All rights reserved.
6/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●I2C BUS communication
○I2C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
2
acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by
2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
P
STOP
condition
Fig.34 Data transfer timing
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition
is satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Slave address
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A2
A2
A2
A2
P2
A2
A2
A1
A1
A1
P1
P1
A1
A1
A0
A0
PS
P0
P0
A0
A0
―
R/W
―
R/W
―
R/W
―
R/W
―
R/W
―
R/W
―
Maximum number of
connected buses
8
8
4
2
1
8
8
A0
1
A1
2
A2
3
GND
4
8
BR24A01A-WM
BR24A02-WM
7
BR24A04-WM
BR24A08-WM
6
BR24A16-WM
BR24A32-WM
BR24A64-WM
5
Vcc
WP
SCL
SDA
R/W
PS, P0～P2 are page select bits.
Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
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2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
S
T
A
R
T
SLAVE
ADDRESS
SDA
LINE
W
R
I
T
E
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
Note)
S
T
O
P
DATA
WA
0
D7
D0
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A
C
K
A
C
K
R A *1
/ C
W K
Fig.35 Byte write cycle (BR24A01A/02/04/08/16-WM)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 A2 A1 A0
*
*
WA
0
D0
D7
A
C
K
A
C
K
*1
S
T
O
P
DATA
WAWA
12 11
*
R A
/ C
W K
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
*1 As for WA12, BR24A32-WM becomes Don’t care.
A
C
K
Fig.36 Byte write cycle (BR24A32/64-WM)
S
T
A
R
T
SDA
L IN E
SLAVE
ADDRESS
W
R
I
T
E
1 0 1 0 A 2A 1A 0
N ote )
*
*
R A
/ C
W K
*
1 2 11
*1
SDA
L IN E
SLAVE
ADDRESS
1 0 1 0 A 2A 1A 0
N o te )
W
R
I
T
E
D0
D0
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A
C
K
A
C
K
*2 As for BR24A01A/02-WM becomes (n+7).
(BR24A01A/02/04/08/16-WM)
W ORD
A D D R E S S (n )
WA
7
D A TA (n )
WA
0
R A
/ C *1
W K
Fig.38 Page write cycle
D7
A
C
K
A
C
K
S
T
O
P
D A TA (n + 3 1 )
D A T A (n )
WA
0
WA WA
Fig.37 Page write cycle
S
T
A
R
T
2nd W ORD
A D D R E S S (n )
1 st W O R D
A D D R E S S (n )
D7
D A TA (n +1 5 )
D0
A
C
K
S
T
O
P
*2
*1 As for WA12, BR24A32-WM becomes Don’t care.
D0
A
C
K
A
C
K
(BR24A32/64-WM)
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM）
: Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM）
: Up to 32bytes (BR24A32-WM, BR24A64-WM
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.)
・As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in
BR24A01A-WM) of word address are designated arbitrarily, and as for page write command of BR24A04-WM,
BR24A08-WM, and BR24A16-WM, after page select bit (PS) of slave address is designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is
incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written.
・As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of
word address, or the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
*1
*2
*3
In BR24A16-WM, A2 becomes P2.
In BR24A08-WM, BR24A16-WM, A1 becomes P1.
In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and
BR24A16-WM, A0 becomes P0.
Fig.39 Difference of slave address of each type
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8/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
○Notes on write cycle continuous input
At STOP (stop bit),
write starts.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS（ｎ）
*1
WA
7
1 0 1 0 A2A1A0
R A
/ C
W K
Note)
*2
DATA(n)
WA
0
D7
DATA(n+7)*3
D0
A
C
K
A
C
K
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
1 0 1 0
A
C
K
Next command
tWR(maximum : 5ms)
Command is not accepted for this period.
*1
*2
*3
BR24A01A-WM becomes Don’t care.
BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15).
BR24A32-WM and BR24A64-WM become (n+31).
*1
*2
*3
In BR24A16-WM, A2 becomes P2.
In BR24A08-WM, BR24A16-WM, A1 becomes P1.
In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and in BR24A16-WM, A0 becomes P0.
Fig.42 Difference of each type of slave address
8Byte
Product
number
S
T
A
R
T
D0
Fig.40 Page write cycle
○Notes on page write cycle
List of numbers of page write
Number of Pages
S
T
O
P
16Byte
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A01A-WM
BR24A02-WM
32Byte
BR24A32-WM
BR24A64-WM
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24A02-WM, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.).
○Internal address increment
Page write mode (in the case of BR24A02-WM)
WA7 ----0
----0
----0
-----
WA4
0
0
0
-------------
0
0
0
WA1
0
0
1
WA0
0
1
0
Increment
---------
0
0
0
WA2
0
0
0
---------
---------
06h
WA3
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
Significant bit is fixed.
No digit up
For example, when it is started from address 06h,therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
*06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set VCC (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of
all address is enabled. Be sure to connect this terminal to VCC or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be
read in succession.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
S
T
A
R
T
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2 A 1A 0
WA
0
R A *1
/ C
W K
N o te )
R
E
A
D
SLAVE
ADDRESS
D A TA (n )
1 0 1 0 A 2 A 1A 0
A
C
K
It is necessary to input 'H' to
the last ACK.
S
T
O
P
D0
D7
A
C
K
R A
/ C
W K
*1 As for WA7, BR24A01A-WM become Don’t care.
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
* * *
WA
0
WAWA
12 11
R A
/ C
W K
Note)
2nd WORD
ADDRESS（ｎ）
1st WORD
ADDRESS（ｎ）
1 0 1 0 A2A1A0
S
T
A
R
T
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
A
C
K
DATA(n)
D7
D0
R A
/ C
W K
A
C
K
Fig.43 Random read cycle (BR24A32/64 -WM)
S
T
A
R
T
SDA
L IN E
R
E
A
D
S LA V E
ADDRESS
1 0 1 0 A 2 A 1A 0
D7
It is necessary to input 'H' to
the last ACK.
D0
A
C
K
R A
/ C
W K
N o te)
*1 As for WA12, BR24A32-WM become Don’t care.
S
T
O
P
D A TA (n )
S
T
O
P
Fig.44 Current read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
Note）
D7
S
T
O
P
DATA(n+x)
DATA(n)
D0
R A
/ C
W K
D7
A
C
K
D0
A
C
K
A
C
K
Fig.45 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
*1
In BR24A16-WM, A2 becomes P2.
*2
In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3
In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
Fig.46 Difference of slave address of each type
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10/17
and BR24A16-WM, A0 becomes P0.
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.47(a), Fig.47(b), and Fig.47(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
2
1
13
Normal command
14
SDA
Normal command
Fig.47-(a) The case of dummy clock +START+START+ command input
Start
SCL
Start
Dummy clock×9
1
2
8
9
Normal command
SDA
Normal command
Fig.47-(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL
2
1
7
3
8
9
Normal command
SDA
Normal command
Fig.47-(c) START×9+ command input
※
Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
S
T Slave
A
R address
T
A
C
K
H
A
C
K
H
tWR
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C Word
K address
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
Fig.48 Case to continuously write by acknowledge polling
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2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise
of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.49.) After
execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
・Rise of SDA
SCL
SDA
D1
D0
SDA
ACK
SDA
S
T Slave
A address
R
T
A
C Word
K address
L
ACK
D0
Enlarged view
Enlarged view
A
C
K D7 D6 D5 D4 D3 D2 D1 D0
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP cancel valid area
Write forced end
Data is not written.
Data not guaranteed
WP
Fig.49 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 50.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.50 Case of cancel by start, stop condition during slave address input
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2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA
(2)The bus electric potential○
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2VCC.
Vcc - ILRPU - 0.2Vcc ≧ VIH
∴
RPU ＝
0.8Vcc - VIH
IL
マイコン
Microcontroller
BR24AXX
RPU
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
from (2)
RPU ≦
A
0.8×3- 0.7×3
10×10-6
IL
CBUS
CBUS
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
≦ IOL
IL
Bus line
バスライン容量
capacity
≦ 300 [kΩ]
VCC-VOL
RPU
SDA terminal
∴
RPU ≦
Fig.51 I/O circuit diagram
VC-VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
margin 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
3－0.4
RPU ≧
3×10 -3
≧ 867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or VCC or GND. And,
pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with N.C.PIN
BR24A16/F/FJ -WM
A0, A1, A2
BR24A08/F/FJ-WM
A0, A1
BR24A04/F/FJ -WM
A0
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Cautions on microcontroller connection
○Rs
2
In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
EEPROM
RPU
SCL
RS
SDA
'H' output of microcontroller
Microcontroller
'L' output of EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
Fig.53 Input / output collision timing
Fig.52 I/O circuit diagram
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1VCC.
VCC
(VCC－V OL)×RS
R PU+R S
RPU A
RS
VOL
∴ RS ≦
IOL
Bus line
capacity CBUS
VIL
VIL－VOL－0.1VCC
1.1VCC－V IL
×
R PU
Example） When V CC=3V, V IL =0.3VCC, VOL=0.4V, R PU=20kΩ,
EEPROM
Microcontroller
+ V OL+0.1VCC≦VIL
from(2),
R S ≦ 0.3×3－0.4－0.1×3
1.1×3－0.3×3
Fig.54 I/O circuit diagram
20×103
×
≦ 1.67［kΩ］
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following
relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so
forth. Set the over current to EEPROM 10mA or below.
VCC
≦
RS
RPU
I
'L' output
RS
∴
RS
≧
VCC
I
Over currentⅠ
Example）When VCC =3V, I=10mA
'H' output
Microcontroller
RS
EEPROM
Fig.55 I/O circuit diagram
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≧
3
10×10 -3
≧ 300 ［Ω］
14/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●I2C BUS input / output circuit
○Input (A0,A2,SCL)
Fig.56 Input pin circuit diagram
○Input / output (SDA)
Fig.57 Input / output pin circuit diagram
○Input (A1, WP)
Fig.58 Input pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF,Vbot
tOFF
Vbot
0
tR
tOFF
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Fig.59 Rise waveform diagram
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15/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Fig.60 When SCL= 'H' and SDA= 'L'
tSU:DAT
Fig.61 When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●VCC noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCC and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board VCC and GND.
●Note of use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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16/17
2009.08 - Rev.C
Technical Note
BR24A□□-WM series
●Ordering part number
B
R
2
Part No.
4
A
BUS type
0
1
Operating
Capacity
temperature 01= 1K
24 :I2C
A:-40℃～
+105℃
04= 4K
16=16K
64=64K
F
-
Package
02= 2K
08= 8K
32=32K
W
M
E
Double cell
2
Packaging and forming specification
E2: Embossed tape and reel
TR: Embossed tape and reel
F : SOP8
FJ : SOP-J8
FVM : MSOP8
●Package specifications
SOP8
<Tape and Reel information>
5.0±0.2
(MAX 5.35 include BURR)
6
5
4.4±0.2
6.2±0.3
0.9±0.15
7
0.3MIN
8
+6°
4° −4°
1 2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
0.11
S
1.27
0.42±0.1
Direction of feed
1pin
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
SOP-J8
<Tape and Reel information>
4.9±0.2
(MAX 5.25 include BURR)
+6°
4° −4°
6
5
0.45MIN
7
3.9±0.2
6.0±0.3
8
1
2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.545
0.2±0.1
0.175
1.375±0.1
S
1.27
0.42±0.1
0.1 S
Direction of feed
1pin
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 –0.03
0.475
0.75±0.05
0.08±0.05
0.9MAX
S
+0.05
0.22 –0.04
0.08 S
Direction of feed
0.65
(Unit : mm)
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Reel
17/17
∗ Order quantity needs to be multiple of the minimum quantity.
2009.08 - Rev.C
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
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The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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