Cypress CY7C4801-10AC 256/512/1k/2k/4k/8k x9 x2 double sync fifo Datasheet

CY7C4831/4
1
CY7C4801/4811/4821
CY7C4831/4841/4851
256/512/1K/2K/4K/8K x9 x2
Double Sync FIFOs
Features
• Double high speed, low power, first-in first-out (FIFO)
memories
• Double 256 x 9 (CY7C4801)
• Double 512 x 9 (CY7C4811)
• Double 1K x 9 (CY7C4821)
• Double 2K x 9 (CY7C4831)
• Double 4K x 9 (CY7C4841)
• Double 8K x 9 (CY7C4851)
• Functionally equivalent to two CY7C4201/4211/4221/
4231/4241/4251 FIFOs in a single package
• 0.65 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10 ns read/write cycle
times)
• Offers optimal combination of large capacity, high
speed, design flexibility, and small footprint
• Fully asynchronous and simultaneous read and write
operation
• Four status flags per device: Empty, Full, and programmable Almost Empty/Almost Full
• Low power — ICC1= 60mA
• Output Enable (OEA/OEB) pins
• Depth Expansion Capability
• Width Expansion Capability
• Space-saving 64-pin TQFP
• Pin compatible and functionally equivalent to IDT72801,
72811, 72821, 72831, 72841,72851
Functional Description
The CY7C48X1 are Double high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide and operate as two separate FIFOs. The
CY7C48X1 are pin-compatible to IDT728X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
Cypress Semiconductor Corporation
Document #: 38-06005 Rev. *A
•
These FIFOs have two independent sets of 9-bit input and
output ports that are controlled by separate clock and enable
signals. The input port is controlled by a free-running clock
(WCLKA,WCLKB) and two write-enable pins (WENA1,
WENA2/LDA, WENB1, WENB2/LDB).
When (WENA1,WENB1) is LOW and (WENA2/LDA,
WENB2/LDB) is HIGH, data is written into the FIFO on the
rising edge of the (WCLKA,WCLKB) signal. While (WENA1,
WENA2/LDA, WENB1, WENB2/LDB) is held active, data is
continually written into the FIFO on each WCLKA, WCLKB
cycle. The output port is controlled in a similar manner by a
free-running read clock (RCLKA, RCLKB) and two read-enable pins ((RENA1,RENB1), (RENA2,RENB2)). In addition,
the CY7C48X1 has output enable pins (OEA, OEB) for each
FIFO. The read (RCLKA, RCLKB) and write (WCLKA,
WCLKB) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz
are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
The CY7C48X1 provides two sets of four different status pins: Empty,
Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags
are programmable to single word granularity. The programmable
flags default to Empty+7 and Full–7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLKA,RCLKB) or the write clock
(WCLKA,WCLKB). When entering or exiting the Empty and
Almost Empty states, the flags are updated exclusively by the
(RCLKA,RCLKB). The flags denoting Almost Full, and Full
states are updated exclusively by (WCLKA,WCLKB) The synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle
All configurations are fabricated using an advanced 0.65µ
N-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CY7C4801/4811/4821
CY7C4831/4841/4851
Logic Block Diagram
WCLKA
DA 0-8
LDA
LDB
FLAG
PROGRAM
REGISTER
DB0-8
WCLKB
WENB1
WENB2/LDB
WENA2/LDA
WENA1
EFA
PAEA
PAFA
FFA
EFB
PAEB
PAFB
FFB
FLAG
LOGIC
INPUT
REGISTER
INPUT
REGISTER
WRITE
CONTROL
WRITE
CONTROL
WRITE
POINTER A
RAM
ARRAY A
x9
256
.
.
8k x 9
RAM
ARRAY B
x9
256
.
WRITE
POINTER B
RSB
RESET
LOGIC
READ
POINTER B
READ
CONTROL A
READ
CONTROL B
.
8k x 9
RSA
READ
POINTER A
THREE–STATE
OUTPUT REGISTER
THREE–STATE
OUTPUT REGISTER
OEA
QA0-8
RCLKA
RENA1
OEB
QB0-8
RCLKB
RENB1
RENA2
RENB2
48X1–1
TQFP
Top View
CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DA5
DA4
DA3
DA2
DA1
DA0
PAFA
PAEA
WENB2/LDB
WCLKB
WENB1
RSB
DB8
DB7
DB6
DB5
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
Vcc
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
QA0
FFA
EFA
OEA
RENA2
RCLKA
RENA1
GND
QB8
QB7
QB6
QB5
QB4
QB3
QB2
QB1
Pin Configuration
Document #: 38-06005 Rev. *A
QB0
FFB
EFB
OEB
RENB2
RCLKB
RENB1
GND
Vcc
PAEB
PAFB
DB0
DB1
DB2
DB3
DB4
48X1–1
Page 2 of 23
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Selection Guide
7C48X1-10
7C48X1-15
7C48X1-25
7C48X1-35
Maximum Frequency (MHz)
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Minimum Data or Enable Set-Up (ns)
3
4
6
7
Minimum Data or Enable Hold (ns)
0.5
1
1
2
8
10
15
20
Commercial
60
60
60
60
Industrial
70
70
70
70
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC1) (mA)
CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
Density
Double 256 x 9
Double 512 x 9
Double 1K x 9
Double 2K x 9
Double 4K x 9
Double 8K x 9
Package
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ....................................... −65°C to +150°C
Operating Range[1]
Ambient Temperature with
Power Applied.................................................... −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage .................................................−0.5V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Document #: 38-06005 Rev. *A
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
−40°C to +85°C
5V ± 10%
Industrial
[2]
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
2. TA is the “instant on” case temperature.
Page 3 of 23
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Pin Definitions
Signal Name
Description
I/O
Description
DA0 − 8
Data Inputs
I
Data Inputs for 9-bit bus
DB0 − 8
Data Inputs
I
Data Inputs for 9-bit bus
QA0 − 8
Data Outputs
O
Data Outputs for 9-bit bus
QB0 − 8
Data Outputs
O
Data Outputs for 9-bit bus
Write Enable 1
I
WENA1 and WENB1become the only write enables when the device is configured to
have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when
(WENA1,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO is configured to have two write
enables, data is written on a LOW-to-HIGH transition of WCLK when (WENA1,WENB1) is
LOW and (WENA2/LDA,WENB2/LDB) and (FFA,FFB) are HIGH.
Write Enable 2
I
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. (WENA1,WENB1)
must be LOW and (WENA2/LDA,WENB2/LDB) must be HIGH to write data into the FIFO.
Data will not be written into the FIFO if the (FFA,FFB) is LOW. If the FIFO is configured to have
programmable flags, (WENA2/LDA,WENB2/LDB) is held LOW to write or read the programmable flag offsets.
RENA1
RENA2
RENB1
RENB2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLKA
WCKLB
Write Clock
I
The rising edge clocks data into the FIFO when (WENA1,WENB1) is LOW and
(WENA2/LDA,WENB2/LDB) is HIGH and the FIFO is not Full. When
(WENA2/LDA,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset
register.
RCLKA
RCLKB
Read Clock
I
The rising edge clocks data out of the FIFO when (RENA1 ,RENB1) and (RENA2,RENB2)
are LOW and the FIFO is not Empty. When (WENA2/LDA,WENB2/LDB) is LOW,
(RCLKA,RCLKB) reads data out of the programmable flag-offset register.
EFA,EFB
Empty Flag
O
When (EFA,EFB) is LOW, the FIFO is empty. (EFA,EFB) is synchronized to
(RCLKA,RCLKB).
FFA,FFB
Full Flag
O
When (FFA,FFB) is LOW, the FIFO is full. (FFA,FFB) is synchronized to (WCLKA,WCLKB).
PAEA
PAEB
Programmable
Almost Empty
O
When (PAEA,PAEB) is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
PAFA
PAFB
Programmable
Almost Full
O
When (PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
RSA
RSB
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OEA
OEB
Output Enable
I
When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
WENA1
WENB1
WENA2/LDA
WENB2/LDB
Dual Mode Pin
Document #: 38-06005 Rev. *A
Page 4 of 23
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Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
7C48X1-10
7C48X1-15
7C48X1-25
7C48X1-35
Min.
Min.
Min.
Min.
Max.
2.4
Max.
VOH
Output HIGH Voltage VCC = Min.,
IOH = −2.0 mA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.0
VCC
2.0
VCC
2.0
VCC
VIL
Input LOW Voltage
−0.5
0.8
−0.5
0.8
−0.5
IIX
Input Leakage
Current
VCC = Max.
−10
+10
−10
+10
−10
IOS[4]
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
−90
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
−10
ICC1[5]
Active Power Supply
Current
VCC = Min.,
IOL = 8.0 mA
2.4
Max.
0.4
2.4
0.4
−90
+10
−10
2.4
−10
Unit
V
0.4
0.4
V
2.0
VCC
V
0.8
−0.5
0.8
V
+10
−10
+10
µA
−90
+10
Max.
−90
mA
−10
+10
+10
µA
Com’l
60
60
60
60
mA
Ind
70
70
70
70
mA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
AC Test Loads and Waveforms[7, 8]
R1 1.1KΩ
ALL INPUT PULSES
5V
OUTPUT
3.0V
CL
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
420Ω
OUTPUT
R2
680Ω
GND
≤ 3 ns
48X1–4
90%
10%
90%
10%
≤ 3 ns
48X1–5
1.91V
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. Test no more than one output at a time for not more than one second.
5. Outputs open. Tested at Frequency = 20 MHz.
6. Tested initially and after any design or process changes that may affect these parameters.
7. CL = 30 pF for all AC parameters except for tOHZ.
8. CL = 5 pF for tOHZ.
Document #: 38-06005 Rev. *A
Page 5 of 23
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Switching Characteristics Over the Operating Range
Parameter
Description
7C48X1-10
7C48X1-15
7C48X1-25
7C48X1-35
Min.
Min.
Min.
Min.
Max.
100
Max.
Unit
28.6
MHz
20
ns
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3.5
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3.5
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
10
15
25
35
ns
Width[9]
2
10
40
Max.
fS
8
66.7
Max.
2
15
2
tRS
Reset Pulse
tRSS
Reset Set-Up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[10]
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
3
7
3
8
3
12
3
15
ns
10
Z[10]
15
0
25
0
35
0
ns
ns
tOHZ
Output Enable to Output in High
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
15
15
18
20
ns
Notes:
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
Document #: 38-06005 Rev. *A
Page 6 of 23
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Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDS
tDH
DA0 −DA8
(DB0−DB8)
tENS
tENH
WENA1
(WENB1)
NO OPERATION
NO OPERATION
WENA2(WENB2)
(if applicable)
tWFF
tWFF
FFA (FFB)
tSKEW1 [11]
RCLKA (RCLKB)
RENA1,RENB2
(RENB1, RENB2)
48X1–6
Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENS
tENH
RENA1,RENA2
(RENB1,RENB2)
NO OPERATION
tREF
tREF
EFA(EFB)
tA
QA0−QA8
(QB0−QB8)
VALID DATA
tOLZ
tOHZ
tOE
OEA(OEB)
[12]
tSKEW1
WCLKA,WCLKB
WENA1(WENB1)
WENA2(WENB2)
48X1–7
Notes:
11. tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock
cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the
next (WCLKA,WCLKB) rising edge.
12. tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock
cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next
(RCLKA,RCLKB) rising edge.
Document #: 38-06005 Rev. *A
Page 7 of 23
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Switching Waveforms (continued)
[13]
Reset Timing
tRS
RSA(RSB)
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
RENA1, RENA2
(RENB1,RENB2)
WENA1
(WENB1)
WENA2/LDA
[15]
(WENB2/LDB)
EFA, PAEA
(EFB, PAEB)
tRSF
tRSF
FFA, PAFA
(FFB, PAFB)
tRSF
QA0−QA8
(QB0−QB8)
[14]
OEA(OEB)=1
OEA(OEB)=0
48X1–8
Notes:
13. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.
14. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.
15. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
Document #: 38-06005 Rev. *A
Page 8 of 23
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Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLKA,WCLKB
tDS
DA0−DA8
(DB0−DB8)
D0 (FIRSTVALID WRITE)
D1
tENS
D2
D3
D4
[16]
tFRL
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
tSKEW1
RCLKA(RCLKB)
tREF
EFA(EFB)
[17]
tA
tA
RENA1, RENA2
(RENB1,RENB2)
QA0 −QA8
(QB0−QB8)
D0
D1
tOLZ
tOE
OEA(OEB)
48X1–9
Notes:
16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).
17. The first word is available the cycle after (EFA, EFB) goes HIGH, always.
Document #: 38-06005 Rev. *A
Page 9 of 23
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Switching Waveforms (continued)
Empty Flag Timing
WCLKA,WCLKB
tDS
DA0−DA8
(DB0−DB8)
tDS
DATA WRITE2
DATA WRITE1
tENH
tENS
tENH
tENS
WENA1(WENB1)
tENS
tENH
WENA2(WENB2)
(if applicable)
tENS
tENH
[16]
[16]
tFRL
tFRL
RCLKA(RCLKB)
tSKEW1
tREF
tREF
tREF
tSKEW1
EFA(EFB)
RENA1, RENA2
(RENB1,RENB2)
LOW
OEA(OEB)
tA
QA0−QA8
(QB0−QB8)
Document #: 38-06005 Rev. *A
DATA IN OUTPUT REGISTER
DATA READ
48X1–10
Page 10 of 23
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Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
NO WRITE
WCLKA,WCLKB
[11]
tSKEW1
tDS
DA0−DA8
(DB0−DB8)
[11]
DATA WRITE
tSKEW1
DATA WRITE
tWFF
tWFF
tWFF
FFA(FFB)
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
RCLKA(RCLKB)
tENH
RENA1, RENA2
(RENB1,RENB2)
OEA(OEB)
tENH
tENS
tENS
LOW
tA
tA
QA0−QA8
(QB0−QB8)
DATA IN OUTPUT REGISTER
Document #: 38-06005 Rev. *A
DATA READ
NEXT DATA READ
48X1–11
Page 11 of 23
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Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLKA,WCLKB
tENS tENH
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
tENS tENH
PAEA(PAEB)
[18]
Note
19
N + 1 WORDS
IN FIFO
tPAE
tSKEW2
Note
20
tPAE
RCLKA(RCLKB)
tENS tENH
RENA1, RENA2
(RENB1,RENB2)
48X1–12
Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note
21
WCLKA,WCLKB
tENS tENH
WENA1(WENB1)
Note
22
WENA2(WENB2)
(if applicable)
tENS tENH
PAFA(PAFB)
tPAF
FULL− M WORDS
IN FIFO [23]
FULL− M+1 WORDS
IN FIFO
[24]
tSKEW2
tPAF
RCLKA(RCLKB)
tENS
tENS tENH
RENA1, RENA2
(RENB1,RENB2)
48X1–13
Notes:
18. tSKEW2 is the minimum time between a rising (WCLKA,WCLKB) and a rising (RCLKA,RCLKB) edge for (PAEA,PAEB) to change state during that clock cycle. If the time
between the edge of (WCLKA,WCLKB) and the rising (RCLKA,RCLKB) is less than tSKEW2, then (PAEA,PAEB) may not change state until the next RCLK.
19. (PAEA,PAEB) offset = n.
20. If a read is preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when (PAEA,PAEB) goes LOW.
21. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW.
22. (PAFA,PAFB) offset = m.
23. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841,
8192-m words for CY7C4851.
24. tSKEW2 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge for (PAFA,PAFB) to change during that clock cycle. If the time
between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW2, then (PAFA,PAFB) may not change state until the next
(WCLKA,WCLKB).
Document #: 38-06005 Rev. *A
Page 12 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLKA,WCLKB
tENS
tENH
WENA2/LDA
(WENB2/LDB)
tENS
WENA1(WENB1)
tDS
DA0−DA8
(DB0−DB8)
tDH
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
48X1–14
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLKA(RCLKB)
tENS
tENH
WENA2/LDA
(WENB2/LDB)
tENS
PAF OFFSET
MSB
RENA1, RENA2
(RENB1,RENB2)
tA
QA0−QA8
(QB0−QB8)
Document #: 38-06005 Rev. *A
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
48X1–15
Page 13 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Architecture
The CY7C48X1 functions as two independent FIFOs in a single
package, each with its own separate set of controls. The device consists of two arrays of 256 to 8K words of 9 bits each (implemented by a dual-port array of SRAM cells), two read pointers,
two write pointers, control signals (RCLKA, RCLKB, WCLKA,
WCLKB, RENA1, RENB1, RENA2, RENB2, WENA1, WENB1,
WENA2, WENB2, RSA, RSB), and flags (EFA,EFB, PAEA,PAEB,
PAFA,PAFB, FFA,FFB).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RSA,
RSB) cycle. This causes the FIFO to enter the Empty condition signified by (EFA,EFB) being LOW. All data outputs (QA0−8,QB0−8) go
LOW tRSF after the rising edge of RSA, RSB. In order for the FIFO
to reset to its default state, a falling edge must occur on (RSA,RSB)
and the user must not read or write while (RSA,RSB) is LOW. All flags
are guaranteed to be valid tRSF after (RSA,RSB) is taken LOW.
FIFO Operation
When the (WENA1,WENB1) signal is active LOW and
(WENA2,WENB2) is active HIGH, data present on the
(DA0−8,DB0−8) pins is written into the FIFO on each rising edge
(WCLKA,WCLKB) of the (WCLKA,WCLKB) signal. Similarly, when
the (RENA1,RENB1) and (RENA2,RENB2) signals are active LOW,
data in the FIFO memory will be presented on the (QA0−8,QB0−8)
outputs. New data will be presented on each rising edge of
(RCLKA,RCLKB) while (RENA1,RENB1) and (RENA2,RENB2) are
active. (RENA1,RENB1) and (RENA2,RENB2) must set up tENS before (RCLKA,RCLKB) for it to be a valid read function.
(WENA1,WENB1) and (WENA2,WENB2) must occur tENS before
(WCLKA,WCLKB) for it to be a valid write function.
An output enable (OEA,OEB) pin is provided to three-state the
(QA0−8,QB0−8) outputs when (OEA,OEB) is asserted. When
(OEA,OEB) is enabled (LOW), data in the output register will be available to the (QA0−8,QB0−8) outputs after tOE.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its (QA0−8,QB0−8)
outputs even after additional reads occur.
Write Enable 1 (WENA1,WENB1) - If the FIFO is configured
for programmable flags, Write Enable 1 (WENA1,WENB1) is
the only write enable control pin. In this configuration, when
Write Enable 1 (WENA1,WENB1) is LOW, data can be loaded
into the input register and RAM array on the LOW-to-HIGH
Document #: 38-06005 Rev. *A
transition of every write clock (WCLKA,WCLKB). Data is
stored is the RAM array sequentially and independently of any
on-going read operation.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) - This is a
dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows
for depth expansion. If Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) is set active HIGH at Reset (RSA,RSB=LOW),
this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable 1 (WENA1,WENB1) is LOW and Write Enable 2/Load
(WENA2/LDA, WENB2/LDB) is HIGH, data can be loaded into the
input register and RAM array on the LOW-to-HIGH transition of every
write clock (WCLKA,WCLKB). Data is stored in the RAM array sequentially and independently of any on-going read operation.
Programming
When (WENA2/LDA, WENB2/LDB) is held LOW during Reset, this
pin is the load (LDA,LDB) enable for flag offset programming. In this
configuration, (WENA2/LDA, WENB2/LDB) can be used to access
the four 8-bit offset registers contained in the CY7C48X1 for writing
or reading data to these registers.
When the device is configured for programmable flags and
both (WENA2/LDA, WENB2/LDB) and (WENA1,WENB1) are
LOW, the first LOW-to-HIGH transition of (WCLKA,WCLKB) writes
data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth LOW-to-HIGH transitions of
(WCLKA,WCLKB) store data in the empty offset most significant bit
(MSB) register, full offset LSB register, and full offset MSB register,
WENB2/LDB)
and
respectively,
when
(WENA2/LDA,
(WENA1,WENB1) are LOW. The fifth LOW-to-HIGH transition of
(WCLKA,WCLKB) while (WENA2/LDA, WENB2/LDB) and
(WENA1,WENB1) are LOW writes data to the empty LSB register
again. Figure 1 shows the register sizes and default values for the
various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the (WENA2/LDA, WENB2/LDB) input HIGH, the FIFO is returned
to normal read and write operation. The next time (WENA2/LDA,
WENB2/LDB) is brought LOW, a write operation stores data in the
next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when (WENA2/LDA, WENB2/LDB) is LOW and both
(RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH
transitions of (RCLKA,RCLKB) read register contents to the data outputs. Writes and reads should not be preformed simultaneously on
the offset registers.
Page 14 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
256 x 9 x 2
8
512 x 9 x 2
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
8
8
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
1K x 9 x 2
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
1
8
(MSB)
0
8
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
(MSB)
00
0
7
8
0
Full Offset (LSB) Reg
Default Value = 007h
0
1
8
0
7
Full Offset (LSB) Reg
Default Value = 007h
8
2K x 9 x 2
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
7
0
7
8
(MSB)
00000
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
2
8
(MSB)
000
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
3
0
4
8
(MSB)
0000
Full Offset (LSB) Reg
Default Value = 007h
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
3
8
(MSB)
000
8
8K x 9 x 2
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
2
8
(MSB)
00
4K x 9 x 2
0
7
0
1
8
(MSB)
0
8
0
1
8
(MSB)
0000
0
4
(MSB)
00000
Figure 1. Offset Register Location and Default Values.
Programmable Flag (PAEA,PAEB, PAFA,PAFB) Operation
Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable
almost-empty flag (PAEA,PAEB) and programmable almost-full flag
(PAFA,PAFB) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
Table 1. Writing the Offset Registers.
WCLK[25]
LD
WEN
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of (PAEA,PAEB).
(PAEA,PAEB) is synchronized to the LOW-to-HIGH transition of
RCLK by one flip-flop and is LOW when the FIFO contains n or fewer
unread words. (PAEA,PAEB) is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread
words.
The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as
m and determines the operation of (PAFA,PAFB). (PAEA,PAEB) is
synchronized to the LOW-to-HIGH transition of (WCLKA,WCLKB) by
one flip-flop and is set LOW when the number of unread words in the
FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811
(512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841
(4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the
LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of
available memory locations is greater than m.
Notes:
25. The same selection sequence applies to reading form the registers. REN1 and REN2 are enabled and a read is performed on the LOW- to-HIGH transition of
RCLK.
Document #: 38-06005 Rev. *A
Page 15 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Flag Operation
The CY7C48X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, (PAEA,PAEB), and
(PAFA,PAFB) are synchronous.
Full Flag
The Full Flag (FFA,FFB) will go LOW when the device is full. Write
operations are inhibited whenever (FFA,FFB) is LOW regardless of
the state of (WENA1,WENB1) and (WENA2/LDA,WENB2/LDB).
(FFA,FFB) is synchronized to (WCLKA,WCLKB), i.e., it is exclusively
updated by each rising edge of (WCLKA,WCLKB).
Empty Flag
The Empty Flag (EFA,EFB) will go LOW when the device is empty.
Read operations are inhibited whenever (EFA,EFB) is LOW, regardless of the state of (RENA1,RENB1) and (RENA2,RENB2.
(EFA,EFB) is synchronized to (RCLKA,RCLKB), i.e., it is exclusively
Full Flag.
Table 2. Status Flags.
Number of Words in FIFO
CY7C4801
CY7C4811
0
1 to
CY7C4821
0
n[26]
1 to
0
n[26]
1 to
n[26]
FF
PAF
PAE
EF
H
H
L
L
H
H
L
H
(n+1) to (256-(m+1))
(n+1) to (512-(m+1))
(n+1) to (1024 −(m+1))
H
H
H
H
(256−m)[27] to 255
(512−m)[27] to 511
(1024−m)[27] to 1023
H
L
H
H
256
512
1024
L
L
H
H
Number of Words in FIFO
CY7C4831
0
1 to n
CY7C4841
0
[26]
1 to n
CY7C4851
0
[26]
1 to n
[26]
FF
PAF
PAE
EF
H
H
L
L
H
H
L
H
(n+1) to (2048 −(m+1)) (n+1) to (4096 −(m+1))
(n+1) to (8192 −(m+1))
H
H
H
H
(2048−m)[27] to 2047
(4096−m)[27] to 4095
(8192−m)[27] to 8191
H
L
H
H
2048
4096
8192
L
L
H
H
Notes:
26. n =Empty Offset (n=7 default value).
27. m = Full Offset (m=7 default value).
Document #: 38-06005 Rev. *A
Page 16 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Single Device Configuration
When FIFO A(B) is in a Single Device Configuration, the Read
Enable 2 RENA2(RENB2) control input can be grounded (see
Figure 2). in this configuration, the Write Enable2/Load
(WENA2/LDA,WENB2/LDB) pin is set LOW at Reset so that
the pin operates as a control to load and read the programmable flag offsets.
RESET (RSA,RSB)
DATA IN DA0−DA8(DB0−DB8)
DATA OUT QA0−QA8(QB0−QB8)
READ CLOCK (RCLKA,RCLKB)
WRITE CLOCK (WCLKA,WCLKB)
CY7C4801
WRITE ENABLE 1 (WENA1,WENB1)
CY7C4811
READ ENABLE 1 (RENA1,RENB1)
CY7C4821
WRITE ENABLE2/LOAD(WENA2/LDA,WENB/LDB)
CY7C4831
OUTPUT ENABLE (OEA,OEB)
CY7C4841
PROGRAMMABLE (PAFA,PAFB)
FULL FLAG (FFA,FFB)
CY7C4851
PROGRAMMABLE(PAEA,PAEA)
EMPTY FLAG(EFA,EFB)
Read Enable 2 (RENA2,RENB2)
48X1–16
Figure 2. Block Diagram of 256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 Double Sync FIFO
Used in a Single Device Configuration.
Document #: 38-06005 Rev. *A
Page 17 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Width Expansion Configuration
When the CY7C4801/4811/4821/4831/4841/4851 is in a
Width Expansion Configuration, the Read Enable 2 (RENA2
and RENB2) control unputs can be grounded (see Figure 3).
In this configuration, the Write Enable 2/Load
(WENA2/LDA,WENB2/LDB) pins are set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
Word width may be increased simply by connecting the corresponding input control signals of FIFOs A and B. A composite
flag should be created for each of the end-point status flags
EFA and EFB, also FFA and FFB. The partial status flags
PAEA, PAFB, PAFA, PAFB can be detected from any one device. Figure 3 demonstrates an 18-bit word width using the two
FIFOs contained in one CY7C4801/4811/4821/4831/4841
/4851. Any word width can be attained by adding additional
CY7C4801/4811/4821/4831/4841/4851s.
9
RESET
RESET (RSA)
D0−D17
18
9
9
WRITECLOCK
WCLKA
WRITE ENABLE
WENA
WRITE ENABLE 2/LOAD
RESET(RSB)
WEN2/LD
FFA
FULL FLAG
RCLKA
RAM ARRAY A
WCLKB
RENA1
WENB1
OEA
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
WENB2/LDB
RAM ARRAY B
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
RCLKB
READCLOCK
RENB1
READ ENABLE
OEB
OUTPUT ENABLE
EFA
EFB
EF
FF
9
FFB
EMPTY FLAG
Q0−Q17
18
9
Read Enable 2 (RENA2)
Read Enable 2 (RENB2)
48X1–17
Figure 3. Block Diagram of two FIFOs contained in one CY7C4801/4811/4821/4831/4841/4851 configured for an 18-bit
width-expansion.
Document #: 38-06005 Rev. *A
Page 18 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Bidirectional Configuration
FIFO A, and, in turn, processor B can write processor A via
FIFO B.
The two FIFOs of the CY7C4801/4811/4821/4831/4841/4851
can be used to buffer data flow in two directions. In the example that follows, processor A can write data to processor B via
RAM ARRAY A
RENA2
WENA2
RCLKA
WCLKA
9
CLOCK
DATA
9
9-BIT BUS
CONTROL
RENA1
DA0−DA8 QA −QA
0
8
PROCESSOR A
CLOCK
9
CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
Control
Logic
ADDRESS
OEA
9-BIT BUS
PROCESSOR A
WENA1
Control
Logic
VCC
ADDRESS
CONTROL
DATA
9
RAM ARRAY B
RAM
9
9
WENB1
RCLKB
RENB1
WCLKB
OEB
DB0−DB8
QB0−QB8
WENB2
RENB2
RAM
9
9
VCC
48X1–18
Figure 4. Block Diagram of Bidirectional Configuration.
Depth Expansion
CY7C4801/4811/4821/4831/4841/4851can be adapted to applications that require greater than 256/512/1024/2048/4096/
8192 words. The existence of dual enable pins on the read and
write ports allow depth expansion. The Write Enable 2/Load
(WENA2, WENB2) pins are used as a second write enables in
a depth expansion configuration, thus the Programmable flags
are set to the default values. Depth expansion is possible by
using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of
Document #: 38-06005 Rev. *A
data. a typical application would have the expansion logic alternate data access from one device to the next in a sequential
manner. The CY7C4801/4811/4821/4831/4841/ 4851 operates in the Depth Expansion configuration when the following
conditions are met:
1. WENA2/LDA and WENB2/LDB pins are held HIGH during
Reset so that these pins operate as second Write Enables.
2. External logic is used to control the flow of data.
Page 19 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Ordering Information
Double 256x9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4801-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4801-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4801-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4801-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4801-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4801-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4801-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4801-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Double 512x9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4811-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4811-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4811-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4811-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4811-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4811-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4811-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4811-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Double 1Kx9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4821-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4821-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4821-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4821-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4821-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4821-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4821-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4821-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Document #: 38-06005 Rev. *A
Page 20 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Ordering Information (continued)
Double 2Kx9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4831-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4831-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4831-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4831-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4831-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4831-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4831-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4831-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Double 4Kx9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4841-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4841-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4841-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4841-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4841-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4841-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4841-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4841-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Double 8Kx9 FIFO
Speed
(ns)
10
15
25
35
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4851-10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4851-10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4851-15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4851-15AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4851-25AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4851-25AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4851-35AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4851-35AI
A65
64-Lead Thin Quad Flatpack
Industrial
Document #: 38-06005 Rev. *A
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CY7C4801/4811/4821
CY7C4831/4841/4851
Package Diagram
64-Lead Thin Plastic Quad Flat Pack A65
Document #: 38-06005 Rev. *A
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© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4801/4811/4821
CY7C4831/4841/4851
Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync (TM) Fifos
Document Number: 38-06005
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106466
07/11/01
SZV
Change from Spec Number: 38-00538 to 38-06005
*A
122258
12/26/02
RBI
Power up requirements added to Operating Conditions Information
Document #: 38-06005 Rev. *A
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