Cypress CY7C1347F-166BGI 4-mbit (128k x 36) pipelined sync sram Datasheet

CY7C1347F
4-Mbit (128K x 36) Pipelined Sync SRAM
Functional Description[1]
Features
• Fully registered inputs and outputs for pipelined operation
• 128K by 36 common I/O architecture
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.
• 3.3V core power supply
• 2.5V/3.3V I/O operation
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP, 119-pin BGA and
165-pin fBGA packages
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial temperature
ranges
CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC®. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05213 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
CY7C1347F
Selection Guide
-250
-225
-200
-166
-133
Unit
Maximum Access Time
2.6
2.6
2.8
3.5
4.0
ns
Maximum Operating Current
325
290
265
240
225
mA
Maximum CMOS Standby Current
40
40
40
40
40
mA
Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts.
Pin Configurations
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
Document #: 38-05213 Rev. *D
Page 2 of 19
CY7C1347F
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC
NC
D
DQC
DQPC
VSS
NC
VSS
DQPB
DQB
E
F
DQC
VDDQ
DQC
DQC
VSS
VSS
CE1
DQB
DQB
DQB
VDDQ
G
H
J
DQC
DQC
VDDQ
DQC
DQC
VDD
BWC
VSS
NC
OE
ADV
GW
VDD
VSS
VSS
BWB
VSS
NC
DQB
DQB
VDD
DQB
DQB
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
NC
BWA
DQA
DQA
M
N
VDDQ
DQD
DQD
DQD
VSS
VSS
BWE
A1
VSS
VSS
DQA
DQA
VDDQ
DQA
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
T
NC
NC
A
NC
MODE
A
VDD
A
NC
A
A
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
165-Ball fBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
DQC
VSS
DQD
VDDQ
VDDQ
NC
VDDQ
VDD
DQB
NC
DQA
DQB
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC
A
A
NC
A1
NC
A
A
A
NC
MODE
NC
A
A
NC
A0
NC
A
A
A
A
Document #: 38-05213 Rev. *D
VDDQ
VSS
Page 3 of 19
CY7C1347F
Pin Definitions
Name
(BGA,FBGA)
Name
(100TQFP)
I/O
Description
A0,A1,A
A[16:0]
InputSynchronous
Address Inputs used to select one of the 128K address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feeds the 2-bit counter.
BWA,BWB,
BWC,BWD
BW[A:D]
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
GW
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:D] and BWE).
BWE
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
CLK
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
CE2
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
ADV
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
ZZ
InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
DQA, DQB
DQs
DQPs
DQC, DQD
DQPA, DQPB,
DQPC, DQPD
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
VDD
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
VSS
Ground
Ground for the core of the device.
VDDQ
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
VSSQ
I/O Ground
Ground for the I/O circuitry.
MODE
MODE
NC
NC
Document #: 38-05213 Rev. *D
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects.
Page 4 of 19
CY7C1347F
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (TCO) is 2.6 ns
(250-MHz device).
The CY7C1347F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Address Strobe from Processor
(ADSP) or the Address Strobe from Controller (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs (A[16:0])
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
Document #: 38-05213 Rev. *D
BW[A:D] signals. The CY7C1347F provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW[A:D]) input will selectively write to only the
desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs and DQPs is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1347F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Page 5 of 19
CY7C1347F
Linear Burst Sequence
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
First
Address
Fourth
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
11
00
01
00
01
10
Test Conditions
Min.
10
11
00
01
10
11
10
01
00
11
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Snooze mode standby current
ZZ > VDD − 0.2V
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to snooze current
This parameter is sampled
tRZZI
ZZ Inactive to exit snooze current
This parameter is sampled
Max.
Unit
40
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Truth Table[2, 3, 4, 5, 6]
Next Cycle
Add.
Used
Deselect Cycle, Power-down
None
CE1
H
Deselect Cycle, Power-down
None
L
L
X
L
L
X
X
X
X
L-H
three-state
Deselect Cycle, Power-down
None
L
X
H
L
L
X
X
X
X
L-H
three-state
Deselect Cycle, Power-down
None
L
L
X
L
H
L
X
X
X
L-H
three-state
Deselect Cycle, Power-down
None
L
X
H
L
H
L
X
X
X
L-H
three-state
Snooze Mode, Power-down
CE2
X
CE3
X
ZZ
L
ADSP ADSC ADV WRITE
X
L
X
X
OE
X
DQ
CLK
L-H three-state
None
X
X
X
H
X
X
X
X
X
X
three-state
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
three-state
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
three-state
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
three-state
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
three-state
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
three-state
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
three-state
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05213 Rev. *D
Page 6 of 19
CY7C1347F
Truth Table[2, 3, 4, 5, 6]
Next Cycle
Add.
Used
CE2
WRITE Cycle, Suspend Burst Current
CE1
X
WRITE Cycle, Suspend Burst Current
H
X
CE3
X
ZZ
L
X
X
L
ADSP ADSC ADV WRITE
H
H
H
L
X
H
H
L
OE
X
CLK
L-H
DQ
X
L-H
D
D
Partial Truth Table for Read/write[2, 7]
Function
Read
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write Byte A – DQA
Write Byte B – DQB
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C– DQC
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D– DQD
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05213 Rev. *D
Page 7 of 19
CY7C1347F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State ........................................... −0.5V to VDD + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature
VDD
VDDQ
0°C to +70°C
3.3V −5%/+10%
2.5V −5%
to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range [8, 9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH
Input LOW
Voltage[8]
Voltage[8]
Input Load Current except ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
0.7
V
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
−5
5
µA
GND ≤ VI ≤ VDDQ
−30
Input Current of MODE Input = VSS
Input = VDDQ
Input Current of ZZ
−5
Input = VSS
Input = VDDQ
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
−5
4-ns cycle, 250 MHz
µA
µA
30
µA
5
µA
325
mA
4.4-ns cycle, 225 MHz
290
mA
5-ns cycle, 200 MHz
265
mA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
4-ns cycle, 250 MHz
120
mA
4.4-ns cycle, 225 MHz
115
mA
5-ns cycle, 200 MHz
110
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133 MHz
ISB2
µA
5
All speeds
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f
Current—CMOS Inputs = 0
90
mA
40
mA
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05213 Rev. *D
Page 8 of 19
CY7C1347F
Electrical Characteristics Over the Operating Range (continued)[8, 9]
Parameter
ISB3
Description
Test Conditions
Automatic CE
Max. VDD, Device Deselected, or
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max.
Unit
4-ns cycle, 250 MHz
Min.
105
mA
4.4-ns cycle, 225 MHz
100
mA
5-ns cycle, 200 MHz
95
mA
6-ns cycle, 166 MHz
85
mA
7.5-ns cycle, 133 MHz
75
mA
45
mA
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Capacitance[10]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
BGA
Package
fBGA
Package
Unit
5
5
5
pF
5
5
5
pF
5
7
7
pF
TA = 25°C, f = 1
MHz,
VDD = 3.3V.
VDDQ = 3.3V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1ns
≤ 1ns
VL = 1.5V
(a)
ALL INPUT PULSES
VDDQ
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
VL = 1.25V
(a)
ALL INPUT PULSES
VDDQ
GND
5 pF
INCLUDING
JIG AND
SCOPE
R =1538Ω
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(c)
(b)
Thermal Resistance[10]
Parameter
Description
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TQFP
Package
BGA
Package
fBGA
Package
Unit
41.83
47.63
20.3
°C/W
9.99
11.71
4.6
°C/W
Note:
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05213 Rev. *D
Page 9 of 19
CY7C1347F
Switching Characteristics Over the Operating Range[15, 16]
-250
Parameter
Description
tPOWER
VDD(min.) to the first access
read or write [11]
tCYC
Min.
-225
Max.
Min.
-200
Max.
Min.
Max.
-166
Min.
Max.
-133
Min.
Max.
Unit
1
1
1
1
1
ms
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
ns
tAS
Address Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.4
tCO
Data Output Valid After CLK
Rise
tDOH
Data Output Hold After CLK
Rise
1.0
1.0
1.0
2.0
2.0
ns
tWES
GW, BWS[3:0] Set-up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
ns
tWEH
GW, BWS[3:0] Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
ns
tALS
ADV/LD Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
0.5
0.5
0.5
ns
tDS
Data Input Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
ns
tDH
Data Input Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
ns
tCES
Chip Enable Set-up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
ns
tCEH
Chip Enable Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
ns
tCHZ
Clock to High-Z[12, 13, 14]
tCLZ
Clock to Low-Z[12, 13, 14]
tEOHZ
OE HIGH to Output
High-Z[12, 13, 14]
tEOLZ
OE LOW to Output
Low-Z[12, 13, 14]
tEOV
OE LOW to Output Valid
0.5
2.6
2.6
0
0.5
2.6
2.6
0
2.6
0
2.6
2.8
4.0
0
3.5
0
2.8
ns
4.0
3.5
0
0
2.6
0.5
3.5
2.8
0
0
2.6
0.5
2.8
ns
ns
4.0
0
3.5
ns
ns
ns
4.5
ns
Notes:
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05213 Rev. *D
Page 10 of 19
CY7C1347F
Switching Waveforms
Read Cycle Timing[17]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BW[A:D]
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Notes:
17. On this diagram when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3is HIGH.
18. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05213 Rev. *D
Page 11 of 19
CY7C1347F
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
BURST READ
DON’T CARE
Document #: 38-05213 Rev. *D
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Page 12 of 19
CY7C1347F
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Note:
19. The data bus (Q)remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
20. GW is HIGH
Document #: 38-05213 Rev. *D
Page 13 of 19
CY7C1347F
Switching Waveforms (continued)
ZZ Mode Timing [21, 22]
CLK
t ZZ
ZZ
t ZZREC
t ZZI
I SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05213 Rev. *D
Page 14 of 19
CY7C1347F
Ordering Information
Speed
(MHz)
250
Ordering Code
CY7C1347F-250AC
CY7C1347F-250BGC
225
CY7C1347F-225AC
200
CY7C1347F-200AC
CY7C1347F-225BGC
BG119
A101
BG119
A101
BG119
CY7C1347F-200BZC
BB165C
CY7C1347F-200BGI
CY7C1347F-166AC
A101
BG119
A101
CY7C1347F-166BGC
BG119
CY7C1347F-166BZC
BB165C
CY7C1347F-166AI
133
A101
CY7C1347F-200BGC
CY7C1347F-200AI
166
Package
Name
A101
CY7C1347F-166BGI
BG119
CY7C1347F-133AC
A101
CY7C1347F-133BGC
BG119
CY7C1347F-133BZC
BB165C
CY7C1347F-133AI
CY7C1347F-133BGI
A101
BG119
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
165-Ball FBGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05213 Rev. *D
Page 15 of 19
CY7C1347F
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05213 Rev. *D
Page 16 of 19
CY7C1347F
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05213 Rev. *D
Page 17 of 19
CY7C1347F
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.20 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
1
Ø0.25 M C A B
2
3
4
5
6
7
8
9
10
Ø0.45±0.05(165X)
11
11
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
J
14.00
E
17.00±0.10
E
H
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
10.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
15.00±0.10
0.15(4X)
SEATING PLANE
0.36
C
B
1.40 MAX.
0.25 C
10
51-85165-*A
Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of International Business
Machines, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05213 Rev. *D
Page 18 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347F
Document History Page
Document Title: CY7C1347F 4-Mbit (128K x 36) Pipelined Sync SRAM
Document Number: 38-05213
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
119829
12/16/02
HGK
New Data Sheet
*A
123117
01/18/03
RBI
Added power-up requirements to AC test loads and waveforms information
*B
127632
06/13/03
DPM
Final Data Sheet
*C
200660
See ECN
SWI
Improvements:
Updated thermal resistance and capacitance
Updated R5 pin of 119-Ball BGA from VDD to NC
Updated all switching waveforms
Clarifications:
Updated footnotes
Updated ZZ mode electrical characteristics
*D
213342
See ECN
VBL
Update Ordering Info section: Delete -100, shade -250, -225
Delete -100, Shade -250, -225 data from selection guide and characteristics
Document #: 38-05213 Rev. *D
Page 19 of 19
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