White Electronic Designs EDI88257CA 256Kx8 Monolithic SRAM FEATURES The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. Access Times of 20, 25, 35, 45, 55ns Data Retention Function (LPA Versions) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 256Kx8 Commercial, Industrial and Military Temperature Ranges JEDEC Approved Evolutionary Pinout The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the two megabit device. The device is upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order address. A Low Power version, EDI88257LPA, offers a data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) This product is subject to change without notice. Single +5V (±10%) Supply Operation FIGURE 1 – PIN CONFIGURATION PIN DESCRIPTION 32 DIP TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 I/O0-7 A0-17 WE# CS# OE# VCC VSS NC VCC A15 A17 WE# A13 A8 A9 A11# OE A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected BLOCK DIAGRAM Memory Array A0-17 Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88257CA ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ TRUTH TABLE Value -0.5 to 7.0 Unit V -40 to +85 -55 to +125 -65 to +150 1.5 20 175 °C °C °C W mA °C OE# X H L X CS# H L L L WE# X H H L Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power ICC2, ICC3 ICC1 ICC1 ICC1 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 VCC +0.5 +0.8 Unit V V V V CAPACITANCE Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 12 14 Unit pF pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5V, TA = +25°C Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Conditions VIN = 0V to VCC VI/O = 0V to VCC Operating Power Supply Current ICC1 WE#, CS# = VIL, II/O = 0mA, Min Cycle Standby (TTL) Power Supply Current ICC2 Full Standby Power Supply Current ICC3 Output Low Voltage Output High Voltage VOL VOH CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH CS# ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V IOL = 8.0mA IOH = -4.0mA (20-25ns) (35-55ns) C LP Min -10 -10 — — — — — — 2.4 Typ — — Max +10 +10 225 200 60 25 20 0.4 — — — — — Units µA µA mA mA mA mA mA V V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Q Input Pulse Levels Vcc 480Ω 30pF Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V Output Load Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 Q 255Ω VSS to 3.0V 255Ω 5pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88257CA AC CHARACTERISTICS – READ CYCLE VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ 20ns Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ Min 20 25ns Max Min 25 20 20 3 0 0 Min 35 3 0 0 3 0 0 15 12 0 0 8 Min 45 10 15 Min 55 Max 45 45 3 0 0 20 15 0 0 55ns Max 35 35 10 10 45ns Max 25 25 8 0 0 35ns Max 55 55 3 0 0 20 25 0 0 20 25 0 0 20 Units ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C Symbol Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) 20ns 25ns Max Min 25 35ns Alt. tWC Min 20 tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tCW tCW tAS tAS tAW tAW tWP tWP 15 15 0 0 15 15 15 15 17 17 0 0 17 17 17 17 25 25 0 0 25 25 25 25 30 30 0 0 30 30 30 30 30 30 0 0 30 30 30 30 ns ns ns ns ns ns ns ns tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWR tWR tDH tDH tWHZ tDW tDW tWLZ 0 0 0 0 0 10 10 0 0 0 0 0 0 12 12 0 0 0 0 0 0 20 20 0 0 0 0 0 0 25 25 0 0 0 0 0 0 25 25 0 ns ns ns ns ns ns ns ns 30 Min 35 Max 25 Min 45 55ns JEDEC tAVAV 30 Max 45ns Max 30 Min 55 Max 30 Units ns 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88257CA FIGURE 2 – TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS tAVQV CS# tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE# DATA I/O DATA 1 DATA OUT DATA 2 READ CYCLE 2 (WE# HIGH) READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) FIGURE 3 – WRITE CYCLE - WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS# tAVWL tWLWH WE# tWHDX tDVWH DATA IN DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE# CONTROLLED FIGURE 4 – WRITE CYCLE - CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH tEHAX CS# tAVEL tWLEH WE# tDVEH DATA IN DATA OUT tEHDX DATA VALID HIGH Z WRITE CYCLE 2, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88257CA DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY) -55°C ≤ TA ≤ +125°C Characteristic Low Power Version only Sym Conditions Min Typ Max Units Data Retention Voltage Data Retention Quiescent Current VCC ICCDR VCC = 2.0V CS# ≥ VCC -0.2V 2 – – – – 2 V µA Chip Disable to Data Retention Time Operation Recovery Time tCDR TR VIN ≥ VCC -0.2V or VIN ≤ 0.2V 0 tAVAV – – – – ns ns FIGURE 5 – DATA RETENTION - CS# CONTROLLED DATA RETENTION MODE 4.5V VCC VCC 4.5V tCDR CS# tR CS# = VCC -0.2V DATA RETENTION, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88257CA PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.200 0.125 0.061 0.017 0.155 0.115 0.100 TYP 0.020 0.016 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 257 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com