AD AD7357YRUZ-RL Differential input,dual,simultaneous sampling, 4.25 msps, 14-bit, sar adc Datasheet

Preliminary Technical Data
Differential Input,Dual,Simultaneous
Sampling, 4.25 MSPS, 14-Bit, SAR ADC
AD7357
FEATURES
Dual 14-bit SAR ADC
Simultaneous Sampling
Throughput rate: 4.25 MSPS Per Channel
Specified for VDD of 2.5 V
Power dissipation:
35 mW at 4.25 MSPS
On-chip reference:
2.048 V ± 0.5% max @ 25°C, 10ppm/°C
Dual conversion with read
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
−40°C to +125°C operation
Shutdown mode: 10 µA max
16-lead TSSOP package
FUNCTIONAL BLOCK DIAGRAM
Vdrive
Vdd
AD7357
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
VINA+
T/H
VINA-
SDATAA
BUF
CONTROL
LOGIC
REF
SCLK
CS
BUF
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
VINB+
VINB-
T/H
AGND
SDATAB
AGND REFGND DGND
Figure 1.
GENERAL DESCRIPTION
The AD73571 is a dual, 14-bit, high speed, low power, successive
approximation ADC that operates from a single 2.5 V power supply
and features throughput rates up to 4.25 MSPS. The part contains
two ADCs, each preceded by a low noise, wide bandwidth trackand-hold circuit that can handle input frequencies in excess of
200 MHz.
The conversion process and data acquisition use standard control
inputs allowing for easy interfacing to microprocessors or DSPs.
The input signal is sampled on the falling edge of CS; conversion is
also initiated at this point. The conversion time is determined by
the SCLK frequency.
The AD7357 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 2.5 V supply and
a 4.25 MSPS throughput rate, the part consumes 14 mA typically.
The part also offers flexible power/throughput rate management
when operating in normal mode as the quiescent current
consumption is so low.
The analog input range for the part is the differential common
mode +/- Vref/2. The AD7357 has an on-chip 2.048 V reference
that can be overdriven when an external reference is preferred.
PRODUCT HIGHLIGHTS
1.
Two Complete ADC Functions Allow Simultaneous Sampling
and Conversion of Two Channels.
The conversion result of both channels is simultaneously
available on separate data lines or in succession on one data
line if only one serial port is available.
2.
High Throughput with Low Power Consumption.
The AD7357 offers a 4.25 MSPS throughput rate with 35 mW
power consumption.
3.
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
CS input and once off conversion control.
1
Protected by U.S. Patent No. 6,681,332
Table 1: Related Devices.
Generic
AD7356
AD7352
Resolution
12
12
Throughput
5MSPS
3MSPS
Analog Input
Differential
Differential
The AD7357 is available in a 16-lead thin shrink small outline
package (TSSOP).
Rev. PrD
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD7357
Preliminary Technical Data
TABLE OF CONTENTS
Revision Historyx ............................................................................. 2
ADC Transfer Function............................................................. 11
Specifications..................................................................................... 3
Analog Input Structure.............................................................. 11
AD7357 Specifications................................................................. 3
Analog Inputs ............................................................................. 12
Timing Specifications .................................................................. 5
Modes of Operation ....................................................................... 13
Absolute Maximum Ratings............................................................ 6
Normal Mode.............................................................................. 13
ESD Caution.................................................................................. 6
Partial Power-Down Mode ....................................................... 13
Pin Configuration and Function Descriptions............................. 7
Full Power-Down Mode ............................................................ 13
Typical Performance Characteristics ............................................. 8
Power-Up Times......................................................................... 15
Terminology ...................................................................................... 9
Serial Interface ................................................................................ 16
Theory of Operation ...................................................................... 11
Outline Dimensions ....................................................................... 17
Circuit Information.................................................................... 11
Ordering Guide............................................................................... 17
Converter Operation.................................................................. 11
REVISION HISTORYX
09/07—Revision PrD
Rev. PrD | Page 2 of 17
Preliminary Technical Data
AD7357
SPECIFICATIONS
AD7357 SPECIFICATIONS
VDD = 2.5 +/-10% V, VDRIVE = 2.5 V to 3.3 +10% V, internal VREF = 2.048 V, unless otherwise noted, FCLKIN = 80 MHz, FSAMPLE = 4.25 MSPS;
TA = TMIN to TMAX1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
SAMPLE AND HOLD
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Error Match
Gain Error
Gain Error Match
ANALOG INPUT
Fully Differential Input Range: Vin+ and Vin−
DC Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
VREF Input Voltage Range
DC Leakage Current
VREF Output Voltage
VREF Temperature Coefficient
VREF Long Term Stability
VREF Output Voltage Hysteresis2
VREF Noise
VREF Output Impedance
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
Specification
Unit
Test Conditions/Comments
fIN = 1 MHz sine wave
78
77
TBD
TBD
dB min
dB min
dB max
dB max
TBD
TBD
−85
dB typ
dB typ
dB typ
fIN = TBD kHz, fNOISE = TBD kHz
5
40
15
200
30
ns max
ps max
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
14
±2
±0.99
±10
±1
±6
±10
±1
±6
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
VCM ± VREF⁄2
V
±1
35
10
µA max
pF typ
pF typ
2.048+100mV / Vdd
±1
2.048
10
100
50
TBD
TBD
TBD
V min / V max
µA max
V
ppm⁄°C typ
ppm typ
ppm typ
µV Typ
Ω Typ
pF typ
0.6 × Vdrive
0.3 × Vdrive
±1
10
V min
V max
µA max
pF typ
fa = TBD Hz, fb = TBD Hz
Rev. PrD | Page 3 of 17
Guaranteed no missed codes to 14 bits
VCM = common-mode voltage , Vin+ and Vin− must
remain within GND⁄VDD
When in track
When in hold
±0.5% max @ 25°C
For 1000 hours
When in track
VIN = 0 V or VDRIVE
AD7357
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD
Normal Mode (Operational)
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
1
2
Preliminary Technical Data
Specification
Vdrive-0.2
0.2
±1
TBD
Unit
Test Conditions/Comments
V min
V max
µA max
pF typ
Straight Binary
t2 + 15.5 × tSCLK
30
4.25
ns
ns max
MSPS max
2.5
2.5/3.3
V
V min/max
14
7
5
10
mA typ
mA typ
mA typ
µA typ
35
17.5
12.5
2.5
mW typ
mW typ
mW typ
µW typ
Full-scale step input
Digital I⁄PS = 0 V or VDRIVE
Temperature ranges are as follows: Y Grade: −40°C to +125°C, B Grade: −40°C to +85°C.
See theTerminology section.
Rev. PrD | Page 4 of 17
SCLK off
SCLK on or off
SCLK off
SCLK on or off
Preliminary Technical Data
AD7357
TIMING SPECIFICATIONS
VDD = 2.5 +/-10%V, VDRIVE = 2.5 V to 3.3 +10% V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN , TMAX
Unit
fSCLK
50
80
t2 +15.5 × tSCLK
5
kHz min
MHz max
ns max
ns min
tCONVERT
tQUIET
t2
t3
t42
t5
t6
t7
t8
t9
t10
Latency
1
2
5
TBD
TBD
0.40 tSCLK
0.40 tSCLK
TBD
TBD
TBD
TBD
TBD
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
1 Conversion Latency
Description
14 bit resolution, tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until DOUTA and DOUTB are three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to DOUTA, DOUTB, high impedance
CS rising edge to falling edge pulse width
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
Temperature ranges are as follows: Y Grade: −40°C to +125°C, B Grade: −40°C to +85°C.
The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrD | Page 5 of 17
AD7357
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to AGND, DGND, REFGND
VDRIVE to AGND, DGND, REFGND
VDD to VDRIVE
AGND to DGND to REFGND
Analog Input Voltages1 to AGND
Digital Input Voltages2 to DGND
Digital Output Voltages3 to DGND
Input Current to Any Pin Except
Supplies4
Operating Temperature Range
Y Grade
B Grade
Storage Temperature Range
Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 to 30 sec)
ESD
Rating
−0.3 V to +2.8V
−0.3 V to +3.8V
+2.8V to −3.8V
−0.3 V to +0.3 V
−0.3 V to VDD + 0.3 V
−0.3V to VDRIVE + 0.3V
−0.3 V to VDRIVE + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +125°C
−40°C to +85°C
−65°C to +150°C
150°C
143°C/W
45°C/W
255°C
TBD kV
1
Analog input voltages are VINA+, VINA-, VINB+, VINB-, REFA and REFB.
Digital input voltages are CS and SCLK.
3
Digital output voltages are SDATAA and SDATAB.
4
Transient currents of up to 100 mA will not cause SCR latch up.
2
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Rev. PrD | Page 6 of 17
Preliminary Technical Data
AD7357
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VINA+ 1
16
VDRIVE
VINA-
2
15
SCLK
REFA 3
14
SDATAA
13
SDATAB
12
DGND
REFGND 4
AGND 5
AD7357
TOP VIEW
(Not to Scale)
REFB
6
11
AGND
VINB-
7
10
CS
9
VDD
VINB+ 8
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
9
VDD
16
VDRIVE
10
CS
15
SCLK
14,13
SDATAA,
SDATAB
12
DGND
5, 11
AGND
4
REFGND
3, 6
REFA, REFB
1, 2
8, 7
VINA-, VINA+
VINB-, VINB+
Power Supply Input. The VDD range for the AD7357 is 2.5V +/- 5%. The supply should be decoupled to AGND
with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7357 and framing the serial data transfer.
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This
clock is also used as the clock source for the conversion process.
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the
AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by
a trailing zero. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two
further trailing zeros will appear after the 14 bits of data. If CS is held low for a further 18 SCLK cycles on either
SDATAA or SDATAB , the data from the other ADC follows on the SDATA pin. This allows data from a
simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input
signals and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.
Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between
this pin and the REFA and REFB pins.
Reference decoupling capacitor pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple the each
reference pin with a 10µF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048V
and this appears at these pins. These pins can also be overdriven by an external reference. The input voltage
range for the external reference is 2.048+100mV to Vdd.
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
Rev. PrD | Page 7 of 17
AD7357
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Typical FFT
Figure 6. Channel to Channel Isolation
Figure 4. Typical DNL
Figure 7. Histogram of Codes
Figure 5. Typical INL
Rev. PrD | Page 8 of 17
Preliminary Technical Data
AD7357
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, 1 LSB below the first code
transition, and full scale, 1 LSB above the last code transition.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
CMRR (dB) = 10log (Pf/PfS)
where:
Offset Error
The deviation of the first code transition (00 . . .000) to (00 . . .
001) from the ideal (that is, -VREF + 0.5 LSB).
Offset Error Match
This is the difference in offset error between the two ADCs.
Gain Error
The deviation of the last code transition (111 . . .110) to (111 . . .
111) from the ideal (that is, VREF – 1.5 LSB) after the offset error
has been adjusted out.
Gain Error Match
The difference in gain error between the two ADCs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale sine wave signal to one of the two channels and applying a
50 kHz signal to the other channel. The channel-to-channel
isolation is defined as the ratio of the power of the 50 kHz
signal on the converted channel to the power of the noise signal
on the other channel that appears in the FFT of this channel.
The noise frequency on the unselected channel varies from
40 kHz to 740 kHz. The noise amplitude is at 2 × VREF, while the
signal amplitude is at 1 × VREF. See Figure 6.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the input varies from 1 kHz to 1 MHz.
PSRR (dB) = 10log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
The theoretical signal-to-noise and distortion ratio for an ideal
N-bit converter with a sine wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB and for a 14 bit
converter, this is 86dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7356, it is defined as
THD (dB ) = −20log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Rev. PrD | Page 9 of 17
AD7357
Preliminary Technical Data
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb), and (fa − 2fb).
The AD7356 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Thermal Hysteresis
Thermal Hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
T_HYS– = +25°C to TMIN to +25°C
It is expressed in ppm using the following equation:
VHYS ( ppm) =
VREF (25°C ) − VREF (T _ HYS)
× 10 6
VREF (25°C )
where:
VREF(25°C) = VREF at 25°C
VREF(T_HYS) = Maximum change of VREF at T_HYS+ or
T_HYS–.
Rev. PrD | Page 10 of 17
Preliminary Technical Data
AD7357
The AD7357 is a fast, dual, 14-bit, single-supply, successive
approximation analog-to-digital converter. The part operates
from a 2.5 V power supply and features throughput rates up to
4.25 MSPS.
The AD7357 contains two on-chip differential track-and-hold
amplifiers, two successive approximation analog-to-digital
converters and a serial interface with two separate data output
pins. They part is housed in a 16-lead TSSOP package, offering
the user considerable space-saving advantages over alternative
solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The AD7357 has an on-chip 2.048V reference. If an
external reference is desired the internal reference can be
overdriven with a reference of value ranging from (2.048V +
100mV) to Vdd. If the internal reference is to be used elsewhere
in the system, then the reference output needs to be buffered
first. The differential analog input range for the AD7357 is VCM
± VREF∕2.
The AD7357 features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7357 has two successive approximation analog-todigital converters, each based around two capacitive DACs.
Figure 8 and Figure 9 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 8 (the acquisition phase), SW3 is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays may
acquire the differential signal on the input.
CS
VIN+
VIN–
A
SW2
CS
A SW1
A
VIN–
SW3
SW2
CS
SW3
CONTROL
LOGIC
B
VREF
CAPACITIVE
DAC
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7357 is straight binary. The
designed code transitions occur at successive LSB values (1 LSB,
2 LSBs and so on). The LSB size is (2 ×VREF)/16384 for the
AD7357. The ideal transfer characteristic of the AD7357 is
shown in Figure 10.
111...111
111...110
111...101
–VREF+1 LSB
–VREF+0.5 LSB
+VREF–1 LSB
+VREF–1.5 LSB
ANALOG INPUT
COMPARATOR
A SW1
COMPARATOR
CS
B
VIN+
000...010
000...001
000...000
CAPACITIVE
DAC
B
CAPACITIVE
DAC
04603-014
CIRCUIT INFORMATION
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the VIN+ and VIN- pins must be matched,
otherwise, the two inputs will have different settling times,
resulting in errors.
ADC CODE
THEORY OF OPERATION
CONTROL
LOGIC
Figure 10. AD7356 Ideal Transfer Characteristic
B
CAPACITIVE
DAC
04603-013
ANALOG INPUT STRUCTURE
VREF
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion (Figure 9), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
Figure 11 shows the equivalent circuit of the analog input
structure of the AD7357. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300mV. This causes these diodes to become forwardbiased and start conducting into the substrate. These diodes can
Rev. PrD | Page 11 of 17
AD7357
Preliminary Technical Data
conduct up to 10mA without causing irreversible damage to the
part.
The C1 capacitors in Figure 11 are typically TBD pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about TBD Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of TBD pF typically.
be tolerated. The THD increases as the source impedance
increases and performance degrades. Figure 12 shows a graph
of the THD vs. the analog input signal frequency for different
source impedances.
Figure 13 shows a graph of the THD vs. the analog input
frequency while sampling at 4.25 MSPS. In this case the source
impedance is TBD Ω.
VDD
D
VIN+
C1
R1 C2
D
VDD
D
VIN–
D
04603-015
C1
R1 C2
Figure 13.THD vs. Analog Input Frequency
Figure 11.Equivalent Analog Input Circuit,
Conversion Phase – Switches Open, Track Phase – Switches Closed
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the analog input pins. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC and may necessitate the use of an input buffer
amplifier. The choice of the op amp will be a function of the
particular application.
ANALOG INPUTS
Differential signals have some benefits over single-ended
signals, including noise immunity based on the devices
common-mode rejection and improvements in distortion
performance.
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN- pins in each
differential pair (VIN+ - VIN-). VIN+ and VIN- should be
simultaneously driven by two signals each of amplitude VREF
that are 180° out of phase. This amplitude of the differential
signal is, therefore –VREF to +VREF peak-to –peak regardless of
the common mode (CM).
The common mode is the average of the two signals and is
therefore the voltage on which the two inputs are centered.
CM = (VIN+ + VIN-)/2
This results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally. When a conversion takes
place, the common mode is rejected resulting in a virtually
noise free signal of amplitude –VREF to +VREF corresponding to
the digital codes of 0 to 16383 for the AD7357.
Figure 12.THD vs. Analog Input Frequency for Various Source Impedances
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of THD that can
Rev. PrD | Page 12 of 17
Preliminary Technical Data
AD7357
MODES OF OPERATION
The mode of operation of the AD7357 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial powerdown mode and full power-down mode. After a conversion has
been initiated, the point at which CS is pulled high determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for the
differing application requirements.
NORMAL MODE
This mode is intended for applications needing fastest
throughput rates since the user does not have to worry about
any power-up times with the AD7357 remaining fully powered
at all times. Figure 14 shows the general diagram of the
operation of the AD7357 in this mode.
CS
10
14
LEADING ZEROS + CONVERSION RESULT
04603-029
DOUTA
DOUTB
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7357 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffers.
To enter partial power, the conversion process must be
interrupted by bringing CS high anywhere after the 2nd falling
edge of SCLK and before the 10th falling edge of SCLK, as
shown in Figure 15. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and SDATAA and SDATAB go back into three-state.
If CS is brought high before the 2nd SCLK falling edge, the part
remains in normal mode and does not power down. This avoids
accidental power-down due to glitches on the CS line.
CS
1
Figure 14. Normal Mode Operation
2
10
14
SCLK
The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10th SCLK falling
edge but before the 16th SCLK falling edge, the part remains
powered up, but the conversion is terminated and SDATAA and
SDATAB go back into three-state. 16 serial clock cycles are
required to complete the conversion and access the conversion
result for the AD7357. The SDATA lines do not return to threestate after 16 SCLK cycles have elapsed, but instead do so when
CS is brought high again. If CS is left low for another 2 SCLK
cycles, two trailing zeros are clocked out after the data. If CS is
left low for a further 16 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line as
shown in Figure 20 (see the Serial Interface section).
Once 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32nd SCLK falling edge. If CS is brought high
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion if so desired,
since the bus still returns to three-state upon completion of the
dual result read.
DOUTA
DOUTB
THREE-STATE
04603-030
1
SCLK
Once a data transfer is complete and SDATAA and SDATAB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time has been allowed).
Figure 15. Entering Partial Power-Down Mode
To exit this mode of operation and power up the AD7357 again,
a dummy conversion is performed. On the falling of CS, the
device begins to power up, and continues to power up as long as
CS is held low until after the falling edge of the 10th SCLK. The
device is fully powered up after approximately TBD μs has
elapsed, and valid data results from the next conversion, as
shown in Figure 16. If CS is brought high before the 2nd falling
edge of SCLK, the AD7357 again goes into partial power-down.
This avoids accidental power-up due to glitches on the CS line.
Although the device may begin to power up on the falling edge
of CS, it powers down again on the rising edge of CS. If the
AD7357 is already in partial power-down mode and CS is
brought high between the 2nd and 10th falling edges of SCLK, the
device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from a partial power-down. This
Rev. PrD | Page 13 of 17
AD7357
Preliminary Technical Data
has been brought high in this window of SCLKs, the part
completely powers down.
mode is more suited to applications where a series of
conversions performed at a relatively high throughput rate are
followed by a long period of inactivity and thus, power-down.
When the AD7357 is in full power-down, all analog circuitry is
powered down. Full power-down is entered in a similar way as
partial power-down, except the timing sequence shown in
Figure 15 must be executed twice. The conversion process must
be interrupted in a similar fashion by bringing CS high
anywhere after the 2nd falling edge of SCLK and before the 10th
falling edge of SCLK. The device enters partial power down at
this point.
Note that it is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down mode and power-up the AD7357, a
dummy conversion is performed, as when powering up from
partial power-down. One the falling edge of CS , the device
begins to power up, as long as CS is held low until after the
falling edge of the 10th SCLK. The required power-up time must
elapse before a conversion can be initiated, as shown in Figure
18.
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 17. Once CS
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
THE PART BEGINS
TO POWER UP.
tPOWER-UP1
CS
1
10
14
1
14
DOUTA
INVALID DATA
DOUTB
04603-031
SCLK
VALID DATA
Figure 16. Exiting Partial Power-Down Mode
THE PART ENTERS
PARTIAL POWER DOWN.
THE PART BEGINS
TO POWER UP.
THE PART ENTERS
FULL POWER DOWN.
CS
1
2
DOUTA
10
14
1
2
10
THREE-STATE
THREE-STATE
INVALID DATA
DOUTB
14
INVALID DATA
04603-032
SCLK
Figure 17. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
DOUTA
DOUTB
10
1
14
INVALID DATA
14
1
VALID DATA
Figure 18. Exiting Full Power-Down Mode
Rev. PrD | Page 14 of 17
04603-033
SCLK
Preliminary Technical Data
AD7357
POWER-UP TIMES
The AD7357 has two power-down modes, partial power-down
and full power-down, which are described in detail in the
previous sections. This section deals with the power-up time
required when coming out of either of these modes.
To power up from partial power-down mode, one dummy cycle
is required. The device is fully powered up after approximately
TBD µs from the falling edge of CS has elapsed. Once the
partial power-up time has elapsed, the ADC is fully powered up
and the input signal is acquired properly. The quiet time, tQUIET,
must still be allowed from the point where the bus goes back
into three-state after the dummy conversion to the next falling
edge of CS.
To power up from full power-down, approximately TBD μs
should be allowed from the falling edge of CS, shown in Figure
18 as tPOWER-UP2.
When power supplies are first applied to the AD7357, the ADC
can power up in either of the power-down modes or in normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the part is to be kept
in partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge; in the second cycle, CS must be brought high between the
second and 10th SCLK falling edges (see Figure 15).
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge; the second and third dummy cycles
place the part into full power-down mode (see Figure 17). See
the Modes of Operation section.
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is powered
down, returns to track mode after the first SCLK edge that the
part receives after the falling edge of CS.
Rev. PrD | Page 15 of 17
AD7357
Preliminary Technical Data
SERIAL INTERFACE
Figure 19 shows the detailed timing diagram for serial
interfacing to the AD7357. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7357 during conversion.
A minimum of 16 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7357. CS going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 14-bit
result then follows with the final bit in the data transfer valid on
the 16th falling edge, having being clocked out on the previous
(15th) falling edge. In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the CS
falling edge would have the second leading zero provided, and
the 15th rising SCLK edge would have DB0 provided.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode at
which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 16 SCLKs to complete. Once 15
SCLK falling edges have elapsed, the track and hold will go back
into track on the next SCLK rising edge, as shown in Figure 19
at point B. On the rising edge of CS, the conversion will be
terminated and SDATAA and SDATAB will go back into threestate. If CS is not brought high, but is instead held low for a
further 16 SCLK cycles on SDATAA, the data from the
conversion on ADCB will be output on SDATAA.
Likewise, if CS is held low for a further 16 SCLK cycles on
SDATAA, the data from the conversion on ADCA will be output
on SDATAB. This is illustrated in Figure 20 where the case for
SDATAA is shown. In this case, the SDATA line in use will go
back into three-state on the 32nd SCLK falling edge or the rising
edge of CS, which ever occurs first.
t ACQUISITION
CS
t9
t CONVERT
t2
t6
SCLK
1
3
2
4
t3
t4
DOUTA
0
DB13
0
DOUTB THREESTATE
2 LEADING ZEROS
DB12
B
5
15
16
t5
t7
DB11
DB2
DB10
t8
DB0
DB1
0
tQUIET
THREE-STATE
Figure 19. Serial Interface Timing Diagram
CS
t6
t2
SCLK
1
2
3
5
4
16
15
18
17
31
32
t5
t3
DOUTA
0
0
THREESTATE 2 LEADING
ZEROS
t4
DB13A
DB12 A
DB11 A
t7
DB0 A
0
0
DB13 B
DB12B
2 ZEROS
Figure 20. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
Rev. PrD | Page 16 of 17
DB1 B
DB0 B
0
THREESTATE
Preliminary Technical Data
AD7357
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 21. 16-LeadThin Shrink Small Outline Package
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7357BRUZ
AD7357BRUZ-500RL7
AD7357BRUZ-RL
AD7357YRUZ
AD7357YRUZ-500RL7
AD7357YRUZ-RL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06003-0-9/07(PrD)
Rev. PrD | Page 17 of 17
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
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