Revised January 2004 MM74C925 • MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers General Description Features The MM74C925 and MM74C926 CMOS counters consist of a 4-digit counter, an internal output latch, NPN output sourcing drivers for a 7-segment display, and an internal multiplexing circuitry with four multiplexing outputs. The multiplexing circuit has its own free-running oscillator, and requires no external clock. The counters advance on negative edge of clock. A HIGH signal on the Reset input will reset the counter to zero, and reset the carry-out LOW. A LOW signal on the Latch Enable input will latch the number in the counters into the internal output latches. A HIGH signal on Display Select input will select the number in the counter to be displayed; a LOW level signal on the Display Select will select the number in the output latch to be displayed. ■ Wide supply voltage range: The MM74C925 is a 4-decade counter and has Latch Enable, Clock and Reset inputs. The MM74C926 is like the MM74C925 except that it has a display select and a carry-out used for cascading counters. The carry-out signal goes HIGH at 6000, goes back LOW at 0000. 3V to 6V ■ Guaranteed noise margin: 1V ■ High noise immunity: 0.45 VCC (typ.) ■ High segment sourcing current: 40 mA @ VCC − 1.6V, VCC = 5V ■ Internal multiplexing circuitry Design Considerations Segment resistors are desirable to minimize power dissipation and chip heating. The DS75492 serves as a good digit driver when it is desired to drive bright displays. When using this driver with a 5V supply at room temperature, the display can be driven without segment resistors to full illumination. The user must use caution in this mode however, to prevent overheating of the device by using too high a supply voltage or by operating at high ambient temperatures. The input protection circuitry consists of a series resistor, and a diode to ground. Thus input signals exceeding VCC will not be clamped. This input signal should not be allowed to exceed 15V. Ordering Code: Order Number Package Number Package Description MM74C925N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74C926N N18B 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagrams Pin Assignments for DIP Top View MM74C925 © 2004 Fairchild Semiconductor Corporation Top View MM74C926 DS005919 www.fairchildsemi.com MM74C925 • MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers October 1987 MM74C925 • MM74C926 Functional Description Reset Segment Output — Current sourcing with 40 mA @VOUT = VCC − 1.6V (typ.) Also, sink capability = 2 LTTL loads — Asynchronous, active high Display Select — High, displays output of counter Low, displays output of latch Digit Output — Current sourcing with 1 mA @VOUT = 1.75V. Also, sink capability = 2 LTTL loads Latch Enable — High, flow through condition Low, latch condition Clock Carry-Out —Negative edge sensitive Logic Diagrams MM74C925 MM74C926 www.fairchildsemi.com 2 — 2 LTTL loads. See carry-out waveforms. GND − 0.3V to VCC + 0.3V Voltage at Any Output Pin GND − 0.3V to +15V Voltage at Any Input Pin Operating Temperature −40°C to +85°C Range (TA) −65°C to +150°C Storage Temperature Range Power Dissipation (PD) Refer to PD(MAX) vs TA Graph Operating VCC Range Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. 3V to 6V VCC 6.5V Lead Temperature 260°C (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply at −40°C ≤ tj≤ + 85°C, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage VCC = 5V VIN(0) Logical “0” Input Voltage VCC = 5V VOUT(1) Logical “1” Output Voltage VCC = 5V, IO = −10 µA 3.5 V 1.5 (Carry-Out and Digit Output Only) 4.5 VOUT(0) Logical “0” Output Voltage VCC = 5V, IO = 10 µA IIN(1) Logical “1” Input Current VCC = 5V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 5V, VIN = 0V ICC Supply Current VCC = 5V, Outputs Open Circuit, V 0.005 −1 V 0.5 V 1 µA −0.005 20 µA 1000 µA 0.8 V VIN = 0V or 5V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VOUT(1) VOUT(0) VCC − 2 Logical “1” Output Voltage VCC = 4.75V, (Carry-Out and Digit Output Only) IO = −360 µA Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE VOUT RON Output Voltage IOUT = −65 mA, VCC = 5V, Tj = 25°C (Segment Sourcing Output) IOUT = −40 mA, VCC = 5V VCC − 2 VCC − 1.3 V Tj = 100°C VCC − 1.6 VCC − 1.2 V Tj = 150°C VCC − 2 VCC − 1.4 V Output Resistance IOUT = −65 mA, VCC = 5V, Tj = 25°C 20 32 Ω (Segment Sourcing Output) IOUT = −40 mA, VCC = 5V Tj = 100°C 30 40 Ω Tj = 150°C 35 50 Ω 0.6 0.8 %/°C Output Resistance (Segment Output) Temperature Coefficient ISOURCE Output Source Current VCC = 4.75V, VOUT = 1.75V, Tj = 150°C −1 −2 mA −1.75 −3.3 mA 1.75 3.6 mA (Digit Output) ISOURCE Output Source Current VCC = 5V, VOUT = 0V, Tj = 25°C (Carry-Out) ISINK Output Sink Current VCC = 5V, VOUT = VCC, Tj = 25°C (All Outputs) θjA Thermal Resistance MM74C925: (Note 2) 75 100 °C/W MM74C926 70 90 °C/W Note 2: θjA measured in free-air with device soldered into printed circuit board. 3 www.fairchildsemi.com MM74C925 • MM74C926 Absolute Maximum Ratings(Note 1) MM74C925 • MM74C926 AC Electrical Characteristics (Note 3) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol fMAX Parameter Maximum Clock Frequency Conditions VCC = 5V, Tj = 25°C Square Wave Clock Tj = 100°C tr, tf Maximum Clock Rise or Fall Time VCC = 5V tWR Reset Pulse Width VCC = 5V tWLE Latch Enable Pulse Width tSET(CK, LE) Clock to Latch Enable Set-Up Time Min Typ 2 4 1.5 3 Max MHz MHz 15 VCC = 5V VCC = 5V Units µs Tj = 25°C 250 100 ns Tj = 100°C 320 125 ns Tj = 25°C 250 100 ns Tj = 100°C 320 125 ns Tj = 25°C 2500 1250 ns Tj = 100°C 3200 1600 ns 0 −100 ns ns tLR Latch Enable to Reset Wait Time VCC = 5V Tj = 25°C Tj = 100°C 0 −100 tSET(R, LE) Reset to Latch Enable Set-Up Time VCC = 5V Tj = 25°C 320 160 ns Tj = 100°C 400 200 ns fMUX Multiplexing Output Frequency VCC = 5V CIN Input Capacitance Any Input (Note 4) 1000 Hz 5 pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Typical Performance Characteristics Typical Segment Current vs Output Voltage Maximum Power Dissipation vs Ambient Temperature Note: VD = Voltage across digit driver Typical Average Segment Current vs Segment Resistor Value www.fairchildsemi.com 4 MM74C925 • MM74C926 Typical Performance Characteristics (Continued) Segment Output Driver Input Protection Common Cathode LED Display Segment Identification 5 www.fairchildsemi.com MM74C925 • MM74C926 Switching Time Waveforms Input Waveforms Multiplexing Output Waveforms T = 1/fMUX Carry-Out Waveforms www.fairchildsemi.com 6 MM74C925 • MM74C926 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E 7 www.fairchildsemi.com MM74C925 • MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N18B Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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