CD54/74FCT373, CD54/74FCT373AT, CD54/74FCT533 Data sheet acquired from Harris Semiconductor SCHS272 FCT Interface Logic Octal Transparent Latch, Three-State February 1996 Features Description • CD54/74FCT373, CD54/74FCT373AT - Non-Inverting The CD54/74FCT373, 373AT, and 533 octal transparent latches use a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output-HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 32mA to 48mA. • CD54/74FCT533 - Inverting • Buffered inputs • Typical Propagation Delay: 3.9ns at VCC = 5V, TA = +25oC, CL = 50pF (FCT373AT) • SCR-Latchup-Resistant BiCMOS Process and Circuit Design The CD54/74FCT373, 373AT, and 533 outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the highimpedance state. The latch operation is independent of the state of the Output Enable. • FCTXXX Types - Speed of Bipolar FAST®/AS/S; FCTXXXAT Types - 30% Faster than FAST/AS/S with Significantly Reduced Power Consumption • 48mA to 32mA Output Sink Current (Commercial/ Extended Industrial) • Output Voltage Swing Limited to 3.7V at VCC = 5V Ordering Information • Controlled Output-Edge Rates PART NUMBER TEMP. RANGE (oC) PACKAGE • Input/Output Isolation to VCC CD54/74FCT373E -55 to 125, 0 to 70 20 Ld PDIP • BiCMOS Technology with Low Quiescent Power CD54/74FCT373ATE -55 to 125, 0 to 70 20 Ld PDIP CD54/74FCT533E -55 to 125, 0 to 70 20 Ld PDIP CD54/74FCT373M -55 to 125, 0 to 70 20 Ld SOIC CD54/74FCT373ATM -55 to 125, 0 to 70 20 Ld SOIC CD54/74FCT533M -55 to 125, 0 to 70 20 Ld SOIC CD54/74FCT373SM -55 to 125, 0 to 70 20 Ld SSOP CD54/74FCT533SM -55 to 125, 0 to 70 20 Ld SSOP CD54FCT373H -55 to 125 CD54FCT533H -55 to 125 Functional Diagram TRUTH TABLE D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 11 373 533 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 LE OUTPUT ENABLE LATCH ENABLE DATA 373, 373AT OUTPUT L H H H L L H L L H L L I L H L L h H L H X X Z Z H = HIGH voltage level. L = LOW voltage level. X = Irrelevant. Z = HIGH Impedance. OE 533 OUTPUT I = LOW voltage level one setup time prior to the high-to-low latch enable transition. h = HIGH voltage level one setup time prior to the high-to-low latch enable transition. FAST® is a registered trademark of Fairchild Semiconductor Corporation. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1996 1 File Number 2230.2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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