Anpec APW8822 System power pwm controller for notebook computers with charge pump Datasheet

APW8822/A/B/C
System Power PWM Controller for Notebook Computers with Charge Pump
Simplified Application Circuit
Features
•
•
ENILIM1 EN LDO ENILIM2
VIN
6V~25V
Wide Input voltage Range from 6V to 25V
Provide 5 Independent Outputs with ±1.0% Accu-
VLDO5
racy Over-Temperature
VOUT1
- PWM1 Controller with Adjustable (2V to 5.5V) Output
- PWM2 Controller with Adjustable (2V to 5.5V) Out-
Q1
LDO5
LDO3
PWM1
PWM2
L1
L2
Q2
C1
D1
D2
D3 C3
C2
VOUT2
Q4
Charge Pump
put
- 100mA Low Dropout Regulator (LDO5) with Fixed
5V Output
VLDO3
Q3
VCP
D4
C4
- 100mA Low Dropout Regulator (LDO3) with Fixed
3.3V Output
•
•
•
•
•
•
•
•
•
•
•
•
•
•
- 270kHz Clock Signal for 15V Charge Pump (Used
General Description
VOUT1 as Its Power Supply)
Excellent Line/Load Regulations about ±1.5% Over-
The APW8822/A/B/C integrates dual step-down, constanton-time, synchronous PWM controllers (that drives dual
Temperature Range
Built in POR Control Scheme Implemented
N-channel MOSFETs for each channel) and two low dropout regulators as well as various protections into a chip.
Constant On-Time Control Scheme with Frequency
Compensation for PWM Mode
The PWM controllers step down high voltage of a battery
to generate low-voltage for NB applications. The output
Selectable Switching Frequency in PWM Mode
Built-in Digital Soft-Start for PWM Outputs and Soft-
of PWM1 and PWM2 can be adjusted from 2V to 5.5V by
setting a resistive voltage-divider from VOUTx to GND.
Stop for PWM Outputs and LDO Outputs
Integrated Bootstrap Forward P-CH MOSFET
The linear regulators provide 5V and 3.3V output for
standby power supply. The linear regulators provide up
High Efficiency over Light to Full Load Range
(PWMs)
to 100mA output current. When the PWMx output voltage
is higher than LDOx bypass threshold, the related LDOx
Built-in Power Good Indicators (PWMs)
Independent Enable Inputs (PWMs, LDO)
regulator is shut off and its output is connected to VOUTx
by internal switchover MOSFET. It can save power
70% Under-Voltage and 125% Over-Voltage Protections (PWM)
dissipation. The charge pump circuit with 270kHz clock
driver uses VOUT1 as its power supply to generate ap-
Adjustable Current-Limit Protection (PWMs)
- Using Sense Low-Side MOSFET’s RDS(ON)
proximately 15V DC voltage.
The APW8822/A/B/C provides excellent transient
Over-Temperature Protection
3mmx3mm Thin QFN-20 (TQFN3x3-20) package
response and accurate DC output voltage in either PFM
or PWM Mode. In Pulse-Frequency Mode (PFM), the
Lead Free and Green Device Available (RoHS
Compliant)
APW8822/A/B/C provides very high efficiency over light
to heavy loads with loading-modulated switching
frequencies. The Forced-PWM Mode works nearly at
constant frequency for low-noise requirements. The
unique ultrasonic mode maintains the switching
frequency above 25kHz, which eliminates noise in
audio application.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
1
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APW8822/A/B/C
General Description (Cont.)
Applications
The APW8822/A/B/C is equipped with accurate sourc-
•
•
•
•
•
•
•
ing and current-limit, output under-voltage output overvoltage protections, being perfect for NB applications. A
1.4ms (typ.) digital soft-start can reduce the start-up
current. A soft-stop function actively discharges the
output capacitors by the discharge device. The
APW8822/A/B has individual enable controls for each
PWM channels. Pulling both EN1/2 pin low shuts down
the all of outputs unless LDO3 output. The LDO3 and
Notebook and Sub-Notebook Computers
Portable Devices
DDR1, DDR2, and DDR3 Power Supplies
3-Cell and 4-Cell Li+ Battery-Powered Devices
Graphic Cards
Game Consoles
Telecommunications
LDO5 of APW8822A/C are always on standby power.
The APW8822/A/B/C is available in a TQFN3x3-20
package.
Ordering and Marking Information
APW8822
APW8822A
APW8822B
APW8822C
Package Code
QB: TQFN3x3-20
Operating Ambient Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APW
8822
XXXXX
XXXXX - Date Code
APW
8822A
XXXXX
XXXXX - Date Code
APW8822B QB :
APW
8822B
XXXXX
XXXXX - Date Code
APW8822C QB :
APW
8822C
XXXXX
XXXXX - Date Code
APW8822 QB :
APW8822A QB :
DEVICE NUMBER
ENABLE FUNCTION
SKIP MODE
ALWAYS ON-LDO
APW8822QBI
EN1/EN2
Auto-skip
LDO3
APW8822AQBI
ENLDO/ENILIM1/ENILIM2
Auto-skip
LDO3 & LDO5
APW8822BQBI
EN1/EN2
Ultra-sonic
LDO3
APW8822CQBI
EN1/EN2
Auto-skip
LDO3 & LDO5
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
EN1
VCLK
PHASE1
BOOT1
UGATE1
ENLDO
VCLK
PHASE1
BOOT1
UGATE1
Pin Configuration
20
19
18
17
16
20
19
18
17
16
FB1
2
14
BYP
LDO3
3
13
LDO5
FB2
4
12
VIN
ILIM2
5
11
LGATE2
15
LGATE1
FB1
2
14
BYP
LDO3
3
13
LDO5
FB2
4
12
VIN
ENILIM
2
5
11
LGATE2
7
8
9
10
6
BOOT2
UGATE2
NC
Bottom
APW8822A
View
PHASE2
EN2
6
1
POK
APW8822
Bottom
View
APW8822B
APW8822C
ENILIM1
7
8
9
10
UGATE2
LGATE1
BOOT2
15
PHASE2
1
POK
ILIM1
TQFN 3X3-20
Top View
TQFN 3X3-20
Top View
= GND and Thermal Pad (connected to GND plane for better hat dissipation)
Absolute Maximum Ratings
Symbol
VIN
VBOOT
(Note 1)
Parameter
Rating
Unit
Input Power Voltage (VIN to GND)
-0.3 ~ 28
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
<20ns pulse width
>20ns pulse width
-5 ~ 42
-0.3 ~ 35
V
<20ns pulse width
>20ns pulse width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
<20ns pulse width
>20ns pulse width
-5 ~ VLDO5+0.3
-0.3 ~ VLDO5+0.3
V
-5 ~ 35
-0.3 ~ 28
V
-0.3 ~ 6
V
BOOT Supply Voltage (BOOT to GND)
VBOOT-GND
UGATE Voltage (UGATE to PHASE)
VUG-PHASE
LGATE Voltage (LGATE to GND)
VLG-GND
PHASE Voltage (PHASE to GND)
VPHASE
TJ
<20ns pulse width
>20ns pulse width
All Other Pins (LDOx, FBx, VOUTx, LDO5, LDO3, REF, VCLK, EN
LDO, ENILIMx to GND)
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Thermal Characteristics (Note 2)
Symbol
Parameter
Typical Value
θJA
Thermal Resistance - Junction to Ambient
95
θJC
Thermal Resistance - Junction to Case
60
Unit
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The thermal pad
of package is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
Range
Unit
VIN
PWM1/2 Converter Input Voltage
6 ~ 25
V
VOUT1
PWM1 Converter Output Voltage
2 ~ 5.5
V
VOUT2
PWM2 Converter Output Voltage
CIN
CLDO
Parameter
2 ~ 5.5
V
PWM1/2 Converter Input Capacitor (MLCC)
10 ~
µF
LDO Output Capacitor (MLCC)
1.0 ~
µF
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8822
Test Conditions
Unit
Min.
Typ.
Max.
Supply current1, VOUT1=0V,
EN1=EN2=5V, VFB1 = VFB2 = 2.05V
-
0.86
1.2
mA
Supply current2, VOUT1=5V,
EN1=EN2=5V, VFB1 = VFB2 = 2.05V,
PVIN+PLDO5
-
5
7
mW
Standby current1, VOUT1=0V,
EN1=EN2=0V (For APW8822/B)
-
-
80
Standby current2, VOUT1=0V,
EN1=EN2=0V (For APW8822A/C)
-
180
245
Shutdown current, ENLDO=0V,
ENILIMx=0V (For APW8822A)
-
20
40
4.1
4.2
4.3
INPUT SUPPLY POWER
IVN
VIN Supply Current
µA
UNDER-VOLTAGE LOCK OUT PROTECTION (UVLO)
LDO5 UVLO threshold
Rising Edge
Hysteresis
LDO3 UVLO threshold
Rising Edge
Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
4
V
-
0.1
-
V
3.0
3.15
3.3
V
-
0.8
-
V
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APW8822/A/B/C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8822
Test Conditions
Unit
Min.
Typ.
Max.
Rising threshold1, LDO3 enable
-
3.8
-
V
Rising threshold1_A/C, LDO3 &
LDO5 enable (For APW8822A/C)
-
3.8
-
V
Rising threshold2, LDO5 enable
-
5.1
-
V
-
5.0
-
V
-
3.7
-
V
2
-
5.5
V
1.98
2.0
2.02
V
-20
-
20
nA
UNDER-VOLTAGE LOCK OUT PROTECTION (UVLO)
VIN POR threshold
Falling threshold2, PWMx shutdown
with soft stop.
When PWMx soft stop is complete,
LDO5 will begin to shutdown
Falling threshold1, LDOx shutdown
with soft stop
PWM CONTROLLERS
Output Voltage Adjust Range
VOUT1, VOUT2
o
o
VFB
FBx Reference Voltage
IFB
FBx input current
VFBX=2.0V, TA=25 C
TSS
Soft-Start Ramp Time
ENx High to VOUT 95% Regulation,
LDO5=5V
-
1.4
-
ms
Soft-Stop Time
ENx low to VFBX<0.1V
-
1.7
-
ms
FSW1
PWM1 Switching Frequency
VIN=20V, PWM1=5V
240
300
360
FSW2
PWM2 Switching Frequency
VIN=20V, PWM2=3.33V
280
355
430
200
350
500
ns
TA = -40 C to 85 C
o
UGATEx Minimum Off-Time
kHz
LOW DROUPUT LINEAR REGULATORS (LDO5/LDO3)
VTHBYP5
LDO5 Output Voltage
VOUT1=GND, 6V<VIN<25V,
0<ILDO5<100mA
4.8
5.0
5.2
V
LDO3 Output Voltage
VOUT2=GND, 6V<VIN<25V,
0<ILDO3<100mA
3.2
3.33
3.46
V
4.55
4.7
4.85
0.15
0.25
0.3
VOUT1 Regulation Voltage Rising
LDO5 Bypass Threshold for
VOUT1-to-LDO5 Switch On
Hysteresis
VOUT1-to-LDO5 Switch On Resistance
VOUT1=5V, 50mA
LDOx Current Limit
VOUTx=GND, LDOx = GND
LDOx Discharge On Resistance
ILDOX=5mA
V
-
1.5
3
Ω
150
250
350
mA
-
50
100
Ω
-
4.92
-
0.06
-
-
270
-
kHz
120
125
130
%
CHARGE PUMP CLOCK
VCLKH
High level voltage
IVCLK=-10mA, LDO5=5V, TA=25 oC
o
VCLKL
Low level voltage
IVCLK=10mA, LDO5=5V, TA=25 C
FCLK
Clock frequency
TA=25 oC
V
PWM1/2 PROTECTIONS
Over Voltage Protection Threshold
VFBX Rising
Over Voltage Fault Propagation Delay
Delta voltage=10mV
-
3
-
µs
VILIMx=1V, TA = 25 C
9
10
11
µA
On the basis of 25 oC
-
4500
-
ppm/oC
o
Current Limit Current Source
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8822
Test Conditions
Unit
Min.
Typ.
Max.
0.2
-
2
V
0.515
-
2
V
205
250
-
mV
-8
0
8
mV
PWM1/2 PROTECTIONS
ILIMx Adjustment Range
VILIMx-GND
ENILIMx Adjustment Range
VENILIMx-GND
Maximum setting voltage
Current limit comparator offset
Zero-Crossing Threshold
VILIMx =5V, Setting Current Limit
Threshpld
(VILIMx-GND-VPGND-PHASEx),
VILIMx=920mV
-5
0
5
mV
Under-Voltage Protection Threshold
65
70
75
%
Under-Voltage Protection Debounce
Interval
-
25
-
µs
From EN signal go high to SS_OK
-
2
-
ms
TJ Rising
-
160
-
Hysteresis
-
25
-
87
90
93
-
3
-
120
125
130
-
63
-
µs
-
2
-
ms
Under-Voltage Protection Enable
Blanking Time
Over-Temperature Protection Threshold
VPGND – PHASE
o
C
POWER GOOD
POK in from Lower
(POK goes high)
POK Threshold
POK hysteresis
POK in from higher (POK goes low)
POK Propagation Delay
POK Enable Delay
From EN signal go high to POK go
High
POK Sink current
VPOK = 500mV
POK Leakage Current
2.5
7.5
-
0.1
1
-
-
1.2
0.6
-
-
0.1
1
300
400
500
Hysteresis
-
60
-
Shutdown
-
-
0.4
VPOK = 5V
%
mA
µA
LOGIC LEVELS
ENx Input Voltage Level
Enable
Shutdown
Input leakage current
ENILIMx Input Voltage
VEN=5V
Enable
V
µA
mV
ENLDO Input Voltage
Enable, VCLK=off
0.8
-
1.6
Enable, VCLK=on
2.4
-
-
-
1
-
µA
ENLDO pin pull high function
Short Current, ENLDO is short to
GND
Open Voltage, ENLDO is open(pull
high to internal regulator)
2.4
3.34
-
V
Copyright  ANPEC Electronics Corp.
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6
V
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APW8822/A/B/C
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8822
Test Conditions
Unit
Min.
Typ.
Max.
GATE DRIVERS
UG Pull-Up Resistance
VBOOTx – VUGATEx=250mV
-
3
5
Ω
UG Sink Resistance
VUGATEx – VPHASEx=250mV
-
1.7
2.5
Ω
LG Pull-Up Resistance
VLDO5 – VLGATEx=250mV
-
3
5
Ω
LG Sink Resistance
VLGATEx – VPGND=250mV
-
1
2
Ω
Dead Time
UG falling to LG rising
-
20
-
ns
LG falling to UG rising
-
20
-
ns
BOOTSTRAP SWITCH
VF
Forward Voltage
VLDO5 – VBOOTx-GND, IF = 10mA
-
0.4
0.5
V
IR
Reverse Leakage
VBOOTx-GND = 30V, VPHASEx = 25V,
VLDO5 = 5V
-
-
0.5
µA
Copyright  ANPEC Electronics Corp.
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APW8822/A/B/C
Typical Operating Characteristics
Load Regulation
Load Regulation
5.15
3.43
Vout=5V
Vout=3.3V
VIN=8V
Outpur Voltage (V)
Outpur Voltage (V)
5.1
VIN=12V
5.05
VIN=20V
5
VIN=12V
VIN=20V
3.33
3.28
495
4.9
0.001
VIN=8V
3.38
0.01
0.1
1
3.23
0.001
10
Output current(A)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
0.01
0.1
1
10
Output current(A)
8
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APW8822/A/B/C
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA=25oC unless otherwise specified.
Output-Discharge
Start-Up
VEN1=EN2
VEN1=EN2
VOUT1
1
1
2
3
VOUT2
2
VPOK
4
4
VOUT1
VOUT2
VPOK
CH1: EN1=EN2, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VOUT2, 2V/Div
CH4: VPOK, 10V/Div
TIME: 500us/Div
CH1: EN1=EN2, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VOUT2, 2V/Div
CH4: VPOK, 10V/Div
TIME: 500us/Div
3.3V Load Transient
5V Load Transient
Vout2
Vout1
1
2
VOUT2
2
VOUT1
1
VPHASE1
VPHASE2
3
3
IOUT2
IOUT1
4
4
CH1: Vout1, 100mV/Div, AC
CH2: Vout2, 100mV/Div, AC
CH3: VPHASE2, 20V/Div, DC
CH4: IOUT2, 5A/Div
TIME: 20us/Div
CH1: Vout1, 100mV/Div, AC
CH2: Vout2, 100mV/Div, AC
CH3: VPHASE1, 20V/Div, DC
CH4: IOUT1, 5A/Div
TIME: 20us/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Pin Description
PIN
NO.
APW8822/B/C
FUNCTION
APW8822A
NAME
1
-
ILIM1
-
1
ENILIM1
2
2
FB1
3
3
LDO3
4
4
FB2
Current Limit Adjustment. There is an internal 10µA current source from LDO5
to ILIM1 and connected a resistor from ILIM1 to GND to set the current limit
threshold. The PGND-PHASE1 current-limit threshold is 1/8th the voltage set
at ILIM1 over a 0.2 to 2V range. The logic current limit threshold is default to
250mV value if ILIM1 is 5V.
PWM1 Enable and Current Limit Adjustment. There is an internal 10µA
current source from LDO5 to ENILIM1 and connected a resistor from
ENILIM1 to GND to set the current limit threshold. The PGND-PHASE1
current-limit threshold is 1/8th the voltage set at ENILIM1 over a 0.515 to 2V
range. The logic current limit threshold is default to 250mV value if ENILIM1
is 5V. PWM1 and VCLK are enabled when ENILIM1=1. When ENILIM1=0,
PWM1 and VCLK are in shutdown.
Output voltage feedback pin (PWM1). It can use a resistive divider from
VOUT1 to GND to adjust the output from 2V to 5.5V.
3.3V Linear Regulator Output. LDO3 can provide a total of 100mA, 3.3V
external loads. Bypass to GND with a minimum of 1.0uF ceramic capacitor
for stability.
Output voltage feedback pin (PWM2). It can use a resistive divider from
VOUT2 to GND to adjust the output from 2V to 5.5V.
Current Limit Adjustment. There is an internal 10µA current source from
LDO5 to ILIM2 and connected a resistor from ILIM2 to GND to set the current
limit threshold. The PGND-PHASE2 current-limit threshold is 1/8th the
voltage set at ILIM2 over a 0.2 to 2V range. The logic current limit threshold
is default to 250mV value if ILIM2 is 5V.
PWM2 Enable and Current Limit Adjustment. There is an internal 10µA
current source from LDO5 to ENILIM2 and connected a resistor from
ENILIM2 to GND to set the current limit threshold. The PGND-PHASE2
current-limit threshold is 1/8th the voltage set at ENILIM2 over a 0.515 to 2V
range. The logic current limit threshold is default to 250mV value if ENILIM2
is 5V. PWM2 is enabled when ENILIM2=1. When ENILIM2=0, PWM2 is in
shutdown.
5
-
ILIM2
-
5
ENILIM2
6
-
EN2
PWM2 Enable. PWM2 is enabled when EN2=1. When EN2=0, PWM2 is in
shutdown.
-
6
NC
No Connection
7
7
POK
8
8
PHASE2
9
9
BOOT2
Supply Input for The UGATE2 Gate Driver and an internal level-shift circuit.
Connect to an external capacitor to create a boosted voltage suitable to drive
a logic-level N-channel MOSFET.
10
10
UGATE2
Output of The High-Side MOSFET Driver for PWM2. Connect this pin to Gate
of the high-side MOSFET.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
Power-Good Output Pin of Both PWMs (Logic AND). POK is an open-drain
output used to indicate the status of the PWMx output voltage. Connect the
POK in to +5V through a pull-high resistor.
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and
The Low-Side MOSFET Drain for PWM2. Connect this pin to the Source of
the high-side MOSFET. PHASE2 serves as the lower supply rail for the
UGATE2 high-side gate driver. PHASE2 is the current-sense input for the
PWM2.
10
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APW8822/A/B/C
Pin Description (Cont.)
PIN
NO.
FUNCTION
NAME
APW8822/B/C
APW8822A
11
11
LGATE2
12
12
VIN
13
13
LDO5
14
14
BYP
15
15
LGATE1
16
16
UGATE1
17
17
BOOT1
18
18
PHASE1
19
19
VCLK
20
-
EN1
-
20
ENLDO
Output of The Low-Side MOSFET Driver for PWM2. Connect this pin to Gate
of the low-side MOSFET. Swings from PGND to LDO5.
Battery voltage input pin. VIN powers linear regulators and is also used for
the constant on-time PWM on-time one-shot circuits. Connect VIN to the
battery input and bypass with a 1µF capacitor for noise interference.
5V Linear Regulator Output. LDO5 can provide a total of 100mA, 5V external
loads. When LDO5 is at 5V and PWM1 output voltage is over 4.7V bypass
threshold, the internal LDO will shut down, and LDO5 output pin connects to
VOUT1 through a 1.5Ω switch. Bypass to GND with a minimum of 1.0uF
ceramic capacitor for stability.
BYP is the input pin of switchover voltage for the LDO5. This pin makes a
direct measurement of the PWM1 output voltage.
Output of The Low-Side MOSFET Driver for PWM1. Connect this pin to Gate
of the low-side MOSFET. Swings from PGND to LDO5.
Output of The High-Side MOSFET Driver for PWM1. Connect this pin to Gate
of the high-side MOSFET.
Supply Input for The UGATE1 Gate Driver and an internal level-shift circuit.
Connect to an external capacitor to create a boosted voltage suitable to drive
a logic-level N-channel MOSFET.
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and
The Low-Side MOSFET Drain for PWM1. Connect this pin to the Source of
the high-side MOSFET. PHASE1 serves as the lower supply rail for the
UGATE1 high-side gate driver. PHASE1 is the current-sense input for the
PWM1.
250kHz Clock Output for 15V Charge Pump.
PWM1 Enable. PWM1 is enabled when EN1=1. When EN1=0, PWM1 is in
shutdown.
Master Enable Input. The LDOx is enabled when ENLDO=1. When
ENLDO=0, the LDOx is shutdown. See the table2 “Power-Up Control
Logics”.
Thermal Pad
Thermal Pad
GND
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
Signal Ground for The IC.
11
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APW8822/A/B/C
Block Diagram
BOOT2
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE2
PWM FREQUENCY
CONTROL
PHASE2
PHASE1
TON
Generator
BOOT1
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE1
PHASE2
PHASE1
ZC2
LDO5
LGATE2
ZC1
SMPS1
PWM2
CONTROLLER
SMPS2
PWM2
CONTROLLER
LDO5
LGATE1
PGND
VIN
LDO UVLO
LDO3
LDO5
THERMAL
SHUTDOWN
LDO3
LDO5
EN ENABLE
POWER ON SEQUENCE
CLEAR FAULT LATCH
EN2
EN1
VTHBYP5
PHASE1
ILIM2 /
ENILIM2
ILIM1 /
ENILIM1
BYP
PHASE2
CURRENT LIMIT
CONTROLLER
ENLDO
(APW8822A only)
CHARGE PUMP
OSCILLATOR
SOFT START
POK
VCLK
POK2
POK1
90% VFB2
90% VFB1
125% VFB2
125% VFB1
OV2
OV1
FAULT
LATCH
LOGIC
FB2
FB1
UV1
UV2
70% VFB2
LGATE2
70% VFB1
SOFT
STOP
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
ENLDO or
EN2 /
ENILIM2
ENLDO or
EN1 /
ENILIM1
12
SOFT
STOP
LGATE1
GND
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APW8822/A/B/C
Typical Application Circuit
For APW8822/B/C
VIN : 6V to 25V
LDO5
CLDO5
1µF
LDO3
VIN
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
330µF/10V
9m ohm
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
CBOOT1
0.1µF
Q3
APM4810
RBOOT2
0
UGATE1
UGATE2
PHASE1
PHASE2
CBOOT2
0.22µF
Q2
APM4810
LGATE1
GND
RTOP1
30k
LGATE2
GND
LOUT2
2.2µH
VOUT2
3.3V/11A
Q4
APM4810
COUT2
330µF/6.3Vx2
4m ohm
RTOP2
13k
BYP
FB1
FB2
ILIM2
ILIM1
RILIM2
200k
RILIM1
200k
RGND1
20k
ON
OFF
CIN2
10µF
ON
RGND2
20k
EN2
EN1
OFF
GND
GND
VCLK
CCP1
100nF
D1
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
13
CCP2
100nF
VCP
15V
CCP3
100nF
D2
D3
D4
CCP4
1µF
www.anpec.com.tw
APW8822/A/B/C
Typical Application Circuit
For APW8822A
VIN : 6V to 25V
LDO5
CLDO5
1µF
LDO3
VIN
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
330µF/10V
9m ohm
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
CBOOT1
0.1µF
Q3
APM4810
RBOOT2
0
UGATE1
UGATE2
PHASE1
PHASE2
CBOOT2
0.22µF
Q2
APM4810
LGATE1
GND
RTOP1
30k
LGATE2
GND
LOUT2
2.2µH
VOUT2
3.3V/11A
Q4
APM4810
COUT2
330µF/6.3Vx2
4m ohm
RTOP2
13k
BYP
FB1
CIN2
10µF
FB2
ENILIM1
ENILIM2
RILIM2
200k
RILIM1
200k
ON
RGND1
20k
RGND2
20k
ENLDO
OFF
GND
GND
VCLK
CCP1
100nF
D1
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
14
CCP3
100nF
D2
CCP2
100nF
D3
D4
VCP
15V
CCP4
1µF
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APW8822/A/B/C
Function Description
Where FSW is the nominal switching frequency of the converter in PWM mode. Similarly, the on-time of ultrasonic
Constant-On-Time PWM Controller with Input Feed-Forward
The constant-on-time control architecture is a pseudo-
mode is the same with PFM mode. The description of
ultrasonic mode will be illustrated later.
fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective
The load current at handoff from PFM to PWM mode is
given by:
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
ILOAD(PFM to PWM) =
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
=
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
1 VIN − VOUT
×
× TON −PFM
2
L
VIN − VOUT
V
1
×
× OUT
2L
F SW
VIN
Linear Regulator (LDO3 and LDO5)
The LDO3 and LDO5 regulators can supply up to 100mA
erator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
for external loads. Bypass to GND with a minimum of 1uF
ceramic capacitor for stability. For APW8822A, when
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
ENLDO is enabled, the VLDO3 is fixed 3.33V and the
VLDO5 is fixed 5V in standby mode. For APW8822C, When
is more outstanding than a conventional constant-ontime controller, which has large switching frequency varia-
VIN reaches POR rising threshold, the VLDO3 is fixed 3.
33V and the VLDO5 is fixed 5V in standby mode. Let is
tion over input voltage, output current and temperature.
Both in PFM and PWM, the on-time generator, which
see the table2”Power-Up Control Logic” for the detail
description about standby mode. For all of APW8822
senses input voltage on VIN pin, provides very fast ontime response to input line transients.
series, When PWM1 output voltage is over whose bypass threshold (PWM1 is 4.7V), the internal LDO5 to
Another one-shot sets a minimum off-time (typ.: 350ns).
The on-time one-shot is triggered if the error comparator
VOUT1 switchover is active. These actions change the
current path to power the loads from the PWM regulator
is high, the low-side switch current is below the currentlimit threshold, and the minimum off-time one-shot has
voltage, rather than from the internal linear regulator.
timed out.
Power -On-Reset
A Power-On-Reset (POR) function is designed to prevent
Pulse-Frequency Modulation (PFM) Mode
In PFM mode, an automatic switchover to pulse-frequency
wrong logic controls. The POR function continually monitors the supply voltage on the LDO5 pins. LDO5 POR
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
circuitry inhibits wrong switching. When the rising VLDO5
voltage reaches the rising POR threshold (4.3V typical),
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
the PWM output voltages begin to ramp up. When the
LDO5 voltage is lower than 4.2V(typ.) or LDO3 voltage is
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
lower than 2.374V(typ.), both switch power supplies are
shut off. This is non-latch protection. LDO5 POR thresh-
operation (also known as the critical conduction point).
The on-time of PFM is given by:
old could reset the under-voltage, over-voltage.
TON - PFM =
V
1
× OUT
FSW
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Function Description (Cont.)
Soft-Stop (PWMs)
Soft Start
The APW8822/A/B/C integrates soft-start circuit to ramp
up the PWMx output voltage of the converter to the pro-
In the event of PWM under-voltage or shutdown, the chip
enables the soft-stop function. The soft-stop function discharges the PWM output voltages to low voltage by the
grammed regulation set point at a predictable slew rate.
The slew rate of PWMx output voltage is internally con-
soft stop method. The reference remains active to provide an accurate threshold and to provide over-voltage
trolled to limit the inrush current through the output capacitors during soft start process. When the ENx pin is
protection.
pulled above the rising threshold voltage, the related PWM
initiates a soft-start process to ramp up the output voltage.
Power Good Indicator (PWMs)
The soft-start interval is 1.4ms(typical) and independent
of the UGATE switching frequency.
POK is actively held low in shutdown, standby, and softstart. In the soft-start process, the POK is an open-drain
Enable Controls
The APW8822/A/B/C has two independent enable con-
output, and it is released with enable delay after the latest ENx goes high (about 2ms typ.). In normal operation,
trols for PWM part. When the ENx pin is high (ENILIMx=1)
at standby mode, the PWMx initiates a soft-start process
the POK window is from 90% to its OVP threshold of the
converter reference voltage. Both of VOUT1 and VOUT2
to ramp
up the output voltage. The PWM1 and PWM2 are con-
have to stay within this window for POK to be high (AND
gated). In order to prevent false POK drop, capacitors
trolled individually by EN1 and EN2. When EN1 and EN2
are both low, the chip is in its low-power standby state.
need to parallel at the output to confine the voltage deviation with severe load step transient.
The APW8822/B only consumes 80µA of current while in
standby mode.
Under-Voltage Protection (PWMs)
When the EN1 is high, the clock signal becomes available from VCLK pin. Both PWM outputs are discharged
In the process of operation, if a short-circuit occurs, the
to low voltage by the soft stop method and both LDO
outputs are discharged to 0V through a 50Ω switch in
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
soft stop state. Driving EN1 and EN2 (logic AND) below
low threshold clears the over-voltage, and under-voltage
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
fault latches.
after soft-start is completed. If a load step is strong enough
to pull the output voltage lower than the under-voltage
Charge Pump
threshold for at least 25µs, the PWM controller starts a
soft-stop process to shut down the output gradually. As
The condition of the 270kHz clock signal can be used is
long as either of PWM channels triggers under-voltage,
both of PWM channels active under-voltage protection and
that the EN1 is high. When VOUT1 regulates at 5V and
the clock signal uses VOUT1 as its power supply, the
latched off when the soft-stop process is completed.
The under-voltage threshold is 70% of the nominal out-
charge pump circuit can generate 15V DC voltage
approximately. The example of charge pump circuit is
put voltage. Under-voltage protection is ignored for at least
2ms (typical) after a rising edge on EN. Re-toggling EN1
shown in typical application circuit.
and EN2 (logic AND) signal will clear the latch and bring
the chip back to operation.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Function Description (Cont.)
Over Voltage Protection (OVP)
IPEAK
INDUCTOR CURRENT
Should the output voltage of VOUT1 and VOUT2 increase
over 25% of the setting voltage due to the high-side
MOSFET failure or for other reasons, the over voltage
protection will active. As long as either of PWM channels
triggers over voltage, the other PWM channel will be soft
stop state. Over voltage protection will force the low-side
MOSFET gate driver fully turn on. This action actively pulls
down the output voltage. When the OVP occurs, the POK
IOUT
ΔI
ILIMIT
0
Time
pin will pull down and latch-off the converter. This OVP
scheme only clamps the voltage overshoot, and does
Figure 1. Current-Limit Algorithm
not invert the output voltage when otherwise activated
with a continuously high output from low-side MOSFET
Both PWM controllers use the low-side MOSFETs onresistance RDS(ON) to monitor the current for protection
against shorted outputs. The MOSFET’s RDS(ON) is varied
driver. It’s a common problem for OVP schemes with a
latch. Once an over-voltage fault condition is set, it can be
by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
reset by re-toggling EN1 and EN2 (logic AND) signal.
datasheet.
The current Limit threshold of APW8822/A/B/C is adjusted
Over-Temperature Protection
with an external resistor. For APW8822A, the ENILIMx pin
adjustment range is from 515mV to 2V. In the adjustable
When the junction temperature increases above the rising threshold temperature 160 oC, the IC will enter the
mode, the current-limit threshold voltage is 1/8th the voltage at ILIMx pin. As shown in Figure 2, The ILIMx pin can
over temperature protection (OTP). When the OTP occurs,
LDO and PWM controllers circuitry shuts down. It is nonlatch protection.
source 10µA. The voltage at ILIMx pin is equal to 10µA x
RILIM. The logic current limit threshold is default to 250mV
value if voltage at ILIMx pin is above 2V(ENILIMx is 5V).
The relationship between the sampled voltage VILIM and
Current Limit (PWMs)
the current limit threshold ILIMIT is given by:
The current limit circuit employs a "valley" current-sens-
1
× VILIMX = ILIMIT × RDS( ON)
8
ing algorithm (See Figure 1). The APW8822/A/B/C uses
the low-side MOSFET’s RDS(ON) of the synchronous recti-
1
× VENILIMX = ILIMIT × RDS(ON)
8
fier as a current-sensing element. If the magnitude of the
current-sense signal at PHASE pin is above the currentlimit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current-
---APW8822/B/C
---APW8822A
Where VILIMX is the voltage at the ILIMx pin. RDS(ON) is
the low side MOSFETs conducive resistance. ILIMIT is
the setting current limit threshold. ILIMIT can be ex-
limit threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic
pressed as IOUT minus half of peak-to-peak inductor
current.
and maximum load capability are a function of the sense
resistance, inductor value, and input voltage.
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
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APW8822/A/B/C
Function Description (Cont.)
ILIM/ENI
LIM
VILIM/ENI
R ILIM
LIM
10 µA
7R
TO CURRENT
LIMIT LOGIC
R
Figure 2. Current-Limit Setting Block Diagram
Table 1. Operating Mode Truth Table
MODE
CONDITION
COMMENT
APW8822/B/C
ENx = 1
APW8822A
ENLDO = 1,
ENILIMx = 1
APW8822/B
ENx = 0
PWMx is in shutdown with soft stop, and then LDO5 is also in shutdown with
discharge function after soft stop function in PWMx is completed. LDO3 is
active.
ENx=0
PWMx is in shutdown with soft stop function. LDO3 and LDO5 are active.
ENILIMx=0,
ENLDO=1
PWMx is in shutdown with soft stop function. LDO3 and LDO5 are active.
PWM is in normal operation.
Run
Standby & Soft
APW8822C
Stop
APW8822A
APW8822/B/C
Shutdown
OVP
OTP
-
PWMx is in shutdown with soft stop, and then LDOx is also in shutdown with
discharge function after soft stop function in PWMx is completed. In this
mode, all circuitry is off.
The soft stop function will enable to pull low output voltage. LDOx is active.
Either VOUT1, or VOUT2 < 70% of
Reset by toggling EN1 and EN2 (logic AND). This action will re-start LDO5 at
nominal output voltage
the same time. (For APW8822/B).
LGATE of the PWM channel, which occurs OVP event is forced high, the
Either VOUT1 and VOUT2>125% of other PWM channel is in shutdown with soft stop. LDOx is active. Reset by
normal output voltage
toggling EN1 and EN2 (logic AND). This action will re-start LDO5 at the same
time. (For APW8822/B).
All circuitry off. It is non-latch protection after the junction temperature cools
o
TJ > +160 C
by 25℃.
APW8822A
UVP
ENLDO=0
Copyright  ANPEC Electronics Corp.
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APW8822/A/B/C
Function Description (Cont.)
Table 2. Power-Up Control Logics
For APW8822/B
VEN1
VEN2
LDO5
LDO3
PWM1
PWM2
VCLK
OFF
OFF
OFF
ON
Low
Low
OFF
ON
High
High
ON
ON
ON
ON
High
Low
ON
ON
ON
OFF
ON
High
ON
ON
OFF
ON
OFF
VEN2
LDO5
LDO3
PWM1
Low
For APW8822C
VEN1
PWM2
VCLK
OFF
OFF
OFF
Low
Low
ON
ON
High
High
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
High
Low
ON
ON
Low
High
ON
ON
For APW8822A
VENLDO
Low
0.8V~1.6V
VENILIM1
VENILIM2
LDO5
LDO3
PWM1
PWM2
VCLK
OFF
OFF
OFF
Don’t Care
Don’t Care
OFF
OFF
Low
Low
ON
ON
OFF
OFF
OFF
ON
ON
OFF
0.8V~1.6V
High
High
ON
ON
0.8V~1.6V
High
Low
ON
ON
ON
OFF
OFF
0.8V~1.6V
Low
High
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
>2.4V
Low
Low
ON
ON
>2.4V
High
High
ON
ON
ON
ON
>2.4V
High
Low
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
>2.4V
Low
High
Copyright  ANPEC Electronics Corp.
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OFF
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APW8822/A/B/C
Application Information
Output Voltage Selection
ripple current occurs at the maximum input voltage. A
The output voltage of PWM1 can be adjusted from 2V to
5.5V with a resistor-driver at FB1 between VOUT1 and
good starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
GND. Using 1% or better resistors for the resistive divider is recommended. The FB1 pin is the inverter input
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
of the error amplifier, and the reference voltage is 2V.
Take the example, the output voltage of PWM1 is deter-
rent without going into saturation. In some types of
inductors, especially core that is made of ferrite, the ripple
mined by:
current will increase abruptly when it saturates. This will
be result in a larger output ripple voltage.
VOUTI

R
= 2 ×  1 + TOP1
R GND1

Output Capacitor Selection




Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher
Where RTOP1 is the resistor connected from VOUTI to VFB1
and RGND1 is the resistor connected from FB1 to GND.
capacitor value and lower ESR reduce the output ripple
and the load transient drop. Therefore, selecting high
Similarly, the output voltage of PWM2 can be alsoadjusted
from 2V to 5.5V.
performance low ESR capacitors is intended for switching regulator applications. In addition to high frequency
Output Inductor Selection
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by:
is fixed, it can be written as:
D=
VOUT
VIN
∆VESR
The inductor value determines the inductor ripple current
and affects the load transient reponse. Higher inductor
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current can be
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
approxminated by:
IRIPPLE =
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
VIN - VOUT VOUT
×
VIN
FSW × L
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
Increasing the inductor value and frequency will re-
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing
duce the ripple current and voltage. However, there is a
tradeoff between the inductor’s ripple current and the
the noise is also recommended, and the voltage rating
of the output capacitors must also be considered.
regulator load transient response time.
To support a load transient that is faster than the
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
switching frequency, more capacitors have to be used
to reduce the voltage excursion during load step change.
current. Increasing the switching frequency (FSW ) also
reduces the ripple current and voltage, but it will
Another aspect of the capacitor selection is that the
total AC current going through the capacitors has to be
increase the switching loss of the MOSFETs and the
power dissipation of the converter. The maximum
less than the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
Copyright  ANPEC Electronics Corp.
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APW8822/A/B/C
Application Information (Cont.)
(CRSS) and maximum output current requirement. The
Input Capacitor Selection
losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
side MOSFETs, the losses are approximately given by
the following equations:
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
2
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
current rating requirement is approximately IOUT/2, where
IOUT is the load current. During power up, the input capaci-
2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
tors have to handle large amount of surge current. In lowduty notebook appliactions, ceramic capacitors are
Where
I
is the load current
OUT
remmended. The capacitors must be connected between
the drain of high-side MOSFET and the source of low-
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
side MOSFET with very low-impeadance PCB layout.
tSW is the switching interval
D is the duty cycle
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transi-
be used. The design has to trade off the gate charge with
the RDS(ON) of the MOSFET:
tion loss. The switching internal, t SW , is the function
of the reverse transfer capacitance CRSS. The (1+TC) term
•
is to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
For the low-side MOSFET, before it is turned on, the
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this
•
curve of the power MOSFET.
MOSFET.
Layout Consideration
In the turning off process of the low-side MOSFET,
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
the load current will shift to the body diode first. The
high dv/dt of the phase node voltage will charge the
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
miller capacitor through the low-side MOSFET driver
sinking current path. This results in much less
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
switching loss of the low-side MOSFETs. The duty
cycle is often very small in high battery voltage
of the PWM MOSFET. Before turn-off condition, the
MOSFET is carrying the full load current. During turn-off,
applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, the less
current stops flowing in the MOSFET and is freewheeling
by the lower MOSFET and parasitic diode. Any parasitic
the RDS(ON) of the low-side MOSFET, the less the power
loss. The gate charge for this MOSFET is usually a
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short and
secondary consideration. The high-side MOSFET
does not have this zero voltage switching
wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And
condition, and because it conducts for less time
compared to the low-side MOSFET, the switching
signal and power grounds are to be kept separating and
finally combined to use the ground plane construction or
loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both
single point grounding. The best tie-point between the
signal ground and the power ground is at the negative
the gate driver loss and switching loss will be
minimized.
The selection of the N-channel power MOSFETs are de-
side of the output capacitor on each channel, where there
is less noise. Noisy traces beneath the IC are not
termined by the RDS(ON), reversing transfer capacitance
recommended. Below is a checklist for your layout:
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
21
www.anpec.com.tw
APW8822/A/B/C
Application Information (Cont.)
Layout Consideration (Cont.)
•
3mm
Keep the switching nodes (UGATEx, LGATEx, BOOTx,
and PHASEx) away from sensitive small signal nodes
(ILIMx, and FBx) since these nodes are fast moving
signals. Therefore, keep traces to these nodes as
short as possible and there should be no other weak
0.2mm
signal traces in parallel with theses traces on any layer.
The signals going through theses traces have both
1.66 mm
•
0.5mm *
high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers
•
0.4mm
to the MOSFETs (UGATEx and LGATEx) should be short
and wide.
1.66 mm
0.17mm
0.5mm
Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of
•
3mm
TQFN3x3-20
* Just Recommend
the node.
Decoupling capacitor, the resistor dividers, boot
capacitors, and current-limit stetting resistor should
be close to their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
•
capacitors are also placednear the drain).
The input capacitor should be near the drain of the
upper MOSFET; the high quality ceramic decoupling
capacitor can be put close to the VCC and GND pins;
the output capacitor should be near the loads. The
input capacitor GND should be close to the output ca-
•
pacitor GND and the lower MOSFET GND.
The drain of the MOSFETs (VIN and PHASEx nodes)
should be a large plane for heat sinking. And PHASEx
pin traces are also the return path for UGATEx. Con-
•
nect these pins to the respective converter’s upper
MOSFET source.
The controller used ripple mode control. Build the resistor divider close to the FB1 pin so that the high
impedance trace is shorter when the output voltage is
in ad justable mode. And the FB1 pin traces can’t be
•
close to the switching signal traces (UGATEx, LGATEx,
BOOTx, and PHASEx).
The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs
for current-limit accuracy.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
22
www.anpec.com.tw
APW8822/A/B/C
Package Information
TQFN3x3-20
D
E
b
A
Pin 1
A1
A3
D2
NX
aaa C
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN3x3-20
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.25
0.006
0.010
A3
0.20 REF
0.008 REF
b
0.15
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
0.50
0.012
e
0.40 BSC
L
0.30
K
0.20
0.016 BSC
0.008
0.08
aaa
0.020
0.003
Note : 1. Followed from JEDEC MO-220 WEEE
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
23
www.anpec.com.tw
APW8822/A/B/C
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN3x3-20
A
H
T1
C
d
D
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
TQFN3x3-20
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
Unit
Tape & Reel
Quantity
3000
24
www.anpec.com.tw
APW8822/A/B/C
Taping Direction Information
TQFN3x3-20
USER DIRECTION OF FEED
Classification Profile
Supplier Tp≧Tc
User Tp≦Tc
TC
TC -5oC
User tp
Supplier tp
Tp
tp
Temperature
Max. Ramp Up Rate = 3oC/s
Max. Ramp Down Rate = 6oC/s
TL
Tsmax
TC -5oC
t
Preheat Area
Tsmin
tS
25
Time 25oC to Peak
Time
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
25
www.anpec.com.tw
APW8822/A/B/C
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
26
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW8822/A/B/C
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Nov., 2012
27
www.anpec.com.tw