CS3865C CS3865C High Performance Dual Channel Current Mode Controller with ENABLE Description The CS3865C is a high performance, fixed frequency, dual current mode controller. It is used in Off-Line and DC to DC converter applications and require a minimum number of external components. This integrated circuit features a unique oscillator for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, and two high current totem pole outputs ideally suited Features for driving power MOSFETs. One of the outputs VOUT2 is switchable via the ENABLE 2 pin. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, and a latch for single pulse metering of each output. The CS3865C has a 14V start voltage and is pin compatible with the MC34065H. Block Diagram VCC 5.0V Ref VREF VCC Undervoltage Lockout VREF Undervoltage Lockout VOUT1 SYNC Latching PWM 1 CT Package Options Oscillator RT - Error Amp 1 VOUT2 COMP1 Latching PWM 2 ENABLE2 VFB2 16L PDIP & SO Wide Sense1 + VFB1 ■ Oscillator has Precise Duty Cycle Limit and Frequency Control ■ 500kHz Current Mode Operation ■ Automatic Feed Forward Compensation ■ Separate Latching PWMs for Cycle-By-Cycle Current Limiting ■ Internally Trimmed Reference with Undervoltage Lockout ■ Switchable Second Output ■ Two High Current Totem Pole Outputs ■ Input Undervoltage Lockout with Hysteresis ■ Low Start-Up and Operating Current + - Sense2 Error Amp 2 COMP2 Gnd SYNC 1 16 VCC CT 2 15 VREF RT 3 14 ENABLE2 VFB1 4 13 VFB2 12 COMP2 Sense1 6 11 Sense2 VOUT1 7 10 VOUT2 Gnd 8 9 Pwr Gnd COMP1 5 Pwr Gnd Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 12/16/96 1 A ® Company CS3865C Absolute Maximum Ratings Total Power Supply and Zener Current .........................................................................................................................50mA Output Current, Source or Sink (Note 1)...........................................................................................................................1.0A Output Energy (capacitive load per cycle) .......................................................................................................................5.0µJ Current Sense, Enable and Voltage ......................................................................................................................-0.3 to +5.5V Feedback Inputs High State (Voltage)..........................................................................................................................................5.5V Low State (Reverse Current) ......................................................................................................................-5.0mA Error Amp Output Sink Current......................................................................................................................................10mA Storage Temperature Range ................................................................................................................................-65 to +150°C Operating Junction Temperature...................................................................................................................................+150°C Operating Ambient Temperature.............................................................................................................................0 to +70°C Lead Temperature Soldering Wave Solder (through hole styles only) .................................................................................10 sec. max, 260°C peak Reflow (SMD styles only) ..................................................................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: VCC = 15V, RT = 8.2kΩ, CT = 3.3nF, for typical values TA=25˚C, for min/max values TA is the operating ambient temperature range that applies [Note 3]. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.9 5.0 5.1 V ■ Reference Section Reference Output Voltage, VREF IOUT=1.0mA, TJ=25°C Line Regulation 11V≤VCC≤15V 2.0 20.0 mV Load Regulation 1.0mA≤IOUT≤10mA 3.0 25.0 mV 5.15 V Total Output Variation over Line, Load and Temperature 4.85 Output Short Circuit Current 30 100 46.5 49.0 51.5 kHz 0.2 1.0 % 49.5 52.0 % 170 80 250 160 µA 2.50 2.58 V -0.1 -1.0 µA mA ■ Oscillator and PWM Sections Total Frequency Variation over Line and Temperature 11V≤VCC≤15V, Tlow≤TA≤Thigh Frequency Change with Voltage 11V≤VCC≤15V Duty Cycle at each Output Maximum Sync Input Current High State VIN=2.4V Low State VIN=0.8V 46.0 ■ Error Amplifiers Voltage Feedback Input VOUT=2.5V 2.42 Input Bias Current VFB=5.0V Open-Loop Voltage Gain VOUT=2.0 to 4.0V 65 100 dB Unity Gain Bandwidth TJ=25°C (note 6) 0.7 1.0 MHz Power Supply Rejection Ratio VCC=11V to 15V 60 90 dB -0.45 2.00 -1.00 12.00 mA mA 5.0 6.2 V Output Current Source VOUT=3.0V, VFB=2.3V Sink VOUT=1.2V, VFB=2.7V Output Voltage Swing High State, RL=15k to ground, VFB=2.3V Low State, RL=15k to VREF, VFB = 2.7V 2 0.8 1.1 ambient temperature range that applies [Note 3]. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ■ Current Sense Section Current Sense Input Voltage Gain (Notes 4 and 5) 2.75 3.00 3.25 V/V Maximum Current Sense Input Threshold (Note 4) 430 480 530 mV -2.0 -10.0 µA 150 300 ns VREF 1.5 V V Input Bias Current Propagation Delay Current Sense Input to Output (Note 6) ■ Output 2 Enable Pin Enable Pin Voltage High State Low State Output 2 enabled Output 2 disabled 3.5 0.0 Low State Input Current VIL= 0V 100 250 400 µA 0.4 2.5 13.0 12.0 0.1 1.6 13.5 13.4 V V V V VCC=6.0V, ISINK=1.0mA 0.1 1.1 V Output Voltage Rise Time CL=1.0nF (Note 6) 28 150 ns Output Voltage Fall Time CL=1.0nF (Note 6) 25 150 ns 13 14 15 V 9.0 10.0 11.0 V ■ Drive Outputs Output Voltage Low State High State Output Voltage with UVLO Activated ISINK=20mA ISINK=200mA ISOURCE=20mA ISOURCE=200mA ■ Undervoltage Lockout Section Start-Up Threshold CS3865C Minimum Operating Voltage After Turn-On Hysteresis 4 V ■ Total Device Start-Up Current Operating Current VCC=12V (Note 7) Power Supply Zener Voltage ICC=30mA 15.5 Note 1: Maximum package power dissipation limits must be observed. 1.0 25 mA mA 17.0 19.0 V Note 6: These parameters are guaranteed by design but not 100% tested in production. Note 3: Adjust VCC above the Start-Up threshold before setting to 15V. Note 7: Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible: Tlow=0°C ; Thigh=+70°C Note 4: This parameter is measured at latch trip point with VFB =0V. Note 5: Comparator gain is defined as: 0.6 20 ∆V Compensation AV = ∆V Current Sense 3 CS3865C Electrical Characteristics: VCC = 15V, RT = 8.2kΩ, CT = 3.3nF, for typical values TA=25˚C, for min/max values TA is the operating PACKAGE PIN # PIN SYMBOL FUNCTION 16 L PDIP & SO Wide 1 SYNC A positive going pulse applied to this input will synchronize the oscillator. A DC voltage within the range of 2.4V to 5.5V will inhibit the oscillator. 2 CT Timing capacitor CT connects pin to ground setting oscillator frequency. 3 RT Resistor RT connects to ground setting the charge current for CT. Its value must be between 4.0k and 16k. 4 VFB1 The inverting input of error amplifier 1. Normally it is connected to the switching power supply output. 5 COMP1 The output of error amplifier 1, for loop compensation. 6 Sense1 Output 1 pulse by pulse current limit. 7 VOUT1 Drives the power switch at output 1. 8 Gnd 9 Pwr Gnd 10 VOUT2 Drives the power switch at output 2. 11 Sense2 Output 2 pulse by pulse current limit. 12 COMP2 Output of error amplifier 2, for loop compensation. 13 VFB2 14 ENABLE2 15 VREF 5.0V reference output. It can source current in excess of 30mA. 16 VCC The positive supply of the IC. Logic ground Power ground. Power device return is connected to this pin. Inverting input of error amplifier 2. Normally it is connected to the switching power supply output. Output 2 disable. A logic low at this pin disables VOUT2. Typical Performance Characteristics Timing Resistor vs. Oscillator Frequency Max. Output Duty Cycle vs. Oscillator Frequency 50 MAXIMUM DUTY CYCLE (%) F 100p pF 220 pF F pF 500 330 2.2n nF nF 5.0 F 10n 10 3.3 12 F 1.0n 14 C T= RT TIMING RESISTOR (KΩ) 16 8.0 VCC= 6.0 15V TA=25°C 4.0 10k 30k 50k 100k 300k 500k 48 OUT 2 46 OUT 1 44 42 VCC = 15V RT = 4.0kΩ to 16kΩ CL = 15pF TA = 25°C 40 38 10k 1.0M f OSC OSCILLATOR FREQUENCY (Hz) 40 30 60 PHASE 90 20 120 0 150 -20 10k 100k 1.0k 10k 100k 1.0M Vth, CURRENT SENSE INPUT THRESHHOLD (V) 60 100k 300k 500k 1.0M 0.6 Phase Margin (DEGREES) VCC = 15V VO = 1.5V TO 2.5V RL = 100kΩ TA = 25°C GAIN 50k Current Sense Input Threshold vs. Error Amp Output Voltage 0 100 80 30k f OSC OSCILLATOR FREQUENCY (Hz) Error Amp Open-Loop Gain & Phase vs. Frequency AVOL, OPEN-LOOP VOLTAGE GAIN (dB) CS3865C Package Pin Description 180 10M VCC = 15V 0.5 0.4 TA = 125°C TA = 25°C 0.3 TA = -55°C 0.2 0.1 0 0 f, FREQUENCY (Hz) 1.0 2.0 3.0 4.0 5.0 6.0 ERROR AMP OUTPUT VOLTAGE (V) 4 7.0 Reference Voltage Change vs. Source Current Reference Short Circuit Current vs. Temperature ISC, REFERENCE SHORT CIRCUIT CURRENT (mA) 0 ∆ VREF, REFERENCE Voltage (mV) VCC = 15V -4.0 -8.0 TA = –55°C -12 TA = 25°C -16 TA = 125°C -20 -24 0 20 40 60 80 100 I ref, REFERENCE SOURCE CURRENT (mA) 120 100 80 60 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) Supply Current vs. Supply Voltage CS3865C Output Saturation Voltage vs. Load Current 32 VCC SOURCE SATURATION (LOAD TO GROUND) -1.0 VCC=15V 80µS PULSED LOAD 120Hz RATE TA=25°C ICC, SUPPLY CURRENT (mA) 0 Vsat, OUTPUT SATURATION VOLTAGE (V) 120 -2.0 TA= –55°C TA= –55°C 2.0 TA=25°C 1.0 GND 0 0 SINK SATURATION (LOAD TO VCC) 200 400 600 OUTPUT LOAD CURRENT (mA) RT=8.2kΩ CT=3.3nF VFB 1.2=0V 24 CURRENT SENSE 1.2=0V TA=25°C 16 8.0 0 0 800 4.0 8.0 12 16 20 VCC, SUPPLY VOLTAGE (V) Operating Description The CS3865C is a high performance, fixed frequency, dual channel current mode PWM controller specifically designed for off-line and DC to DC converter applications. It offers the designer a cost effective solution with minimal external components where independent regulation of two power converters is required. Each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. The oscillator, reference, and undervoltage lockout circuits are common to both channels. charging, and the primary is enabled during the discharge. Even at 500kHz, each output is capable of approximately 44% duty cycle, making this controller suitable for high frequency power conversion applications. In many noise sensitive applications, it may be necessary to synchronize the converter with an external system clock. This can be accomplished by applying an external clock signal. For reliable synchronization, the oscillator frequency should be set about 10% slower than the clock frequency. The rising edge of the clock signal applied to SYNC, terminates CT‘s charging and VOUT2‘s conduction. By tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. Oscillator The oscillator uses precise frequency and duty cycle control. The frequency is programmed by the values RT and CT. Capacitor, CT, is charged and discharged by an equal magnitude internal current source and sink, generating a symmetrical 50 percent duty cycle waveform at CT. The oscillator peak and valley thresholds are 3.5V and 1.6V respectively. The source/sink current magnitude is controlled by resistor RT. For proper operation over temperature range, its value should be between 4.0kΩ and 16kΩ. Error Amplifier Each channel contains a fully-compensated error amplifier. The output and inverting input nodes are accessible. The amplifier features a typical dc voltage gain of 100 dB, and a unity gain bandwidth of 1.0 MHz with 71 degrees of phase margin. The non-inverting input is internally biased at 2.5V. The converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. The maximum input bias current is -1.0µA which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider resistance. As CT charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non-overlapping output duty cycles. The second output, VOUT2 is enabled while CT is 5 CS3865C Typical Performance Characteristics: continued CS3865C Operating Description continued The error amp is compensated externally thru the VFB and COMP pins. Its output voltage is offset by two diode drops (≈1.4V) and divided by three before it connects to the inverting input of the current sense comparator. This guarantees that both outputs are disabled when the error amplifier output is at its lowest state which occurs when the power supply is operating at light or no-load conditions, or at the beginning of a soft-start interval. Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stages are enabled. Power supply terminal (VCC) and the reference output (VREF) are monitored by separate comparator. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The upper and lower thresholds of the VCC comparator are 14V and 10V respectively. The minimum allowable error amplifier feedback resistance is limited by the amplifier’s source current capability (0.5 mA) and the output voltage (VOH) required to reach the current sense comparator 0.5V clamp level with the error amplifier inverting input at ground. This condition happens during initial system start up or when the sensed output is shorted: 3 x 0.5V + 1.4V = 5800Ω RF(min) ≈ 0.5mA The VREF comparator disables the drive outputs until the internal circuitry is functional. This comparator has upper and lower thresholds of 3.6V and 3.4V. A 17V zener is connected as a shunt regulator from VCC to ground to protect the IC and power MOSFET gate from excessive voltage. The guaranteed minimum operating voltage after turn-on is 11V. Outputs and Power Ground Current Sense Comparator and PWM Latch Each channel contains a single totem-pole output stage that is specifically designed for direct drive of power MOSFET’s. The outputs have up to ±1.0A peak current capability and have a typical rise and fall time of 28 ns with a 1.0nF load. Internal circuitry has been added to keep the outputs in active pull-down mode whenever an undervoltage lockout is active, eliminating the need for an external pull-down resistor. The CS3865C operates as a current mode controller. Output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output. Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The current sense comparator-PWM Latch combination ensures that only a single pulse appears at the drive output (VOUT) during any given oscillator cycle. The current is converted to a voltage by connecting a sense resistor RSense in series with the source of output switch Q1 and ground. This voltage is monitored through the Sense1,2 pins and compared to a voltage derived from the error amp output. The peak current under normal operating conditions is controlled by the voltage at COMP where: Although the outputs are optimized for MOSFET’s, they can easily supply the negative base current required by bipolar NPN transistors for enhanced turn-off. Since the outputs do not contain internal current limits an external series resistor will be required to prevent the peak output current from exceeding the ±1.0A maximum rating. The sink saturation (VOL) is less than 0.4V at 100mA. A separate ground pin, Pwr Gnd, is provided. Properly implemented, will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes important when the Ipk(max) clamp level is reduced. Ipk = V(COMP) – 1.4V 3RSense Abnormal operating conditions occur when the power supply output is overloaded or if output voltage is too high. Under these conditions, the current sense comparator threshold will be internally clamped to 0.5V. Therefore the maximum peak switch current is: 0.5V Ipk(max) = RSense Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk (max) clamp voltage. ENABLE2 This input is used to switch VOUT2. VOUT1 is used to control circuitry that runs continuously, e.g. volatile memory, the system clock, or a remote controlled receiver. VOUT2 output can control the high power circuitry that is turned off when not needed. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. The addition of an RC filter on the current sense input reduces this spike to an acceptable level. Voltage Reference The 5.0V bandgap reference is trimmed to ±2.0% tolerance. The reference has short circuit protection and is capable of sourcing 30mA for powering any additional external circuitry. 6 ter capacitor. Ceramic bypass capacitors (0.1µF) connected directly to VCC and VREF may be required to improve noise filtering. They provide a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs. The error amp compensation circuitry and the converter output voltage-divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Design Considerations High frequency circuit layout techniques are imperative to prevent pulse-width jitter. This is usually caused by excessive noise pick-up imposed on the current sense and voltage feed-back inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit board layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input fil- Timing Diagram SYNC CT Latch 1 “Set” Input COMP1 Sense1 Latch 1 “Reset” Input VOUT1 ENABLE2 0V Latch 2 “Set” Input COMP2 Sense2 Latch 2 “Reset” Input VOUT2 Applications Diagram Dual Boost Regulator VIN VCC CF1 + 5.0V CF2 VREF 2.5V R Reference Regulator Internal Bias R + - + 3.4V - VREF UVLO + - VCC + UVLO - 17V 14V L1 D1 20kΩ Sync VOUT1 RT CT RFB1 VFB1 RFB2 COMP1 + + Current Sense 2R Comparator 1 + + Error 1.0mA R + 0.5V Amp 1 RFB4 + Error Amp 2 L2 VOUT1 D2 RSense1 + Sense1 Q2 + VOUT2 VFB2 PWM Latch 1 S Q R 250µA ENABLE2 RFB3 Q1 Oscillator Current Sense Comparator 1 2R + 1.0mA R 0.5V PWM Latch 2 S RQ R VOUT2 Sense2 COMP2 Gnd Pwr Gnd 7 VOUT1 COUT1 RSense2 VOUT2 COUT2 CS3865C Operating Description: continued CS3865C Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA D Lead Count Metric Max Min 19.69 18.67 10.50 10.10 16L PDIP 16L SO Thermal Data English Max Min .775 .735 .413 .398 RΘJC RΘJA typ typ 16 Lead PDIP 42 80 16 Lead SO 23 105 ˚C/W ˚C/W Surface Mount Wide Body (DW); 300 mil wide 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 2.49 (.098) 2.24 (.088) 1.27 (.050) 0.40 (.016) 2.65 (.104) 2.35 (.093) 0.32 (.013) 0.23 (.009) 0.30 (.012) 0.10 (.004) D REF: JEDEC MS-013 Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) REF: JEDEC MS-001 D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. Ordering Information Part Number CS3865CGN16 CS3865CGDW16 CS3865CGDWR16 Rev. 12/16/96 Description 16L PDIP 16L SO Wide 16L SO Wide (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 8 © 1999 Cherry Semiconductor Corporation