CET CEU05N65 N-channel enhancement mode field effect transistor Datasheet

CED05N65/CEU05N65
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
650V, 4A, RDS(ON) = 2.4Ω @VGS = 10V.
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
D
Lead-free plating ; RoHS compliant.
TO-251 & TO-252 package.
G
D
G
S
CEU SERIES
TO-252(D-PAK)
ABSOLUTE MAXIMUM RATINGS
Parameter
G
D
S
CED SERIES
TO-251(I-PAK)
Tc = 25 C unless otherwise noted
Symbol
Limit
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous @ TC = 25 C
@ TC = 100 C
ID
Drain Current-Pulsed a
IDM
Maximum Power Dissipation @ TC = 25 C
PD
- Derate above 25 C
Single Pulsed Avalanche Energy
S
d
Single Pulsed Avalanche Current d
Operating and Store Temperature Range
650
Units
V
±30
V
4
A
2.5
A
16
A
56
W
0.45
W/ C
EAS
43
mJ
IAS
3.5
A
TJ,Tstg
-55 to 150
C
Thermal Characteristics
Symbol
Limit
Units
Thermal Resistance, Junction-to-Case
Parameter
RθJC
2.2
C/W
Thermal Resistance, Junction-to-Ambient
RθJA
50
C/W
Rev 3. 2011.Nov
http://www.cetsemi.com
Details are subject to change without notice .
1
CED05N65/CEU05N65
Electrical Characteristics
Parameter
Tc = 25 C unless otherwise noted
Symbol
Test Condition
Min
Drain-Source Breakdown Voltage
BVDSS
VGS = 0V, ID = 250µA
650
Zero Gate Voltage Drain Current
IDSS
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
Typ
Max
Units
VDS = 650V, VGS = 0V
25
µA
IGSSF
VGS = 30V, VDS = 0V
100
nA
IGSSR
VGS = -30V, VDS = 0V
-100
nA
4
V
2.4
Ω
Off Characteristics
V
On Characteristics b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
VGS(th)
VGS = VDS, ID = 250µA
RDS(on)
VGS = 10V, ID = 2A
Dynamic Characteristics c
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = 25V, VGS = 0V,
f = 1.0 MHz
2
2
570
pF
105
pF
20
pF
Switching Characteristics c
Turn-On Delay Time
td(on)
Turn-On Rise Time
tr
Turn-Off Delay Time
td(off)
VDD = 300V, ID = 4A,
VGS = 10V, RGEN = 25Ω
23
46
ns
13
35
26
70
ns
ns
Turn-Off Fall Time
tf
11
22
ns
Total Gate Charge
Qg
8.3
11
nC
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 480V, ID = 4A,
VGS = 10V
3
nC
3.1
nC
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
IS
Drain-Source Diode Forward Voltage b
VSD
VGS = 0V, IS = 4A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d.L = 7mH, IAS = 3.5A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C
2
4
A
1.5
V
CED05N65/CEU05N65
9
VGS=10,8,7V
5
ID, Drain Current (A)
ID, Drain Current (A)
6
4
VGS=5V
3
2
1
0
0.0
5
10
15
20
25
TJ=125C
1
2
-55 C
3
4
5
6
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
Ciss
600
400
Coss
200
Crss
0
5
10
15
20
25
3.0
2.5
ID=2A
VGS=10V
2.0
1.5
1.0
0.5
0.0
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
VDS=VGS
ID=250µA
1.1
1.0
0.9
0.8
0.7
0.6
-50
25 C
1.5
VGS, Gate-to-Source Voltage (V)
IS, Source-drain current (A)
C, Capacitance (pF)
VTH, Normalized
Gate-Source Threshold Voltage
3
VDS, Drain-to-Source Voltage (V)
800
1.2
4.5
30
1000
1.3
6
0
1200
0
7.5
-25
0
25
50
75
100
125
VGS=0V
10
1
10
0
10-1
0.4
150
0.7
1.0
1.3
1.7
2.0
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
10
VDS=480V
ID=4A
10
8
ID, Drain Current (A)
VGS, Gate to Source Voltage (V)
CED05N65/CEU05N65
6
4
2
0
0
2
4
6
8
10
0
10
-1
10
10
1
RDS(ON)Limit
100ms
1ms
10ms
DC
TC=25 C
TJ=175 C
Single Pulse
-2
10
0
10
1
10
2
10
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
t on
RL
V IN
D
VGS
RGEN
toff
tr
td(on)
td(off)
tf
90%
90%
VOUT
VOUT
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
Figure 9. Switching Test Circuit
10
0
D=0.5
0.2
10
-1
PDM
0.1
t1
0.05
0.02
0.01
Single Pulse
10
-2
10
-5
t2
1. RθJA (t)=r (t) * RθJA
2. RθJA=See Datasheet
3. TJM-TA = P* RθJC (t)
4. Duty Cycle, D=t1/t2
10
-4
10
-3
10
-2
10
-1
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
10
0
10
1
3
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