AD AD7787BRMZ-RL Low power, 2-channel 24-bit sigma-delta adc Datasheet

Low Power, 2-Channel
24-Bit Sigma-Delta ADC
AD7787
Data Sheet
FEATURES
APPLICATIONS
Power
Supply: 2.5 V to 5.25 V operation
Normal mode: 75 µA max
Power-down mode: 1 µA max
RMS noise: 1.1 µV at 9.5 Hz update rate
19.5-bit p-p resolution (22 bits effective resolution)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Rail-to-rail input buffer
VDD monitor channel
Temperature range: −40°C to +105°C
10-lead MSOP
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
GENERAL DESCRIPTION
The AD7787 is a low power, complete analog front end for low
frequency measurement applications. It contains a low noise
24-bit Σ-Δ ADC with one differential input and one singleended input that can be buffered or unbuffered.
INTERFACE
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 µV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a
reduction in the current consumption. The update rate, cutoff
frequency, and settling time scales with the clock frequency.
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 µW maximum. It is housed in a 10-lead MSOP.
FUNCTIONAL BLOCK DIAGRAM
GND
VDD
REFIN
AD7787
VDD
DOUT/RDY
AIN1(–)
BUF
MUX
Σ-∆
ADC
AIN2
CLOCK
GND
DIN
SCLK
CS
04477-0-001
AIN1(+)
SERIAL
INTERFACE
AND
LOGIC
CONTROL
Figure 1.
Rev. A
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DOCUMENTATION
• MS-2210: Designing Power Supplies for High Speed ADC
Application Notes
• AN-607: Selecting a Low Bandwidth (<15 kSPS) SigmaDelta ADC
DESIGN RESOURCES
• AN-968: Current Sources: Options and Circuits
• PCN-PDN Information
Data Sheet
• Quality And Reliability
• AD7787: Low Power, 2-Channel 24-Bit Sigma-Delta ADC
Data Sheet
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SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7791 IIO Low Power Sigma-Delta ADC Linux Driver
TOOLS AND SIMULATIONS
• Sigma-Delta ADC Tutorial
REFERENCE DESIGNS
• CN0354
• AD7787 Material Declaration
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AD7787
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Overview ..................................................................................... 14
Timing Characteristics..................................................................... 5
Noise Performance ..................................................................... 14
Absolute Maximum Ratings............................................................ 7
Reduced Current Modes ........................................................... 14
ESD Caution .................................................................................. 7
Digital Interface .......................................................................... 15
Pin Configuration and Function Descriptions ............................. 8
Circuit Description......................................................................... 18
Typical Performance Characteristics ............................................. 9
Analog Input Channel ............................................................... 18
On-Chip Registers .......................................................................... 10
Bipolar/Unipolar Configuration .............................................. 18
Communications Register (RS1, RS0 = 0, 0) .......................... 10
Data Output Coding .................................................................. 18
Status Register (RS1, RS0 = 0, 0; Power-On/Reset
= 0×8C) ........................................................................................ 11
Reference Input........................................................................... 18
Mode Register (RS1, RS0 = 0, 1; Power-On/Reset
= 0×02) ......................................................................................... 12
Filter Register (RS1, RS0 = 1, 0; Power-On/Reset
= 0×04) ......................................................................................... 13
Data Register (RS1, RS0 = 1, 1; Power-On/Reset
= 0×000000) ................................................................................ 13
VDD Monitor ................................................................................ 19
Grounding and Layout .............................................................. 19
Applications ................................................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
ADC Circuit Information .............................................................. 14
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Changes to Figure 13 .......................................................................15
Change to Reference Input Section ...............................................18
Updated Outline Dimensions ........................................................20
Changes to Ordering Guide ...........................................................20
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD7787
SPECIFICATIONS
Temperature range is −40°C to +105°C. VDD = 2.5 V to 5.25 V; REFIN = 2.5 V; GND = 0 V; CDIV1 = CDIV0 = 0; all specifications TMIN to
TMAX, unless otherwise noted.
Table 1.
Parameter
ADC CHANNEL SPECIFICATION
Output Update Rate
ADC CHANNEL
No Missing Codes 1
Resolution
Output Noise
Integral Nonlinearity
Offset Error
Offset Error Drift vs. Temperature
Full-Scale Error 2
Gain Drift vs. Temperature
Power Supply Rejection
ANALOG INPUTS
Bipolar Input Voltage Range
Unipolar Voltage Range
Absolute AIN Voltage Limits1
Analog Input Current
Average Input Current1
Average Input Current Drift
Absolute AIN Voltage Limits1, 3
Analog Input Current
Average Input Current
Average Input Current Drift
Normal Mode Rejection1
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common-Mode Rejection (AIN1)
@ DC
@ 50 Hz, 60 Hz1
REFERENCE INPUT
REFIN Voltage
Reference Voltage Range1
Average Reference Input Current
Average Reference Input Current Drift
Normal Mode Rejection1
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
AD7787B
Unit
Test Conditions/Comments
9.5
120
Hz min nom
Hz max nom
24
19.5
1.1
±15
±3
±10
±10
±0.5
90
Bits min
Bits p-p
µV rms typ
ppm of FSR max
µV typ
nV/°C typ
µV typ
ppm/°C typ
dB min
Update rate ≤ 20 Hz.
9.5 Hz update rate.
±REFIN
V nom
Because AIN2 is single-ended, it can have a negative
voltage of 100 mV minimum (see Page 18).
0 to REFIN
GND + 100 mV
VDD – 100 mV
V nom
V min
V max
±1
±5
GND – 100 mV
VDD + 30 mV
nA max
pA/°C typ
V min
V max
±400
±50
nA/V typ
pA/V/°C typ
65
80
80
dB min
dB min
dB min
90
100
dB min
dB min
2.5
0.1
VDD
0.5
±0.03
V nom
V min
V max
µA/V typ
nA/V/°C typ
65
80
80
dB min
dB min
dB min
3.5 ppm typ.
100 dB typ, AIN = 1 V.
Buffered mode.
Buffered mode.
Unbuffered mode.
Unbuffered mode. Current varies with input voltage.
Rev. A | Page 3 of 20
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 4.
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014.
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114.
AIN = 1 V.
100 dB typ.
50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114).
73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004.
90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014.
90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114.
AD7787
Parameter
LOGIC INPUTS
All Inputs Except SCLK1
VINL, Input Low Voltage
VINH, Input High Voltage
SCLK Only (Schmitt-Triggered Input)1
VT(+)
VT(−)
VT(+) − VT(−)
VT(+)
VT(−)
VT(+) − VT(−)
Input Currents
Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage1
VOL, Output Low Voltage1
VOH, Output High Voltage1
VOL, Output Low Voltage1
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
POWER REQUIREMENTS 5
Power Supply Voltage
VDD − GND
Power Supply Currents
IDD Current 6
IDD (Power-Down Mode)
Data Sheet
AD7787B
Unit
Test Conditions/Comments
0.8
0.4
2.0
V max
V max
V min
VDD = 5 V.
VDD = 3 V.
VDD = 3 V or 5 V.
1.4/2
0.8/1.4
0.3/0.85
0.9/2
0.4/1.1
0.3/0.85
±1
10
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
µA max
pF typ
VDD = 5 V.
VDD = 5 V.
VDD = 5 V.
VDD = 3 V.
VDD = 3 V.
VDD = 3 V.
VIN = VDD or GND.
All Digital Inputs.
VDD − 0.6
0.4
4
0.4
±1
10
Offset Binary
V min
V max
V min
V max
µA max
pF typ
VDD = 3 V, ISOURCE = 100 µA.
VDD = 3 V, ISINK = 100 µA.
VDD = 5 V, ISOURCE = 200 µA.
VDD = 5 V, ISINK = 1.6 mA.
2.5/5.25
V min/max
75
145
80
160
1
µA max
µA max
µA max
µA max
µA max
65 µA typ, VDD = 3.6 V, unbuffered mode.
130 µA typ, VDD = 3.6 V, buffered mode.
73 µA typ, VDD = 5.25 V, unbuffered mode.
145 µA typ, VDD = 5.25 V, buffered mode.
Specification is not production tested but is supported by characterization data at initial product release.
Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
3
The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase.
4
FS[2:0] are the three bits used in the filter register to select the output word rate.
5
Digital inputs equal to VDD or GND.
6
The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).
1
2
Rev. A | Page 4 of 20
Data Sheet
AD7787
TIMING CHARACTERISTICS
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed
from a voltage level of 1.6 V (see Figure 3 and Figure 4).
VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 2.
Parameter
t3
t4
Read Operation
t1
t2 1
t5 3, 4
t6
t7
Write Operation
t8
t9
t10
t11
Limit at TMIN, TMAX (B Version)
100
100
Unit
ns min
ns min
Conditions/Comments
SCLK High Pulse Width
SCLK Low Pulse Width
0
60
80
0
60
80
10
80
100
10
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns max
ns min
CS Falling Edge to DOUT/RDY Active Time
VDD = 4.75 V to 5.25 V
VDD = 2.5 V to 3.6 V
SCLK Active Edge to Data Valid Delay 2
VDD = 4.75 V to 5.25 V
VDD = 2.5 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
0
30
25
0
ns min
ns min
ns min
ns min
CS Falling Edge to SCLK Active Edge Setup Time2
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
The SCLK active edge is the falling edge of SCLK.
3
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
4 RDY
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
1
2
Rev. A | Page 5 of 20
AD7787
Data Sheet
ISINK (1.6mA WITH VDD = 5V,
100A WITH VDD = 3V)
TO OUTPUT
PIN
1.6V
ISOURCE (200A WITH VDD = 5V,
100A WITH VDD = 3V)
04477-0-002
50pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
t6
t1
t5
MSB
DOUT/RDY (O)
LSB
t7
t2
t3
04477-0-003
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
t9
DIN (I)
MSB
LSB
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
Rev. A | Page 6 of 20
04477-0-004
t10
Data Sheet
AD7787
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog Input Voltage to GND
Reference Input Voltage to GND
Total AIN/REFIN Current (Indefinite)
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
MSOP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
30 mA
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
206°C/W
44°C/W
300°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 20
AD7787
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS 2
AIN1(+) 3
10 DIN
AD7787
TOP VIEW
AIN1(–) 4 (Not to Scale)
REFIN 5
9
DOUT/RDY
8
VDD
7
GND
6
AIN2
04477-0-005
SCLK 1
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
Mnemonic
SCLK
2
CS
3
4
5
AIN1(+)
AIN1(–)
REFIN
6
7
8
9
AIN2
GND
VDD
DOUT/RDY
10
DIN
Function
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a
continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or
from the ADC in smaller batches of data.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems
with more than one device on the serial bus or as a frame synchronization signal in communicating with the device.
CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface
with the device.
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).
Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
Reference Input. REFIN can be anywhere between VDD and GND + 0.1 V. The nominal reference voltage is 2.5 V, but the
part functions with a reference from 0.1 V to VDD.
Analog Input. AIN2 is a single-ended analog input.
Ground Reference Point.
Supply Voltage, 2.5 V to 5.25 V.
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to
access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or
control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a
conversion. If the data is not read after the conversion, the pin will go high before the next update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an
external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is
placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is
three-stated, but the RDY bit remains active.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers
within the ADC; the register selection bits of the communications register identifying the appropriate register.
Rev. A | Page 8 of 20
Data Sheet
AD7787
TYPICAL PERFORMANCE CHARACTERISTICS
0
9
–30
VDD = 3V
VREF = 2.048V
8 1.1875Hz
UPDATE RATE
TA = 25°C
7 RMS NOISE = 1.25µF
–40
6
–10
OCCURRENCE
–20
–60
–70
–80
3
–90
2
04477-0-012
–100
–110
–120
0
20
40
80
60
100
FREQUENCY (Hz)
120
140
1
0
8388592
160
100
80
8388616
CODE
Figure 6. Frequency Response with 16.6 Hz Update Rate
Figure 9. Noise Histogram for Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1)
VDD = 3V
VREF = 2.048V
9.5Hz UPDATE RATE
TA = 25°C
RMS NOISE = 1µV
8388616
60
CODE
OCCURRENCE
5
4
04477-0-014
dB
–50
40
04477-0-010
20
8388592
8388619
CODE
Figure 7. Noise Distribution Histogram (CDIV1 = CDIV0 = 0)
0
3.0
RMS NOISE (µV)
CODE
0
200
400
600
READ NO.
100
2.0
1.5
1.0
04477-0-015
0.5
04477-0-011
800
80
VDD = 5V
UPDATE RATE = 16.6Hz
TA = 25°C
2.5
8388591
40
60
READ NO.
Figure 10. Noise Plot in Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1)
8388619
VDD = 3V, VREF = 2.048V, 9.5Hz UPDATE RATE
TA = 25°C, RMS NOISE = 1µV
20
04477-0-013
0
8388591
VDD = 3V, VREF = 2.048V
1.1875Hz UPDATE RATE
TA = 25°C, RMS NOISE = 1.25µF
0
1000
0
Figure 8. Typical Noise Plot with 16.6 Hz Update Rate (CDIV1 = CD1V0 = 0)
Rev. A | Page 9 of 20
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
3.5
4.0
Figure 11. RMS Noise vs. Reference Voltage
4.5
5.0
AD7787
Data Sheet
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the
communications register. The data written to the communications register determines whether the next operation is a read or write
operation and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to
the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the
default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the
communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN
high returns the ADC to this default state by resetting the entire part.
Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are
in the communications register. CR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset
default status of that bit.
CR7
WEN (0)
CR6
0 (0)
CR5
RS1 (0)
CR4
RS0 (0)
CR3
R/W (0)
CR2
CREAD (0)
CR1
CH1 (0)
CR0
CH0 (0)
Table 5. Communications Register Bit Designations
Bit
Location
CR7
Bit
Name
WEN
CR6
CR5 to
CR4
CR3
0
RS1 to
RS0
R/W
CR2
CREAD
CR1 to
CR0
CH1 to
CH0
Description
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a
1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until
a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications
register.
This bit must be programmed to Logic 0 for correct operation.
Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected during
this serial interface communication (see Table 6).
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates
that the next operation is a read from the designated register.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface
is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on
the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be
written to for data reads. To enable continuous read mode, the instruction 00111100 (Channel AIN1) or 00111101
(Channel AIN2) must be written to the communications register. To exit the continuous read mode, the instruction
001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode,
the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode.
Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous
read mode until an instruction is to be written to the device.
These bits are used to select the analog input channel. Channel AIN1 or AIN2 can be selected or an internal short
(AIN1(−)/AIN1(−)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the
voltage on the power supply, which is useful for monitoring power supply variation. To perform this measurement,
the power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a
1.17
V ± 5% on-chip reference as the reference source when this channel is selected. Any change in channel resets the
filter and a new conversion is started.
Rev. A | Page 10 of 20
Data Sheet
AD7787
Table 6. Register Selection
RS1
0
0
0
1
1
RS0
0
0
1
0
1
Register
Communications Register during a Write Operation
Status Register during a Read Operation
Mode Register
Filter Register
Data Register
Register Size
8-Bit
8-Bit
8-Bit
8-Bit
24-Bit
Table 7. Channel Selection
CH1
0
0
1
1
CH0
0
1
0
1
Channel
AIN1(+) − AIN1(−)
AIN2
AIN1(−) − AIN1(−)
VDD Monitor
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in the parenthesis indicates the power-on/reset default status of that bit.
SR7
RDY (1)
SR6
ERR (0)
SR5
0 (0)
SR4
0 (0)
SR3
1 (1)
SR2
1 (1)
SR1
CH1 (0)
SR0
CH0 (0)
Table 8. Status Register Bit Designations
Bit
Location
SR7
Bit
Name
RDY
SR6
ERR
SR5 to
SR4
SR3 to
SR2
SR1 to
SR0
0
Description
Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the
ADC data register has been read or a period of time before the data register is updated with a new conversion result
to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode.
The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status
register for monitoring the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC
data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write
operation to start a conversion.
These bits are automatically cleared.
1
These bits are automatically set.
CH1 to
CH0
These bits indicate which channel is being converted by the ADC.
Rev. A | Page 11 of 20
AD7787
Data Sheet
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0×02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 9 outlines the bit
designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7
denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. Any write to
the setup register resets the modulator and filter and sets the RDY bit.
MR7
MD1 (0)
MR6
MD0 (0)
MR5
0 (0)
MR4
0 (0)
MR3
BO (0)
MR2
U/B (0)
MR1
BUF (1)
MR0
0 (0)
Table 9. Mode Register Bit Designations
Bit
Location
MR7 to
MR6
Bit
Name
MD1 to
MD0
MR5 to
MR4
MR3
0
MR2
U/B
MR1
BUF
MR0
0
BO
Description
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby
mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the
data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the
device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK
pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the
communications register. After power-on, the first conversion is available after a period 2/fADC while subsequent
conversions are available at a frequency of fADC. In single conversion mode, the ADC is placed in power-down mode
when conversions are not being performed. When single conversion mode is selected, the ADC powers up and
performs a single conversion, which occurs after a period 2/fADC. The conversion result is placed in the data register,
RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY
remains active (low) until the data is read or another conversion is performed (see Table 10).
These bits must be programmed with a Logic 0 for correct operation.
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are
enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the
buffer is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input results in 0x000000 output and
a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative fullscale differential input results in an output code of 0x000000, zero differential input results in an output code of
0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF.
Configures the AD7787 for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered
mode, lowering the power consumption of the device. If set, the device operates in buffered mode, allowing the
user to place source impedances on the front end without contributing gain errors to the system.
This bit must be programmed with a Logic 0 for correct operation.
Table 10. Operating Modes
MD1
0
0
1
1
MD0
0
1
0
1
Mode
Continuous Conversion Mode (Default)
Reserved
Single Conversion Mode
Power-Down Mode
Rev. A | Page 12 of 20
Data Sheet
AD7787
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output
word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are
in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status
of that bit.
FR7
0 (0)
FR6
0 (0)
FR5
CDIV1 (0)
FR4
CDIV0 (0)
FR3
0 (0)
FR2
FS2 (1)
FR1
FS1 (0)
FR0
FS0 (0)
Table 11. Filter Register Bit Designations
Bit
Location
FR7 to
FR6
FR5 to
FR4
FR3
FR2 to
FR0
Bit Name
0
Description
These bits must be programmed with a Logic 0 for correct operation.
CLKDIV1
to CDIV0
These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the
power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing
the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00
Normal Mode
01
Clock Divided by 2
10
Clock Divided by 4
11
Clock Divided by 8
This bit must be programmed with a Logic 0 for correct operation.
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the
noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes, the
update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2, the
corresponding update rates are divided by 2 also.
0
FS2 to FS0
Table 12. Update Rates
FS2
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
fADC (Hz)
120
100
33.3
20
16.6
16.7
13.3
9.5
f3dB (Hz)
28
24
8
4.7
4
4
3.2
2.3
RMS Noise (µV)
40
25
3.36
1.6
1.5
1.5
1.2
1.1
Rejection
25 dB @ 60 Hz
25 dB @ 50 Hz
80 dB @ 60 Hz
65 dB @ 50 Hz/60 Hz (Default Setting)
80 dB @ 50 Hz
67 dB @ 50 Hz/60 Hz
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
Rev. A | Page 13 of 20
AD7787
Data Sheet
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7787 is a low power ADC that incorporates an Σ-Δ
modulator, a buffer, and an on-chip digital filter intended for
the measurement of wide dynamic range, low frequency signals,
such as those in pressure transducers, weigh scales, and
temperature measurement applications.
The part has one differential input and one single-ended input. The
inputs can be operated in buffered or unbuffered mode. Buffering
the input channel means that the part can accommodate significant
source impedances on the analog input .The device requires an
external reference of 2.5 nominal. Figure 12 shows the basic
connections required to operate the part.
differential input voltage of 0 V. The peak-to-peak resolution
figures represent the resolution for which there is no code
flicker within a six-sigma limit. The output noise comes from
two sources. The first is the electrical noise in the semiconductor
devices (device noise) used in the implementation of the
modulator. The second is quantization noise, which is added when
the analog input is converted into the digital domain. The device
noise is at a low level and is independent of frequency. The
quantization noise starts at an even lower level but rises rapidly
with increasing frequency to become the dominant noise source.
Table 13. Typical Peak-to-Peak Resolution
(Effective Resolution) vs. Update Rate
POWER
SUPPLY
0.1F
Update Rate
9.5
13.3
16.7
16.6
20
33.3
100
120
10F
VDD
REFIN
IN+
AD7787
OUT–
OUT+
CS
AIN+
DOUT/RDY
MICROCONTROLLER
SCLK
AIN–
IN–
DIN
10k
Peak-to-Peak
Resolution
19.5
19
19
19
18.5
17.5
14.5
14
Effective
Resolution
22
21.5
21.5
21.5
21
20
17
16.5
GND
THERMISTOR
04477-0-006
AIN2
Figure 12. Basic Connection Diagram
The output rate of the AD7787 (fADC) is user programmable
with the settling time equal to 2 × tADC. Normal mode rejection
is the major function of the digital filter. Table 12 lists the
available update rates from the AD7787. Simultaneous 50 Hz
and 60 Hz rejection is optimized when the update rate equals
16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this
update rate (see Figure 6).
NOISE PERFORMANCE
Table 13 shows the output rms noise, rms resolution, and peakto-peak resolution (rounded to the nearest 0.5 LSB) for the
different update rates and input ranges for the AD7787. The
numbers given are for the bipolar input range with a reference
of 2.5 V. These numbers are typical and generated with a
REDUCED CURRENT MODES
The AD7787 has a current consumption of 160 μA maximum
when operated with a 5 V power supply, the buffer enabled, and
the clock operating at its maximum speed. The clock frequency
can be divided by a factor of 2, 4, or 8 before being applied to
the modulator and filter, resulting in a reduction in the current
consumption of the AD7787. Bits CDIV1 and CDIV0 in the
filter register are used to enter these low power modes (see
Table 14).
When the internal clock is reduced, the update rate is also
reduced. For example, if the filter bits are set to give an update
rate of 16.6 Hz when the AD7787 is operated in full power
mode, the update rate equals 8.3 Hz in divide-by-2 mode. In the
low power modes, there may be some degradation in the ADC
performance.
Table 14. Low Power Mode Selection
CDIV[1:0]
00
10
10
11
Clock
1
1/2
1/4
1/8
Typ Current, Buffered (μA)
146
87
56
41
Typ Current, Unbuffered (μA)
75
45
30
25
Rev. A | Page 14 of 20
50 Hz/60 Hz Rejection (dB)
65
64
75
86
Data Sheet
AD7787
DIGITAL INTERFACE
operation to the input shift register. In all modes, except
continuous read mode, it is possible to read the same word from
the data register several times even though the DOUT/RDY line
returns high after the first read operation. However, care must be
taken to ensure that the read operations have been completed
before the next output update occurs. In continuous read mode, the
data register can only be read once.
As previously outlined, the AD7787’s programmable functions
are controlled using a set of on-chip registers. Data is written to
these registers via the part’s serial interface and read access to
the on-chip registers is also provided by this interface. All
communications with the part must start with a write to the
communications register. After power-on or reset, the device
expects a write to its communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part begins with a
write operation to the communications register followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register followed by a read
operation from the selected register.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7787. The end of the conversion can
be monitored using the RDY bit in the status register. This
scheme is suitable for interfacing to microcontrollers. If CS is
required as a decoding signal, it can be generated from a port
pin. For microcontroller interfaces, it is recommended that
SCLK idle high between data transfers.
The AD7787’s serial interface consists of four signals: CS, DIN,
SCLK, and DOUT/RDY. The DIN line is used to transfer data
into the on-chip registers while DOUT/RDY is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT/RDY) occur with respect to the SCLK signal.
The AD7787 can be operated with CS being used as a frame
synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by CS, because CS would normally occur after the falling
edge of SCLK in DSPs. The SCLK can continue to run between
data transfers, provided the timing numbers are obeyed.
The DOUT/ RDY pin operates as a data-ready signal as well as
a DOUT pin. Each time a conversion is available in the output
register, DOUT/RDY goes low. DOUT/RDY resets high when a
read operation from the data register is completed. It also goes
high prior to the updating of the data register to indicate when
not to read from the device to ensure that a data read is not
attempted while the register is being updated. CS is used to
select a device. It can be used to decode the AD7787 in systems
where several components are connected to the serial bus.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7787 line for at least
32 serial clock cycles, the serial interface is reset. In 3-wire
systems, this ensures that the interface can be reset to a known
state if the interface gets lost due to a software error or some
glitch in the system. Reset returns the interface to the state in
which it is expecting a write to the communications register.
This operation resets the contents of all registers to their poweron values.
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7787 with CS being used to decode the part. Figure 3
shows the timing for a read operation from the AD7787’s
output shift register, while Figure 4 shows the timing for a write
The AD7787 can be configured to continuously convert or to
perform a single conversion (see Figure 13 through Figure 15).
CS
DIN
0x10
0x82
0x38
DATA
04477-0-007
DOUT/RDY
SCLK
Figure 13. Single Conversion
Rev. A | Page 15 of 20
AD7787
Data Sheet
Single Conversion Mode
Continuous Conversion Mode
In single conversion mode, the AD7787 is placed in shutdown
mode between conversions. When a single conversion is
initiated by setting MD1 to 1 and MD0 to 0 in the mode
register, the AD7787 powers up, performs a single conversion,
and then returns to shutdown mode. When a single conversion
is initiated, the AD7787’s oscillator requires 1 ms to power up
and settle. The AD7787 then performs a conversion which
requires 2 × tADC. DOUT/RDY is high while the conversion is
being performed and goes low to indicate the completion of the
conversion. When the data word has been read from the data
register, DOUT/RDY goes high. If CS is low, DOUT/RDY
remains high until another conversion is initiated and
completed. The data register can be read several times, if
required, even when DOUT/RDY has gone high.
This is the default power-up mode. The AD7787 will
continuously converts with the RDY pin in the status register
going low each time a conversion is complete. If CS is low, the
DOUT/RDY line also goes low when a conversion is complete.
To read a conversion, the user can write to the communications
register, indicating that the next operation is a read of the data
register. The digital conversion is placed on the DOUT/RDY
pin as soon as SCLK pulses are applied to the ADC.
DOUT/RDY returns high when the conversion is read. The
user can read this register additional times, if required.
However, the user must ensure that the data register is not being
accessed at the completion of the next conversion or the new
conversion word is lost.
CS
0x38
0x38
DIN
DATA
DATA
04477-0-009
DOUT/RDY
SCLK
Figure 14. Continuous Conversion
Rev. A | Page 16 of 20
Data Sheet
AD7787
be read once. Also, the user must ensure that the data-word is
read before the next conversion is complete. If the user has not
read the conversion before the completion of the next
conversion, or if insufficient serial clocks are applied to the
AD7787 to read the word, the serial output register is reset
when the next conversion is complete, and the new conversion
is placed in the output serial register.
Continuous Read Mode
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7787 can be
placed in continuous read mode. By writing 00111100
(Channel AIN1) or 00111101 (Channel AIN2) to the
communications register, the user only needs to apply the
appropriate number of SCLK cycles to the ADC, and the 24-bit
word is automatically placed on the DOUT/RDY line when a
conversion is complete.
To exit the continuous read mode, the instruction 001110XX
must be written to the communications register while the RDY
pin is low. While in the continuous read mode, the ADC
monitors activity on the DIN line so that it can receive the
instruction to exit the continuous read mode. Additionally, a
reset occurs if 32 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is written to the device.
When DOUT/RDY goes low to indicate the end of a
conversion, sufficient SCLK cycles must be applied to the ADC,
and the data conversion is placed on the DOUT/RDY line.
When the conversion is read, DOUT/RDY returns high until
the next conversion is available. In this mode, the data can only
CS
DOUT/RDY
0x3C
DATA
DATA
DATA
04477-0-008
DIN
SCLK
Figure 15. Continuous Read
Rev. A | Page 17 of 20
AD7787
Data Sheet
CIRCUIT DESCRIPTION
ANALOG INPUT CHANNEL
The AD7787 has two analog input channels that are connected
to the on-chip buffer amplifier when the device is operated in
buffered mode and directly to the modulator when the device is
operated in unbuffered mode. In buffered mode (the BUF bit in
the mode register is set to 1), the input channel feeds into a high
impedance input stage of the buffer amplifier. Therefore, the
input can tolerate significant source impedances and is tailored
for direct connection to external resistive-type sensors, such as
strain gauges or resistance temperature detectors (RTDs).
When BUF = 0, the part is operated in unbuffered mode.
This results in a higher analog input current. Note that this
unbuffered input path provides a dynamic load to the driving
source. Therefore, resistor/capacitor combinations on the input
pins can cause dc gain errors, depending on the output
impedance of the source that is driving the ADC input. Table 15
shows the allowable external resistance/capacitance values for
the unbuffered mode such that no gain error at the 20-bit level
is introduced.
Table 15. External R-C Combination for No 20-Bit Gain
Error
C (pF)
50
100
500
1000
5000
R (Ω)
16.7 k
9.6 k
2.2 k
1.1 k
160
The voltage on AIN2 is referenced to GND. Therefore, when
bipolar mode is selected and the part is operated in unbuffered
mode, the voltage on AIN2 can vary from GND − 100 mV to
+2.5 V. In unipolar mode, the voltage on AIN2 can vary from
0 V to 2.5 V. The bipolar/unipolar option is chosen by
programming the U/B bit in the mode register.
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 00...00, a midscale voltage
resulting in a code of 100...000, and a full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Code  2 N  AIN /VREF 
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000...000, a zero differential input voltage resulting
in a code of 100...000, and a positive full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Code  2 N1  AIN /VREF   1
where AIN is the analog input voltage and N = 24.
The absolute input voltage range in buffered mode is restricted
to a range between GND + 100 mV and VDD − 100 mV. Care
must be taken in setting up the common-mode voltage so that
these limits are not exceeded. Otherwise, there is degradation in
linearity and noise performance.
The absolute input voltage in unbuffered mode includes the
range between GND − 100 mV and VDD + 30 mV resulting
from being unbuffered. The negative absolute input voltage
limit does allow the possibility of monitoring small true bipolar
signals with respect to GND.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog input to the AD7787 can accept either unipolar or
bipolar input voltage ranges. Unipolar and bipolar signals on
the AIN1(+) input are referenced to the voltage on the AIN(−)
input. For example, if AIN1(−) is 2.5 V and the ADC is
configured for unipolar mode, the input voltage range on the
AIN1(+) pin is 2.5 V to 5 V when REFIN = 2.5 V. If the ADC is
configured for bipolar mode, the analog input range on the
AIN1(+) input is 0 V to 5 V.
REFERENCE INPUT
The AD7787 has a single-ended reference that is 2.5 V nominal,
but the AD7787 is functional with reference voltages from 0.1 V
to VDD. In applications where the excitation (voltage or current)
for the transducer on the analog input also drives the reference
voltage for the part, the effect of the low frequency noise in the
excitation source is removed because the application is
ratiometric. If the AD7787 is used in a nonratiometric
application, a low noise reference should be used.
Recommended 2.5 V reference voltage sources for the AD7787
include the ADR381 and ADR391, which are low noise, low
power references. In a system that operates from a 2.5 V power
supply, the reference voltage source requires some headroom. In
this case, a 2.048 V reference, such as the ADR380, can be used,
requiring only 300 mV of headroom. Also note that the
reference input provides a high impedance, dynamic load.
Because the input impedance of the reference input is dynamic,
resistor/capacitor combinations on this input can cause dc gain
errors, depending on the output impedance of the source
driving the reference inputs.
Rev. A | Page 18 of 20
Data Sheet
AD7787
Reference voltage sources like those previously recommended,
e.g., ADR391, will typically have low output impedances and
are, therefore, tolerant to having decoupling capacitors on
REFIN without introducing gain errors in the system. Deriving
the reference input voltage across an external resistor means
that the reference input sees a significant external source
impedance. External decoupling on the REFIN pin is not
recommended in this type of circuit configuration.
possible to the paths the currents took to reach their
destinations. Avoid forcing digital currents to flow through the
AGND sections of the layout.
The AD7787’s ground plane should be allowed to run under the
AD7787 to prevent noise coupling. The power supply lines to
the AD7787 should use as wide a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching signals, such as clocks, should
be shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best, but it is not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
VDD MONITOR
Along with converting external voltages, the AD7787 can
monitor the voltage on the VDD pin. When the CH1 and CH0
bits in the communications register are set to 1, the voltage on
the VDD pin is internally attenuated by 5 and the resultant
voltage is applied to the Σ-Δ modulator using an internal
1.17 V reference for the analog-to-digital conversion. This is
useful because variations in the power supply voltage can be
monitored.
Good decoupling is important when using high resolution
ADCs. VDD should be decoupled with 10 μF tantalum in parallel
with 0.1 μF capacitors to GND. To achieve the best from these
decoupling components, they should be placed as close as
possible to the device, ideally right up against the device. All
logic chips should be decoupled with 0.1 μF ceramic capacitors
to DGND.
GROUNDING AND LAYOUT
The digital filter provides rejection of broadband noise on the
power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs, provided that these noise
sources do not saturate the analog modulator. As a result, the
AD7787 is more immune to noise interference than a
conventional high resolution converter. However, because the
resolution of the AD7787 is so high, and the noise levels from
the AD7787 are so low, care must be taken with regard to
grounding and layout.
APPLICATIONS
Battery Monitoring
In battery monitoring, the battery current and voltage are
measured. The current is passed through a 100 μΩ resistor.
Because the current is from −200 A to +2000 A, the result is a
voltage from −20 mV to +200 mV. Channel AIN1 of the
AD7787 can be connected directly to the shunt resistor to
measure this current. The battery voltage can vary from 12 V to
42 V with peaks up to 60 V. This voltage is attenuated using an
external resistor network before being applied to the AD7787.
The buffers onboard the AD7787 mean that channel AIN2 can
be connected directly to the high impedance attenuator circuit
without introducing gain errors.
The printed circuit board that houses the AD7787 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes because it gives
the best shielding.
It is recommended that the AD7787’s GND pin be tied to the
AGND plane of the system. In any layout, it is important that
the user keep in mind the flow of currents in the system,
ensuring that the return paths for all currents are as close as
GND
REFIN
VDD
AD7787
DOUT/RDY
AIN1(+)
+
–
12V OR 42V
(60V PEAK)
–200A TO
+2000A
RSHUNT AIN1(–)
100
AIN2
MUX
-
ADC
SERIAL
INTERFACE
AND
LOGIC
CONTROL
DIN
SCLK
CS
04477-0-016
ATTENUATION
CIRCUIT
Figure 16. Battery Monitoring
Rev. A | Page 19 of 20
AD7787
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 17. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Models 1
AD7787BRM
AD7787BRMZ
AD7787BRM-REEL
AD7787BRMZ-RL
EVAL-AD7787EB
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
10-Lead Mini Small Outline Package (MSOP)
10-Lead Mini Small Outline Package (MSOP)
10-Lead Mini Small Outline Package (MSOP)
10-Lead Mini Small Outline Package (MSOP)
Evaluation Board
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D04477-0-3/13(A)
Rev. A | Page 20 of 20
Package Option
RM-10
RM-10
RM-10
RM-10
Branding
C1T
C42
C1T
C42