F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Concerto Microcontrollers 1 F28M35x ( Concerto™) MCUs 1.1 Features • Master Subsystem — ARM® Cortex™-M3 – 100 MHz – Embedded Memory • Up to 512KB Flash (ECC) • Up to 32KB RAM (ECC or Parity) • Up to 64KB Shared RAM • 2KB IPC Message RAM – 5 Universal Asynchronous Receiver/Transmitters (UARTs) – 4 Synchronous Serial Interfaces (SSIs)/ Serial Peripheral Interface (SPI) – 2 Inter-integrated Circuits (I2Cs) – Universal Serial Bus On-the-Go (USB-OTG) + PHY – 10/100 ENET 1588 MII – 2 Controller Area Networks (CANs) – 32-Channel Direct Memory Access (µDMA) – Dual Security Zones (128-Bit Password per Zone) – External Peripheral Interface (EPI) – Micro Cyclic Redundancy Check (µCRC) Module – 4 General-Purpose Timers – 2 Watchdog Timer Modules – Endianness: Little Endian • Clocking – On-chip Crystal Oscillator/External Clock Input – Dynamic PLL Ratio Changes Supported • 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design • Interprocessor Communications (IPC) – 32 Handshaking Channels – 4 Channels Generate IPC Interrupts – Can be Used to Coordinate Transfer of Data Through IPC Message RAMs • Up to 74 Individually Programmable, Multiplexed GPIO Pins – Glitch-free I/Os • Control Subsystem — TMS320C28x™ 32-Bit CPU – 150 MHz – Embedded Memory • Up to 512KB Flash (ECC) • Up to 36KB RAM (ECC or Parity) • Up to 64KB Shared RAM • 2KB IPC Message RAM – IEEE-754 Single-Precision Floating-Point Unit (FPU) – Viterbi, Complex Math, CRC Unit (VCU) – Serial Communications Interface (SCI) – Serial Peripheral Interface (SPI) – Inter-integrated Circuit (I2C) – 6-Channel Direct Memory Access (DMA) – 9 Enhanced Pulse Width Modulator (ePWM) Modules • 18 Outputs (16 High-Resolution) – 6 32-Bit Enhanced Capture (eCAP) Modules – 3 32-Bit Enhanced Quadrature Encoder (eQEP) Modules – Multichannel Buffered Serial Port (McBSP) – External Peripheral Interface (EPI) – One Security Zone (128-Bit Password) – 3 32-Bit Timers – Endianness: Little Endian • Analog Subsystem – Dual 12-Bit Analog-to-Digital Converters (ADCs) – Up to 2.88 MSPS – Up to 20 Channels – 4 Sample-and-Hold (S/H) Circuits – Up to 6 Comparators With 10-Bit Digital-toAnalog Converter (DAC) • Package – 144-Pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Concerto, TMS320C28x, PowerPAD, C28x, C2000, Piccolo, Delfino, XDS are trademarks of Texas Instruments. Cortex is a trademark of ARM Limited. ARM is a registered trademark of ARM Ltd or its subsidiaries. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2011–2012, Texas Instruments Incorporated PRODUCT PREVIEW 12345 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 1.2 www.ti.com Description The Concerto™ family is a multi-core system-on-chip microcontroller (MCU) with independent communication and real-time control subsystems. The F28M35x is the first series in the Concerto family. The communications subsystem is based on the industry-standard 32-bit ARM® Cortex™-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, CAN, UART, SSI, I2C, and an external interface. The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x™ Floating-Point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s C2000™ Piccolo™ and Delfino™ families. In addition, the C28-CPU has been enhanced with the addition of the Viterbi, Complex Math, CRC Unit (VCU) instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs and CRC algorithms. A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), Parity, and Code Secure Memory, as well as documentation to assist with system-level industrial safety certification. PRODUCT PREVIEW 2 F28M35x ( Concerto™) MCUs Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 1.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Functional Block Diagram GPIO_MUX1 1.8V VREG 1.2V VREG 1.8V VMON 1.2V VMON SECURE C1 RAM 8 KB (ECC) SECURE FLASH WDOG (2) uCRC NMI WDOG GP TIMER (4) SSI (4) UART (5) I2C (2) EMAC CAN (2) EPI USB+PHY (OTG) BOOT ROM C3 RAM 8 KB (parity) SECURE C0 RAM 8 KB (ECC) 512 KB (ECC) 64 KB C2 RAM 8 KB (parity) REGS ONLY APB BUS AHB BUS uDMA BUS ADC_1 MODULE M3 BUS MATRIX M3 uDMA 4 COMP INPUTS ANALOG COMMON INTERFACE BUS GPIO_MUX2 8 PINS 6 COMPARE 6 + DAC COMP UNITS OUT PUTS MPU M3 CPU NVIC CLOCKS I-CODE BUS D-CODE BUS M3 SYSTEM BUS C28 CPU/DMA ACCESS TO EPI INTERPROC COMM FREQ GASKET RESETS S0 MEM32 TO AHB BUS BRIDGE NMI DEBUG S1 10 PINS AIO_MUX2 PRODUCT PREVIEW AIO_MUX1 10 PINS 10 ADC INPUTS S2 S3 S4 S5 S6 S7 IPC 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB MTOC MSG RAM (parity) 2 KB CTOM MSG RAM (parity) 2 KB S0-S7 SHARED RAM (parity) INTERPROC COMM SECURITY 4 COMP INPUTS C28 DMA BUS C28 DMA ADC_2 10 MODULE ADC INPUTS C28 VCU C28 CPU PIE C28 FPU C28 CPU BUS ANALOG SUBSYSTEM 32BIT PF3 32BIT PF1 16BIT PF2 16/32 - BIT PF0 TIMER (3) McBSP EPWM (9) ECAP (6) EQEP (3) NMI WDOG SPI SCI I2C XINT (3) BOOT ROM 64 KB SECURE FLASH 512 KB (ECC) GPIO_MUX1 66 PINS SECURE L1 RAM 8 KB (ECC) L3 M1 RAM 8 KB (parity) RAM 2 KB (ECC) SECURE L0 RAM 8 KB (ECC) L2 M0 RAM 8 KB (parity) RAM 2 KB (ECC) Figure 1-1. Functional Block Diagram F28M35x ( Concerto™) MCUs Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com ........................ 1 ............................................. 1 1.2 Description ........................................... 2 1.3 Functional Block Diagram ........................... 3 Revision History .............................................. 5 2 Device Overview ....................................... 10 2.1 Device Characteristics .............................. 11 2.2 Memory Maps ...................................... 13 2.3 Master Subsystem .................................. 23 2.4 Control Subsystem ................................. 29 2.5 Analog Subsystem .................................. 33 2.6 Master Subsystem NMIs ........................... 36 2.7 Control Subsystem NMIs ........................... 36 2.8 Resets .............................................. 38 2.9 Internal Voltage Regulation and Monitoring ........ 43 2.10 Input Clocks and PLLs ............................. 47 2.11 Master Subsystem Clocking ........................ 57 2.12 Control Subsystem Clocking ....................... 60 2.13 Analog Subsystem Clocking ....................... 63 2.14 Shared Resources Clocking ........................ 63 2.15 Loss of Input Clock (NMI Watchdog Function) ..... 63 2.16 GPIOs and Other Pins .............................. 65 2.17 Emulation/JTAG .................................... 81 2.18 Code Security Module (CSM) ...................... 84 2.19 µCRC Module ...................................... 85 1 F28M35x ( Concerto™) MCUs 1.1 PRODUCT PREVIEW 4 3 Features 4 5 ............................................. 87 .................................... 87 3.2 Terminal Functions ................................. 88 Device Operating Conditions ...................... 111 4.1 Absolute Maximum Ratings ....................... 111 4.2 Recommended Operating Conditions ............. 111 4.3 Electrical Characteristics .......................... 112 Electrical Specifications ............................ 113 5.1 Current Consumption ............................. 113 5.2 Thermal Design Considerations .................. 114 5.3 Timing Parameter Symbology ..................... 115 Device Pins 3.1 Pin Assignments 5.4 Clock Frequencies, Requirements, and Characteristics .................................... 116 ................................ Peripheral Information and Timings ............. 6.1 Analog and Shared Peripherals ................... 6.2 Master Subsystem Peripherals .................... 6.3 Control Subsystem Peripherals ................... Device and Documentation Support ............. 7.1 Device Support .................................... 7.2 Documentation Support ........................... 7.3 Community Resources ............................ 5.5 6 7 8 Power Sequencing 119 123 123 151 166 185 185 186 186 Mechanical Packaging and Orderable Information ............................................ 187 ........................ ............................ 8.1 Thermal Data for Package 187 8.2 Packaging Information 187 Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the SPRS742C device-specific data sheet to make it an SPRS742D revision. Scope: Added new sections. See table below. ADDITIONS, DELETIONS, AND MODIFICATIONS Features: • Changed "Up to 72 Individually Programmable, Multiplexed GPIO Pins" to "Up to 74 Individually Programmable, Multiplexed GPIO Pins" – Added "Glitch-free I/Os" feature • Control Subsystem — TMS320C28x™ 32-Bit CPU: – Added "External Peripheral Interface (EPI)" feature • Analog Subsystem: – Removed "On-chip Temperature Sensor" Figure 1-1 Updated Functional Block Diagram Table 2-1 Hardware Features: • 12-Bit ADC 1: – Removed "Temperature Sensor" • Updated "Voltage Regulator and Monitor" • Updated "Clocking" Table 2-3 Control Subsystem Peripheral Frame 0 (Includes Analog): • 0000 1780 – 0000 17FF: Added C Hardware Logic BIST Registers Table 2-8 Control Subsystem Flash, ECC, OTP, Boot ROM: • Added "M Address (Byte-Aligned)" column • Added "µDMA Access" column • 0030 0000 – 003F 7FFF: Added EPI0 • 003F 8000 – 003F FFFF: Added C28x Boot ROM • Added "The letter "M" refers to the Master Subsystem" footnote • Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote Table 2-12 Master Subsystem Analog and EPI: • Added "C Address (x16 Aligned)" column • Added "C DMA Access" column • 6000 0000 – DFFF FFFF: Updated the above two new columns • Added "The letter "C" refers to the Control Subsystem" footnote • Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote Section 2.3 Master Subsystem: • Updated "The Master Subsystem includes ..." paragraph Section 2.3.1 Cortex™-M3 CPU: • Removed "MPU is not available on silicon revision 0 devices" NOTE Section 2.3.2 Added "Cortex™-M3 Core Hardware Logic Built-In Test (LBIST)" section Figure 2-1 Updated "Master Subsystem" figure Table 2-14 Interrupts from NVIC to Cortex™-M3: • Interrupt Number: Changed 91 to "91–133". Updated "Vector Number" column. Updated "Vector Address or Offset" column. Section 2.3.6 Cortex™-M3 Local Peripherals: • Updated "The Cortex™-M3 local peripherals include two Watchdogs ..." paragraph Section 2.3.8 Cortex™-M3 Accessing Shared Resources and Analog Peripherals: • Updated "There are several memories ..." paragraph • Updated "The Shared Resources ..." paragraph • Updated "The Analog Subsystem has ADC1 ..." paragraph Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW LOCATION Section 1.1 5 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com LOCATION PRODUCT PREVIEW 6 ADDITIONS, DELETIONS, AND MODIFICATIONS Section 2.4 Control Subsystem: • Updated "The Control Subsystem includes ..." paragraph Figure 2-2 Updated "Control Subsystem" figure Table 2-16 PIE Peripheral Interrupts: • INTx.3, INT12: Changed from "C28FLFSM" to "Reserved" Section 2.4.5 C28x Local Peripherals: • Updated "The C28x local peripherals include an NMI Watchdog ..." paragraph Section 2.4.7 C28x Accessing Shared Resources and Analog Peripherals: • Updated "The Shared Resources ..." paragraph Section 2.5 Analog Subsystem: • Updated "The Analog Subsystem has ADC1 ..." paragraph Section 2.5.1 ADC1: • Updated "The ADC1 consists of a 12-bit Analog-to-Digital converter ..." paragraph Figure 2-3 Updated "Analog Subsystem" figure Section 2.5.4 Analog Common Interface Bus (ACIB): • Updated "The ACIB bus links the Master and Control Subsystems ..." paragraph Section 2.6 Master Subsystem NMIs: • Updated "The inputs to the Cortex™-M3 NMI block include ..." paragraph Section 2.7 Control Subsystem NMIs: • Updated "The inputs to the C28x NMI block include ..." paragraph Figure 2-4 Updated "Cortex™-M3 NMI and C28x NMI" figure Section 2.8 Resets: • Updated "The XRS pin can receive an external reset signal ..." paragraph Figure 2-5 Updated "Resets" figure Section 2.8.3 Analog Subsystem and Shared Resources Resets: • Added "EPI is a shared peripheral ..." paragraph Section 2.8.4 Device Boot Sequence: • Updated "Boot Mode 7 ..." paragraph • Updated "Boot Mode 1 causes the Master boot program to branch ..." paragraph • Updated "Boot Modes 0, 2, 3, ..." paragraph Table 2-17 Master Subsystem Boot Mode Selection: • Added Boot Modes 8–15 • Updated and added footnotes Section 2.9 Added "Internal Voltage Regulation and Monitoring" section Section 2.10 Added "Input Clocks and PLLs" section Figure 2-10 Updated "Cortex™-M3 Clocks and Low-Power Modes" figure Section 2.12 Control Subsystem Clocking: • Updated "The C28x processor outputs two clocks ..." paragraph Figure 2-11 Updated "C28x Clocks and Low-Power Modes" figure Section 2.12.3 C28x Standby Mode: • Updated "In Standby Mode, the C28x processor stops executing instructions ..." paragraph • Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46 Section 2.14 Shared Resources Clocking: • Updated "... are clocked by PLLSYSCLK." paragraph • Added "EPI is a shared peripheral ..." paragraph Section 2.15 Added "Loss of Input Clock (NMI Watchdog Function)" section Section 2.16 GPIOs and Other Pins: • Updated "Most of the I/O pins of the Concerto™ MCU ..." paragraph Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS GPIO_MUX1: • Updated " ... pins of the GPIO_MUX1 block can be selectively mapped ..." paragraph • Updated "Pin-Level Mux assigns Master Subsystem peripheral signals ..." paragraph • Updated "The configuration registers for the muxing of Master Subsystem peripherals ..." paragraph • Updated "In addition to passing mostly digital signals ..." paragraph • Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46 Figure 2-13 Updated "GPIOs and Other Pins" figure Figure 2-14 Updated "GPIO_MUX1 Block" figure Figure 2-15 Updated "GPIO_MUX1 Pin Mapping Through Register Set A" figure Table 2-27 GPIO_MUX1 Pin Assignments (M3 Primary Modes): • PB6_GPIO14: Updated "M3 Primary Mode 8" column • PB7_GPIO15: Updated "M3 Primary Mode 8" column • PE4_GPIO28: Updated "M3 Primary Mode 8" column • PE5_GPIO29: Updated "M3 Primary Mode 8" column • PF2_GPIO34: Updated "M3 Primary Mode 8" column • PF3_GPIO35: Updated "M3 Primary Mode 8" column • PF6_GPIO38: – Updated "M3 Primary Mode 1" column – Updated "M3 Primary Mode 3" column – Updated "M3 Primary Mode 8" column – Updated "M3 Primary Mode 10" column • PG2_GPIO42: Updated "M3 Primary Mode 8" column • PG5_GPIO45: Updated "M3 Primary Mode 8" column • PG6_GPIO46: – Updated "M3 Primary Mode 3" column – Updated "M3 Primary Mode 8" column – Updated "M3 Primary Mode 10" column • Added footnote about muxing option availability Table 2-28 GPIO_MUX1 Pin Assignments (M3 Alternate Modes): • PA6_GPIO6: Updated "M3 Alternate Mode 12" column • PE4_GPIO28: Updated "M3 Alternate Mode 14" column • Added footnote about muxing option availability Table 2-29 GPIO_MUX1 Pin Assignments (C28x Peripheral Modes): • PF6_GPIO38: Updated "C28x Peripheral Mode 0" column • PG6_GPIO46: Updated "C28x Peripheral Mode 0" column Section 2.16.2 GPIO_MUX2: • Updated "Peripheral Modes 0, 1, 2, and 3 are chosen ..." paragraph Table 2-30 Updated "GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)" table Figure 2-16 Updated "Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure Section 2.17 Added "Emulation/JTAG" section Section 2.18 Added "Code Security Module (CSM)" section Section 2.19 Added "µCRC Module" section Figure 3-1 144-Pin RFP PowerPAD™ HTQFP (Top View): • Pin 109: Changed signal name from "GPIO199/COMP5OUT" to "GPIO135/COMP5OUT" • Pin 110: Changed signal name from "GPIO198" to "GPIO134" • Pin 111: Changed signal name from "GPIO197/COMP4OUT" to "GPIO133/COMP4OUT" • Pin 112: Changed signal name from "GPIO196/COMP3OUT" to "GPIO132/COMP3OUT" • Pin 118: Changed signal name from "ADC1VREFLO, VSSA1" to "VSSA1" • Pin 135: Changed signal name from "ADC2VREFLO, VSSA2" to "VSSA2" • Pin 140: Changed signal name from "GPIO192" to "GPIO128" • Pin 141: Changed signal name from "GPIO193/COMP1OUT" to "GPIO129/COMP1OUT" • Pin 142: Changed signal name from "GPIO194/COMP6OUT" to "GPIO130/COMP6OUT" • Pin 143: Changed signal name from "GPIO195/COMP2OUT" to "GPIO131/COMP2OUT" • Added footnote about GPIO135 PRODUCT PREVIEW Section 2.16.1 Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com LOCATION PRODUCT PREVIEW 8 ADDITIONS, DELETIONS, AND MODIFICATIONS Section 3.2 Terminal Functions: • Removed "Input Clock Configurations" figure. This figure is being replaced by the new "Connecting Input Clocks to a Concerto Device" figure (Figure 2-7). Table 3-1 Terminal Functions: • Made extensive updates to Terminal Functions table • Added footnote about pullup and pulldown • Added footnote about GPIO135 • Added footnote about muxing option availability Section 4.1 Absolute Maximum Ratings: • Added Free-Air temperature, TA Section 4.2 Recommended Operating Conditions: • Added Free-Air temperature, TA • Updated Junction temperature, TJ • Removed footnote about ambient temperature Section 5 Added "Electrical Specifications" section Section 5 Electrical Specifications: • Moved "Current Consumption" section from "Peripheral Information and Timings" section to "Electrical Specifications" section • Moved "Power Sequencing" section from "Peripheral Information and Timings" section to "Electrical Specifications" section Table 5-1 Changed table title from "F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" to "Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" Table 5-1 Updated "Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" table and footnotes Section 5.2 Added "Thermal Design Considerations" section Section 5.3 Added "Timing Parameter Symbology" section Section 5.4 Added "Clock Frequencies, Requirements, and Characteristics" section Section 5.5 Updated "Power Sequencing" section Section 5.5.1 Added "Changing the Frequency of the Main PLL" section Table 5-14 Updated "Power Management and Supervisory Circuit Solutions" table Section 6.1 Updated "Analog and Shared Peripherals" section Figure 6-1 Updated "ADC" figure Section 6.1.1.3 Updated "Analog Inputs" section Section 6.1.2 Updated "Comparator + DAC Units" section Figure 6-2 Updated "Comparator + DAC Units" figure Section 6.1.3 Updated "Inter-Processor Communications (IPC)" section Figure 6-3 Updated "Interprocessor Communications (IPC)" figure Section 6.1.4 Updated "External Peripheral Interface (EPI)" section Section 6.2 Master Subsystem Peripherals: • Updated "Master Subsystem peripherals are located on the APB Bus and AHB Bus ..." paragraph Section 6.2.1 Added "Synchronous Serial Interface (SSI)" section Section 6.2.2 Added "Universal Asynchronous Receiver/Transmitter (UART)" section Section 6.2.3 Added "Cortex™-M3 Inter-Integrated Circut (I2C)" section Section 6.2.4 Added "Cortex™-M3 Controller Area Network (CAN)" section Section 6.2.5 Added "Cortex™-M3 Universal Serial Bus (USB) Controller" section Section 6.2.6 Added "Cortex™-M3 Ethernet Media Access Controller (EMAC)" section Section 6.3 Control Subsystem Peripherals: • Updated "Control Subsystem peripherals are accessible from the C28x CPU ..." paragraph Section 6.3.1 Changed section title from "Pulse Width Modulator (PWM) and High-Resolution PWM (HRPWM) Modules" to "High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules" Section 6.3.1 High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules: • Updated "There are 9 SOCA PWM outputs and 9 SOCB PWM outputs ..." paragraph Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Changed figure caption from "ePWM, eQEP, eCAP" to "PWM, eCAP, eQEP" Figure 6-15 Updated "PWM, eCAP, eQEP" figure Figure 6-16 Changed figure caption from "ePWM/HRPWM" to "Internal Structure of PWM" Figure 6-16 Updated "Internal Structure of PWM" figure Section 6.3.2 Added "Enhanced Capture (eCAP) Module" section Section 6.3.3 Added "Enhanced Quadrature Encoder Pulse (eQEP) Module" section Section 6.3.4 Added "C28x Inter-Integrated Circuit Module (I2C)" section Section 6.3.5 Added "C28x Serial Communications Interface (SCI)" section Section 6.3.6 Added "C28x Serial Peripheral Interface (SPI)" section Section 6.3.7 Added "C28x Multichannel Buffered Serial Port (McBSP)" section Section 8.1 Added "Thermal Data for Package" section PRODUCT PREVIEW Figure 6-15 Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2 Device Overview The Concerto™ microcontroller (MCU) comprises three subsystems: the Master Subsystem, the Control Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and peripherals, they can also share data and events through shared memories and peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other events to initialize subsystem processors and the rest of the chip to a known state. The Clocking Blocks support multiple low-power modes where clocks to the processors and peripherals can be slowed down or stopped in order to manage power consumption. NOTE Throughout this document, the Master Subsystem is denoted by the color "blue"; the Control Subsystem is denoted by the color "green"; and the Analog Subsystem is denoted by the color "orange". PRODUCT PREVIEW 10 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Device Characteristics Table 2-1 lists the features of the F28M35Hx devices. Table 2-1. Hardware Features FEATURE TYPE (1) H20B1 H20C1 H22B1 H22C1 H32B1 H32C1 H50B1 H50C1 H52B1 H52C1 Speed (MHz) – 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) 100 (2) Flash (KB) – 256 256 256 256 256 512 512 512 512 512 RAM ECC (KB) – 16 16 16 16 16 16 16 16 16 16 RAM Parity (KB) – 16 16 16 16 16 16 16 16 16 16 IPC Message RAM Parity (KB) – 2 2 2 2 2 2 2 2 2 2 Security Zones – 2 2 2 2 2 2 2 2 2 2 10/100 ENET 1588 MII 0 No Yes No Yes No Yes No Yes No Yes USB OTG FS 0 No Yes No Yes No Yes No Yes No Yes Synchronous Serial Interface (SSI)/ Serial Peripheral Interface (SPI) 0 4 4 4 4 4 4 4 4 4 4 Universal Asynchronous Receiver/Transmitter (UART) 0 5 5 5 5 5 5 5 5 5 5 Inter-integrated circuit (I2C) 0 2 2 2 2 2 2 2 2 2 2 Controller Area Network (CAN) 0 2 2 2 2 2 2 2 2 2 2 Direct Memory Access (µDMA) 0 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch 32-ch External Peripheral Interface (EPI) 0 1 1 1 1 1 1 1 1 1 1 Micro Cyclic Redundancy Check (µCRC) Module 0 1 1 1 1 1 1 1 1 1 1 General-Purpose Timers – 4 4 4 4 4 4 4 4 4 4 Watchdog Timer Modules – 2 2 2 2 2 2 2 2 2 2 PRODUCT PREVIEW Master Subsystem — ARM® Cortex™-M3 Control Subsystem — C28x Floating-Point Unit (FPU)/Viterbi, Complex Math, CRC Unit (VCU) Speed (MHz) 150 150 150 150 150 150 150 150 150 150 Flash (KB) 256 256 256 256 512 256 512 512 512 512 RAM ECC (KB) 20 20 20 20 20 20 20 20 20 20 RAM Parity (KB) 16 16 16 16 16 16 16 16 16 16 IPC Message RAM Parity (KB) 2 2 2 2 2 2 2 2 2 2 Security Zones 1 1 1 1 1 1 1 1 1 1 Enhanced Pulse Width Modulator (ePWM) modules 2 9: 18 outputs High-Resolution PWM outputs 2 16 outputs Enhanced Capture (eCAP) modules/ PWM outputs 0 6 (32-bit) Enhanced Quadrature Encoder (eQEP) modules 0 3 (32-bit) Fault Trip Zones – 12 on any of 64 GPIO pins (1) (2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. An integer divide ratio must be maintained between the C28x and Cortex™-M3 clock frequencies; thus, when the C28x is configured to run at maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex™-M3 will be 75 MHz. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-1. Hardware Features (continued) TYPE (1) H20B1 H20C1 H22B1 H22C1 H32B1 H32C1 H50B1 H50C1 H52B1 H52C1 Multichannel Buffered Serial Port (McBSP)/ Serial Peripheral Interface (SPI) 1 1 1 1 1 1 1 1 1 1 1 Serial Communications Interface (SCI) 0 1 1 1 1 1 1 1 1 1 1 Serial Peripheral Interface (SPI) 0 1 1 1 1 1 1 1 1 1 1 Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1 1 1 1 Direct Memory Access (DMA) 0 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch 32-Bit Timers – 3 3 3 3 3 3 3 3 3 3 FEATURE Shared Supplemental RAM (KB) MSPS Conversion Time 0 0 64 64 64 64 0 0 64 64 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns Channels 10 10 10 10 10 10 10 10 10 10 Sample-and-Hold (S/H) 2 2 2 2 2 2 2 2 2 2 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 2.88 12-Bit ADC 1 3 PRODUCT PREVIEW MSPS Conversion Time 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns 350 ns Channels 10 10 10 10 10 10 10 10 10 10 Sample-and-Hold (S/H) 2 2 2 2 2 2 2 2 2 2 6 6 6 6 6 6 6 6 6 6 12-Bit ADC 2 3 Comparators with Integrated DACs 0 Voltage Regulator and Monitor Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC) Clocking See Section 2.10 Additional Safety Master Subsystem 2 Watchdogs, NMI Watchdog: CPU, Memory Control Subsystem NMI Watchdog: CPU, Memory Shared Critical Register and I/O Function Lock Protection; RAM Fetch Protection Packaging Package Type Temperature options 144-Pin RFP PowerPAD™ HTQFP – Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes S: –40°C to 125°C – No No No No No No No No No No Q: –40°C to 125°C (3) (4) (5) – No No No No No No No No No No – xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... xF28M35... Product status (6) (3) (4) (5) (6) 12 Available at Prototype Sampling T: –40°C to 105°C "Q" refers to Q100 qualification for automotive applications. The "Q" temperature option is not available for the F28M35Mxxx1 series. The "Q" temperature option is not available for the F28M35ExxC1 series, but this temperature option will be available for the F28M35ExxB1 series. The "xF28M35..." product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. See Section 7.1.2, Device Nomenclature, for descriptions of device stages. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Memory Maps Section 2.2.1 shows the Control Subsystem Memory Map. Section 2.2.2 shows the Master Subsystem Memory Map. 2.2.1 Control Subsystem Memory Map Table 2-2. Control Subsystem M0, M1 RAM (1) C DMA Access (1) C Address (x16 Aligned) (1) Size (Bytes) no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K Control Subsystem M0, M1 RAM The letter "C" refers to the Control Subsystem. Table 2-3. Control Subsystem Peripheral Frame 0 (Includes Analog) Control Subsystem Peripheral Frame 0 (Includes Analog) Size (Bytes) 0000 0800 – 0000 087F Reserved 0000 0880 – 0000 0890 Control Subsystem Device Configuration Registers (Read Only) 0000 0891 – 0000 0ADF Reserved 0000 0AE0 – 0000 0AEF C28x CSM Registers 0000 0AF0 – 0000 0AFF Reserved 0000 0B00 – 0000 0B0F ADC1 Result Registers 0000 0B10 – 0000 0B3F Reserved 0000 0B40 – 0000 0B4F ADC2 Result Registers 0000 0B50 – 0000 0BFF Reserved no 0000 0C00 – 0000 0C07 CPU Timer 0 16 no 0000 0C08 – 0000 0C0F CPU Timer 1 16 no 0000 0C10 – 0000 0C17 CPU Timer 2 16 0000 0C18 – 0000 0CDF Reserved no 0000 0CE0 – 0000 0CFF PIE Registers 64 no 0000 0D00 – 0000 0DFF PIE Vector Table 512 no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512 0000 0F00 – 0000 0FFF Reserved 0000 1000 – 0000 11FF C28x DMA Registers 0000 1200 – 0000 16FF Reserved no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256 no 0000 1780 – 0000 17FF C Hardware Logic BIST Registers 256 0000 1800 – 0000 3FFF Reserved no no yes yes no (1) C Address (x16 Aligned) (1) 34 PRODUCT PREVIEW C DMA Access (1) 32 32 32 1K The letter "C" refers to the Control Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-4. Control Subsystem Peripheral Frame 3 C DMA Access (1) no no no no no no yes PRODUCT PREVIEW (1) (2) 14 C Address (x16 Aligned) (1) Control Subsystem Peripheral Frame 3 0000 4000 – 0000 4181 C28x Flash Control Registers 0000 4182 – 0000 42FF Reserved 0000 4300 – 0000 4323 C28x Flash ECC Error Log Registers 0000 4324 – 0000 43FF Reserved 0000 4400 – 0000 443F M Clock Control Registers (2) 0000 4440 – 0000 48FF Reserved 0000 4900 – 0000 497F RAM Configuration Registers 0000 4980 – 0000 49FF Reserved 0000 4A00 – 0000 4A7F RAM ECC/Parity/Access Error Log Registers 0000 4A80 – 0000 4DFF Reserved 0000 4E00 – 0000 4E3F CtoM and MtoC IPC Registers 0000 4E40 – 0000 4FFF Reserved Size (Bytes) M Address (Byte-Aligned) (2) µDMA Access 128 400F B800 – 400F B87F no 256 400F B200 – 400F B2FF no 256 400F B300 – 400F B3FF no 128 400F B700 – 400F B77F no 772 72 0000 5000 – 0000 503F McBSP-A 0000 5040 – 0000 50FF Reserved 128 yes 0000 5100 – 0000 517F EPWM1 (Hi-Resolution) 256 yes 0000 5180 – 0000 51FF EPWM2 (Hi-Resolution) 256 yes 0000 5200 – 0000 527F EPWM3 (Hi-Resolution) 256 yes 0000 5280 – 0000 52FF EPWM4 (Hi-Resolution) 256 yes 0000 5300 – 0000 537F EPWM5 (Hi-Resolution) 256 yes 0000 5380 – 0000 53FF EPWM6 (Hi-Resolution) 256 yes 0000 5400 – 0000 547F EPWM7 (Hi-Resolution) 256 yes 0000 5480 – 0000 54FF EPWM8 (Hi-Resolution) 256 yes 0000 5500 – 0000 557F EPWM9 256 0000 5580 – 0000 57FF Reserved The letter "C" refers to the Control Subsystem. The letter "M" refers to the Master Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 2-5. Control Subsystem Peripheral Frame 1 C DMA Access (1) C Address (x16 Aligned) (1) 0000 5800 – 0000 59FF Reserved no 0000 5A00 – 0000 5A1F ECAP1 64 no 0000 5A20 – 0000 5A3F ECAP2 64 no 0000 5A40 – 0000 5A5F ECAP3 64 no 0000 5A60 – 0000 5A7F ECAP4 64 no 0000 5A80 – 0000 5A9F ECAP5 64 no 0000 5AA0 – 0000 5ABF ECAP6 64 0000 5AC0 – 0000 5AFF Reserved 0000 5B00 – 0000 5B3F EQEP1 128 no 0000 5B40 – 0000 5B7F EQEP2 128 no 0000 5B80 – 0000 5BBF EQEP3 128 0000 5BC0 – 0000 5F7F Reserved 0000 5F80 – 0000 5FFF C GPIO Group 1 Registers (1) 0000 6000 – 0000 63FF Reserved no 0000 6400 – 0000 641F COMP1 Registers 64 no 0000 6420 – 0000 643F COMP2 Registers 64 no 0000 6440 – 0000 645F COMP3 Registers 64 no 0000 6460 – 0000 647F COMP4 Registers 64 no 0000 6480 – 0000 649F COMP5 Registers 64 no 0000 64A0 – 0000 64BF COMP6 Registers 64 0000 64C0 – 0000 6F7F Reserved 0000 6F80 – 0000 6FFF C GPIO Group 2 Registers and AIO Mux Registers (1) no no (1) Size (Bytes) 256 PRODUCT PREVIEW no Control Subsystem Peripheral Frame 1 256 The letter "C" refers to the Control Subsystem. Table 2-6. Control Subsystem Peripheral Frame 2 C DMA Access (1) Control Subsystem Peripheral Frame 2 Size (Bytes) 0000 7000 – 0000 70FF Reserved 0000 7010 – 0000 702F C28x System Control Registers 0000 7030 – 0000 703F Reserved no 0000 7040 – 0000 704F SPI-A 32 no 0000 7050 – 0000 705F SCI-A 32 no 0000 7060 – 0000 706F NMI Watchdog Interrupt Registers 32 no 0000 7070 – 0000 707F External Interrupt Registers 32 0000 7080 – 0000 70FF Reserved no 0000 7100 – 0000 717F ADC1 Configuration Registers (Only 16-bit read/write access supported) 256 no 0000 7180 – 0000 71FF ADC2 Configuration Registers (Only 16-bit read/write access supported) 256 0000 7200 – 0000 78FF Reserved 0000 7900 – 0000 793F I2C-A 0000 7940 – 0000 7FFF Reserved no no (1) C Address (x16 Aligned) (1) 64 128 The letter "C" refers to the Control Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 15 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-7. Control Subsystem RAMs C DMA Access (1) C Address (x16 Aligned) (1) no 0000 8000 – 0000 8FFF L0 RAM (ECC, Secure) 8K no 0000 9000 – 0000 9FFF L1 RAM (ECC, Secure) 8K yes 0000 A000 – 0000 AFFF L2 RAM (Parity, Interleaving) 8K yes 0000 B000 – 0000 BFFF L3 RAM (Parity, Interleaving) 8K yes 0000 C000 – 0000 CFFF S0 RAM (Parity, Shared) 8K yes 0000 D000 – 0000 DFFF S1 RAM (Parity, Shared) yes 0000 E000 – 0000 EFFF S2 RAM (Parity, Shared) yes 0000 F000 – 0000 FFFF yes PRODUCT PREVIEW M Address (Byte-Aligned) (2) µDMA Access 2000 8000 – 2000 9FFF yes 8K 2000 A000 – 2000 BFFF yes 8K 2000 C000 – 2000 DFFF yes S3 RAM (Parity, Shared) 8K 2000 E000 – 2000 FFFF yes 0001 0000 – 0001 0FFF S4 RAM (Parity, Shared) 8K 2001 0000 – 2001 1FFF yes yes 0001 1000 – 0001 1FFF S5 RAM (Parity, Shared) 8K 2001 2000 – 2001 3FFF yes yes 0001 2000 – 0001 2FFF S6 RAM (Parity, Shared) 8K 2001 4000 – 2001 5FFF yes yes 0001 3000 – 0001 3FFF S7 RAM (Parity, Shared) 8K 2001 6000 – 2001 7FFF yes 0001 4000 – 0003 F7FF Reserved yes 0003 F800 – 0003 FBFF CtoM MSG RAM (Parity) 2K 2007 F000 – 2007 F7FF yes read only yes read only 0003 FC00 – 0003 FFFF MtoC MSG RAM (Parity) 2K 2007 F800 – 2007 FFFF yes 0004 0000 – 0004 7FFF Reserved 0004 8000 – 0004 8FFF L0 RAM - ECC Bits 8K no 0004 9000 – 0004 9FFF L1 RAM - ECC Bits 8K no 0004 A000 – 0004 AFFF L2 RAM - Parity Bits 8K no 0004 B000 – 0004 BFFF L3 RAM - Parity Bits 8K no 0004 C000 – 0004 CFFF S0 RAM - Parity Bits 8K 2008 8000 – 2008 9FFF no no 0004 D000 – 0004 DFFF S1 RAM - Parity Bits 8K 2008 A000 – 2008 BFFF no no 0004 E000 – 0004 EFFF S2 RAM - Parity Bits 8K 2008 C000 – 2008 DFFF no no 0004 F000 – 0004 FFFF S3 RAM - Parity Bits 8K 2008 E000 – 2008 FFFF no no 0005 0000 – 0005 0FFF S4 RAM - Parity Bits 8K 2009 0000 – 2009 1FFF no no 0005 1000 – 0005 1FFF S5 RAM - Parity Bits 8K 2009 2000 – 2009 3FFF no no 0005 2000 – 0005 2FFF S6 RAM - Parity Bits 8K 2009 4000 – 2009 5FFF no 8K 2009 6000 – 2009 7FFF no no no 16 Size (Bytes) 0005 3000 – 0005 3FFF S7 RAM - Parity Bits 0005 4000 – 0007 EFFF Reserved 0007 F000 – 0007 F3FF M0 RAM - ECC Bits 2K no 0007 F400 – 0007 F7FF M1 RAM - ECC Bits 2K no 0007 F800 – 0007 FBFF CtoM MSG RAM - Parity Bits 2K 200F F000 – 200F F7FF no no 0007 FC00 – 0007 FFFF MtoC MSG RAM - Parity Bits 2K 200F F800 – 200F FFFF no 0008 0000 – 0009 FFFF Reserved no (1) (2) Control Subsystem RAMs The letter "C" refers to the Control Subsystem. The letter "M" refers to the Master Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 2-8. Control Subsystem Flash, ECC, OTP, Boot ROM C Address (x16 Aligned) (1) no 0010 0000 – 0010 1FFF Sector N (not available for 256KB Flash configuration) 16K no 0010 2000 – 0010 3FFF Sector M (not available for 256KB Flash configuration) 16K no 0010 4000 – 0010 5FFF Sector L (not available for 256KB Flash configuration) 16K no 0010 6000 – 0010 7FFF Sector K (not available for 256KB Flash configuration) 16K no 0010 8000 – 0010 FFFF Sector J (not available for 256KB Flash configuration) 64K no 0011 0000 – 0011 7FFF Sector I (not available for 256KB Flash configuration) 64K no 0011 8000 – 0011 FFFF Sector H (not available for 256KB Flash configuration) 64K no 0012 0000 – 0012 7FFF Sector G 64K no 0012 8000 – 0012 FFFF Sector F 64K no 0013 0000 – 0013 7FFF Sector E 64K no 0013 8000 – 0013 9FFF Sector D 16K no 0013 A000 – 0013 BFFF Sector C 16K no 0013 C000 – 0013 DFFF Sector B 16K no 0013 E000 – 0013 FFFF Sector A (CSM password in the high address) 16K 0014 0000 – 001F FFFF Reserved 0020 0000 – 0020 7FFF Flash - ECC Bits (1/8 of Flash used = 64 KBytes) 0020 8000 – 0024 01FF Reserved no no (1) (2) (3) Control Subsystem Flash, ECC, OTP, Boot ROM Size (Bytes) M Address (Byte-Aligned) (2) µDMA Access 6000 0000 – DFFF FFFF yes PRODUCT PREVIEW C DMA Access (1) 64K 0024 0200 – 0024 03FF TI OTP 0024 0400 – 002F FFFF Reserved 1K yes 0030 0000 – 003F 7FFF EPI0 (External Peripheral/Memory Interface) (3) 2G no 003F 8000 – 003F FFFF C28x Boot ROM (64 KBytes) 64K The letter "C" refers to the Control Subsystem. The letter "M" refers to the Master Subsystem. The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 17 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.2.2 www.ti.com Master Subsystem Memory Map Table 2-9. Master Subsystem Flash, ECC, OTP, Boot ROM M Address (Byte-Aligned) (1) no 0000 0000 – 0000 FFFF Boot ROM - Dual-mapped to 0x0100 0000 (Both maps access same physical location.) 0001 0000 – 001F FFFF Reserved no 0020 0000 – 0020 3FFF Sector N (Zone 1 CSM password in the low address.) 16K no 0020 4000 – 0020 7FFF Sector M 16K no 0020 8000 – 0020 BFFF Sector L 16K no 0020 C000 – 0020 FFFF Sector K 16K no 0021 0000 – 0021 FFFF Sector J 64K no 0022 0000 – 0022 FFFF Sector I (not available for 256KB Flash configuration) 64K no 0023 0000 – 0023 FFFF Sector H (not available for 256KB Flash configuration) 64K no 0024 0000 – 0024 FFFF Sector G (not available for 256KB Flash configuration) 64K no 0025 0000 – 0025 FFFF Sector F (not available for 256KB Flash configuration) 64K no 0026 0000 – 0026 FFFF Sector E 64K no 0027 0000 – 0027 3FFF Sector D 16K no 0027 4000 – 0027 7FFF Sector C 16K no 0027 8000 – 0027 BFFF Sector B 16K 0027 C000 – 0027 FFFF Sector A (Zone 2 CSM password in the high address.) 16K 0028 0000 – 005F FFFF Reserved 0060 0000 – 0060 FFFF Flash - ECC Bits (1/8 of Flash used = 64 KBytes) 0061 0000 – 0068 047F Reserved no 0068 0480 – 0068 07FF TI OTP no 0068 0800 OTP – Security Lock 0068 0804 Reserved 0068 0808 Reserved no 0068 080C OTP – Zone 2 Flash Start Address 4 no 0068 0810 OTP – EMAC Address 0 4 no 0068 0814 OTP – EMAC Address 1 4 PRODUCT PREVIEW µDMA Access no no no no no (1) 18 Master Subsystem Flash, ECC, OTP, Boot ROM Size (Bytes) 64K 64K 896 4 0068 0818 – 0070 00FF Reserved 0070 0100 – 0070 0102 OTP – ECC Bits – Application Use (1/8 of OTP used = 3 Bytes) 0070 0103 – 00FF FFFF Reserved 0100 0000 – 0100 FFFF Boot ROM – Dual-mapped to 0x0000 0000 (Both maps access same physical location.) 0101 0000 – 03FF FFFF Reserved 0400 0000 – 07FF FFFF ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC. Accessing this area of memory by the µCRC peripheral will cause an access in 0000 0000 – 03FF FFFF memory space. Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped ROM address) Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF (Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register, when reading a block of data.) 0800 0000 – 1FFF FFFF Reserved 3 64K 64M The letter "M" refers to the Master Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 2-10. Master Subsystem RAMs M Address (Byte-Aligned) (1) C Address (x16 Aligned) (2) C DMA Access (2) no 2000 0000 – 2000 1FFF C0 RAM (ECC, Secure) 8K no 2000 2000 – 2000 3FFF C1 RAM (ECC, Secure) 8K yes 2000 4000 – 2000 5FFF C2 RAM (Parity) 8K yes 2000 6000 – 2000 7FFF C3 RAM (Parity) 8K yes 2000 8000 – 2000 9FFF S0 RAM (Parity, Shared) 8K 0000 C000 – 0000 CFFF yes yes 2000 A000 – 2000 BFFF yes 2000 C000 – 2000 DFFF S1 RAM (Parity, Shared) 8K 0000 D000 – 0000 DFFF yes S2 RAM (Parity, Shared) 8K 0000 E000 – 0000 EFFF yes yes 2000 E000 – 2000 FFFF S3 RAM (Parity, Shared) 8K 0000 F000 – 0000 FFFF yes yes 2001 0000 – 2001 1FFF S4 RAM (Parity, Shared) 8K 0001 0000 – 0001 0FFF yes yes 2001 2000 – 2001 3FFF S5 RAM (Parity, Shared) 8K 0001 1000 – 0001 1FFF yes yes 2001 4000 – 2001 5FFF S6 RAM (Parity, Shared) 8K 0001 2000 – 0001 2FFF yes yes 2001 6000 – 2001 7FFF S7 RAM (Parity, Shared) 8K 0001 3000 – 0001 3FFF yes Master Subsystem RAMs Size (Bytes) 2001 8000 – 2007 EFFF Reserved yes read only 2007 F000 – 2007 F7FF CtoM MSG RAM (Parity) 2K 0003 F800 – 0003 FBFF yes yes 2007 F800 – 2007 FFFF MtoC MSG RAM (Parity) 2K 0003 FC00 – 0003 FFFF yes read only no 2008 0000 – 2008 1FFF C0 RAM - ECC Bits 8K no 2008 2000 – 2008 3FFF C1 RAM - ECC Bits 8K no 2008 4000 – 2008 5FFF C2 RAM - Parity Bits 8K no 2008 6000 – 2008 7FFF C3 RAM - Parity Bits 8K no 2008 8000 – 2008 9FFF S0 RAM - Parity Bits 8K 0004 C000 – 0004 CFFF no no 2008 A000 – 2008 BFFF S1 RAM - Parity Bits 8K 0004 D000 – 0004 DFFF no no 2008 C000 – 2008 DFFF S2 RAM - Parity Bits 8K 0004 E000 – 0004 EFFF no no 2008 E000 – 2008 FFFF S3 RAM - Parity Bits 8K 0004 F000 – 0004 FFFF no no 2009 0000 – 2009 1FFF S4 RAM - Parity Bits 8K 0005 0000 – 0005 0FFF no no 2009 2000 – 2009 3FFF S5 RAM - Parity Bits 8K 0005 1000 – 0005 1FFF no no 2009 4000 – 2009 5FFF S6 RAM - Parity Bits 8K 0005 2000 – 0005 2FFF no no 2009 6000 – 2009 7FFF S7 RAM - Parity Bits 8K 0005 3000 – 0005 3FFF no 2009 8000 – 200F EFFF Reserved no 200F F000 – 200F F7FF CtoM MSG RAM - Parity Bits 2K 0007 F800 – 0007 FBFF no no 200F F800 – 200F FFFF MtoC MSG RAM - Parity Bits 2K 0007 FC00 – 0007 FFFF no 2010 0000 – 21FF FFFF Reserved 2200 0000 – 23FF FFFF Bit Banded RAM Zone (Dedicated address for each RAM bit of Cortex™-M3 RAM blocks above) 32M 2400 0000 – 27FF FFFF All RAM Spaces – MirrorMapped for µCRC. Accessing this memory by the µCRC peripheral will cause an access to 2000 0000 – 23FF FFFF memory space. (Read cycles from this space cause the µCRC peripheral to continuously update data checksum inside a register when reading a block of data.) 64M 2800 0000 – 3FFF FFFF Reserved yes yes (1) (2) PRODUCT PREVIEW µDMA Access The letter "M" refers to the Master Subsystem. The letter "C" refers to the Control Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 19 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-11. Master Subsystem Peripherals µDMA Access M Address (Byte-Aligned) (1) yes 4000 0000 – 4000 0FFF Watchdog Timer 0 Registers 4K yes 4000 1000 – 4000 1FFF Watchdog Timer 1 Registers 4K PRODUCT PREVIEW 4000 2000 – 4000 3FFF Reserved 4000 4000 – 4000 4FFF M GPIO Port A (APB Bus) (1) 4K yes 4000 5000 – 4000 5FFF M GPIO Port B (APB Bus) (1) 4K yes 4000 6000 – 4000 6FFF M GPIO Port C (APB Bus) (1) 4K yes 4000 7000 – 4000 7FFF M GPIO Port D (APB Bus) (1) 4K yes 4000 8000 – 4000 8FFF SSI0 4K yes 4000 9000 – 4000 9FFF SSI1 4K yes 4000 A000 – 4000 AFFF SSI2 4K yes 4000 B000 – 4000 BFFF SSI3 4K yes 4000 C000 – 4000 CFFF UART0 4K yes 4000 D000 – 4000 DFFF UART1 4K yes 4000 E000 – 4000 EFFF UART2 4K yes 4000 F000 – 4000 FFFF UART3 4K 4K 4001 0000 – 4001 0FFF UART4 4001 1000 – 4001 FFFF Reserved no 4002 0000 – 4002 07FF I2C0 Master 2K no 4002 0800 – 4002 0FFF I2C0 Slave 2K no 4002 1000 – 4002 17FF I2C1 Master 2K no 4002 1800 – 4002 1FFF I2C1 Slave 2K 4002 2000 – 4002 3FFF Reserved yes 4002 4000 – 4002 4FFF M GPIO Port E (APB Bus) (1) 4K yes 4002 5000 – 4002 5FFF M GPIO Port F (APB Bus) (1) 4K yes 4002 6000 – 4002 6FFF M GPIO Port G (APB Bus) (1) 4K (1) 4K yes 4002 7000 – 4002 7FFF M GPIO Port H (APB Bus) 4002 8000 – 4002 FFFF Reserved yes 4003 0000 – 4003 0FFF GP Timer 0 4K yes 4003 1000 – 4003 1FFF GP Timer 1 4K yes 4003 2000 – 4003 2FFF GP Timer 2 4K yes 4003 3000 – 4003 3FFF GP Timer 3 4K 4003 4000 – 4003 CFFF Reserved 4003 D000 – 4003 DFFF M GPIO Port J (APB Bus) (1) 4003 E000 – 4003 FFFF Reserved 4004 8000 – 4004 8FFF ENET MAC0 4004 9000 – 4004 FFFF Reserved 4005 0000 – 4005 0FFF USB MAC0 4005 1000 – 4005 7FFF Reserved 4005 8000 – 4005 8FFF M GPIO Port A (AHB Bus) (1) 4K yes 4005 9000 – 4005 9FFF M GPIO Port B (AHB Bus) (1) 4K yes 4005 A000 – 4005 AFFF M GPIO Port C (AHB Bus) (1) 4K yes 4005 B000 – 4005 BFFF M GPIO Port D (AHB Bus) (1) 4K yes 4005 C000 – 4005 CFFF M GPIO Port E (AHB Bus) (1) 4K yes 4005 D000 – 4005 DFFF M GPIO Port F (AHB Bus) (1) 4K yes 4005 E000 – 4005 EFFF M GPIO Port G (AHB Bus) (1) 4K yes yes yes yes 20 Size (Bytes) yes yes (1) (2) Master Subsystem Peripherals C Address (x16 Aligned) (2) C DMA Access (2) 4K 4K 4K The letter "M" refers to the Master Subsystem. The letter "C" refers to the Control Subsystem. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 2-11. Master Subsystem Peripherals (continued) µDMA Access M Address (Byte-Aligned) (1) yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus) (1) 4K yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus) (1) 4K 4006 1000 – 4006 FFFF Reserved no 4007 0000 – 4007 3FFF CAN0 16K no 4007 4000 – 4007 7FFF CAN1 16K 4007 8000 – 400C FFFF Reserved 400D 0000 – 400D 0FFF EPI0 (Registers only) 400D 1000 – 400F 9FFF Reserved 400F A000 – 400F A303 M Flash Control Registers (1) 400F A304 – 400F A5FF Reserved 400F A600 – 400F A647 M Flash ECC Error Log Registers (1) 400F A648 – 400F B1FF Reserved 400F B200 – 400F B2FF RAM Configuration Registers no 400F B300 – 400F B3FF RAM ECC/Parity/Access Error Log Registers no 400F B400 – 400F B5FF M CSM Registers(1) 512 128 no no no no no 400F B600 – 400F B67F µCRC 400F B680 – 400F B6FF Reserved 400F B700 – 400F B77F CtoM and MtoC IPC Registers Size (Bytes) C Address (x16 Aligned) (2) C DMA Access (2) 256 0000 4900 – 0000 497F no 256 0000 4A00 – 0000 4A7F no 128 0000 4E00 – 0000 4E3F no 0000 4400 – 0000 443F no 4K 772 72 400F B780 – 400F B7FF Reserved no 400F B800 – 400F B87F M Clock Control Registers(1) 128 no 400F B880 – 400F B8BF M LPM Control Registers(1) 64 no 400F B8C0 – 400F B8FF M Reset Control Registers(1) 64 no 400F B900 – 400F B93F Device Configuration Registers 64 400F B940 – 400F B97F Reserved no 400F B980 – 400F B9FF M Write Protect Registers(1) 128 no 400F BA00 – 400F BA7F M NMI Registers(1) 128 400F BA80 – 400F EFFF Reserved 400F F000 – 400F FFFF µDMA Registers 4010 0000 – 41FF FFFF Reserved 4200 0000 – 43FF FFFF Bit Banded Peripheral Zone (Dedicated address for each register bit of Cortex™-M3 peripherals above.) 4400 0000 – 4FFF FFFF Reserved no yes PRODUCT PREVIEW no Master Subsystem Peripherals 0000 0880 – 0000 0890 (Read Only) 4K 32M Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 21 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-12. Master Subsystem Analog and EPI µDMA Access yes yes yes (1) (2) (3) M Address (Byte-Aligned) (1) Master Subsystem Analog and EPI Size (Bytes) 5000 0000 – 5000 15FF Reserved 5000 1600 – 5000 161F ADC1 Result Registers 5000 1620 – 5000 167F Reserved 5000 1680 – 5000 169F ADC2 Result Registers 5000 16A0 – 5FFF FFFF Reserved 6000 0000 – DFFF FFFF EPI0 (External Peripheral/Memory Interface) C Address (x16 Aligned) (2) C DMA Access (2) 0030 0000 – 003F 7FFF (3) yes 32 32 2G The letter "M" refers to the Master Subsystem. The letter "C" refers to the Control Subsystem. The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Table 2-13. Cortex™-M3 Private Bus PRODUCT PREVIEW µDMA Access Cortex™-M3 Address (Byte-Aligned) no E000 0000 – E000 0FFF ITM (Instrumentation Trace Macrocell) 4K no E000 1000 – E000 1FFF DWT (Data Watchpoint and Trace) 4K no E000 2000 – E000 2FFF FPB (Flash Patch and Breakpoint) 4K E000 3000 – E000 E007 Reserved no E000 E008 – E000 E00F System Control Block 8 no E000 E010 – E000 E01F System Timer 16 E000 E020 – E000 E0FF Reserved no E000 E100 – E000 E4EF Nested Vectored Interrupt Controller (NVIC) E000 E4F0 – E000 ECFF Reserved no E000 ED00 – E000 ED3F System Control Block E000 ED40 – E000 ED8F Reserved no E000 ED90 – E000 EDB8 Memory Protection Unit E000 EDB9 – E000 EEFF Reserved E000 EF00 – E000 EF03 Nested Vectored Interrupt Controller (NVIC) E000 EF04 – FFFF FFFF Reserved no Cortex™-M3 Private Bus Size (Bytes) 1008 64 41 4 NOTE MPU is not available on silicon revision 0 devices. 22 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Master Subsystem The Master Subsystem includes the Cortex™-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC), Cortex™-M3 Peripherals, and Local Memory. Additionally, the Cortex™-M3 CPU and µDMA can access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can also receive events from the NMI block and send events to the Resets block. Figure 2-1 shows the Master Subsystem. 2.3.1 Cortex™-M3 CPU Most of the interrupts to the Cortex™-M3 CPU come from the Nested Vectored Interrupt Controller (NVIC), which manages the interrupt requests from peripherals and assigns handling priorities. There are also several exceptions generated by Cortex™-M3 CPU that can return to the Cortex™-M3 as interrupts after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not properly serviced. The Cortex™-M3 CPU has two low-power modes: Sleep and Deep Sleep. 2.3.2 Cortex™-M3 Core Hardware Logic Built-In Test (LBIST) The Concerto™ microcontroller Cortex™-M3 CPU core includes a Logic Built-In Self Test (LBIST) controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working correctly. During a test cycle, all interrupts are logged by the LBIST controller and re-issued after the test cycle completes to ensure that no interrupts are missed. In the event of a logic error, the LBIST controller generates an NMI on both cores to signal that an error has been detected. This action allows for the software to gracefully handle any detected logic errors. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 23 PRODUCT PREVIEW The 32-bit Cortex™-M3 processor offers high performance, fast interrupt handling, and access to a variety of communication peripherals (including Ethernet and USB). The Cortex™-M3 features a Memory Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex™-M3 System Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible by the Control Subsystem) and to the Analog Subsystem through the Analog Common Interface Bus (ACIB). Another bus bridge allows bus cycles from both the Cortex™-M3 System Bus and those of the µDMA bus to access the Master Subsystem peripherals (via the APB bus or the AHP bus). F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com M3PORRST M3 NMI RESETS M3SYSRST M3NMIINT M3NMIINT M3NMIRST M3NMI M3NMIINT M3WDRST (1:0) NVIC M3HRDFLT 3 2 FIXED PRIORITY INTERRUPTS 1 M3 PERIPHERALS M3SWRST WDOG (2) uCRC NMI WDOG GP TIMER (4) SSI (4) CAN (2) UART (5) I2C (2) EMAC USB + PHY (OTG) EPI GPIO_MUX1 PERIPHERAL I/O s M3DBGRST EOC INTERRUPTS EPI REQ USB MAC REQ EMACRX EMACTX REQ UART (5:1) REQ uDMA ADC INT (8:1) GPIO (S:A) IRQ EPI IRQ USB MAC IRQ EMAC IRQ I2C (1:0) IRQ M3 CPU GPTA/B (3:0) (3:0) REQ SSI (3:0) REQ BUS MATRIX DMA INTRS CAN0/1 (1:0) (1:0) IRQ UART (1:5) IRQ SSI (0:3) IRQ GPTA/B (3:0) (3:0) IRQ DMA ERR IRQ DMA SW IRQ WDT (1:0) IRQ NVIC (NESTED VECTORED INTERRUPT CONTROLLER) FLSINGER RAMSINGERR FLFSM USAGE FAULT SVCALL DBG MONITOR PENDING SV SYS TICK EXCEPTIONS FROM M3 CORE INTERRUPTS CTOM IPC (4:1) APB BUS (REG ACCESS ONLY) uDMA BUS M3 SYSTEM BUS MEMORY MNGMT PRODUCT PREVIEW ANALOG SUBSYSTEM APB BUS AHB BUS PROGRAMMABLE PRIORITY INTERRUPTS LOCAL MEMORY SECURE C0/C1 RAM (ECC) C2 - C3 RAM (parity) BOOT ROM SECURE FLASH (ECC) IPC REGS S0-S7 SHARED RAM (parity) MTOC MSG RAM (parity) CTOM MSG RAM (parity) SHARED RESOURCES FREQ GASKET MPU / BRIDGE BUS BRIDGE DATA INSTRUCTIONS I-CODE BUS D-CODE BUS RAMACCVIOL RAMUNCERR FLASHUNCERR RAMUNCERR CONTROL SUBSYSTEM BUS CNTRL/FAULT LOGIC BUSFAULT Figure 2-1. Master Subsystem 24 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.3.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Cortex™-M3 DMA and NVIC The Cortex™-M3 direct memory access (µDMA) module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the Cortex™-M3 CPU. The Nested Vectored Interrupt Controller (NVIC) manages and prioritizes interrupt handling for the Cortex™-M3 CPU. The Cortex™-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the Cortex™-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral, REQ/DONE will directly drive IRQ to the NVIC so that the Cortex™-M3 CPU can transfer the data. For those peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing the DMA. This case is true for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the µDMA or the NVIC (only to the Resets block). Cortex™-M3 Interrupts Table 2-14 shows all interrupt assignments for the Cortex™-M3 processor. Most interrupts (16–107) are associated with interrupt requests from Cortex™-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions generated by the Cortex™-M3 core itself. These processor exceptions are detailed in Table 2-15. Table 2-14. Interrupts from NVIC to Cortex™-M3 Interrupt Number (Bit in Interrupt Registers) Vector Number – 0–15 0x0000.0000–0x0000.003C Processor exceptions 0 16 0x0000.0040 GPIO Port A 1 17 0x0000.0044 GPIO Port B 2 18 0x0000.0048 GPIO Port C 3 19 0x0000.004C GPIO Port D 4 20 0x0000.0050 GPIO Port E 5 21 0x0000.0054 UART0 6 22 0x0000.0058 UART1 7 23 0x0000.005C SSI0 0x0000.0060 I2C0 – Reserved Vector Address or Offset Description 8 24 9–17 25–33 18 34 0x0000.0088 Watchdog Timers 0 and 1 19 35 0x0000.008C Timer 0A 20 36 0x0000.0090 Timer 0B 21 37 0x0000.0094 Timer 1A 22 38 0x0000.0098 Timer 1B 23 39 0x0000.009C Timer 2A 24 40 0x0000.00A0 Timer 2B 25–27 41–43 – Reserved 28 44 0x0000.00B0 System Control 29 45 0x0000.00B4 Flash State Machine 30 46 0x0000.00B8 GPIO Port F 31 47 0x0000.00BC GPIO Port G 32 48 0x0000.00C0 GPIO Port H 33 49 0x0000.00C4 UART2 34 50 0x0000.00C8 SSI1 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 25 PRODUCT PREVIEW 2.3.4 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-14. Interrupts from NVIC to Cortex™-M3 (continued) PRODUCT PREVIEW 26 Interrupt Number (Bit in Interrupt Registers) Vector Number 35 51 0x0000.00CC Timer 3A 36 52 0x0000.00D0 Timer 3B 37 53 0x0000.00D4 I2C1 38–41 54–57 – Reserved 42 58 0x0000.00E8 Ethernet Controller 44 60 0x0000.00F0 USB 45 61 – Reserved 46 62 0x0000.00F8 µDMA Software 47 63 0x0000.00FC µDMA Error 48–52 64–68 – Reserved 53 69 0x0000.0114 EPI 54 70 0x0000.0118 GPIO Port J 55–56 71–72 – Reserved 57 73 0x0000.0124 SSI 2 58 74 0x0000.0128 SSI 3 59 75 0x0000.012C UART3 0x0000.0130 UART4 – Reserved Vector Address or Offset Description 60 76 61–63 77–79 64 80 0x0000.0140 CAN1 INT0 65 81 0x0000.0144 CAN1 INT1 66 82 0x0000.0148 CAN1 INT0 67 83 0x0000.014C CAN1 INT1 68–71 84–87 – Reserved 72 88 0x0000.0160 ADCINT1 73 89 0x0000.0164 ADCINT2 74 90 0x0000.0168 ADCINT3 75 91 0x0000.016C ADCINT4 76 92 0x0000.0170 ADCINT5 77 93 0x0000.0174 ADCINT6 78 94 0x0000.0178 ADCINT7 79 95 0x0000.017C ADCINT8 80 96 0x0000.0180 CTOMIPC1 81 97 0x0000.0184 CTOMIPC2 82 98 0x0000.0188 CTOMIPC3 83 99 0x0000.018C CTOMIPC4 84–87 100–103 – Reserved 88 104 0x0000.01A0 RAM Single Error 89 105 0x0000.01A4 System / USB PLL Out of Lock 90 106 0x0000.01A8 M3 Flash Single Error 91–133 107–149 – Reserved Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Exception Type – Reset Non-Maskable Interrupt (NMI) Hard Fault Memory Management Priority (1) Vector Number Vector Address or Offset (2) Activation – 0 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. –3 (highest) 1 0x0000.0004 Asynchronous –2 2 0x0000.0008 Asynchronous On Concerto devices activated by clock fail condition, C28 PIE error, external M3GPIO NMI input signal, and C28 NMI WD timeout reset. –1 3 0x0000.000C – programmable (3) 4 0x0000.0010 Synchronous 5 0x0000.0014 Synchronous when precise and asynchronous when imprecise. On Concerto devices activated by memory access errors and RAM and flash uncorrectable data errors. Synchronous Bus Fault programmable (3) Usage Fault programmable (3) 6 0x0000.0018 – 7–10 – programmable (3) 11 0x0000.002C Synchronous (3) Synchronous – SVCall Debug Monitor 12 0x0000.0030 – 13 – PendSV programmable (3) 14 0x0000.0038 Asynchronous SysTick programmable (3) 15 0x0000.003C Asynchronous 16 and above 0x0000.0040 and above Asynchronous – Interrupts (1) (2) (3) (4) programmable Reserved programmable (4) Reserved 0 is the default priority for all the programmable priorities See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x Technical Reference Manual (literature number SPRUH22). See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number SPRUH22). See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number SPRUH22). 2.3.5 Cortex™-M3 Vector Table Each peripheral interrupt of Table 2-14 is assigned an address offset containing the location of the peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 16–107). Similarly, each exception interrupt of Table 2-15 (including Reset) is also assigned an address offset containing the location of the exception interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 1–15). In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table location 0. Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000 0200 to 0x3FFF FE00. Note that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27 PRODUCT PREVIEW Table 2-15. Exceptions from Cortex™-M3 Core to NVIC F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.3.6 www.ti.com Cortex™-M3 Local Peripherals The Cortex™-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB + PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus (Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem. The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and AHB bus cycles originate from the CPU System Bus or the µDMA Bus via a bus bridge. While the Cortex™-M3 CPU has access to all the peripherals, the µDMA has access to most, with the exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The Cortex™-M3 peripherals connect to the Concerto™ device pins via GPIO_MUX1. Most of the peripherals also generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets block. See Section 6.2 for more information on the Cortex™-M3 peripherals. 2.3.7 Cortex™-M3 Local Memory PRODUCT PREVIEW The Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure C0/C1 RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the Cortex™-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex™-M3 CPU; the C2/C3 RAM is also accessible by the µDMA. Two types of error correction events can be generated during access of the Local Memory: uncorrectable errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a Bus Fault Exception to the Cortex™-M3 CPU. The less critical single errors go to the NVIC where they can result in maskable interrupts to the Cortex™-M3 CPU. 2.3.8 Cortex™-M3 Accessing Shared Resources and Analog Peripherals There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem. The Shared Resources include the External Peripheral Interface (EPI), Inter-Processor Communications (IPC) registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity Error Checking. The Message RAMs and the Shared RAMs can be accessed by the Cortex™-M3 CPU and µDMA. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having r/w access for the Cortex™-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having r/w access for the C28x/DMA and read-only access for the Cortex™-M3/µDMA. The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. 28 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The Cortex™-M3 CPU accesses the ACIB through the System Bus, and the µDMA through the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations in both the Master Subsystem and the Control Subsystem. See Section 6.1 for more information on shared resources and analog peripherals. 2.4 Control Subsystem The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block, DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals via the Analog Common Interface Bus. 2.4.1 C28x CPU/FPU/VCU The F28M35x Concerto™ MCU family is a member of the TMS320C2000™ MCU platform. The Concerto™ C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Piccolo™ MCUs, combined with a single-precision (32-bit) IEEE 754 floating-point unit (FPU) of TI’s existing Delfino™ MCUs. Each F28M35x device is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. Each F28M35x device also enables math algorithms to be developed using C/C++. The device is equally efficient at DSP math tasks and at system control tasks. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. With the addition of the fast interrupt response with automatic context save of critical registers, the device is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special conditional store operations further improve performance. The VCU extends the capabilities of the C28x CPU and C28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have been made to existing instructions, pipeline, or memory bus architecture. Therefore, programs written for the C28x are completely compatible with the C28x+VCU. There are two events generated by the FPU block that go to the C28x Peripheral Interrupt Expansion (PIE): LVF and LUV. Inside PIE, these and other events from C28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into the C28x CPU. The C28x CPU also receives three additional interrupts directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block (C28uNMIINT). The C28x has two low-power modes: Idle and Standby. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 29 PRODUCT PREVIEW Figure 2-2 shows the Control Subsystem. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com RAMUNCERR EPI RAMUNCERR MASTER SUBSYSTEM GPIO_MUX1 C28x NMI ECCDBLERR FREQ GASKET S0-S7 SHARED RAM (parity) IPC REGS BUS BRIDGE MTOC MSG RAM (parity) GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) FLASHUNCERR SHARED RESOURCES C28x LOCAL MEMORY CTOM MSG RAM (parity) MTOCIPC (4:1) SECURE FLASH (ECC) BOOT ROM PRODUCT PREVIEW FLFSM FLSINGERR RAMACCVIOL ANALOG SUBSYSTEM SECURE L0/L1 RAM (ECC) LPM WAKEUP M0/M1 RAM (ECC) L2/L3 RAM (parity) RAMSINGERR LVF LPMWAKE LUF PIE (PERIPHERAL INTERRUPT EXPANSION) C28x FPU PIEINTRS (12:1) EOC INTERRUPTS DINTCH (6:1) ADCINT (8:1) ADCINT (4:1) MXINTA, MRINTA I2CINT1A, I2CINT2A SCIRXINTA, SCITXINTA TINT 0,1,2 C28x CPU SOC TRIGGERS C28x DMA TINT 0,1,2 SPIRXINTA, SPITXINTA EQEP(3:1)INT XINT 2 XINT 1,2,3 EPWM(9:1)INT EPWM(9:1)TZINT SOCA (9:1), SOCB(9:1) SOCA (9:1), SOCB(9:1) ECAP(6:1)INT C28 DMA BUS C28 CPU BUS TINT1 C28x PERIPHERALS TINT2 C28NMI NMI WDOG TIMER (3) XINT (3) ECAP (6) EQEP ERR EPWM (9) EQEP (3) McBSP SPI SCI I2C GPIO_MUX1 PERIPHERAL I/O s ECCDBLERR C28x VCU C28NMIINT EMUSTOP PIENMIERR SOCAO SOCBO GPIO_MUX1 SYNCO CLOCKFAIL M3 CLOCKS GPTRIP (12:1) GPTRIP (12:7) GPTRIP (6:4) GPIO_MUX1 C28NMIRST RESETS M3 NMI C28x NMI Figure 2-2. Control Subsystem 30 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.4.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 C28x™ Core Hardware Logic Built-In Test (LBIST) The Concerto™ microcontroller C28x CPU core includes a Logic Built-In Self Test (LBIST) controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working correctly. During a test cycle, all interrupts are logged by the LBIST controller and re-issued after the test cycle completes to ensure that no interrupts are missed. In the event of a logic error, the LBIST controller generates an NMI on both cores to signal that an error has been detected. This action allows for the software to gracefully handle any detected logic errors. 2.4.3 C28x Peripheral Interrupt Expansion (PIE) Table 2-16. PIE Peripheral Interrupts (1) PIE INTERRUPTS CPU INTERRUPTS (1) INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1 C28.LPMWAKE (C28LPM) 0x0D4E TINT0 (TIMER 0) 0x0D4C Reserved – 0x0D4A XINT2 – 0x0D48 XINT1 – 0x0D46 Reserved – 0x0D44 ADCINT2 (ADC) 0x0D42 ADCINT1 (ADC) 0x0D40 INT2 EPWM8_TZINT (ePWM8) 0x0D5E EPWM7_TZINT (ePWM7) 0x0D5C EPWM6_TZINT (ePWM6) 0x0D5A EPWM5_TZINT (ePWM5) 0x0D58 EPWM4_TZINT (ePWM4) 0x0D56 EPWM3_TZINT (ePWM3) 0x0D54 EPWM2_TZINT (ePWM2) 0x0D52 EPWM1_TZINT (ePWM1) 0x0D50 INT3 EPWM8_INT (ePWM8) 0x0D6E EPWM7_INT (ePWM7) 0x0D6C EPWM6_INT (ePWM6) 0x0D6A EPWM5_INT (ePWM5) 0x0D68 EPWM4_INT (ePWM4) 0x0D66 EPWM3_INT (ePWM3) 0x0D64 EPWM2_INT (ePWM2) 0x0D62 EPWM1_INT (ePWM1) 0x0D60 INT4 EPWM9_TZINT (ePWM9) 0x0D7E Reserved – 0x0D7C ECAP6_INT (eCAP6) 0x0D7A ECAP5_INT (eCAP5) 0x0D78 ECAP4_INT (eCAP4) 0x0D76 ECAP3_INT (eCAP3) 0x0D74 ECAP2_INT (eCAP2) 0x0D72 ECAP1_INT (eCAP1) 0x0D70 INT5 EPWM9_INT (ePWM9) 0x0D8E Reserved – 0x0D8C Reserved – 0x0D8A Reserved – 0x0D88 Reserved – 0x0D86 EQEP3_INT (eQEP3) 0x0D84 EQEP2_INT (eQEP2) 0x0D82 EQEP1_INT (eQEP1) 0x0D80 INT6 Reserved – 0x0D9E Reserved – 0x0D9C MXINTA (McBSPA) 0x0D9A MRINTA (McBSPA) 0x0D98 Reserved – 0x0D96 Reserved – 0x0D94 SPITXINTA (SPIA) 0x0D92 SPIRXINTA (SPIA) 0x0D90 INT7 Reserved – 0x0DAE Reserved – 0x0DAC DINTCH6 (C28 DMA) 0x0DAA DINTCH5 (C28 DMA) 0x0DA8 DINTCH4 (C28 DMA) 0x0DA6 DINTCH3 (C28 DMA) 0x0DA4 DINTCH2 (C28 DMA) 0x0DA2 DINTCH1 (C28 DMA) 0x0DA0 INT8 Reserved – 0x0DBE Reserved – 0x0DBC Reserved – 0x0DBA Reserved – 0x0DB8 Reserved – 0x0DB6 Reserved – 0x0DB4 I2CINT2A (I2CA) 0x0DB2 I2CINT1A (I2CA) 0x0DB0 INT9 Reserved – 0x0DCE Reserved – 0x0DCC Reserved – 0x0DCA Reserved – 0x0DC8 Reserved – 0x0DC6 Reserved – 0x0DC4 SCITXINTA (SCIA) 0x0DC2 SCIRXINTA (SCIA) 0x0DC0 INT10 ADCINT8 (ADC) 0x0DDE ADCINT7 (ADC) 0x0DDC ADCINT6 (ADC) 0x0DDA ADCINT5 (ADC) 0x0DD8 ADCINT4 (ADC) 0x0DD6 ADCINT3 (ADC) 0x0DD4 ADCINT2 (ADC) 0x0DD2 ADCINT1 (ADC) 0x0DD0 INT11 Reserved – 0x0DEE Reserved – 0x0DEC Reserved – 0x0DEA Reserved – 0x0DE8 MTOCIPCINT4 (IPC) 0x0DE6 MTOCIPCINT3 (IPC) 0x0DE4 MTOCIPCINT2 (IPC) 0x0DE2 MTOCIPCINT1 (IPC) 0x0DE0 INT12 LUF (C28FPU) 0x0DFE LVF (C28FPU) 0x0DFC EPI_INT (EPI) 0x0DFA Reserved – 0x0DF4 C28FLSINGERR (Memory) 0x0DF2 XINT3 (Ext. Int. 3) 0x0DF0 C28RAMACCVIOL C28RAMSINGERR (Memory) (Memory) 0x0DF8 0x0DF6 Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: 1) No peripheral within the group is asserting interrupts. 2) No peripheral interrupts are assigned to the group (example PIE group 11). Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 31 PRODUCT PREVIEW The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28M35x, 66 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. See Table 2-16 for PIE interrupt assignments. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.4.4 www.ti.com C28x DMA The C28x direct memory access (DMA) module provides a hardware method of transferring data between peripherals, between memory, and between peripherals and memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher priority than the others. 2.4.5 C28x Local Peripherals PRODUCT PREVIEW The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2C), an External Peripheral Interface (EPI), and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are accessible by the C28x CPU via the C28x Memory Bus. Additionally, the McBSP and ePWM are accessible by the C28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The Serial Port Peripherals and the Control Peripherals connect to Concerto’s pins via the GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and the Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and sends a counter timeout event to the Cortex™-M3 NMI block and the Resets block to flag a potentially critical condition. The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1. See Section 6.3 for more information on C28x peripherals. 2.4.6 C28x Local Memory The C28x Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of error correction events can be generated during access of the C28x Local Memory: uncorrectable errors and single errors. The uncorrectable errors propagate to the NMI block where they can become the C28NMI to the C28x NMI Watchdog and the C28NMIINT non-maskable interrupt to the C28x CPU. The less critical single errors go to the PIE block where they can become maskable interrupts to the C28x CPU. 2.4.7 C28x Accessing Shared Resources and Analog Peripherals There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem. The Shared Resources include the External Peripheral Interface (EPI), Inter-Processor Communications (IPC) registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have ParityError Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having r/w access for the Cortex™-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having r/w access for the C28x/DMA and read-only access for the Cortex™M3/µDMA. 32 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling). The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem. See Section 6.1 for more information on shared resources and analog peripherals. 2.5 Analog Subsystem There are 22 possible SOC (Start-Of-Conversion) sources from the C28x Subsystem that are mapped to a total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2). Going the other way, eight EOC (End-Of-Conversion) sources from ADC1 and eight EOC sources from ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the C28x DMA. The Concerto™ MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six Analog Comparators + DAC units; and an Analog Common Interface Bus (ACIB) to facilitate analog data communications with Concerto’s two digital subsystems (Cortex™-M3 and C28x). Figure 2-3 shows the Analog Subsystem. 2.5.1 ADC1 The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally pre-assigned to two Sample-and-Hold (S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. Start-of-Conversion (SOC) triggers from the Control Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC) interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC1 result registers. See Section 6.1.1 for more information on ADC peripherals. 2.5.2 ADC2 The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs are converted sequentially. Start-of-Conversion (SOC) triggers from the Control Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC) interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read from ADC2 result registers. See Section 6.1.1 for more information on ADC peripherals. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 33 PRODUCT PREVIEW The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed via the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex™-M3 Subsystem. In addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 10 AIO_MUX1 GPIO MUX 4 ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ANALOG COMMON INTERFACE BUS ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 ANALOG BUS MCIBSTATUS REG ANALOG BUS GPIO_MUX2 PRODUCT PREVIEW EOC INTERRUPTS (8:1) GPIO MUX 8 ADC1INT (8:1) VDDA (3.3V) ADCINT(8:1) ADC2INT (8:1) COMPOUT (6:1) VSSA (0V) COMPA4 COMPA5 COMPA6 M3 uDMA BUS M3 SYSTEM BUS COMPB2 6 COMPARATOR + DAC UNITS 8 M3 uDMA TRIGS (8:1) ADC 1 COMPA1 COMPA2 COMPA3 M3 CPU C28 CPU BUS C28 DMA BUS COMPB5 CCIBSTATUS REG C28x CPU TRIGS (8:1) ADC 2 SOC TRIGGERS (8:1) ADCINT (4:1) C28x DMA TINT (2:0) ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 XINT2 SOC (9:1) A TRIG8SEL REG SOC (9:1) B TRIG7SEL REG ... GPIO TRIG2SEL REG MUX 4 AIO_MUX2 TRIG1SEL REG TIMER (3) XINT2 EPWM (9) 10 Figure 2-3. Analog Subsystem 34 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.5.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Analog Comparator + DAC There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs, resulting in six digital comparison outputs. The external analog inputs that are being compared in the comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be mapped to six out of eight available pins. Note that in order to use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be assigned to selected 12 ePWM Trip Inputs. See Section 6.1.2 for more information on the analog comparator + DAC. Analog Common Interface Bus (ACIB) The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the Cortex™-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex™-M3 uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem side. Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems. The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines because it is unlikely that any application would need all 16 interrupts at the same time. Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22 possible trigger sources to each SOC trigger. There are two registers that provide status of ACIB to the Master Subsystem and to the Control Subsystem. The Cortex™-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly propagating between the Master, Control, and Analog subsystems. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 35 PRODUCT PREVIEW 2.5.4 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.6 www.ti.com Master Subsystem NMIs The Cortex™-M3 NMI Block generates an M3NMIINT non-maskable interrupt to the Cortex™-M3 CPU and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside the Concerto™ MCU. When able to respond to the M3NMIINT interrupt, the Cortex™-M3 CPU may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an M3NMIRST reset signal is sent to the Resets block. The inputs to the Cortex™-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR, VREGWARN, EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the C28x Peripheral Interrupt Expansion (PIE) block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. The VREGWARN input communicates a power anomaly. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency. MLBISTERR is generated by the Cortex™-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected. PRODUCT PREVIEW The Cortex™-M3 NMI block can be accessed via the Cortex™-M3 NMI configuration registers—including the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI. 2.7 Control Subsystem NMIs The C28x NMI Block generates a C28NMIINT non-maskable interrupt to the C28x CPU and a C28NMI event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto™ MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the C28NMIRST reset signal is sent to the Resets block and the Cortex™-M3 NMI Block, where the Cortex™M3 NMI Block can generate an NMI to the Cortex™-M3 processor. The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR, PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x Peripheral Interrupt Expansion (PIE) block. MLBISTERR is generated by the Cortex™-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected. The C28x NMI block can be accessed via the C28x NMI configuration registers—including the CNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force the flags to active state, respectively. Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI. 36 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 M3 BIST 1.2V VREG M3BISTERR M3 NMI WDOG VREGWARN M3NMI M3 WDOG (2) M3NMIRST M3WDRST (1:0) NMI M3NMI M3EXTNMI M3 NMI C28BISTERR M3NMIINT M3 CPU C28NMIRST ACIBERR ANALOG SUBSYSTEM PRODUCT PREVIEW M3BISTERR GPIO_MUX M3WDRST (1:0) M3NMIRST RESETS C28NMIRST CLOCKFAIL CLOCKS PIENMIERR M3BISTERR RAMUNCERR SHARED RAM C28NMIINT C28x NMI C28BISTERR C28x CPU C28NMI C28x LOCAL RAM C28BISTERR C28x BIST FLASHUNCERR C28NMI C28x FLASH C28NMIRST C28x NMI WDOG Figure 2-4. Cortex™-M3 NMI and C28x NMI Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 37 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.8 www.ti.com Resets The Concerto™ MCU has two external reset pins: XRS for the Master and Control Subsystems, and ARS for the Analog Subsystem. TI recommends that these two pins be externally tied together with a board signal trace. The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control Subsystems. A reset pulse can also be driven out of the XRS pin by the voltage monitoring block of the Master and Control Subsystems (see Section 2.9). A reset pulse can be driven out of the XRS pin when the two Cortex™-M3 Watchdogs or the Cortex™-M3 NMI Watchdog time out. There are some requirements on the XRS pin: 1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is stable. This requirement is to enable the entire device to start from a known condition. 2. During power down, the XRS pin must be pulled low at least 8 µs prior to VDDIO reaching 1.5 V. This requirement is to enhance Flash reliability. 3. TI recommends that no voltage larger than 0.7 V be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can lead to unpredictable results. PRODUCT PREVIEW The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset pulse can be driven out of the ARS pin by the voltage monitoring block of the Analog Subsystem. Figure 2-5 shows the resets. 2.8.1 Cortex™-M3 Resets The Cortex™-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR (Power-On Reset) or the M3SYSRST reset signal. In both cases, the Cortex™-M3 CPU restarts program execution from the address provided by the reset entry in the vector table. A register can later be referenced to determine the source of the reset. The M3SYSRST signal also propagates to the Cortex™M3 peripherals and the rest of the Cortex™-M3 Subsystem. The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS is set in response to time-out conditions of the two Cortex™-M3 Watchdogs or the Cortex™M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two resets also propagate to the C28x Subsystem and the Analog Subsystem. The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from the Cortex™-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface Bus. In addition to driving reset signals to other parts of the chip, the Cortex™-M3 can also detect a C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS register. Cortex™-M3 software can also set bits in the SRCR register to selectively reset individual Cortex™-M3 peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause register (MRESC) can be read to find out if the latest reset was caused by External Reset, VMON/POR/BOR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC. 38 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 M3 WDOG (1) M3WDOGS M3 WDOG (0) JTAG CONTROLLER CRESSTS REG M3 BIST ( SETS DEFAULT VALUES ) SOFTWARE CRESCNF REG MLBISTRST M3PORRST POR ACIBRST M3RSNIN C28SYSRST M3 NVIC M3 CPU XRS M3 NMI WDOG M3SYSRST XRS FLASH PUMP M3SYSRST PRODUCT PREVIEW VOLTAGE REGULATION AND MONITORING XRS M3SWRST PERIPHERAL SOFTWARE RESETS M3DBGRST M3 SUBSYSTEM SRCR REG MRESC REG CONTAINS RESET CAUSES DC REG GLOBAL PERIPHERAL ENABLES ACIBRST ANALOG SUBSYSTEM ARS PIN SRXRST XRS GPIO_MUX SHARED RESOURCES M3WDOGS POR C28x BIST C28x SUBSYSTEM CLBISTRST XRS PIN ‘0’ C28RSTIN C28SYSRST XRS C28x CPU SYNC DEGLITCH ACIBRST M3SSCLK XRS C28x NMI WDOG RESET INPUT SIGNAL STATUS DEVICECNF REG C28NMIWD Figure 2-5. Resets Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 39 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.8.2 www.ti.com C28x Resets The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the address provided at the top of the Boot ROM Vector Table. The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex™-M3 processor in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex™-M3 Subsystem to selectively reset the C28x Subsystem from Cortex™-M3 software. The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin by reading the DEVICECNF register. 2.8.3 Analog Subsystem and Shared Resources Resets Both the Analog Subsystem and the resources shared between the C28x and Cortex™-M3 subsystems (IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog Subsystem is also reset by the internal ACIBRST signal from the Cortex™-M3 Subsystem and the external ARS pin (which should be externally tied to the XRS pin). PRODUCT PREVIEW The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the NVIC. These two resets must be first enabled by the Cortex™-M3 processor in order to propagate to the Analog Subsystem and the Shared Resources. Although EPI is a shared peripheral, it is physically located inside the Cortex™-M3 Subsystem; therefore, EPI is reset by M3SYSRST. 2.8.4 Device Boot Sequence Concerto’s boot sequence is used to configure the Master Subsystem and the Control Subsystem for execution of application code. The boot sequence involves both internal resources, and resources external to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factoryprogrammed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected Cortex™-M3 and C28x peripherals for loading the application code into the Master and Control Subsystems. The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by device power up, external reset, debugger reset, software reset, Cortex™-M3 watchdog reset, or Cortex™-M3 NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and then both bootloaders work in tandem to configure the device, load application code for both processors (if not already in the Flash), and branch the execution of each processor to a selected location in the application code. Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem, the C-Bootloader enters the C28x processor into the idle mode (to wait for the MBootloader to wake up the C28x processor later via the MTOCIPC1 interrupt). Next, the M-Bootloader reads four GPIO pins (see Table 2-17) to determine the boot mode for the rest of the M-Bootloader operation. 40 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Boot Mode No. Master Subsystem Boot Modes PF2_GPIO34 (BOOT_3)(1) PF3_GPIO35 (BOOT_2)(1) PG7_GPIO47 (BOOT_1)(1) PG3_GPIO43 (BOOT_0)(1) 0(2) Boot from Parallel GPIO 0 0 0 0 1(2) Boot to Master Subsystem RAM 0 0 0 1 2(2) Boot from Master Subsystem serial peripherals (UART0/SSI0/I2C0) 0 0 1 0 Boot from Master Subsystem CAN interface 0 0 1 1 4(2) Boot from Master Subsystem Ethernet interface 0 1 0 0 5(2) Not supported (Defaults to Boot-to-Flash), future boot from Cortex™-M3 USB 0 1 0 1 6(2) Not supported (Defaults to Boot-to-Flash) 0 1 1 0 7(2) Boot to Master Subsystem Flash memory 0 1 1 1 8(3) Not supported (Defaults to Boot-to-Flash) 1 0 0 0 9(3) Boot from Master Subsystem serial peripheral – SSI0 Master 1 0 0 1 10(3) Boot from Master Subsystem serial peripheral – I2C0 Master 1 0 1 0 11(3) Not supported (Defaults to Boot-to-Flash) 1 0 1 1 12(3) Not supported (Defaults to Boot-to-Flash) 1 1 0 0 13(3) Not supported (Defaults to Boot-to-Flash) 1 1 0 1 (3) Not supported (Defaults to Boot-to-Flash) 1 1 1 0 Boot to Master Subsystem Flash memory 1 1 1 1 3 (2) 14 15(3)(4)(5) (1) By default, GPIO terminals are not pulled up (they are floating). (2) Boot Modes 0–7 are pin-compatible with future members of the Concerto family (they use same GPIO terminals). (3) Boot Modes 8–15 are not supported on silicon revision 0. (4) This Boot Mode uses a faster Flash power-up sequence. The maximum supported OSCCLK frequency for this mode is 30 MHz. (5) This Boot Mode is the same as Boot Mode 7, but in Fast Mode. Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the Master Flash memory. This branching requires that the Master Flash be already programmed with valid code; otherwise, a hard fault exception is generated and the Cortex™-M3 goes back to the above reset sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until the emulator is connected and a debug session started.) If the Master Subsystem Flash has already been programmed, the application code will start execution. Typically, the Master Subsystem application code will then establish data communication with the C28x [through the IPC (Interprocessor Communications peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Boot Mode 15 (Fast Boot to Flash Mode) supported on this device is a special boot to Flash mode, which configures Flash for a faster power up, thus saving some boot time. Boot Mode 7 and other modes which default to Flash do not configure Flash for a faster power up like Boot Mode 15 does. Note that following reset, the internal pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four external pullups. Boot Mode 1 causes the Master boot program to branch to Cortex™-M3 RAM, where the Cortex™-M3 processor starts executing code that has been preloaded earlier. Typically, this mode is used during development of application code meant for Flash, but which has to be first tested running out of RAM. In this case, the user would typically load the application code into RAM using the debugger, and then issue a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot process on the Master Subsystem side is controlled by the application code. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 41 PRODUCT PREVIEW Table 2-17. Master Subsystem Boot Mode Selection F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external peripheral before branching to the application code. This process is different from the process in Boot Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into RAM by the emulator. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins. If the boot pins are set to 0010b, the application code will be loaded from the Master Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the F28M35x device. If the boot pins are set to 1001b or 1010b, then the application code will be loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. If the boot pins are set to 1100b, then the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are F28M35x IOs, which are available only in a BGA package. PRODUCT PREVIEW Regardless of the type of boot mode selected, once the Master application code is resident in Master Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the application code takes over control from the M-Bootloader, and the boot process continues as prescribed by the application code. At this stage, the Master application program typically establishes communication with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the C28x to go into Idle mode. To wake the Control Subsystem out of Idle mode, the Master application issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1). Once the data communication has been established through the IPC, the boot process can now also continue on the Control Subsystem side. The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to branch to preloaded code in RAM (development mode), or to upload the Control application code from one of several available peripherals (see Table 2-18). As before, once the Control application code is in place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the application code takes over. Table 2-18. Control Subsystem Boot Mode Selection Control Subsystem Boot Modes MTOCIPCBOOTMODE Register Value Description BOOT_FROM_RAM 0x0000 0001 Upon receiving this command from the Master Subsystem, C-Boot ROM will branch to the Control Subsystem RAM entry point location and start executing code from there. BOOT_FROM_FLASH 0x0000 0002 Upon receiving this command, C-Boot ROM will branch to the Control Subsystem FLASH entry point and start executing code from there. BOOT_FROM_SCI 0x0000 0003 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SCI peripheral. BOOT_FROM_SPI 0x0000 0004 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem SPI interface. BOOT_FROM_I2C 0x0000 0005 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem I2C interface. BOOT_FROM_PARALLEL 0x0000 0006 Upon receiving this command, C-Boot ROM will boot from the Control Subsystem GPIO. 42 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 The boot process can be considered completed once the Cortex™-M3 and C28x are both running out of their respective application programs. Note that following the boot sequence, the C-Bootloader is still available to interpret and act upon an assortment of IPC commands that can be issued from the Master Subsystem to perform a variety of configuration, housekeeping, and other functions. See the Concerto F28M35x Technical Reference Manual (literature number SPRUH22) for additional information on Concerto boot modes, IPC commands, and the underlying boot philosophy. 2.9 Internal Voltage Regulation and Monitoring While Concerto’s analog functions draw power from a single dedicated external power source—VDDA, its digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This section describes the sourcing, regulation, monitoring, and other considerations for these three digital power rails. The Analog and Digital Subsystems each have their own power regulation and monitoring functions that operate independently, but which can—when the ARS and XRS reset pins are externally tied together—simultaneously reset the entire Concerto device when power loss is imminent. See Figure 2-6 for a snapshot of the digital power regulation and monitoring functions provided within Concerto’s Analog and Digital Subsystems. 2.9.1 Analog Subsystem Voltage Regulation and Monitoring The Analog Subsystem internally provides voltage regulation and monitoring functions. Internal voltage monitoring features consist of the Power-On Reset (POR) function that holds the device in reset state during power up, and the Brown-Out Reset (BOR) functions that reset the device just before the VDDIO and VDD18 power rails dip or VDD18 spikes outside of operational voltage range. 2.9.1.1 Analog Subsystem’s Internal 1.8-V VREG The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8-V VREG provides 1.8 V to digital logic associated with the analog functions of the Analog Subsystem. When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided externally; however, a 1.2-µF capacitor is required for each VDD18 pin to stabilize the internally generated voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is provided from an external supply. Note that the same VREG18EN pin that enables the internal 1.8-V VREG also enables the 1.8-V BOR function of the Analog Subsystem. Also note that while removing the need for an external power supply, enabling the internal VREG will increase the VDDIO power consumption. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 43 PRODUCT PREVIEW Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the Cortex™-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses VDD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems share a common VDDIO rail to power their 3.3-V I/O buffers through which Concerto’s digital signals communicate with the outside world. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE ARS PIN XRS PIN CONCERTO DEVICE M3WDOGS ARS XRS DE-GLITCH DE-GLITCH ‘0’ ‘0’ VOLTAGE MONITORING (DIGITAL SUBSYSTEM) 1.8V BOR 3.3V BOR CHECKS FOR HI/LOW CHECKS FOR LOW 3.3V POR 1.8V TRISTATE 3.3V VMON 3.3V POR 1.2V 1.2V POR VREGWARN NMI ANALOG SUBSYSTEM GPIOS DIGITAL LOGIC (DIGITAL SUBSYSTEM) M3 NVIC CHECKS FOR HI/LOW M3 CPU M3 NMI M3 WDOGS (0,1) M3 NMI WDOG DIGITAL LOGIC (ANALOG SUBSYSTEM) RESETS ACIBRST M3RSNIN I/O 1.8V 1.2V 1.8V 1.2V 1.8V VREG (ANALOG SUBSYSTEM) CRESCNF REG RST CONTROL SUBSYSTEM I/O 1.2V VREG (DIGITAL SUBSYSTEM) 3.3V VREG18EN PIN 1.2V BOW DIGITAL SUBSYSTEM GPIOS PRODUCT PREVIEW TRISTATE VOLTAGE MONITORING (ANALOG SUBSYSTEM) POR 3.3V 1.8V SUPPLY PINS 3.3V SUPPLY PINS 1.2V SUPPLY PINS VREG12EN PIN Figure 2-6. Voltage Regulation and Monitoring 44 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 2.9.1.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Analog Subsystem’s Voltage Monitoring The Voltage Monitoring Block of the Analog Subsystem consists of the POR function and BOR functions. POR holds the device in reset during power up, until power stabilizes and voltage levels reach operational range. Once the device is properly powered up, the BOR functions search for power dips and spikes, and assert ARS when voltage levels venture outside of operational range. 2.9.1.2.1 Analog Subsystem’s POR POR keeps the ARS reset signal asserted during device power up, and deasserts the signal only when the 3.3-V power rail reaches operational voltage level. While in most applications, the POR-generated reset has a long enough duration to also reset other system ICs, some applications may require a longerlasting reset pulse. In these cases, the ARS reset pin (which is open-drain) can also be driven from outside in, to match the time the device is held in reset state with the rest of the system. When POR (or BOR) drives the ARS pin low, POR (or BOR) also resets the digital logic associated with analog functions, and puts the GPIO pins of the Analog Subsystem General-Purpose IO block in a highimpedance state. The Analog Subsystem has two BOR functions that assert ARS when VDDIO or VDD18 dips below minimum voltage levels, or when VDD18 surges above the maximum operational voltage. The internal 1.8-V VREG must be enabled to activate the VDD18 BOR function (by pulling the VREG18EN pin low). When BOR (or POR) drives the ARS pin low, BOR (or POR) also resets the digital logic associated with analog functions, and puts the GPIO pins of the Analog Subsystem General-Purpose IO block in a highimpedance state. 2.9.2 Digital Subsystem Voltage Regulation and Monitoring The internal voltage monitoring features of the Digital Subsystem consist of the POR function that holds the device in reset state during power up, and the BOW (Brown-Out Warning) function that issues a nonmaskable interrupt (NMI) to warn the device before impending power loss on the VDD12 rail. The NMI allows software to safely shut down the device and for the reset of the system before power falls into regions outside of specification, and potentially causing unexpected or erroneous system behavior. 2.9.2.1 Digital Subsystem’s Internal 1.2-V VREG The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic associated with the processors, memory, and peripherals of the Digital Subsystem. When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided externally; however, a 492-nF capacitor is required for each VDD12 pin to stabilize the internally generated voltages. These load capacitors are not required if the internal 1.2-V VREG is disabled and the 1.2 V is provided from an external supply. Note that while removing the need for an external power supply, enabling the internal VREG will increase the VDDIO power consumption. 2.9.2.2 Digital Subsystem’s Voltage Monitoring The Voltage Monitoring Block of the Digital Subsystem consists of POR functions and a BOW function. POR functions hold the device in reset during power up, until power stabilizes and voltage levels reach operational range. Once the device is properly powered up, the BOW function searches for dips and spikes on the 1.2-V rail, and asserts VREGWARN NMI when voltage levels venture outside of minimum or maximum values. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 45 PRODUCT PREVIEW 2.9.1.2.2 Analog Subsystem’s BOR F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.9.2.2.1 Digital Subsystem’s POR POR keeps the XRS reset signal asserted during device power up, and deasserts the signal only when the 1.2-V and 3.3-V power rails reach operational range. While in most applications, the POR-generated reset has a long enough duration to also reset other system ICs, some applications may require a longerlasting system reset pulse. In these cases, the XRS reset pin (which is open-drain) can also be driven from outside in, to match the time the device is held in reset state with the rest of the system. When POR drives the XRS pin low, POR also resets all digital logic of the Digital Subsystem, and puts the GPIO pins of the Digital Subsystem General-Purpose IO block in a high-impendance state. In addition to the POR reset, the Digital Subsystem’s Resets block also receives reset inputs from NVIC, the Cortex™-M3 Watchdogs (0, 1), and from the Cortex™-M3 NMI Watchdog. The resulting reset output signal is then fed back to the XRS pin after being ANDed with the POR reset (see Figure 2-6). On a related note, only the Master Subsystem comes out of reset state immediately following the device power up. The Control and Analog Subsystems continue to be held in reset until the Master Processor (Cortex™-M3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF Register (see Figure 2-6). 2.9.2.2.2 Digital Subsystem’s BOW PRODUCT PREVIEW The Digital Subsystem has a BOW function that can send a VREGWARN NMI (Non-Maskable Interrupt) to the Cortex™-M3 NMI block when VDD12 starts drifting outside of operational range. The NMI block simultaneously sends the M3NMIINT to the Cortex™-M3 NVIC/CPU and starts the counter inside the Cortex™-M3 NMI Watchdog. While the NMI Watchdog is counting down, the Cortex™-M3 CPU can attempt to safely shut down the device and the system. When the count reaches "0", the NMI Watchdog asserts a reset input to the Resets block, forcing the entire Digital Subsystem to go into a reset state, including the CRESCNF register, which by default also resets the Analog and Control Subsystems. By default, the BOW function is disabled after reset. 2.9.3 Connecting ARS and XRS Pins In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external means—such as through a signal trace on a PCB board. Tying the ARS and XRS pins enables the internal BOR functions of the Analog Subsystem to also reset the Digital Subsystem during internally detected power brown-out conditions. Tying the ARS and XRS pins also ensures that other reset sources will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where the reset condition occurs. 46 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.10 Input Clocks and PLLs Concerto devices have multiple input clock pins from which all internal clocks and the output clock are derived. Figure 2-7 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 and XCLKIN. CONCERTO DEVICE CONCERTO DEVICE X1 vssosc X2 X1 vssosc X2 RESONATOR CRYSTAL C L2 C L1 CONCERTO DEVICE CONCERTO DEVICE X1 3.3V vssosc X2 NC NC XCLKIN 3.3V CLK VDD PRODUCT PREVIEW RD OUT CLK VDD OUT GND GND 3.3V OSCILLATOR 3.3V OSCILLATOR Figure 2-7. Connecting Input Clocks to a Concerto Device 2.10.1 Internal Oscillator (Zero-Pin) Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency clocks: 10MHZCLK and 32MHZCLK. These clocks are not configurable by the user. They are used inside the Master Subsystem to implement low-power modes. The 10MHZCLK is also used by the Missing Clock Detect circuit. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 47 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC) The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used (version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin VSSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors connected to the two crystal terminals as shown in Figure 2-7. 2.10.3 External Oscillators (Pins X1 and XCLKIN) Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 2-7 shows how to connect external oscillators to the X1 and XCLKIN terminals. When connecting an external oscillator, use good design practices to minimize EMI as well as clock jitter induced by external noise sources. Minimize the loop area formed between the forward current path (from the oscillator OUT terminal to the MCU X1 or XCLKIN terminal) and the return path (from the MCU VSS terminal to the oscillator GND terminal). PRODUCT PREVIEW Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer. Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the electromagnetic fields created by the two opposite currents cancel each other out as much as possible, thus reducing parasitic inductances that radiate EMI. 2.10.4 Main PLL The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. The output clock from the Main PLL must be between 110 MHz and 550 MHz. The PLL output clock is then divided by 2 before entering a mux that selects between this clock and the PLL input clock – OSCCLK (used in PLL bypass mode). The PLL bypass mode is selected by setting the SPLLIMULT field of the SYSPLLMULT register to 0. The output clock from the mux next enters a divider controlled by the SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK. Figure 2-8 shows the Main PLL function and configuration examples. Table 2-19 to Table 2-22 list the integer multiplier configuration values. 48 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 SYSPLLMULT REG SPLLIMULT SYSPLLCTL REG SPLLFMULT SPLLEN (2) SYSDIVSEL REG SPLLCLKEN OSCCLK 0 2 /1 /2 /4 /8 MAIN PLL PIN X1 INTEGER MULTIPLIER MAIN OSC FRACTIONAL MULTIPLIER PLLOUT (1) OSCCLK 0000000 : 0000001 : 0000010 : 0000011 : . . . x x x x 1 1 2 3 00: NOT USED 01: x 0.25 10: x 0.50 11: x 0.75 /2 PLLSYSCLK PRODUCT PREVIEW 7 SYSDIVSEL (1:0) = 00 ( /1 ) 1 OUPUT OF MAIN PLL IS ALWAYS DIVIDED BY 2 1111101: x 125 1111110: x 126 1111111: x 127 (1) OUPUT OF THE MAIN PLL MUST RANGE BETWEEN 110- 550 MHz (2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF EXAMPLE 1: X1 = 100 MHZ SPLLIMULT = 0000000 ( BYPASS PLL) EXAMPLE 2: X1 = 10 MHz SPLLIMULT = 0010100 ( x 20 ) SPLLFM ULT = 00 ( NOT USED) N/A PLLSYSCLK = [ ( 10 x 20) EXAMPLE 3: X1 = 20 MHz SPLLIMULT = 0111100 ( x 60 ) SPLLF MULT = 01 ( x 0.25 ) PLLSYSCLK = [ ( 20 x 60 x 0.25 ) / 2 ] / 1 = 150 MHz PLLSYSCLK = 100 MHz / 2 ] / 1 = 100 MHz Figure 2-8. Main PLL Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 49 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-19. Main PLL Integer Multiplier Configuration (Bypass PLL to x 31) PRODUCT PREVIEW 50 SPLLIMULT(6:0) MULT VALUE 0000000 b Bypass PLL 0000001 b x1 0000010 b x2 0000011 b x3 0000100 b x4 0000101 b x5 0000110 b x6 0000111 b x7 0001000 b x8 0001001 b x9 0001010 b x 10 0001011 b x 11 0001100 b x 12 0001101 b x 13 0001110 b x 14 0001111 b x 15 0010000 b x 16 0010001 b x 17 0010010 b x 18 0010011 b x 19 0010100 b x 20 0010101 b x 21 0010110 b x 22 0010111 b x 23 0011000 b x 24 0011001 b x 25 0011010 b x 26 0011011 b x 27 0011100 b x 28 0011101 b x 29 0011110 b x 30 0011111 b x 31 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 SPLLIMULT(6:0) MULT VALUE 0100000 b x 32 0100001 b x 33 0100010 b x 34 0100011 b x 35 0100100 b x 36 0100101 b x 37 0100110 b x 38 0100111 b x 39 0101000 b x 40 0101001 b x 41 0101010 b x 42 0101011 b x 43 0101100 b x 44 0101101 b x 45 0101110 b x 46 0101111 b x 47 0110000 b x 48 0110001 b x 49 0110010 b x 50 0110011 b x 51 0110100 b x 52 0110101 b x 53 0110110 b x 54 0110111 b x 55 0111000 b x 56 0111001 b x 57 0111010 b x 58 0111011 b x 59 0111100 b x 60 0111101 b x 61 0111110 b x 62 0111111 b x 63 PRODUCT PREVIEW Table 2-20. Main PLL Integer Multiplier Configuration (x 32 to x 63) Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 51 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-21. Main PLL Integer Multiplier Configuration (x 64 to x 95) PRODUCT PREVIEW 52 SPLLIMULT(6:0) MULT VALUE 1000000 b x 64 1000001 b x 65 1000010 b x 66 1000011 b x 67 1000100 b x 68 1000101 b x 69 1000110 b x 70 1000111 b x 71 1001000 b x 72 1001001 b x 73 1001010 b x 74 1001011 b x 75 1001100 b x 76 1001101 b x 77 1001110 b x 78 1001111 b x 79 1010000 b x 80 1010001 b x 81 1010010 b x 82 1010011 b x 83 1010100 b x 84 1010101 b x 85 1010110 b x 86 1010111 b x 87 1011000 b x 88 1011001 b x 89 1011010 b x 90 1011011 b x 91 1011100 b x 92 1011101 b x 93 1011110 b x 94 1011111 b x 95 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 SPLLIMULT(6:0) MULT VALUE 1100000 b x 96 1100001 b x 97 1100010 b x 98 1100011 b x 99 1100100 b x 100 1100101 b x 101 1100110 b x 102 1100111 b x 103 1101000 b x 104 1101001 b x 105 1101010 b x 106 1101011 b x 107 1101100 b x 108 1101101 b x 109 1101110 b x 110 1101111 b x 111 1110000 b x 112 1110001 b x 113 1110010 b x 114 1110011 b x 115 1110100 b x 116 1110101 b x 117 1110110 b x 118 1110111 b x 119 1111000 b x 120 1111001 b x 121 1111010 b x 122 1111011 b x 123 1111100 b x 124 1111101 b x 125 1111110 b x 126 1111111 b x 127 PRODUCT PREVIEW Table 2-22. Main PLL Integer Multiplier Configuration (x 96 to x 127) 2.10.5 USB PLL The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the internal OSCCLK (originating from the external crystal or oscillator via the X1/X2 pins). An input mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 2-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. The output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider). Figure 2-9 shows the USB PLL function and configuration examples. Table 2-23 and Table 2-24 list the integer multiplier configuration values. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 53 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com UPLLMULT REG UPLLCLKSRC UPLLIMULT UPLLCTL REG UPLLFMULT UPLLEN (2) UPLLCLKEN 0 6 2 PRODUCT PREVIEW PIN X1 USB PLL MAIN OSC OSCCLK 0 USBPLLCLK INTEGER MULTIPLIER FRACTIONAL MULTIPLIER PLLOUT (1) PLLINP XCLKIN 000000 : 000001 : 000010 : 000011 : . . . 1 PIN XCLKIN x x x x 1 1 2 3 00: NOT USED 01: x 0.25 10: x 0.50 11: x 0.75 /4 1 OUPUT OF THE USB PLL IS ALWAYS DIVIDED BY 4 111101: x 61 111110: x 62 111111: x 63 (1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLCLK IS 60MHZ ) (2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF N/A EXAMPLE 1: X1 OR XCLKIN = 60 MHZ UPLLIMULT = 000000 ( BYPASS PLL) PLLSYSCLK = 60 MHz EXAMPLE 2: X1 OR XCLKIN = 10 MHz UPLLIMULT = 011000 ( x 24 ) UPLLFMULT = 00 ( NOT USED) PLLSYSCLK = ( 10 x 24) EXAMPLE 3: X1 OR XCLKIN = 30 MHz UPLLIMULT = 010000 ( x 16 ) UPLLFMULT = 10 ( x 0.50) PLLSYSCLK = ( 30 x 16 x 0.50 ) / 4 = 60 MHz / 4 = 60 MHz Figure 2-9. USB PLL 54 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 SPLLIMULT(5:0) MULT VALUE 000000 b Bypass PLL 000001 b x1 000010 b x2 000011 b x3 000100 b x4 000101 b x5 000110 b x6 000111 b x7 001000 b x8 001001 b x9 001010 b x 10 001011 b x 11 001100 b x 12 001101 b x 13 001110 b x 14 001111 b x 15 010000 b x 16 010001 b x 17 010010 b x 18 010011 b x 19 010100 b x 20 010101 b x 21 010110 b x 22 010111 b x 23 011000 b x 24 011001 b x 25 011010 b x 26 011011 b x 27 011100 b x 28 011101 b x 29 011110 b x 30 011111 b x 31 PRODUCT PREVIEW Table 2-23. USB PLL Integer Multiplier Configuration (Bypass PLL to x 31) Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 55 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-24. USB PLL Integer Multiplier Configuration (x 32 to x 63) PRODUCT PREVIEW 56 SPLLIMULT(5:0) MULT VALUE 100000 b x 32 100001 b x 33 100010 b x 34 100011 b x 35 100100 b x 36 100101 b x 37 100110 b x 38 100111 b x 39 101000 b x 40 101001 b x 41 101010 b x 42 101011 b x 43 101100 b x 44 101101 b x 45 101110 b x 46 101111 b x 47 110000 b x 48 110001 b x 49 110010 b x 50 110011 b x 51 110100 b x 52 110101 b x 53 110110 b x 54 110111 b x 55 111000 b x 56 111001 b x 57 111010 b x 58 111011 b x 59 111100 b x 60 111101 b x 61 111110 b x 62 111111 b x 63 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.11 Master Subsystem Clocking The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divideddown output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register. There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The 10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this signal can trip the ePWM peripherals. The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex™-M3 Subsystem as possible sources for the Deep Sleep Clock. The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 2-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals. Figure 2-10 shows the Cortex™-M3 clocks and the Master Subsystem low-power modes. Table 2-25. Master Subsystem Low-Power Modes Cortex™-M3 State of Low-Power Cortex™-M3 Mode CPU Clock to Cortex™-M3 Peripherals Register Used to Gate Clocks to Cortex™M3 Peripherals Main PLL USB PLL Clock to C28x Clock to Shared Resources Clock to Analog Subsystem Run Active M3SSCLK (1) RCGC On On PLLSYSCLK (2) PLLSYSCLK (2) ASYSCLK (3) Sleep Stopped M3SSCLK (1) RCGC or SCGC (4) On On PLLSYSCLK (2) PLLSYSCLK (2) ASYSCLK (3) Deep Sleep Stopped M3DSDIVCLK (5) RCGC or DCGC (4) Off Off Off Off Off (1) (2) (3) (4) (5) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes 10MHZCLK divided-down per the M3SSDIVSEL register. PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK. Depends on the ACG bit of the RCC register. 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL register (source determined inside the DSLPCLKCFG register). 2.11.1 Cortex™-M3 Run Mode In Run Mode, the Cortex™-M3 processor, memory, and most of the peripherals are clocked by the M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is accomplished via corresponding peripheral configuration registers. Clock gating for individual peripherals is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to peripherals that are enabled in a corresponding DC (Device Configuration) register. Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex™-M3 CPU and forces the Cortex™-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of the SLEEPDEEP bit of the Cortex™-M3 SYSCTRL register. To come out of a low-power mode, any properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex™-M3 processor/subsystem to Run Mode. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 57 PRODUCT PREVIEW There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. Cortex™-M3 can regain write ownership of these registers through the MCLKREQUEST register. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com REGISTER ACCESS M3 CPU INTR ASSERT ANY INTERRUPT TO EXIT SLEEP OR DEEP SLEEP NVIC SELECTS TYPE OF WAKEUP execution of WFI or WFE instr activates low power modes REGISTER ACCESS SLEEPONEXIT FCLK HCLK M3SSCLK PERIPH LOGIC WDOG 0 M3CLKENBx M3SSCLK M3SSCLK SYSCTRL REG M3SSCLK SELECTS BETWEEN SLEEP AND DEEP SLEEP MODES RCC REG uCRC ACG OSCCLK SLEEPDEEP ENABLE CLOCK MODE ENTER A LOW POWER MODE PERIPH LOGIC CLOCKS (Auto Clock Gate) NMI WDOG WDOG 1 M3SSCLK OSCCLK CAN 1,2 XCLKIN M3RUN PRODUCT PREVIEW GP TIMER (4) PERIPHERAL CLOCK ENABLES SSI (4) RCGC REG ( CLOCK GATING – RUN ) SCGS REG ( CLOCK GATING – SLEEP ) DCGC REG ( CLOCK GATING – DEEP SLEEP ) M3CLKENBx UART (5) M3SLEEP USB + PHY (OTG) M3DEEPSLEEP USBPLLCLK M3DEEPSLEEP DC REG DSLPCLKCFG REG ( GLOBAL PERIPHERAL ENABLES ) DSOSCSRC I2C (2) PLL DIS M3SSDIVSEL REG DSDIVOVRIDE USB PLL OSCCLK M3SSDIVSEL XCLKIN 32KHZCLK /1 /2 … /16 10MHZCLK EMAC OSCCLK M3DSDIVCLK 1 /1 /2 /4 M3SSCLK 0 OSCCLK EPI XCLKIN GPIO_MUX1 MCLKREQUEST REG uDMA SYSDIVSEL REG SYSDIVSEL SYSPLLSTAT REG 32KHZCLK 10MHZCLK OSCCLK IPC SYSPLLMULT REG X2 SYSPLLCTL REG MAIN OSC X1 INTERNAL OSC MISSING CLK DETECT PLL DIS MAIN PLL 0 /2 10MHZCLK M3 NMI CLOCKFAIL M3SSCLK OFF OSCCLK /1 /2 /4 /8 1 0 CLOCKFAIL MSG RAMS 1 CLOCKFAIL 10MHZCLK SHARED RAMS PLLSYSCLK CLPMSTAT REG SHARED RESOURCES OSCCLK CONTROL SUBSYSTEM Figure 2-10. Cortex™-M3 Clocks and Low-Power Modes 58 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.11.2 Cortex™-M3 Sleep Mode In Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking, and thus the code is no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clockgating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode. Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Sleep Mode. When the Sleeponexit bit is 0, the processor wakes up permanently (for the ISR and thereafter). In Deep Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking and thus the code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If 32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates OSCCLK) is turned off. The Cortex™-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is already in the Standby mode. Typically, just before entering the Standby mode, the C28x will record in the CLPMSTAT that it is about to do so. The Cortex™-M3 processor can read the CLPMSTAT register to check if the C28x is in Standby mode, and only then should the Cortex™-M3 processor go into Deep Sleep. The reason for the Cortex™-M3 processor to confirm that the C28x is in Standby mode before the Cortex™-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to C28x and its peripherals, and if this clock shutdown is not expected by the C28x, unintended consequences could result for some of the C28x control peripherals. Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep Mode depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to Deep Sleep Mode. When the Sleeponexit bit is 0, the processor wakes up permanently (for the ISR and thereafter). Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 59 PRODUCT PREVIEW 2.11.3 Cortex™-M3 Deep Sleep Mode F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.12 Control Subsystem Clocking The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1 external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. The Cortex™-M3 can regain write ownership of these registers through the MCLKREQUEST register. Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is done via the CPCLKCR0,2,3 registers. The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by OSCCLK or 10MHZCLK (see Figure 2-11). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and PIE. The Control Subsystem operates in one of three modes: Normal Mode, Idle Mode, or Standby Mode. Table 2-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and peripherals. Figure 2-11 shows the Control Subsystem clocks and low-power modes. Table 2-26. Control Subsystem Low-Power Modes (1) PRODUCT PREVIEW State of C28x CPU C28CPUCLK (2) C28SYSCLK (3) Registers Used to Gate Clocks to C28x Peripherals Normal Active On On CPCLKCR0,1,3 Idle Stopped Off On CPCLKCR0,1,3 Standby Stopped Off Off N/A C28x Low-Power Mode (1) (2) (3) The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem enters the Deep Sleep mode. C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE. C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals. 2.12.1 C28x Normal Mode In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK, OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals; and the HISPCP register can be programmed to provide a dedicated clock (C28HSPCLK) to stretch three outputs from ePWM peripherals. Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into Idle mode or Standby Mode. 2.12.2 C28x Idle Mode In Idle Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The C28SYSCLK continues to run. Exit from Idle Mode is accomplished by any enabled interrupt or the C28NMIINT (C28x non-maskable interrupt). Upon exit from Idle Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the Idle Mode. 60 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 C28x NMI MASTER SUBSYSTEM CLOCKFAIL OSCCLK SYSDIVSEL REG CLPMSTAT REG OFF /1 /2 /4 /8 SYSPLLSTAT REG SOCBO SOCAO SYNCO SYSPLLMULT REG HISPCP REG SYSPLLCTL REG HSPCLK CCLKREQUEST REG PLLSYSCLK CXCLK REG XPLLCLKCFG REG XCLKOUTDIV /4 /2 /1 OFF C28SYSCLK LOSPCP REG XPLLCLKOUTDIV OFF CLKOFF REG EPWM (9) ‘0’ LSPCLK C28SYSCLK XCLKOUT /4 GPIO_MUX1 (NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4) SCI SPI PIEINTRS (1) I2C MTOCIPC(1) TIMER 2 STANDBY MODE C28CLKIN C28x CPU EXIT STANDBY MODE C28 DMA execution of IDLE instruction activates the IDLES signal ENTER STANDBY MODE IDLES EXIT IDLE MODE ENTER IDLE MODE Requests To Wake From IDLE Mode Requests To Wake From STANDBY Mode McBSP 0 1 2 3 TINT2 /1 /2 /4 … /14 C28LSPCLK M3SSCLK ASYSCLK PF2_GPIO34 /1 /2 /4 … /14 C28HSPCLK SRXRST CLKDIV 10MHZCLK PULSE STRETCH ACIBRST ANALOG SUBSYSTEM ASYSRST CCLKCTL REG PRODUCT PREVIEW GPIO_MUX1 TINT 1 TIMER 1 TIMER 0 C28 XINT(3) PIEINTRS (12:1) C28x PIE C28NMIINT C28 FPU/VCU EQEP (3) C28x PIE LPM(1) LPM(0) CLPMCR0 REG ECAP (6) C28SYSCLK C28CPUCLK C28SYSCLK LPMWAKE CPCLKCR3 REG GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) LPMSEL1 REG LPMSEL2 REG C28SYSCLK OSCCLK GPIO_MUX1 CTMR2CLK PRESCALE IPC C28x NMI 10MHZCLK /1 /2 /4 /8 /16 TMR2CLK C28CLKENBx TMR2CLKSRCSEL SELECT ONE OF 62 GPIs CPCLKCR1 REG CPCLKCR0 REG CLKCTL REG SELECT QUALIFICATION LPM WAKEUP Figure 2-11. C28x Clocks and Low-Power Modes Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 61 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.12.3 C28x Standby Mode In Standby Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and C28SYSCLK are turned off. Exit from Standby Mode is accomplished by 1 of 62 GPIOs from the GPIO_MUX1 block, or MTOCIPCINT1 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the CPCLKCR0 register) before propagating into the wake request logic. Cortex™-M3 should use CLPMSTAT register bits to tell the C28x to go into Standby mode before going into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control software is not expecting this clock to shut off. When the device is in Deep Sleep/Standby mode, wake-up should happen only from the Master Subsystem, since all C28x clocks are off (C28CLKIN, C28CPUCLK, C28SYSCLK), thus preventing the C28x from waking up first. Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE instruction that originally triggered the Standby Mode. NOTE PRODUCT PREVIEW For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 3-1 are not available). 62 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.13 Analog Subsystem Clocking The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of ASYSCLK, it is possible for the Cortex™-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem. The ASYSCLK is shut down when the Cortex™-M3 processor enters the Deep Sleep mode. 2.14 Shared Resources Clocking The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK. Although EPI is a shared peripheral, it is physically located inside the Cortex™-M3 Subsystem; therefore, EPI is clocked by M3SSCLK. The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to enable other chip components to take corrective or recovery action from such event (see Figure 2-12). The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator) so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex™-M3 NMI circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK. Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a corresponding CPU, while starting the associated NMI watchdog counter. If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in the device reset. If the software does react to the NMI, the software can prevent the impending reset by disabling the watchdog timers, and then the software can initiate necessary corrective action such as switching over to an alternative clock source (if available) or the software can initiate a shut-down procedure for the system. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 63 PRODUCT PREVIEW 2.15 Loss of Input Clock (NMI Watchdog Function) F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 X2 PIN www.ti.com 1 MAIN OSC X1 PIN OSCCLK MAIN PLL 4 ADDITIONAL CLOCK CONTROL LOGIC PLLSYSCLK MISSING CLK DETECT 10MHZCLK C28CLKIN M3SSCLK 3 2 M3 CPU INTERNAL OSC 7 5 PRODUCT PREVIEW 3 CLOCKFAIL M3 NMI CLOCKFAIL RESETS 3 C28x NMI 1 2 CLOCKFAIL SIGNAL BECOMES ACTIVE 3 CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX 4 PLLSYSCLK SWITCHES TO THE 10MHZCLK 5 CPUS RESPOND TO NMIS AND THE WATCHDOGS START COUNTING 6 SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION 7 IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT M3 NMI WDOG OTHER NMI SOURCES TYPICAL ACTIVITY FOLLOWING A MISSING CLOCK DETECTION : THE INPUT CLOCK IS DISRUPTED M3NMI C28NMI C28x NMI WDOG CLOCKFAIL 5 3 7 C28x CPU EPWM 6 EPWM_A EPWM_B C28CLKIN GPIO_MUX1 PIN PIN Figure 2-12. Missing Clock Detection 64 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.16 GPIOs and Other Pins Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished through several I/O muxes where a specific physical pin can be assigned to selected signals of internal peripherals. Most of the I/O pins of the Concerto™ MCU can also be configured as programmable GPIOs. Exceptions include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in 2 programmable blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 2-13 shows the GPIOs and other pins. Sixty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all Cortex™-M3 peripherals, to all C28x peripherals, to 66 General-Purpose Inputs, to 66 GeneralPurpose Outputs, or a mixture of all of the above. Sixty-two pins of GPIO_MUX1 (GPIO0–GPIO63 minus GPIO39 and GPIO44) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the C28x PIE, and the C28x Standby Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex™-M3 peripherals (and not to C28x peripherals). Figure 2-14 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the configuration registers are programmed in the blue and green blocks (see Figure 2-15 for the configuration registers). Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to the 66 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[A:J] IRQ signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The nine GPIO[A:J] IRQ signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can be selected to wake up the C28x CPU from Low-Power Mode. Sixty-six (66) GPI signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see Figure 2-15). The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets (A–J), with each set being responsible for eight pins. These nine sets of registers are programmable by the Cortex™-M3 CPU via the AHB bus or the APB bus. The configuration register for the muxing of Control Subsystem peripherals are organized in three sets (A–C), with each set being responsible for up to 32 pins. These registers are programmable by the C28x CPU via the C28x CPU bus. Figure 2-15 shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one GPIO pin as driven by these registers. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 65 PRODUCT PREVIEW 2.16.1 GPIO_MUX1 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 10 AIO_MUX1 MII TX1 MII TX0 MII TX2 MII TXEN MII TX3 MII MDC MII PHYRSTN MII TXER MII MDIO MII PHYINTRN MII COL MII CRS MII TXCK MII RXCK MII RXDV MII RXER MII RX0 MII RX2 MII RX1 UART (5) NVIC CAN (2) SSI (4) I2C (2) I2C (1:0) SCL I2C (1:0) SDA SSI (3:0) RX SSI (3:0) TX SSI (3:0) CLK SSI (3:0) FSS XCLKIN GPIO CAN (1:0) TX CAN (1:0) RX U (4:0) RX U (4:0) TX U1CTS U1DCD U1RTS U1DSR GPIO_MUX1 U1DTR GPIO GPIO_MUX2 VDDA (3.3V) U1RI GPIO (H:A) IRQ M3EXTNMI MUX 66 SCLA SDAA SPISOMI SPISIMO SPICLK SPISTE EQEP (3:1) I EQEP (3:1) B EQEP (3:1) S EQEP (3:1) A ECAP (6:1) GPTRIP (12:7) GPTRIP (6:4) LPM WAKEUP GPTRIP (12:1) VSSA (0V) EPWM (9:1) B MUX COMPOUT (6:1) 66 GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) EPWM (9:1) A PRODUCT PREVIEW 8 MII RX3 EMAC ADC 1 6 COMPARATOR + DAC UNITS 8 USB0OFLT COMPB2 USB0EPEN USB M3 NMI COMPA1 COMPA2 COMPA3 USB0VBUS USB PLL EPI USB0ID ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 USB0DP ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 XCLKIN 4 USB0DM MUX EPI0S (41:0) GPIO LPMWAKE COMPA4 COMPA5 COMPA6 COMPB5 C28X CPU ADC 2 EPWM (9) ECAP (6) XINT (3) EQEP (3) SPI I2C McBSP VREGS DEBUG RESETS CLOCKS SCIRXDA SCITXDA MFSXA MDXA MDRA MCLXA MCLRA M3EXTNMI LPMWAKE XCLKIN X1 X2 XRS ARS 10 JTAG (7) AIO_MUX2 VREG18EN MUX 4 VREG12EN GPIO NMI MFSRA ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 XCLKOUT ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 SCI Figure 2-13. GPIOs and Other Pins 66 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 M3 AHB BUS BUS BRIDGE M3 APB BUS XCLKIN XCLKIN USB CAN (2) UART (5) EMAC SSI (4) I2C (2) M3 uDMA I2C (1:0) SCL INTERRUPTS M3 PERIPHERAL SIGNAL ROUTING M3 MUX A M3 MUX B 8 M3 MUX D 8 M3 MUX E 8 M3 MUX F 8 M3 CPU I2C (1:0) SDA SSI (3:0) TX SSI (3:0) RX SSI (3:0) FSS SSI (3:0) CLK CAN (1:0) TX CAN (1:0) RX U (4:0) TX U1CTS U (4:0) RX U1DSR U1DCD U1RTS U1DTR U1RI MII TX1 MII TX0 MII TX3 MII TX2 MII MDC MII TXEN MII TXER MII PHYRSTN MII MDIO MII PHYINTRN MII CRS MII COL MII TXCK MII RXCK MII RXDV MII RX0 MII RXER MII RX2 MII RX1 MII RX3 EPI0S (41:0) USB0EPEN USB0OFLT USB0VBUS M3 EXT NMI USB0ID USB0DP USB0DM M3 NMI EPI NVIC M3 MUX H M3 MUX G 7 7 M3 MUX J 8 PRODUCT PREVIEW USB PLL M3 MUX C 8 4 XCLKIN 4 GPTRIP (12:1) GPIO (H:A) IRQ PIN - LEVEL MUX 66 (TERMINALS GPIO 39 AND GPIO 44 ARE NOT PINNED OUT ON THIS DEVICE) 32 30 C28 MUX A C28 MUX B C28 MUX C GPI (63:0) MINUS GPI 39 AND GPI 44 (NOT PINNED OUT) LPM WAKEUP C28 PERIPHERAL SIGNAL ROUTING GPTRIP (12:7) EPWM (9:1) B C28 CPU BUS ECAP (6) EPWM (9:1) A EQEP (3) ECAP (6:1) EQEP (3:1) I EQEP (3:1) S EQEP (3:1) B I2C EQEP (3:1) A SCLA SPI SDAA SPISIMO SPISTE SPISOMI SPICLK SCI SCITXDA SCIRXDA MDXA MFSXA MDRA MCLXA MCLRA MFSRA McBSP LPM WAKE EPWM (9) GPTRIP (12:1) XINT (3) C28x DMA C28x CPU GPTRIP (6:4) C28 DMA BUS Figure 2-14. GPIO_MUX1 Block Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 67 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com PERIPHERALS 1-15 REPRESENT A SET OF UP TO 15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN BLUE REGISTER SET A REPRESENTS 8 OF 66 GPIOs. REMAINING 58 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B, C, D, E, F, I, J, H TO/FROM M3 PERIPH 1-11 TO/FROM M3 PERIPH 12-15 GPIO63 ONLY PRIMARY GPIOPCTL REG GREY LOGIC IS SPECIFIC TO ONE DEVICE I/O PIN GPIO (A) IRQ XCLKIN ALT M3 REG SET A M3 REG SET A M3 REG SET A GPIOIS REG GPIOAMSEL REG GPIOIBE REG PRIMARY AT RESET GPIOAPSEL REG A-H INTR REQUESTS TO M3 M3 CLOCKS GPIOIEV REG GPIOIM REG GPIORIS REG ENB GPIOPUR REG PULL-UP DISABLED ON RESET GPIOODR REG GPIOCSEL REG GPIODEN REG GPIOAFSEL REG GPIOLOCK REG GPIOCR REG M3 REG SET A (USB ANALOG SIGNALS) M3 REG SET A GPIOMIS REG GPIODATA REG GPIOICR REG GPIODIR REG PRODUCT PREVIEW M3 REG SET A NORMAL AT RESET ‘1’ SELECT M3 AT RESET I/O DISABLED AT RESET GPIO MODE AT RESET PULL UP INPUT ‘0’ (4 PINS ONLY) ANALOG USB SIGNALS ONE OF 66 GPIO_MUX1 PINS GPIOAMSEL REG OE OUTPUT DISABLED AFTER RESET (M3 GPIO) OUTPUT OPEN DRAIN LOGIC OE OE ‘1’ ASYNC INPUT ORANGE LOGIC SHOWS USB ANALOG FUNCTIONS (APPLIES TO 4 PINS ONLY) OE XRS SYNC INPUT SYNC GREEN REGISTER SET A SHOWN REPRESENTS 32 OF 66 GPIOs. THE REMAINING 34 GPIOs ARE CONTROLLED BY SIMILAR REGISTER SETS B AND C C28SYSCLK C28 REG SET A GPIO AT RESET GPACTRL REG QUAL (C28 GPIO) OUTPUTS C28 REG SET A 6 SAMPLES GPASET REG 3 SAMPLES GPASEL1 REG SEL(1:0) C28 REG SET A GPACLEAR REG GPASEL2 REG SYNC INPUT AT RESET GPATOGGLE REG GPADIR REG EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT GPADAT REG EACH I/O PIN HAS A DEDICATED PAIR OF BITS FOR MUX SELECT GPAMUX1 REG GPAMUX2 REG SEL(1:0) SEL(1:0) TO C28x CPU WAKE-UP FROM A LOW POWER MODE C28 REG SET A PERIPHERALS 1-3 REPRESENT A SET OF UP TO THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN FROM C28 PERIPH 1-3 GPI (63:0) MINUS GPI 39 AND GPI 64 INPUTS N/C AT RESET N/C TO C28 PERIPH 1-3 GPTRIP1SEL REG … GPTRIP (12:1) TO XINT, ECAP, EPWM GPTRIP12SEL REG Figure 2-15. GPIO_MUX1 Pin Mapping Through Register Set A 68 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 For each of the 8 pins in set A of the Cortex™-M3 GPIO registers, register GPIOPCTL selects between 1 of 11 possible primary Cortex™-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input takes the reverse path. See Table 2-27 and Table 2-28 for the mapping of Cortex™-M3 peripheral signals to GPIO_MUX1 pins. Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along the muxing chain towards a given pin. The input takes the reverse path. See Table 2-29 for the mapping of C28x peripheral signals to GPIO_MUX1 pins. In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital GPIO_MUX1 options as described above. PRODUCT PREVIEW Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always available at these modules where it can be selected through local registers. NOTE For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 3-1 are not available). Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 69 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (1) Device Pin Name M3 Primary Mode 1 M3 Primary Mode 2 M3 Primary Mode 3 M3 Primary Mode 4 M3 Primary Mode 5 M3 Primary Mode 6 M3 Primary Mode 7 – PA0_GPIO0 U0RX – – – – – – PA1_GPIO1 U0TX – – – – – – PA2_GPIO2 SSI0CLK – MMI_TXD2 – – – PA3_GPIO3 SSI0FSS – MMI_TXD1 – – PA4_GPIO4 SSI0RX – MMI_TXD0 – PA5_GPIO5 SSI0TX – – PA6_GPIO6 I2C1SCL – PA7_GPIO7 – PRODUCT PREVIEW Analog Mode (USB Pins) (1) (2) 70 M3 Primary Mode 8 M3 Primary Mode 9 M3 Primary Mode 10 M3 Primary Mode 11 – I2C1SCL U1RX – – – I2C1SDA U1TX – – – – – – – – – – – – – – – – CAN0RX – – – – – – MMI_RXDV – CAN0TX – – – – – – CCP1 MMI_RXCK – – CAN0RX – USB0EPEN U1CTS – – I2C1SDA CCP4 MMI_RXER – – CAN0TX CCP3 USB0PFLT U1DCD – – PB0_GPIO8 CCP0 – – – U1RX – – – – – – – PB1_GPIO9 CCP2 – – CCP1 U1TX – – – – – – – PB2_GPIO10 I2C0SCL – – CCP3 CCP0 – – USB0EPEN – – – – PB3_GPIO11 I2C0SDA – – – – – – USB0PFLT – – – – PB4_GPIO12 – – – U2RX CAN0RX – U1RX EPI0S23 – – – – PB5_GPIO13 – CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22 – – – – PB6_GPIO14 CCP1 CCP7 – – – CCP5 – EPI0S37 (2) – – – – PB7_GPIO15 – – – NMI – – MII_RXD1 EPI0S36 (2) – – – – PD0_GPIO16 PWM0 CAN0RX – U2RX U1RX CCP6 MII_RXDV – U1CTS – – – PD1_GPIO17 PWM1 CAN0TX – U2TX U1TX CCP7 MII_TXER – U1DCD CCP2 – – PD2_GPIO18 U1RX CCP6 – CCP5 – – – EPI0S20 – – – – PD3_GPIO19 U1TX CCP7 – CCP0 – – – EPI0S21 – – – – PD4_GPIO20 CCP0 CCP3 – MII_TXD3 – – – – U1RI EPI0S19 – – PD5_GPIO21 CCP2 CCP4 – MII_TXD2 – – – – U2RX EPI0S28 – – PD6_GPIO22 Fault0 – – MII_TXD1 – – – – U2TX EPI0S29 – – PD7_GPIO23 IDX0 – CCP1 MII_TXD0 – – – – U1DTR EPI0S30 – – PE0_GPIO24 PWM4 SSI1CLK CCP3 – – – – EPI0S8 USB0PFLT – – – PE1_GPIO25 PWM5 SSI1FSS – CCP2 CCP6 – – EPI0S9 – – – – PE2_GPIO26 CCP4 SSI1RX – – CCP2 – – EPI0S24 – – – – PE3_GPIO27 CCP1 SSI1TX – – CCP7 – – EPI0S25 – – – – PE4_GPIO28 CCP3 – – – U2TX CCP2 MII_RXD0 EPI0S34 (2) – – – – PE5_GPIO29 CCP5 – – – – – – EPI0S35 (2) – – – – PE6_GPIO30 – – – – – – – – U1CTS – – – PE7_GPIO31 – – – – – – – – U1DCD – – Blank fields represent Reserved functions. This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Analog Mode (USB Pins) Device Pin Name M3 Primary Mode 1 M3 Primary Mode 2 M3 Primary Mode 3 M3 Primary Mode 4 M3 Primary Mode 5 M3 Primary Mode 6 M3 Primary Mode 7 M3 Primary Mode 8 M3 Primary Mode 9 M3 Primary Mode 10 M3 Primary Mode 11 – PF0_GPIO32 CAN1RX – – MII_RXCK – – – – – PF1_GPIO33 CAN1TX – – MII_RXER – – – – U1DSR – – U1RTS CCP3 – PF2_GPIO34 – – MII_PHYINTR – – – – – (2) SSI1CLK – – (2) EPI0S32 – PF3_GPIO35 – – MII_MDC – – – – SSI1FSS – – – PF4_GPIO36 CCP0 – MII_MDIO – – – – EPI0S12 SSI1RX – – – PF5_GPIO37 CCP2 – MII_RXD3 – – – – EPI0S15 SSI1TX – – USB0VBUS PF6_GPIO38 CCP1 – MII_RXD2 – – – – EPI0S38(2) – U1RTS – – PF7_GPIO39 (no pin) – – – – – – – – – – – – PG0_GPIO40 U2RX – I2C1SCL – – – USB0EPEN EPI0S13 – – – – PG1_GPIO41 U2TX – I2C1SDA – – – – EPI0S14 – – – – – – – – – EPI0S33 (2) USB0DM PG2_GPIO42 – – MII_COL – – – – – PG3_GPIO43 – – MII_CRS – – – – – – PG4_GPIO44 (no pin) – – – – – – – – EPI0S39 – – – (2) USB0DP PG5_GPIO45 CCP5 – MII_TXEN – – – – EPI0S40 – U1DTR – USB0ID PG6_GPIO46 – – MII_TXCK – – – – EPI0S41(2) – U1RI – – PG7_GPIO47 – – MII_TXER – – – – CCP5 EPI0S31 – – – PH0_GPIO48 CCP6 – MII_PHYRST – – – – EPI0S6 – – – – PH1_GPIO49 CCP7 – – – – – – EPI0S7 – – – – PH2_GPIO50 – – – – – – – EPI0S1 MII_TXD3 – – – PH3_GPIO51 – – – USB0EPEN – – – EPI0S0 MII_TXD2 – – – PH4_GPIO52 – – – USB0PFLT – – – EPI0S10 MII_TXD1 – SSI1CLK – PH5_GPIO53 – – – – – – – EPI0S11 MII_TXD0 – SSI1FSS – PH6_GPIO54 – – – – – – – EPI0S26 MII_RXDV – SSI1RX – PH7_GPIO55 – – MII_RXCK – – – – EPI0S27 – – SSI1TX – PJ0_GPIO56 – – MII_RXER – – – – EPI0S16 – – I2C1SCL – PJ1_GPIO57 – – – – – – – EPI0S17 USB0PFLT – I2C1SDA – PJ2_GPIO58 – – – – – – – EPI0S18 CCP0 – – – PJ3_GPIO59 – – – – – – – EPI0S19 U1CTS CCP6 – – PJ4_GPIO60 – – – – – – – EPI0S28 U1DCD CCP4 – – PJ5_GPIO61 – – – – – – – EPI0S29 U1DSR CCP2 – – PJ6_GPIO62 – – – – – – – EPI0S30 U1RTS CCP1 – – PJ7_GPIO63/ XCLKIN – – – – – – – – U1DTR CCP0 – Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued) 71 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued) Device Pin Name M3 Primary Mode 1 M3 Primary Mode 2 M3 Primary Mode 3 M3 Primary Mode 4 M3 Primary Mode 5 M3 Primary Mode 6 M3 Primary Mode 7 M3 Primary Mode 8 M3 Primary Mode 9 M3 Primary Mode 10 M3 Primary Mode 11 – PC0_GPIO64 (no pin) – – – – – – – – – – – – PC1_GPIO65 (no pin) – – – – – – – – – – – – PC2_GPIO66 (no pin) – – – – – – – – – – – – PC3_GPIO67 (no pin) – – – – – – – – – – – – PC4_GPIO68 CCP5 – MII_TXD3 – CCP2 CCP4 – EPI0S2 CCP1 – – – PC5_GPIO69 CCP1 – – – CCP3 USB0EPEN – EPI0S3 – – – – PC6_GPIO70 CCP3 – – – U1RX CCP0 USB0PFLT EPI0S4 – – – – PC7_GPIO71 CCP4 – – CCP0 U1TX USB0PFLT – EPI0S5 – – – PRODUCT PREVIEW Analog Mode (USB Pins) 72 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 (1) (2) Analog Mode (USB Pins) Device Pin Name M3 Alternate Mode 12 M3 Alternate Mode 13 M3 Alternate Mode 14 M3 Alternate Mode 15 – PA0_GPIO0 – – – – – PA1_GPIO1 – – – SSI1FSS – PA2_GPIO2 – – U1CTS – – PA3_GPIO3 – – U1DCD SSI1CLK – PA4_GPIO4 – – U1DSR – – PA5_GPIO5 – – U1RTS – – PA6_GPIO6 MII_TXD3 – U1DTR – – PA7_GPIO7 MII_RXD1 – U1RI – – PB0_GPIO8 – SSI2TX CAN1TX U4TX – PB1_GPIO9 – SSI2RX – – – PB2_GPIO10 – SSI2CLK CAN1RX U4RX – PB3_GPIO11 – SSI2FSS U1RX – – PB4_GPIO12 – – CAN1TX SSI1TX – PB5_GPIO13 – – CAN1RX SSI1RX – PB6_GPIO14 MII_CRS I2C0SDA U1TX SSI1CLK – PB7_GPIO15 – I2C0SCL U1RX SSI1FSS – PD0_GPIO16 MII_RXD2 SSI0TX CAN1TX USB0EPEN – PD1_GPIO17 MII_COL SSI0RX CAN1RX USB0PFLT – PD2_GPIO18 – SSI0CLK U1TX CAN0RX – PD3_GPIO19 – SSI0FSS U1RX CAN0TX – PD4_GPIO20 – – U3TX CAN1TX – PD5_GPIO21 – – U3RX CAN1RX – PD6_GPIO22 – – I2C1SDA U1TX – PD7_GPIO23 – – I2C1SCL U1RX – PE0_GPIO24 – SSI3TX CAN0RX SSI1TX – PE1_GPIO25 – SSI3RX CAN0TX SSI1RX – PE2_GPIO26 – SSI3CLK U2RX SSI1CLK – PE3_GPIO27 – SSI3FSS U2TX EPI0S38 PRODUCT PREVIEW Table 2-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes) (1) SSI1FSS (2) – PE4_GPIO28 – U0RX – PE5_GPIO29 MII_TXER U0TX – USB0EPEN USB0PFLT – PE6_GPIO30 MII_MDIO CAN0RX – – – PE7_GPIO31 MII_RXD3 CAN0TX – – – PF0_GPIO32 – I2C0SDA TRACED2 – – PF1_GPIO33 – I2C0SCL TRACED3 – – PF2_GPIO34 – – TRACECLK XCLKOUT – PF3_GPIO35 – U0TX TRACED0 – – PF4_GPIO36 – U0RX – – – PF5_GPIO37 – – – MII_TXEN USB0VBUS PF6_GPIO38 – – – – – PF7_GPIO39 (no pin) – – – – Blank fields represent Reserved functions. This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 73 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued) PRODUCT PREVIEW 74 Analog Mode (USB Pins) Device Pin Name M3 Alternate Mode 12 M3 Alternate Mode 13 M3 Alternate Mode 14 M3 Alternate Mode 15 – PG0_GPIO40 MII_RXD2 U4RX – MII_TXCK – PG1_GPIO41 MII_RXD1 U4TX – MII_TXER USB0DM PG2_GPIO42 – – – – – PG3_GPIO43 MII_RXDV – TRACED1 – – PG4_GPIO44 (no pin) – – – – USB0DP PG5_GPIO45 – – – – USB0ID PG6_GPIO46 – – – – – PG7_GPIO47 – – – MII_CRS – PH0_GPIO48 – SSI3TX – MII_TXD3 – PH1_GPIO49 MII_RXD0 SSI3RX – MII_TXD2 – PH2_GPIO50 – SSI3CLK – MII_TXD1 – PH3_GPIO51 – SSI3FSS – MII_TXD0 – PH4_GPIO52 – U3TX – MII_COL – PH5_GPIO53 – U3RX – MII_PHYRST – PH6_GPIO54 MII_TXEN SSI0TX – MII_PHYINTR – PH7_GPIO55 MII_TXCK SSI0RX – MII_MDC – PJ0_GPIO56 – SSI0CLK – MII_MDIO – PJ1_GPIO57 MII_RXDV SSI0FSS – MII_RXD3 – PJ2_GPIO58 MII_RXCK SSI0CLK U0TX MII_RXD2 – PJ3_GPIO59 MII_MDC SSI0FSS U0RX MII_RXD1 – PJ4_GPIO60 MII_COL SSI1CLK – MII_RXD0 – PJ5_GPIO61 MII_CRS SSI1FSS – MII_RXDV – PJ6_GPIO62 MII_PHYINTR U2RX – MII_RXER – PJ7_GPIO63/ XCLKIN MII_PHYRST U2TX – MII_RXCK – PC0_GPIO64 (no pin) – – – – – PC1_GPIO65 (no pin) – – – – – PC2_GPIO66 (no pin) – – – – – PC3_GPIO67 (no pin) – – – – – PC4_GPIO68 – – – – – PC5_GPIO69 – – – – – PC6_GPIO70 – – – – – PC7_GPIO71 – – – – Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 (1) Analog Mode (USB Pins) Device Pin Name C28x Peripheral Mode 0 C28x Peripheral Mode 1 C28x Peripheral Mode 2 C28x Peripheral Mode 3 – PA0_GPIO0 GPIO0 EPWM1A – – – PA1_GPIO1 GPIO1 EPWM1B ECAP6 – – PA2_GPIO2 GPIO2 EPWM2A – – – PA3_GPIO3 GPIO3 EPWM2B ECAP5 – – PA4_GPIO4 GPIO4 EPWM3A – – – PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1 – PA6_GPIO6 GPIO6 EPWM4A – EPWMSYNCO – PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2 – PB0_GPIO8 GPIO8 EPWM5A – ADCSOCAO – PB1_GPIO9 GPIO9 EPWM5B – ECAP3 – PB2_GPIO10 GPIO10 EPWM6A – ADCSOCBO – PB3_GPIO11 GPIO11 EPWM6B – ECAP4 – PB4_GPIO12 GPIO12 EPWM7A – – – PB5_GPIO13 GPIO13 EPWM7B – – – PB6_GPIO14 GPIO14 EPWM8A – – – PB7_GPIO15 GPIO15 EPWM8B – – – PD0_GPIO16 GPIO16 SPISIMOA – – – PD1_GPIO17 GPIO17 SPISOMIA – – – PD2_GPIO18 GPIO18 SPICLKA – – – PD3_GPIO19 GPIO19 SPISTEA – – – PD4_GPIO20 GPIO20 EQEP1A MDXA – – PD5_GPIO21 GPIO21 EQEP1B MDRA – – PD6_GPIO22 GPIO22 EQEP1S MCLKXA – – PD7_GPIO23 GPIO23 EQEP1I MFSXA – – PE0_GPIO24 GPIO24 ECAP1 EQEP2A – – PE1_GPIO25 GPIO25 ECAP2 EQEP2B – – PE2_GPIO26 GPIO26 ECAP3 EQEP2I – – PE3_GPIO27 GPIO27 ECAP4 EQEP2S – – PE4_GPIO28 GPIO28 SCIRXDA – – – PE5_GPIO29 GPIO29 SCITXDA – – – PE6_GPIO30 GPIO30 – – EPWM9A – PE7_GPIO31 GPIO31 – – EPWM9B – PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO – PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO – PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT – PF3_GPIO35 GPIO35 SCITXDA – – – PF4_GPIO36 GPIO36 SCIRXDA – – – PF5_GPIO37 GPIO37 ECAP2 – – USB0VBUS PF6_GPIO38 GPIO38 – – – – PF7_GPIO39 (no pin) – – – – PRODUCT PREVIEW Table 2-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes) (1) Blank fields represent Reserved functions. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 75 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 2-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1) (continued) PRODUCT PREVIEW 76 Analog Mode (USB Pins) Device Pin Name C28x Peripheral Mode 0 C28x Peripheral Mode 1 C28x Peripheral Mode 2 C28x Peripheral Mode 3 – PG0_GPIO40 GPIO40 – – – – PG1_GPIO41 GPIO41 – – – USB0DM PG2_GPIO42 GPIO42 – – – – PG3_GPIO43 GPIO43 – – – – PG4_GPIO44 (no pin) – – – – USB0DP PG5_GPIO45 GPIO45 – – – USB0ID PG6_GPIO46 GPIO46 – – – – PG7_GPIO47 GPIO47 – – – – PH0_GPIO48 GPIO48 ECAP5 – – – PH1_GPIO49 GPIO49 ECAP6 – – – PH2_GPIO50 GPIO50 EQEP1A – – – PH3_GPIO51 GPIO51 EQEP1B – – – PH4_GPIO52 GPIO52 EQEP1S – – – PH5_GPIO53 GPIO53 EQEP1I – – – PH6_GPIO54 GPIO54 SPISIMOA – EQEP3A – PH7_GPIO55 GPIO55 SPISOMIA – EQEP3B – PJ0_GPIO56 GPIO56 SPICLKA – EQEP3S – PJ1_GPIO57 GPIO57 SPISTEA – EQEP3I – PJ2_GPIO58 GPIO58 MCLKRA – EPWM7A – PJ3_GPIO59 GPIO59 MFSRA – EPWM7B – PJ4_GPIO60 GPIO60 – – EPWM8A – PJ5_GPIO61 GPIO61 – – EPWM8B – PJ6_GPIO62 GPIO62 – – EPWM9A – PJ7_GPIO63/ XCLKIN GPIO63 – – EPWM9B – PC0_GPIO64 (no pin) – – – – – PC1_GPIO65 (no pin) – – – – – PC2_GPIO66 (no pin) – – – – – PC3_GPIO67 (no pin) – – – – – PC4_GPIO68 GPIO68 – – – – PC5_GPIO69 GPIO69 – – – – PC6_GPIO70 GPIO70 – – – – PC7_GPIO71 GPIO71 – – – Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.16.2 GPIO_MUX2 The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed through a separate set of registers from those used to program GPIO_MUX1. Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to “00”, “01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00” (Peripheral Mode 0) assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently available. Table 2-30. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes) (1) (1) Device Pin Name C28x Peripheral Mode 0 C28x Peripheral Mode 1 C28x Peripheral Mode 2 C28x Peripheral Mode 3 GPIO128 GPIO128 – – – GPIO129 GPIO129 – – COMP1OUT GPIO130 GPIO130 – – COMP6OUT GPIO131 GPIO131 – – COMP2OUT GPIO132 GPIO132 – – COMP3OUT GPIO133 GPIO133 – – COMP4OUT GPIO134 GPIO134 – – – GPIO135 GPIO135 – – COMP5OUT Blank fields represent Reserved functions. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 77 PRODUCT PREVIEW The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G. They are accessible by the C28x CPU only. The middle portion of Figure 2-16 shows set G of Control Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register selects one of six possible digital output signals from analog comparators, or one of eight general-purpose GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 2-30 for the mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ONE OF 10 AIO_MUX1 PINS ADC1INB0 ADC1INB3 ADC1INB4 ADC1INB7 AIO2 AIO4 AIO6 AIO12 AIOMUX1 REG AIODIR REG ADC 1 AIO_MUX1 AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIODAT REG COMPA1 COMPA2 COMPA3 PRODUCT PREVIEW COMPB2 DIS COMPOUT1 COMPOUT2 COMPOUT3 COMPOUT4 COMPOUT5 COMPOUT6 GPIOPUR GPGPUD REG REG PULL-UP DISABLED ON RESET ‘1’ PULL UP GPGMUX1 REG GPGDIR REG ONE OF 8 GPIO_MUX2 PINS ONE OF 10 AIO_MUX2 PINS AIOMUX2 REG AIODIR REG 6 COMPARATOR + DAC UNITS COMPA4 COMPA5 COMPA6 GPIO128 GPIO129 GPIO130 GPIO131 GPIO132 GPIO133 GPIO134 GPIO135 ADC2INA0 ADC2INA2 ADC2INA3 ADC2INA4 ADC2INA6 ADC2INA7 ANALOG COMMON INTERFACE BUS GPIO_MUX2 ANALOG BUS COMPB5 C28 CPU BUS C28x CPU GPGSET REG GPGCLEAR REG GPGTOGGLE REG GPGDIR REG GPGDAT REG ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 AIO18 AIO20 AIO22 AIO28 ADC 2 AIO_MUX2 AIOSET REG AIOCLEAR REG AIOTOGGLE REG AIODIR REG AIODAT REG Figure 2-16. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2 78 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.16.3 AIO_MUX1 The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. Note that while AIO_MUX1 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1 block is programmed through a separate set of registers from those used to program AIO_MUX2. AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1 register to ‘0’ assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1 register to ‘1’ assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are “don’t cares”. Table 2-31. AIO_MUX1 Pin Assignments (C28x AIO Modes) (1) (2) Device Pin Name (1) (2) (3) (4) C28x AIO Mode 0 (3) C28x AIO Mode 1 (4) ADC1INA0 – ADC1INA0 ADC1INA2 AIO2 ADC1INA2, COMPA1 ADC1INA3 – ADC1INA3 ADC1INA4 AIO4 ADC1INA4, COMPA2 ADC1INA6 AIO6 ADC1INA6, COMPA3 ADC1INA7 – ADC1INA7 ADC1INB0 – ADC1INB0 ADC1INB3 – ADC1INB3 ADC1INB4 AIO12 ADC1INB4, COMPB2 ADC1INB7 – ADC1INB7 Blank fields represent Reserved functions. For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. AIO Mode 0 represents digital general-purpose inputs or outputs. AIO Mode 1 represents analog inputs for ADC1 or the Comparator module. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 79 PRODUCT PREVIEW The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU only. The top portion of Figure 2-16 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX1 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 2-31 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX1. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.16.4 AIO_MUX2 The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-Purpose Outputs. Note that while AIO_MUX2 has been named after the analog signals passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2 block is programmed through a separate set of registers from those used to program AIO_MUX1. The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU only. The bottom portion of Figure 2-16 shows Control Subsystem registers and muxing logic for the associated ten AIO pins. The AIOMUX2 register selects one of ten possible analog input signals or one of four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of the bits (read or write). See Table 2-32 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available. PRODUCT PREVIEW AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2 register to ‘0’ assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2 register to ‘1’ assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are “don’t cares”. Table 2-32. AIO_MUX2 Pin Assignments (C28x AIO Modes) (1) (2) Device Pin Name (1) (2) (3) (4) 80 C28x AIO Mode 0 (3) C28x AIO Mode 1 (4) ADC2INA0 – ADC2INA0 ADC2INA2 AIO18 ADC2INA2, COMPA4 ADC2INA3 – ADC2INA3 ADC2INA4 AIO20 ADC2INA4, COMPA5 ADC2INA6 AIO22 ADC2INA6, COMPA6 ADC2INA7 – ADC2INA7 ADC2INB0 – ADC2INB0 ADC2INB3 – ADC2INB3 ADC2INB4 AIO28 ADC2INB4, COMPB5 ADC2INB7 – ADC2INB7 Blank fields represent Reserved functions. For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs. AIO Mode 0 represents digital general-purpose inputs or outputs. AIO Mode 1 represents analog inputs for ADC2 or the Comparator module. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.17 Emulation/JTAG Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port and the 5-pin Cortex™-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used to connect to debug tools via the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin Cortex™-M3 ITM port can only be accessed through the TI 20-pin JTAG header. The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST signal should always be pulled down via a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1 signals should be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). The JTAG port is TI’s standard debug port. The ITM port uses five GPIO pins that can be mapped to internal Cortex™-M3 ITM trace signals: TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug. Figure 2-18 shows two possible ways to connect the 20-pin header to Concerto’s emulation pins. The left side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the 14-pin header was connected. Note that the JTAG EMU0 and EMU1 signals are mapped to the corresponding terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left unconnected and the ITM trace mode is not available. The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of seven JTAG signals. Note that Concerto’s EMU0 and EMU1 signals are left unconnected in this mode; thus, the emulation functions associated with these two signals are not available when debugging with ITM trace. Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 81 PRODUCT PREVIEW TI emulators, and those from other manufacturers, can connect to Concerto devices via TI’s 14-pin JTAG header or 20-pin JTAG header. See Figure 2-17 to see how the 14-pin JTAG header connects to Concerto’s JTAG port signals. Note that the 14-pin header does not support the ITM debug mode. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com CONCERTO F28M35x TRST 85 2.2K 3.3V TMS 87 1 88 3 TDI 5 7 84 PRODUCT PREVIEW TDO 4.7K TCK EMU0 EMU1 4.7K 9 89 11 83 13 TMS nTRST 2 TDI TDIS 4 PD KEY 6 TDO GND RTCK GND 10 TCK GND 12 EMU0 EMU1 14 8 86 TI 14-PIN JTAG HEADER JTAG PINS GPIO PINS TRACED0 TRACED1 TRACECLK TRACED2 TRACED3 PF3_GPIO35 PG3_GPIO43 PF2_GPIO34 PF0_GPIO32 PF1_GPIO33 81 78 82 104 103 NC NC NC NC NC ITM trace from M3 PROCESSOR Figure 2-17. Connecting to TI 14-Pin JTAG Emulator Header 82 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 CONCERTO F28M35x CONCERTO F28M35x 85 TRST 85 2.2K 2.2K 3.3V TMS 3.3V 87 1 88 3 TMS nTRST 2 TDI TDIS 4 PD KEY 6 TDO GND RTCK GND 10 TCK GND 12 EMU0 EMU1 14 RESETn GND 16 EMU2 EMU3 TDI 5 7 84 TDO 4.7K TCK EMU0 EMU1 9 4.7K 89 11 83 13 86 15 NC JTAG PINS NC 17 19 EMU4 GND TMS 87 1 88 3 TDI 5 8 7 84 TDO 18 4.7K TCK EMU0 EMU1 11 89 83 86 9 4.7K NC NC 13 15 17 NC JTAG PINS 20 19 TI 20-PIN JTAG HEADER PF3_GPIO35 TRACED1 PG3_GPIO43 TRACECLK PF2_GPIO34 TRACED2 PF0_GPIO32 TRACED3 PF1_GPIO33 nTRST 2 TDI TDIS 4 PD KEY 6 TDO GND RTCK GND 10 TCK GND 12 EMU0 EMU1 14 RESETn GND 16 EMU2 EMU3 EMU4 GND 8 18 20 TI 20-PIN JTAG HEADER GPIO PINS TRACED0 TMS PRODUCT PREVIEW TRST GPIO PINS 81 78 82 104 103 NC TRACED0 PF3_GPIO35 NC TRACED1 PG3_GPIO43 NC TRACECLK PF2_GPIO34 NC TRACED2 PF0_GPIO32 NC TRACED3 PF1_GPIO33 81 78 82 104 103 OPEN DRAIN ITM trace from M3 PROCESSOR OPEN DRAIN A LOW PULSE FROM THE EMULATOR CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD ITM trace from M3 PROCESSOR A LOW PULSE FROM THE EMULATOR CAN BE TIED WITH OTHER RESET SOURCES TO RESET THE BOARD Figure 2-18. Connecting to TI 20-Pin JTAG Emulator Header Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 83 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.18 Code Security Module (CSM) The Code Security Module (CSM) is a security feature incorporated in Concerto™ devices. The CSM prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory is not protected—that is, the contents of the memory could be read by any means (for example, by using a debugging tool such as Code Composer Studio™). 2.18.1 Functional Description The security module restricts the CPU access to on-chip secure memory without interrupting or stalling CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This process, in effect, blocks read and write access to various memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-chip secure memories and prevents unauthorized copying of proprietary code or data. PRODUCT PREVIEW The zone is secure when CPU access to the on-chip secure memories associated with that zone is restricted. When secure, two levels of protection are possible, depending on where the program counter is currently pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (that is, through the emulator). This process allows secure code to access secure data. Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User code can dynamically jump in and out of secure memory, thereby allowing secure function calls from unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main program loop is run from unsecure memory. The code security mechanism present in this device offers dual-zone security for the Cortex™-M3 code and single-zone security for the C28x code. In case of dual-zone security on the master subsystem, the different secure memories (RAMs and flash sectors) can be assigned to different security zones by configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the GRABSECT registers. Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by executing the password match flow (PMF). The CSM password for each zone is stored in its dedicated flash sector. The password storage locations in the flash sector store the CSM password. The password is selected by the system designer. If the password locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Since new flash devices have erased flash (all ones), only a read of the password locations is required to bring any zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase routine can result in either an all-zero or unknown password. If a device is reset when the password locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of all zeros will seriously limit the user’s ability to debug secure code or reprogram the flash. NOTE If a device is reset while the password locations of a zone contain all zeros or an unknown value, that zone will be permanently locked unless a method to run the flash erase routine from secure SARAM is embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid introducing a security hole. 84 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 2.19 µCRC Module The µCRC module is part of the master subsystem. This module can be used by Cortex™-M3 software to compute CRC on data and program, which are stored at memory locations that are addressable by Cortex™-M3. On this device, the Cortex™-M3 Flash Bank and ROM are mapped to the code space that is only accessed by the ICODE/DCODE bus of Cortex™-M3; and RAMs are mapped on the SRAM space that is accessible by the SYSTEM bus. Hence, the µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and program. To allow interrupts execution in between CRC calculations for a block of data and to discard the Cortex™-M3 literal pool accesses in between executions of the program (which reads data for CRC calculation), the Cortex™-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The µCRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to mirrored memory space. After grabbing, the µCRC module performs the CRC calculation on the grabbed data and updates the µCRC Result Register (µCRCRES). This register can be read at any time to get the calculated CRC for all the previous read data. The µCRC module only supports CRC calculation for byte accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to all the data. For half-word and word accesses, the µCRC module discards the data and does not update the µCRCRES register. NOTE If a read to a mirrored address space is thrown from the debugger (Code Composer Studio or any other debug platform), the µCRC module ignores the read data and does not update the CRC result for that particular read. 2.19.2 CRC Polynomials The following are the CRC polynomials that are supported by the µCRC module: • CRC8 Polynomial = 0x07 • CRC16 Polynomial-1 = 0x8005 • CRC16 Polynomial-2 = 0x1021 • CRC32 Polynomial = 0x04C11DB7 2.19.3 CRC Calculation Procedure The software procedure for calculating CRC for a set of data that is stored in Cortex™-M3 addressable memory space is as follows: 1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of CRC in nested interrupt 2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register (µCRCCONTROL) to "1" 3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC Configuration Register (µCRCCONFIG) 4. Read the data from memory locations for which CRC needs to be calculated using mirrored address 5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC from the stack and store this value into the µCRC Result Register (uCRCRES) Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 85 PRODUCT PREVIEW 2.19.1 Functional Description F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 2.19.4 CRC Calculation for Data Stored In Secure Memory This device has dual-zone security for the Cortex™-M3 subsystem. Since ZoneX (X → 1/2) software does not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is running from same secure zone, the software cannot read the data stored in Exe-Only sectors. However, hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the read access for this data is initiated by code running from same secure zone. These reads are just dummy reads and, in this case, read data only goes to the µCRC module, not to the CPU. PRODUCT PREVIEW 86 Device Overview Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 3 Device Pins 3.1 Pin Assignments 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PG5_GPIO45 PG2_GPIO42 PG6_GPIO46 PF6_GPIO38 PD7_GPIO23 VDDIO VDD12 PD4_GPIO20 PD5_GPIO21 PJ0_GPIO56 PJ1_GPIO57 PJ2_GPIO58 PJ3_GPIO59 VDDIO VDD12 PJ4_GPIO60 PJ5_GPIO61 VDD12 VDDIO PJ6_GPIO62 PG7_GPIO47 PF5_GPIO37 PG1_GPIO41 PG0_GPIO40 PF4_GPIO36 PH5_GPIO53 PH4_GPIO52 PE1_GPIO25 VDDIO PE0_GPIO24 PH1_GPIO49 PH0_GPIO48 PC7_GPIO71 PC6_GPIO70 PC5_GPIO69 PC4_GPIO68 VDD18 VDDIO VDDIO XRS PA0_GPIO0 PA1_GPIO1 PA2_GPIO2 PA3_GPIO3 PA4_GPIO4 VDDIO VDD12 PA5_GPIO5 PA6_GPIO6 PA7_GPIO7 PB0_GPIO8 FLT1 VDDIO PB1_GPIO9 PB2_GPIO10 PB3_GPIO11 FLT2 PE6_GPIO30 PE7_GPIO31 VDD12 VDDIO PB6_GPIO14 PB7_GPIO15 PD2_GPIO18 PD3_GPIO19 PB4_GPIO12 PB5_GPIO13 PE2_GPIO26 PE3_GPIO27 VDDIO PH3_GPIO51 PH2_GPIO50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 A. B. All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 2.11. See Table 3-1, Terminal Functions, for the complete multiplexed signal names. Figure 3-1. 144-Pin RFP PowerPAD™ HTQFP (Top View) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 87 PRODUCT PREVIEW (A) GPIO135/COMP5OUT GPIO134 GPIO133/COMP4OUT GPIO132/COMP3OUT VREG18EN ADC1INB7 ADC1INB4 ADC1INB3 ADC1INB0 VSSA1 VDDA1 ADC1VREFHI ADC1INA0 ADC1INA2 ADC1INA3 ADC1INA4 ADC1INA6 ADC1INA7 ADC2INA7 ADC2INA6 ADC2INA4 ADC2INA3 ADC2INA2 ADC2INA0 ADC2VREFHI VDDA2 VSSA2 ADC2INB0 ADC2INB3 ADC2INB4 ADC2INB7 GPIO128 GPIO129/COMP1OUT GPIO130/COMP6OUT GPIO131/COMP2OUT ARS 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD18 VDDIO VDDIO VDDIO PF0_GPIO32 PF1_GPIO33 PD0_GPIO16 VREG12EN VDDIO VDD12 PD1_GPIO17 PJ7_GPIO63 VDDIO X2 VSSOSC X1 VDDIO NC VDD12 TCK TDI TMS EMU1 TRST TDO EMU0 PF2_GPIO34 PF3_GPIO35 PH7_GPIO55 PH6_GPIO54 PG3_GPIO43 PE4_GPIO28 PE5_GPIO29 VDD12 VDDIO PD6_GPIO22 Figure 3-1 shows the 144-pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) pin assignments. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 3.2 www.ti.com Terminal Functions Table 3-1 describes the signals. Table 3-1. Terminal Functions(1) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1 ADC1VREFHI 120 I ADC1 External High Reference – used only when in ADC external reference mode. ADC1VREFLO see VSSA1 I ADC1 External Low Reference – used only when in ADC external reference mode. 121 I ADC1 Group A, Channel 0 input I ADC1 Group A, Channel 2 input I Comparator Input A1 ADC1INA0 ADC1INA2 COMPA1 122 AIO2 I/O ADC1INA3 123 ADC1INA4 COMPA2 124 PRODUCT PREVIEW AIO4 I ADC1 Group A, Channel 3 input I ADC1 Group A, Channel 4 input I Comparator Input A2 I/O ADC1INA6 COMPA3 125 AIO6 4 mA Digital AIO2 4 mA Digital AIO4 I ADC1 Group A, Channel 6 input I Comparator Input A3 I/O 4 mA Digital AIO6 ADC1INA7 126 I ADC1 Group A, Channel 7 input ADC1INB0 117 I ADC1 Group B, Channel 0 input ADC1INB3 116 I ADC1 Group B, Channel 3 input I ADC1 Group B, Channel 4 input I Comparator Input B2 ADC1INB4 COMPB2 115 AIO12 I/O ADC1INB7 114 I 4 mA Digital AIO12 ADC1 Group B, Channel 7 input ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2 ADC2VREFHI 133 I ADC2 External High Reference – used only when in ADC external reference mode. ADC2VREFLO see VSSA2 I ADC2 External Low Reference – used only when in ADC external reference mode. 132 I ADC2 Group A, Channel 0 input I ADC2 Group A, Channel 2 input I Comparator Input A4 ADC2INA0 ADC2INA2 COMPA4 131 AIO18 I/O ADC2INA3 130 ADC2INA4 COMPA5 129 AIO20 I ADC2 Group A, Channel 3 input I ADC2 Group A, Channel 4 input I Comparator Input A5 I/O ADC2INA6 COMPA6 128 AIO22 4 mA Digital AIO18 4 mA Digital AIO20 I ADC2 Group A, Channel 6 input I Comparator Input A6 I/O 4 mA Digital AIO22 ADC2INA7 127 I ADC2 Group A, Channel 7 input ADC2INB0 136 I ADC2 Group B, Channel 0 input ADC2INB3 137 I ADC2 Group B, Channel 3 input 88 Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) ADC2INB4 COMPB5 138 AIO28 I ADC2 Group B, Channel 4 input I Comparator Input B5 I/O ADC2INB7 139 DESCRIPTION I PU or PD(3) OUTPUT BUFFER STRENGTH 4 mA Digital AIO28 ADC2 Group B, Channel 7 input ADC Modules Analog Power and Ground VDDA1 119 3.3-V Analog Module 1 Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. VDDA2 134 3.3-V Analog Module 2 Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. VSSA1 118 Analog ground for ADC1, ADC1VREFLO, COMP1–3, and DAC1–3 VSSA2 135 Analog ground for ADC2, ADC2VREFLO, COMP4–6, and DAC4–6 GPIO129 COMP1OUT GPIO130 COMP6OUT GPIO131 COMP2OUT GPIO132 COMP3OUT GPIO133 COMP4OUT GPIO134 140 141 142 143 112 111 110 (4) GPIO135 COMP5OUT 109 I/O General-purpose input/output 128 I/O General-purpose input/output 129 O Compare result from Analog Comparator 1 I/O General-purpose input/output 130 O Compare result from Analog Comparator 6 I/O General-purpose input/output 131 O Compare result from Analog Comparator 2 I/O General-purpose input/output 132 O Compare result from Analog Comparator 3 I/O General-purpose input/output 133 O Compare result from Analog Comparator 4 I/O General-purpose input/output 134 I/O General-purpose input/output 135 O Compare result from Analog Comparator 5 PU 4 mA PU 4 mA PU 4 mA PU 4 mA PU 8 mA PU 4 mA PU 4 mA PU 8 mA Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only) GPIO128 89 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH PU 4 mA PU 4 mA PU 4 mA PU 4 mA PU 4 mA PU 4 mA GPIO Group 1 and Peripheral Signals PA0_GPIO0 I/O/Z M_U0RX M_I2C1SCL I 5 M_U1RX General-purpose input/output 0 UART-0 receive data I/OD I2C-1 clock open-drain bidirectional port I UART-1 receive data C_EPWM1A O Enhanced PWM-1 output A PA1_GPIO1 I/O/Z M_U0TX O M_I2C1SDA M_U1TX UART-0 transmit data I/OD 6 General-purpose input/output 1 I2C-1 data open-drain bidirectional port O UART-1 data transmit M_SSI1FSS I/O SSI-1 frame C_EPWM1B O Enhanced PWM-1 output B I/O Enhanced Capture-6 input/output C_ECAP6 PRODUCT PREVIEW PA2_GPIO2 I/O/Z M_SSI0CLK I/O SSI-0 clock O EMAC MII transmit data bit 2 I UART-1 clear-to-send modem status C_EPWM2A O Enhanced PWM-2 output A PA3_GPIO3 I/O/Z M_SSI0FSS I/O SSI-0 frame M_MIITXD1 O EMAC MII transmit data bit 1 I UART-1 data carrier detect M_MIITXD2 7 M_U1CTS M_U1DCD 8 General-purpose input/output 2 General-purpose input/output 3 M_SSI1CLK I/O SSI-1 clock C_EPWM2B O Enhanced PWM-2 output B C_ECAP5 I/O Enhanced Capture-5 input/output PA4_GPIO4 I/O/Z M_SSI0RX I SSI-0 receive data M_MIITXD0 O EMAC MII transmit data bit 0 I CAN-0 receive data M_U1DSR I UART-1 data set ready C_EPWM3A O Enhanced PWM-3 output A PA5_GPIO5 I/O/Z M_CAN0RX 9 General-purpose input/output 4 General-purpose input/output 5 M_SSI0TX O SSI-0 transmit data M_MIIRXDV I EMAC MII receive data valid M_CAN0TX O CAN-0 transmit data O UART-1 request-to-send C_EPWM3B O Enhanced PWM-3 output B C_MFSRA I McBSP-A receive frame sync C_ECAP1 I/O M_U1RTS 90 12 Enhanced Capture-1 input/output Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) DESCRIPTION PA6_GPIO6 I/O/Z General-purpose input/output 6 M_I2C1SCL I/OD I2C-1 clock open-drain bidirectional port M_CCP1 M_MIIRXCK I EMAC MII receive clock M_CAN0RX I CAN-0 receive data M_USB0EPEN O USB-0 external power enable (optionally used in host mode) M_U1CTS I UART-1 clear-to-send modem status M_U1DTR O UART-1 data terminal ready C_EPWM4A O Enhanced PWM-4 output A C_EPWMSYNCO O Enhanced PWM-4 external sync pulse PA7_GPIO7 I/O/Z General-purpose input/output 7 M_I2C1SDA I/OD I2C-1 data open-drain bidirectional port M_CCP4 M_MIIRXER I EMAC MII receive error M_CAN0TX O CAN-0 transmit data M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) 14 M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_U1DCD I UART-1 data carrier detect M_MIIRXD1 I EMAC MII receive data 1 M_U1RI I UART-1 ring indicator modem status C_EPWM4B O Enhanced PWM-4 output B I McBSP-A receive clock C_ECAP2 I/O PB0_GPIO8 Capture/Compare/PWM-0 (General-purpose Timer) M_U1RX I UART-1 data receive data M_SSI2TX O SSI-2 transmit data M_CAN1TX O CAN-1 transmit data M_U4TX O UART-4 transmit data C_EPWM5A O Enhanced PWM-5 output A O ADC start-of-conversion A C_ADCSOCAO PB1_GPIO9 I/O/Z Capture/Compare/PWM-2 (General-purpose Timer) I/O Capture/Compare/PWM-1 (General-purpose Timer) O UART-1 transmit data M_SSI2RX I SSI-2 receive data C_EPWM5B O Enhanced PWM-5 output B C_ECAP3 I/O Enhanced Capture-3 input/output M_CCP1 18 M_U1TX 4 mA PU 4 mA PU 4 mA General-purpose input/output 9 I/O M_CCP2 PU General-purpose input/output 8 I/O 15 4 mA Enhanced Capture-1 input/output I/O/Z M_CCP0 PU Capture/Compare/PWM-4 (General-purpose Timer) I/O C_MCLKRA OUTPUT BUFFER STRENGTH Capture/Compare/PWM-1 (General-purpose Timer) I/O 13 PU or PD(3) PRODUCT PREVIEW NAME RFP PIN NO. Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 91 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PB2_GPIO10 I/O/Z General-purpose input/output 10 M_I2C0SCL I/OD I2C-0 clock open-drain bidirectional port M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) O USB-0 external power enable (optionally used in the host mode) M_SSI2CLK I/O SSI-2 clock M_CAN1RX I CAN-1 receive data M_U4RX I UART-4 receive data C_EPWM6A O Enhanced PWM-6 output A C_ADCSOCBO O ADC start-of-conversion B M_USB0EPEN 19 PB3_GPIO11 I/O/Z General-purpose input/output 11 M_I2C0SDA I/OD I2C-0 data open-drain bidirectional port PRODUCT PREVIEW M_USB0PFLT M_SSI2FSS M_U1RX I/O SSI-2 frame I UART-1 receive data C_EPWM6B O Enhanced PWM-6 output B C_ECAP4 I/O Enhanced Capture-4 input/output I/O/Z General-purpose input/output 12 PB4_GPIO12 M_U2RX I UART-2 receive data M_CAN0RX I CAN-0 receive data M_U1RX I UART-1 receive data M_EPI0S23 30 I/O EPI-0 signal 23 M_CAN1TX O CAN-1 transmit data M_SSI1TX O SSI-1 transmit data C_EPWM7A O Enhanced PWM-7 output A PB5_GPIO13 I/O/Z I/O Capture/Compare/PWM-5 (General-purpose Timer) M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) O CAN-0 transmit data M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_U1TX O UART-1 transmit data M_EPI0S22 I/O EPI-0 signal 22 M_CAN1RX I CAN-1 receive data M_SSI1RX I SSI-1 receive data C_EPWM7B O Enhanced PWM-7 output B 92 31 PU 4 mA PU 4 mA PU 4 mA PU 4 mA General-purpose input/output 13 M_CCP5 M_CAN0TX OUTPUT BUFFER STRENGTH USB-0 external power error state (optionally used in the host mode) I 20 PU or PD(3) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PB6_GPIO14 I/O/Z DESCRIPTION I/O Capture/Compare/PWM-1 (General-purpose Timer) M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_CCP5 I/O Capture/Compare/PWM-5 (General-purpose Timer) I/O EPI-0 signal 37 26 M_MIICRS I M_I2C0SDA I/OD UART-1 transmit data M_SSI1CLK I/O SSI-1 clock C_EPWM8A O Enhanced PWM-8 output A PB7_GPIO15 I/O/Z I Cortex™-M3 external non-maskable interrupt M_MIIRXD1 I EMAC MII receive data 1 27 M_U1RX I/O EPI-0 signal 36 I/OD I I2C-0 clock open-drain bidirectional port I/O SSI-1 frame C_EPWM8B O Enhanced PWM-8 output B PD0_GPIO16 I/O/Z I CAN-0 receive data M_U2RX I UART-2 receive data M_U1RX I UART-1 receive data M_CCP6 I/O 4 mA Capture/Compare/PWM-6 (General-purpose Timer) I EMAC MII receive data valid I UART-1 clear-to-send modem status M_MIIRXD2 I EMAC MII receive data 2 M_SSI0TX O SSI-0 transmit data M_CAN1TX O CAN-1 transmit data M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) C_SPISIMOA I/O SPI-A slave in, master out 102 PU General-purpose input/output 16 M_CAN0RX M_U1CTS 4 mA UART-1 receive data M_SSI1FSS M_MIIRXDV PU General-purpose input/output 15 M_EXTNMI M_I2C0SCL 4 mA I2C-0 data open-drain bidirectional port O M_EPI0S36 PU EMAC MII carrier sense M_U1TX (5) OUTPUT BUFFER STRENGTH General-purpose input/output 14 M_CCP1 M_EPI0S37(5) PU or PD(3) PRODUCT PREVIEW NAME RFP PIN NO. Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 93 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. PD1_GPIO17 I/O/Z(2) I/O/Z DESCRIPTION O CAN-0 transmit data M_U2TX O UART-2 transmit data M_U1TX O UART-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) M_MIITXER O EMAC MII transmit error M_U1DCD I UART-1 data carrier detect I/O Capture/Compare/PWM-2 (General-purpose Timer) M_MIICOL I EMAC MII collision detect M_SSI0RX I SSI-0 receive data M_CAN1RX I CAN-1 receive data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) C_SPISOMIA I/O PD2_GPIO18 I/O/Z M_CCP2 PRODUCT PREVIEW M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S20 I/O EPI-0 signal 20 M_SSI0CLK I/O SSI-0 clock M_U1TX O UART-1 transmit data M_CAN0RX I CAN-0 receive data I/O O UART-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) I/O Capture/Compare/PWM-0 (General-purpose Timer) M_EPI0S21 I/O EPI-0 signal 21 M_SSI0FSS I/O SSI-0 frame M_U1RX I UART-1 receive data M_CAN0TX O CAN-0 transmit data C_SPISTEA I/O SPI-A slave transmit enable 94 PU 4 mA General-purpose input/output 19 M_U1TX 29 4 mA SPI-A clock I/O/Z M_CCP0 PU UART-1 receive data 28 PD3_GPIO19 4 mA General-purpose input/output 18 I C_SPICLKA PU SPI-A master in, slave out M_U1RX M_CCP5 OUTPUT BUFFER STRENGTH General-purpose input/output 17 M_CAN0TX 98 PU or PD(3) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PD4_GPIO20 I/O/Z DESCRIPTION I/O Capture/Compare/PWM-0 (General-purpose Timer) M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) O EMAC MII transmit data 3 I UART-1 ring indicator modem status M_U1RI 65 M_EPI0S19 I/O EPI-0 signal 19 M_U3TX O UART-3 transmit data M_CAN1TX O CAN-1 transmit data C_EQEP1A I Enhanced QEP-1 input A C_MDXA O McBSP-A transmit data PD5_GPIO21 I/O/Z I/O Capture/Compare/PWM-2 (General-purpose Timer) M_CCP4 I/O Capture/Compare/PWM-4 (General-purpose Timer) O EMAC MII transmit data 2 I UART-2 receive data M_U2RX 64 M_EPI0S28 I/O I UART-3 receive data M_CAN1RX I CAN-1 receive data C_EQEP1B I Enhanced QEP-1 input B I McBSP-A receive data PD6_GPIO22 I/O/Z M_MIITXD1 EMAC MII transmit data 1 M_U2TX O UART-2 transmit data M_EPI0S29 I/O EPI-0 signal 29 73 I/OD I2C-0 data open-drain bidirectional port M_U1TX O UART-1 transmit data C_EQEP1S I/O Enhanced QEP-1 strobe C_MCLKXA O McBSP-A transmit clock PD7_GPIO23 I/O/Z I/O Capture/Compare/PWM-1 (General-purpose Timer) M_MIITXD0 O EMAC MII transmit data 0 O UART-1 data terminal ready I/O EPI-0 signal 30 M_EPI0S30 68 M_I2C1SCL M_U1RX I/OD I 6 mA PU 6 mA PU 6 mA General-purpose input/output 23 M_CCP1 M_U1DTR PU General-purpose input/output 22 O M_I2C1SDA 4 mA EPI-0 signal 28 M_U3RX C_MDRA PU General-purpose input/output 21 M_CCP2 M_MIITXD2 OUTPUT BUFFER STRENGTH General-purpose input/output 20 M_CCP0 M_MIITXD3 PU or PD(3) PRODUCT PREVIEW NAME RFP PIN NO. I2C-1 clock open-drain bidirectional port UART-1 receive data C_EQEP1I I/O Enhanced QEP-1 index C_MFSXA O McBSP-A transmit frame sync Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 95 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PE0_GPIO24 I/O/Z M_SSI1CLK I/O SSI-1 clock M_CCP3 I/O Capture/Compare/PWM-3 (General-purpose Timer) M_EPI0S8 I/O EPI-0 signal 8 USB-0 external power error state (optionally used in the host mode) M_SSI3TX O SSI-3 transmit data M_CAN0RX I CAN-1 receive data M_SSI1TX O SSI-1 transmit data C_ECAP1 I/O Enhanced Capture-1 input/output 43 C_EQEP2A I PRODUCT PREVIEW I/O/Z M_SSI1FSS I/O SSI-1 frame M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) M_CCP6 I/O Capture/Compare/PWM-6 (General-purpose Timer) I/O EPI-0 signal 9 45 I SSI-3 receive data M_CAN0TX O CAN-1 transmit data M_SSI1RX O SSI-1 receive data C_ECAP2 I/O Enhanced Capture-2 input/output I PE2_GPIO26 I M_CCP2 M_EPI0S24 32 M_SSI3CLK M_U2RX I/O Capture/Compare/PWM-2 (General-purpose Timer) I/O EPI-0 signal 24 I/O SSI-3 clock I/O SSI-1 clock C_ECAP3 I/O Enhanced Capture-3 input/output C_EQEP2I I/O Enhanced QEP-2 index I/O/Z I/O Capture/Compare/PWM-1 (General-purpose Timer) M_SSI1TX O SSI-1 transmit data M_CCP7 I/O Capture/Compare/PWM-7 (General-purpose Timer) I/O EPI-0 signal 25 M_SSI3FSS I/O SSI-3 frame M_U2TX O UART-2 transmit data M_SSI1FSS I/O SSI-1 frame C_ECAP4 I/O Enhanced Capture-4 input/output C_EQEP2S I/O Enhanced QEP-2 strobe 96 PU 4 mA General-purpose input/output 27 M_CCP1 33 4 mA UART-2 receive data M_SSI1CLK M_EPI0S25 PU General-purpose input/output 26 SSI-1 receive data I PE3_GPIO27 4 mA Capture/Compare/PWM-4 (General-purpose Timer) I/O M_SSI1RX PU Enhanced QEP-2 input B I/O/Z M_CCP4 4 mA General-purpose input/output 25 M_SSI3RX C_EQEP2B PU Enhanced QEP-2 input A PE1_GPIO25 M_EPI0S9 OUTPUT BUFFER STRENGTH General-purpose input/output 24 I M_USB0PFLT PU or PD(3) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PE4_GPIO28 I/O/Z DESCRIPTION I/O Capture/Compare/PWM-3 (General-purpose Timer) M_U2TX O UART-2 transmit data M_CCP2 I/O Capture/Compare/PWM-2 (General-purpose Timer) I EMAC MII receive data 0 77 M_EPI0S34(5) I/O M_U0RX M_EPI0S38 EPI-0 signal 38 M_USB0EPEN O USB-0 external power enable (optionally used in the host mode) C_SCIRXDA I SCI-A receive data PE5_GPIO29 I/O/Z Capture/Compare/PWM-5 (General-purpose Timer) I/O EPI-0 signal 35 O EMAC MII transmit error M_U0TX O UART-0 transmit data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) C_SCITXDA O SCI-A transmit data PE6_GPIO30 I/O/Z M_MIITXER 76 M_U1CTS M_MDIOD 22 M_CAN0RX I UART-1 clear-to-send modem status I/O EMAC management data input/output CAN-0 receive data C_EPWM9A O Enhanced PWM-9 output A PE7_GPIO31 I/O/Z UART-1 data carrier detect I EMAC MII receive data 3 M_CAN0TX O CAN-0 transmit data C_EPWM9B O Enhanced PWM-9 output B PF0_GPIO32 I/O/Z M_CAN1RX I CAN-1 receive data M_MIIRXCK I EMAC MII receive clock M_U1DSR I UART-1 data set ready M_I2C0SDA 23 104 PU 4 mA PU 4 mA PU 4 mA General-purpose input/output 31 I M_MIIRXD3 4 mA General-purpose input/output 30 I M_U1DCD PU General-purpose input/output 29 I/O M_EPI0S35(5) 4 mA UART-0 receive data I/O M_CCP5 PU EPI-0 signal 34 I (5) OUTPUT BUFFER STRENGTH General-purpose input/output 28 M_CCP3 M_MIIRXD0 PU or PD(3) I/OD PRODUCT PREVIEW NAME RFP PIN NO. General-purpose input/output 32 I2C-0 data open-drain bidirectional port M_TRACED2 O Trace data 2 C_I2CASDA I/OD C_SCIRXDA I SCI-A receive data C_ADCSOCAO O ADC start-of-conversion A(6) I2C-A data open-drain bidirectional port Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 97 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. PF1_GPIO33 I/O/Z(2) I/O/Z M_CAN1TX DESCRIPTION CAN-1 transmit data M_MIIRXER I EMAC MII receive error M_U1RTS O UART-1 request-to-send I/O Capture/Compare/PWM-3 (General-purpose Timer) 103 M_I2C0SCL I/OD M_TRACED3 O C_I2CASCL O Enhanced PWM sync out C_ADCSOCBO O ADC start-of-conversion B(6) I/O/Z I PRODUCT PREVIEW EPI-0 signal 32 M_SSI1CLK I/O SSI-1 clock M_TRACECLK O Trace clock O External output clock I/O Enhanced Capture-1 input/output C_ECAP1 C_SCIRXDA I SCI-A receive data C_XCLKOUT O External output clock BOOT_3 I Boot pin 3 PF3_GPIO35 M_MDIOCK I/O/Z General-purpose input/output 35 I EMAC management data clock M_EPI0S33(5) I/O EPI-0 signal 33 M_SSI1FSS I/O SSI-1 frame O UART-0 transmit data M_TRACED0 O Trace data 0 C_SCITXDA O SCI-A transmit data BOOT_2 I Boot pin 2 M_U0TX 81 PF4_GPIO36 I/O/Z M_CCP0 M_MDIOD M_EPI0S12 48 I/O Capture/Compare/PWM-0 (General-purpose Timer) I/O EMAC management data input/output I/O EPI-0 signal 12 I SSI-1 receive data M_U0RX I UART-0 receive data C_SCIRXDA I SCI-A receive data PF5_GPIO37 I/O/Z M_MIIRXD3 M_EPI0S15 51 I/O Capture/Compare/PWM-2 (General-purpose Timer) I EMAC MII receive data 3 EPI-0 signal 15 O SSI-1 transmit data M_MIITXEN O EMAC MII transmit enable C_ECAP2 I/O Enhanced Capture-2 input/output 98 4 mA PU 4 mA PU 4 mA General-purpose input/output 37 I/O M_SSI1TX PU General-purpose input/output 36 M_SSI1RX M_CCP2 4 mA EMAC PHY MII interrupt I/O M_XCLKOUT PU General-purpose input/output 34 M_EPI0S32(5) 82 4 mA I2C-A clock open-drain bidirectional port C_EPWMSYNCO M_MIIPHYINTR PU I2C-0 clock open-drain bidirectional port Trace data 3 I/OD PF2_GPIO34 OUTPUT BUFFER STRENGTH General-purpose input/output 33 O M_CCP3 PU or PD(3) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PF6_GPIO38 M_USB0VBUS I/O/Z 69 Analog M_CCP1 M_MIIRXD2 M_EPI0S38(5) M_U1RTS PF7_GPIO39 No Pin M_U2RX I EMAC MII receive data 2 I/O EPI-0 signal 38 O UART-1 request-to-send I M_I2C1SCL USB0 VBUS power (5-V tolerant) Capture/Compare/PWM-1 (General-purpose Timer) I/O/Z I/O EPI-0 signal 13 M_MIIRXD2 I EMAC MII receive data 2 M_U4RX I UART-4 receive data I EMAC MII transmit clock I/O/Z M_U2TX O M_I2C1SDA M_EPI0S14 I/O EPI-0 signal 14 EMAC MII receive data 1 M_U4TX O UART-4 transmit data M_MIITXER O EMAC MII transmit error M_MIICOL I/O/Z 71 Analog I I/O PG3_GPIO43 I/O/Z M_MIIRXDV 78 M_TRACED1 BOOT_0 PG4_GPIO44 No Pin EMAC MII carrier sense I EMAC MII receive data valid O Trace data 1 I Boot pin 0 Analog 4 mA PU 4 mA General-purpose input/output 45 USB0 data plus Capture/Compare/PWM-5 (General-purpose Timer) M_MIITXEN O EMAC MII transmit enable M_EPI0S40(5) I/O EPI-0 signal 40 M_U1DTR O UART-1 data terminal ready 72 PU General-purpose input/output 44 is not pinned out. I/O M_CCP5 4 mA General-purpose input/output 43 I I/O/Z M_USB0DP USB0 data minus EPI-0 signal 39 No Pin PG5_GPIO45 PU General-purpose input/output 42 EMAC MII collision detect M_EPI0S39(5) M_MIICRS 4 mA I2C-1 data open-drain bidirectional port I M_USB0DM PU General-purpose input/output 41 M_MIIRXD1 PG2_GPIO42 4 mA UART-2 transmit data I/OD 50 PU I2C-1 clock open-drain bidirectional port M_EPI0S13 PG1_GPIO41 4 mA General-purpose input/output 40 USB-0 external power enable (optionally used in the host mode) M_MIITXCK PU UART-2 receive data I/OD 49 OUTPUT BUFFER STRENGTH General-purpose input/output 39 is not pinned out. O M_USB0EPEN PU or PD(3) General-purpose input/output 38. NOTE: For this pin, only the USB0VBUS function is available on silicon revision 0 devices (GPIO and the four other functions listed are not available). I/O No Pin PG0_GPIO40 DESCRIPTION PRODUCT PREVIEW NAME RFP PIN NO. Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 99 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. PG6_GPIO46 M_USB0ID I/O/Z(2) I/O/Z 70 M_MIITCK Analog I M_EPI0S41(5) USB0 ID (5-V tolerant) EMAC MII transmit error I/O Capture/Compare/PWM-5 (General-purpose Timer) M_EPI0S31 I/O EPI-0 signal 31 M_MIICRS I EMAC MII carrier sense BOOT_1 I Boot pin 1 52 PRODUCT PREVIEW PH0_GPIO48 I/O/Z M_CCP6 M_MIIPHYRST I/O Capture/Compare/PWM-6 (General-purpose Timer) O EMAC PHY MII reset EPI-0 signal 6 M_SSI3TX O SSI-3 transmit data M_MIITXD3 O EMAC MII transmit data 3 C_ECAP5 I/O Enhanced Capture-5 input/output I/O/Z General-purpose input/output 49 41 PH1_GPIO49 M_CCP7 M_EPI0S7 M_MIIRXD0 42 I/O Capture/Compare/PWM-7 (General-purpose Timer) I/O EPI-0 signal 7 I EMAC MII receive data 0 M_SSI3RX I SSI-3 receive data M_MIITXD2 O EMAC MII transmit data 2 I/O Enhanced Capture-6 input/output I/O/Z General-purpose input/output 50 C_ECAP6 PH2_GPIO50 M_EPI0S1 M_MIITXD3 M_SSI3CLK 36 M_MIITXD1 C_EQEP1A PH3_GPIO51 I/O EPI-0 signal 1 O EMAC MII transmit data 3 I/O SSI-3 clock O EMAC MII transmit data 1 I Enhanced QEP-1 input A I/O/Z USB-0 external power enable (optionally used in the host mode) I/O EPI-0 signal 0 O EMAC MII transmit data 2 M_SSI3FSS I/O SSI-3 frame M_MIITXD0 O EMAC MII transmit data 0 C_EQEP1B I Enhanced QEP-1 input B M_EPI0S0 M_MIITXD2 100 35 6 mA PU 4 mA PU 4 mA PU 4 mA PU 4 mA General-purpose input/output 51 O M_USB0EPEN PU General-purpose input/output 48 I/O M_EPI0S6 4 mA General-purpose input/output 47 O M_CCP5 PU General-purpose input/output 46. NOTE: For this pin, only the USB0ID function is available on silicon revision 0 devices (GPIO and the three other functions listed are not available). UART-1 receive data I/O/Z M_MIITXER OUTPUT BUFFER STRENGTH EPI-0 signal 41 I PG7_GPIO47 PU or PD(3) EMAC MII transmit clock I/O M_U1RI DESCRIPTION Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PH4_GPIO52 I/O/Z M_USB0PFLT I DESCRIPTION I/O EPI-0 signal 10 O EMAC MII transmit data 1 M_SSI1CLK I/O SSI-1 clock M_U3TX O UART-3 transmit data M_MIICOL I EMAC MII collision detect C_EQEP1S I/O Enhanced QEP-1 strobe I/O/Z I/O EPI-0 signal 11 M_MIITXD0 O EMAC MII transmit data 0 I/O SSI-1 frame 47 M_U3RX I UART-3 receive data M_MIIPHYRST O EMAC PHY MII reset C_EQEP1I I/O Enhanced QEP-1 index PH6_GPIO54 I/O/Z I/O M_MIIRXDV I EMAC MII receive data valid M_MIITXEN 79 M_SSI0TX M_MIIPHYINTR C_SPISIMOA C_EQEP3A PH7_GPIO55 I SSI-1 receive data O EMAC MII transmit enable O SSI-0 transmit data I EMAC PHY MII interrupt I/O SPI-A slave in, master out I Enhanced QEP-1 input A I/O/Z I I/O EPI-0 signal 27 M_SSI1TX O SSI-1 transmit data I EMAC MII transmit clock I SSI-0 receive data M_MDIOCK O EMAC management data clock C_SPISOMIA I/O SPI-A master in, slave out I Enhanced QEP-3 input B PJ0_GPIO56 I/O/Z M_MIIRXER I M_EPI016 M_I2C1SCL M_SSI0CLK PU 4 mA PU 4 mA General-purpose input/output 56 EMAC MII receive error I/O 63 4 mA EMAC MII receive clock M_SSI0RX C_EQEP3B PU General-purpose input/output 55 M_EPI0S27 80 4 mA EPI-0 signal 26 M_MIIRXCK M_MIITXCK PU General-purpose input/output 54 M_EPI0S26 M_SSI1RX 4 mA General-purpose input/output 53 M_EPI0S11 M_SSI1FSS PU USB-0 external power error state (optionally used in the host mode) M_MIITXD1 PH5_GPIO53 OUTPUT BUFFER STRENGTH General-purpose input/output 52 M_EPI0S10 46 PU or PD(3) PRODUCT PREVIEW NAME RFP PIN NO. EPI-0 signal 16 I/OD I2C-1 clock open-drain bidirectional port I/O SSI-0 clock M_MDIOD I/O EMAC management data input/output C_SPICLKA I/O SPI-A clock C_EQEP3S I/O Enhanced QEP-3 strobe Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 101 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) PJ1_GPIO57 I/O/Z M_EPI0S17 I/O M_USB0PFLT M_MIIRXDV I EMAC MII receive data valid I/O I C_SPISTEA I/O SPI-A slave transmit enable I/O Enhanced QEP-3 index M_EPI0S18 I/O EPI-0 signal 18 M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) I PRODUCT PREVIEW M_U0TX O UART-0 transmit data M_MIIRXD2 I EMAC MII receive data 2 C_MCLKRA I McBSP-A receive clock C_EPWM7A O Enhanced PWM-7 output A PJ3_GPIO59 I/O/Z M_EPI0S19 I/O M_MDIOCK M_SSI0FSS I/O Capture/Compare/PWM-6 (General-purpose Timer) O EMAC management data clock I/O SSI-0 frame I UART-0 receive data M_MIIRXD1 I EMAC MII receive data 1 C_MFSRA I McBSP-A receive frame sync C_EPWM7B O Enhanced PWM-7 output B PJ4_GPIO60 I/O/Z M_EPI0S28 I/O M_U1DCD I UART-1 data carrier detect I/O Capture/Compare/PWM-4 (General-purpose Timer) I EMAC MII collision detect M_MIICOL 57 General-purpose input/output 60 EPI-0 signal 28 M_SSI1CLK I/O M_MIIRXD0 I EMAC MII receive data 0 C_EPWM8A O Enhanced PWM-8 output A 102 6 mA UART-1 clear-to-send M_U0RX M_CCP4 PU General-purpose input/output 59 EPI-0 signal 19 I 60 4 mA EMAC MII receive clock SSI-0 clock M_CCP6 PU General-purpose input/output 58 I/O M_U1CTS 4 mA EMAC MII receive data 3 I/O/Z 61 PU SSI-0 frame PJ2_GPIO58 M_SSI0CLK 4 mA I2C-1 data open-drain bidirectional port M_MIIRXD3 M_MIIRXCK PU General-purpose input/output 57 M_SSI0FSS C_EQEP3I OUTPUT BUFFER STRENGTH USB-0 external power error state (optionally used in the host mode) I/OD 62 PU or PD(3) EPI-0 signal 17 I M_I2C1SDA DESCRIPTION SSI-1 clock Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z(2) PJ5_GPIO61 I/O/Z M_EPI0S29 I/O M_U1DSR I M_CCP2 M_MIICRS Capture/Compare/PWM-2 (General-purpose Timer) I/O I EMAC MII receive data valid C_EPWM8B O Enhanced PWM-8 output B PJ6_GPIO62 I/O/Z M_EPI0S30 I/O EPI-0 signal 30 M_U1RTS O UART-1 request-to-send I/O Capture/Compare/PWM-1 (General-purpose Timer) EMAC PHY MII interrupt M_U2RX I UART-2 receive data M_MIIRXER I EMAC MII receive error C_EPWM9A O Enhanced PWM-9 output A PJ7_GPIO63 I/O/Z O UART-1 data terminal ready M_CCP0 I/O Capture/Compare/PWM-0 (General-purpose Timer) O EMAC PHY MII reset O UART-2 transmit data M_MIIRXCK I EMAC MII receive clock M_XCLKIN I External oscillator input for USB PLL and CAN (always available, see Figure 2-15) O Enhanced PWM-9 output B PC0_GPIO64 No Pin No Pin General-purpose input/output 64 is not pinned out. PC1_GPIO65 No Pin No Pin General-purpose input/output 65 is not pinned out. PC2_GPIO66 No Pin No Pin General-purpose input/output 66 is not pinned out. PC3_GPIO67 No Pin No Pin General-purpose input/output 67 is not pinned out. PC4_GPIO68 I/O/Z I Capture/Compare/PWM-5 (General-purpose Timer) M_MIITXD3 O EMAC MII transmit data 3 I Capture/Compare/PWM-2 (General-purpose Timer) I Capture/Compare/PWM-4 (General-purpose Timer) 37 M_CCP4 M_EPI0S2 M_CCP1 I/O I 4 mA PU 4 mA General-purpose input/output 68 M_CCP5 M_CCP2 PU General-purpose input/output 63 M_U1DTR C_EPWM9B 6 mA General-purpose input/output 62 I M_U2TX PU SSI-1 frame M_MIIPHYINTR 97 6 mA EMAC MII carrier sense M_MIIRXDV M_MIIPHYRST PU UART-1 data set ready I 53 OUTPUT BUFFER STRENGTH General-purpose input/output 61 M_SSI1FSS M_CCP1 PU or PD(3) EPI-0 signal 29 I/O 56 DESCRIPTION PRODUCT PREVIEW NAME RFP PIN NO. EPI-0 signal 2 Capture/Compare/PWM-1 (General-purpose Timer) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 103 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. PC5_GPIO69 I/O/Z M_CCP1 M_CCP3 38 M_USB0EPEN M_EPI0S3 PC6_GPIO70 M_U1RX 39 M_USB0PFLT PRODUCT PREVIEW M_EPI0S4 I Capture/Compare/PWM-3 (General-purpose Timer) O USB-0 external power enable (optionally used in the host mode) I/O EPI-0 signal 3 Capture/Compare/PWM-3 (General-purpose Timer) I UART-1 receive data I Capture/Compare/PWM-0 (General-purpose Timer) I USB-0 external power error state (optionally used in the host mode) I Capture/Compare/PWM-0 (General-purpose Timer) M_U1TX O UART-1 transmit data M_USB0PFLT I USB-0 external power error state (optionally used in the host mode) M_EPI0S5 104 I/O 4 mA PU 4 mA PU 4 mA General-purpose input/output 71 Capture/Compare/PWM-4 (General-purpose Timer) 40 PU EPI-0 signal 4 I M_CCP0 OUTPUT BUFFER STRENGTH General-purpose input/output 70 I I/O/Z M_CCP4 PU or PD(3) General-purpose input/output 69 Capture/Compare/PWM-1 (General-purpose Timer) I/O PC7_GPIO71 DESCRIPTION I I/O/Z M_CCP3 M_CCP0 I/O/Z(2) EPI-0 signal 5 Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH I/OD Digital Subsystem Reset (in) and Watchdog/Brown-out Reset (out). In most applications, TI recommends that the XRS pin be tied with the ARS pin. The Digital Subsystem has a built-in power-on-reset (POR) and brown-outreset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the Digital Subsystem. This pin is also driven low by the Digital Subsystem when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert device reset. In this case, TI recommends that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the Digital Subsystem to terminate execution. The Cortex™-M3 program counter points to the address contained at the location 0x00000004. The C28 program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an opendrain with an internal pullup. PU 4 mA I/OD Analog Subsystem Reset (in) and Brown-out Reset (out). In most applications, TI recommends that the ARS pin be tied with the XRS pin. The Digital Subsystem has a built-in brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a poweron or brown-out condition, this pin is driven low by the Analog Subsystem. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, the Analog Subsystem reset causes the digital logic associated with the Analog Subsystem, to enter reset state. The output buffer of this pin is an open-drain with an internal pullup. PU 4 mA XRS ARS 4 144 Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW Resets 105 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH Clocks X1 93 X2 95 I External oscillator input or on-chip crystaloscillator input. To use the on-chip oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. See Figure 2-7. O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. See Figure 2-7. Clock Oscillator Ground Pin. Use this pin to connect the GND of external crystal load capacitors or the ground pin of 3-terminal ceramic resonators with built-in capacitors. Do not connect to board ground. See Figure 2-7. PRODUCT PREVIEW VSSOSC 94 XCLKIN see PJ7_GPIO63 I XCLKOUT see PF2_GPIO34 O/Z External oscillator input. This pin feeds a clock from an external 3.3-V oscillator to internal USB PLL module and to the CAN peripherals. External oscillator output. This pin outputs a clock divided-down from the internal PLL System Clock. The divide ratio is defined in the XCLKCFG register. Boot Pins BOOT_0 see PG3_GPIO43 I One of four boot mode pins. BOOT_0 selects a specific configuration source from which the Concerto device boots on start-up. BOOT_1 see PG7_GPIO47 I One of four boot mode pins. BOOT_1 selects a specific configuration source from which the Concerto device boots on start-up. PU BOOT_2 see PF3_GPIO35 I One of four boot mode pins. BOOT_2 selects a specific configuration source from which the Concerto device boots on start-up. PU BOOT_3 see PF2_GPIO34 I One of four boot mode pins. BOOT_3 selects a specific configuration source from which the Concerto device boots on start-up. PU PU JTAG TRST 85 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-low test pin and must be maintained low during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. TCK 89 I JTAG test clock TMS 87 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. PU TDI 88 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. PU 106 Device Pins PD Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) NAME TDO EMU0 EMU1 PU or PD(3) OUTPUT BUFFER STRENGTH RFP PIN NO. I/O/Z(2) DESCRIPTION 84 O JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. I/O/Z Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. PU 4 mA I/O/Z Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator to connect to the device and to modify FLASH contents. PU 4 mA 83 86 4 mA PRODUCT PREVIEW TERMINAL ITM Trace (ARM® Instrumentation Trace Macrocell) TRACED0 see PF3_GPIO35 O ITM Trace data 0 4 mA TRACED1 see PG3_GPIO43 O ITM Trace data 1 4 mA TRACED2 see PF0_GPIO32 O ITM Trace data 2 4 mA TRACED3 see PF1_GPIO33 O ITM Trace data 3 4 mA TRACECLK see PF2_GPIO34 O ITM Trace clock 4 mA Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 107 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH Test Pins FLT1 16 I/O FLASH Test Pin 1. Reserved for TI. Must be left unconnected. FLT2 21 I/O FLASH Test Pin 2. Reserved for TI. Must be left unconnected. Internal Voltage Regulator Control VREG18EN 113 Internal 1.8-V VREG Enable/Disable for VDD18. Pull low to enable the internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. PD VREG12EN 101 Internal 1.2-V VREG Enable/Disable for VDD12. Pull low to enable the internal 1.2-V voltage regulator (VREG12), pull high to disable VREG12. PD Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators PRODUCT PREVIEW VDDIO 107 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 10 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 25 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 34 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 44 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 54 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 59 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 105 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 3 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 67 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 74 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 92 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 100 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 96 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 17 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 2 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. VDDIO 106 3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical) close to the pin. 108 Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME RFP PIN NO. I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH Digital Logic Power Pins (Analog Subsystem) VDD18 VDD18 1 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 2.2-µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. 108 1.8-V Digital Logic Power Pins (associated with the Analog Subsystem) - no supply needed when using internal VREG18. Tie with 2.2-µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supply-rail ramp-up time. VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 24 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 55 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 66 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 99 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 75 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 58 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. 11 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. PRODUCT PREVIEW Digital Logic Power Pins (Master and Control Subsystems) Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 109 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME VDD12 RFP PIN NO. 90 I/O/Z(2) DESCRIPTION PU or PD(3) OUTPUT BUFFER STRENGTH 1.2-V Digital Logic Power Pins - no supply needed when using internal VREG12. Tie with 470-nF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used but could impact supplyrail ramp-up time. Digital Logic Ground (Analog, Master, and Control Subsystems) VSS PWR PAD Digital Ground Power Pad (located on the bottom of the chip) No Connect Pins NC 91 No connect (1) Throughout this table, Master Subsystem signals are denoted by the color "blue"; Control Subsystem signals are denoted by the color "green"; and Analog Subsystem signals are denoted by the color "orange". (2) I = Input, O = Output, Z = High Impedance, OD = Open Drain PRODUCT PREVIEW (3) PU = Pullup, PD = Pulldown – GPIO_MUX1 pullups can be enabled or disabled by Cortex™-M3 software (disabled on reset). – GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset). – AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns. – All other pullups are always enabled (XRS, ARS, TMS, TDI, EMU0, EMU1). – All pulldowns are always enabled (VREG18EN, VREG12EN, TRST). (4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 2.11. (5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices. (6) Output from the Concerto ePWM is meant for the external ADC (if present). 110 Device Pins Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 4 Device Operating Conditions Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD18 with respect to VSS –0.3 V to 2.5 V Supply voltage range, VDD12 with respect to VSS –0.3 V to 1.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Free-Air temperature, TA –40°C to 125°C Junction temperature range, TJ (4) Storage temperature range, Tstg (1) (2) (3) (4) 4.2 –40°C to 150°C (4) –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ± 2 mA. Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.46 V Device supply voltage, Analog Subsystem, VDD18 (when internal VREG is disabled and 1.8 V is supplied externally) 1.71 1.8 1.995 Device supply voltage, Master and Control Subsystems, VDD12 (when internal VREG is disabled and 1.2 V is supplied externally) 1.14 V 0 (1) 3.14 Analog ground, VSSA High-level input voltage, VIH (3.3 V) Low-level input voltage, VIL (3.3 V) High-level output source current, VOH = VOH(MIN) , IOH Low-level output sink current, VOL = VOL(MAX), IOL Free-Air temperature, TA Junction temperature, TJ 3.3 V 3.47 V 0 Device clock frequency (system clock) (1) (2) 1.26 V Supply ground, VSS Analog supply voltage, VDDA 1.2 V 2 60 VDDIO * 0.7 VDDIO + 0.3 VSS – 0.3 VDDIO * 0.3 MHz V V All GPIO/AIO pins –4 mA Group 2 (2) –8 mA All GPIO/AIO pins 4 mA Group 2 (2) 8 mA T version –40 105 S version –40 125 Q version (Q100 qualification) –40 125 T version –40 125 S version –40 150 Q version (Q100 qualification) –40 150 °C °C VDDIO and VDDA should be maintained within approximately 0.3 V of each other. Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1, PD0_GPIO16, AIO7, AIO4. Device Operating Conditions Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 111 PRODUCT PREVIEW 4.1 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 4.3 www.ti.com Electrical Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIL IIH Input current (low level) Input current (high level) TEST CONDITIONS MIN IOH = IOH MAX VDDIO * 0.8 IOH = 50 μA VDDIO – 0.2 V IOL = IOL MAX VDDIO * 0.2 All GPIO/AIO –140 XRS pin and ARS pin –300 V VDDIO = 3.3 V, VIN = 0 V Pin with pulldown enabled VDDIO = 3.3 V, VIN = 0 V ±2 Pin with pullup enabled VDDIO = 3.3 V, VIN = VDDIO ±2 Pin with pulldown enabled VDDIO = 3.3 V, VIN = VDDIO 50 VO = VDDIO or 0 V ±2 μA 2 pF Output current, pullup or pulldown disabled CI Input capacitance VDDIO BOR trip point μA μA Falling VDDIO 2.78 VDDIO BOR hysteresis PRODUCT PREVIEW 112 MAX UNIT Pin with pullup enabled IOZ (1) TYP V 35 mV Supervisor reset release delay time Time after BOR/POR/OVR event is removed to XRS release 600 μs VREG VDD18 output Internal VREG18 on 1.8 V VREG VDD12 output Internal VREG12 on 1.2 V When the on-chip VREGs are used, their output is monitored by the POR/BOR circuits, which will reset the device should the core voltages (VDD18, VDD12) go out of range. Device Operating Conditions Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 5 Electrical Specifications 5.1 Current Consumption Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK (1) (2) VREG ENABLED TEST CONDITIONS (3) MODE IDDIO (4) TYP (5) VREG DISABLED IDDA MAX TYP (5) TBD 32 mA IDD18 IDDIO (4) IDD12 MAX TYP (5) MAX TBD 20 mA TBD TYP (5) IDDA MAX TYP (5) MAX TYP (5) MAX TBD 33 mA TBD 32 mA TBD • I2C1 • SSI1, SSI2 • UART0, UART1, UART2 • CAN0 • USB • µDMA • Timer0, Timer1 • µCRC • WDOG0, WDOG1 • Flash • Internal Oscillator 1, Internal Oscillator 2 The following C28x peripherals are exercised: Operational (RAM) • McBSP • eQEP1, eQEP2 • eCAP1, eCAP2, eCAP3, eCAP4 • SCI-A • SPI-A • I2C • DMA • VCU • FPU • Flash 445 mA 367 mA The following Analog peripherals are exercised: (1) (2) (3) (4) (5) • ADC1, ADC2 • Comparator 1, Comparator 2, Comparator 3, Comparator 4, Comparator 5, Comparator 6 Currently only typical current consumption data is available, maximum numbers will come in another release of this data sheet. The numbers in Table 5-1 are not assured at this time, and are subject to change. The following is done in a loop: • Code is running out of RAM. • All I/O pins are left unconnected. • All the communication peripherals are exercised in loop-back mode. • USB – Only logic is exercised by loading and unloading FIFO. • µDMA does memory-to-memory transfer. • DMA does memory-to-memory transfer. • VCU – CRC calculated and checked. • FPU – Float operations performed. • ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled. • Timers and Watchdog serviced. • eCAP in APWM mode generates 36.6-kHz output on 4 pins. • ADC performs continuous conversion. • FLASH is continuously read and in active state. • XCLKOUT is turned off. IDDIO current is dependent on the electrical loading on the I/O pins. The TYP numbers are applicable over room temperature and nominal voltage. Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 113 PRODUCT PREVIEW The following Cortex™-M3 peripherals are exercised: F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK(1)(2) (continued) VREG ENABLED TEST CONDITIONS (3) MODE SLEEP IDLE SLEEP STANDBY PRODUCT PREVIEW DEEP SLEEP STANDBY • PLL is on. • Cortex™-M3 CPU is not executing. • M3SSCLK is on. • C28CLKIN is on. • C28x™ CPU is not executing. • C28CPUCLK is off. • C28SYSCLK is on. • PLL is on. • Cortex™-M3 CPU is not executing. • M3SSCLK is on. • C28CLKIN is off. • C28x™ CPU is not executing. • C28CPUCLK is off. • C28SYSCLK is off. • PLL is off. • Cortex™-M3 CPU is not executing. • M3SSCLK is 32 kHz. • C28CLKIN is off. • C28x™ CPU is not executing. • C28CPUCLK is off. • C28SYSCLK is off. IDDIO (4) VREG DISABLED IDDA IDD18 IDDIO (4) IDD12 IDDA TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX TYP (5) MAX 80 mA – 315 µA – 14 mA – 51 mA – 15 mA – 315 µA – 71 mA – 210 µA – 15 mA – 42 mA – 14 mA – 205 µA – 24 mA – 200 µA – 2 mA – 19 mA – 3 mA – 195 µA – NOTE The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the device will be more than the numbers specified in the current consumption table. 5.2 Thermal Design Considerations Based on the end-application design and operational profile, the IDD12, IDD18, and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. For more details about thermal metrics and definitions, see the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). 114 Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 5.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Timing Parameter Symbology 5.3.1 Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 5.3.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. TESTER PIN ELECTRONICS 25 W Z0 = 50 W TD = 6 ns 15 W (A) DATA SHEET TIMING REFERENCE POINT DEVICE PIN TRANSMISSION LINE 20 pF (B) 20 pF OUTPUT UNDER TEST CONCERTO DEVICE A. B. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 5-1. 3.3-V Test Load Circuit Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 115 PRODUCT PREVIEW Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 5.4 www.ti.com Clock Frequencies, Requirements, and Characteristics This section provides the frequencies and timing requirements of the input clocks; PLL lock times; frequencies of the internal clocks; and the frequency and switching characteristics of the output clock. 5.4.1 Input Clock Frequency and Timing Requirements, PLL Lock Times Table 5-2 shows the frequency requirements for the input clocks to the F28M35x devices. Table 5-3 shows the input clock cycle time. Table 5-4, Table 5-5, Table 5-6, and Table 5-7 show the timing requirements for the input clocks to the F28M35x devices. Table 5-8 shows the PLL lock times for the Main PLL and the USB PLL. The Main PLL operates from the X1 or X1/X2 input clock pins, and the USB PLL operates from the XCLKIN input clock pin. Table 5-2. Input Clock Frequency MIN MAX UNIT PRODUCT PREVIEW f(OSC) Frequency, X1/X2, from external crystal or resonator 2 20 MHz f(OCI) Frequency, X1, from external oscillator (PLL enabled) 2 30 MHz f(OCI) Frequency, X1, from external oscillator (PLL disabled) 2 100 MHz f(XCI) Frequency, XCLKIN, from external oscillator 2 60 MHz UNIT Table 5-3. Input Clock Cycle Time NO. MAX MIN C1 tc(OSC) Cycle time, X1/X2, from external crystal or resonator 500 50 ns C2 tc(OCI) Cycle time, X1, from external oscillator (PLL enabled) 500 33.3 ns C2 tc(OCI) Cycle time, X1, from external oscillator (PLL disabled) 500 10 ns C3 tc(XCI) Cycle time, XCLKIN, from external oscillator 500 16.6 ns MIN MAX UNIT Table 5-4. X1 Timing Requirements - PLL Enabled (1) NO. C4 tf(OCI) Fall time, X1 6 ns C5 tr(OCI) Rise time, X1 6 ns C6 tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45 55 % C7 tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45 55 % MIN MAX (1) The possible Main PLL configuration modes are shown in Table 2-19 to Table 2-22. Table 5-5. X1 Timing Requirements - PLL Disabled NO. C4 C5 tf(OCI) tr(OCI) Fall time, X1 Rise time, X1 Up to 20 MHz 6 20 MHz to 100 MHz 2 Up to 20 MHz 6 20 MHz to 100 MHz 2 UNIT ns ns C6 tw(OCL) Pulse duration, X1 low as a percentage of tc(OCI) 45 55 % C7 tw(OCH) Pulse duration, X1 high as a percentage of tc(OCI) 45 55 % 116 Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 5-6. XCLKIN Timing Requirements - PLL Enabled (1) NO. MIN C8 tf(XCI) Fall time, XCLKIN MAX UNIT 6 ns C9 tr(XCI) Rise time, XCLKIN 6 ns C10 tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45 55 % C11 tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45 55 % MIN MAX (1) The possible USB PLL configuration modes are shown in Table 2-23 and Table 2-24. Table 5-7. XCLKIN Timing Requirements - PLL Disabled NO. C8 tf(XCI) Fall time, XCLKIN C9 tr(XCI) Rise time, XCLKIN Up to 20 MHz 6 20 MHz to 100 MHz 2 Up to 20 MHz 6 20 MHz to 100 MHz 2 UNIT ns ns C10 tw(XCL) Pulse duration, XCLKIN low as a percentage of tc(XCI) 45 55 % C11 tw(XCH) Pulse duration, XCLKIN high as a percentage of tc(XCI) 45 55 % MIN NOM MAX UNIT t(PLL) Lock time, Main PLL (X1, from external oscillator) 2000 (1) input clock cycles t(USB) Lock time, USB PLL (XCLKIN, from external oscillator) 2000 (1) input clock cycles (1) For example, if the input clock to the PLL is 10 MHz, then the PLL lock time is 100 ns x 2000 = 200 µs. 5.4.2 Internal Clock Frequencies Table 5-9 provides the clock frequencies for the internal clocks of the F28M35x devices. Table 5-9. Internal Clock Frequencies (150-MHz Devices) MIN f(USB) Frequency, USBPLLCLK f(PLL) Frequency, PLLSYSCLK 2 f(OCK) Frequency, OSCCLK f(M3C) Frequency, M3SSCLK f(ADC) f(SYS) NOM MAX 60 UNIT MHz 150 MHz 2 100 MHz 2 100 (1) MHz Frequency, ASYSCLK 2 37.5 MHz Frequency, C28SYSCLK 2 150 (1) MHz (1) MHz 150 (1) MHz f(HSP) Frequency, C28HSPCLK 2 f(LSP) Frequency, C28LSPCLK (2) 2 f(10M) Frequency, 10MHzCLK 10 MHz f(32K) Frequency, 32KHzCLK 32 kHz (1) (2) (3) 150 37.5 (3) An integer divide ratio must be maintained between the C28x and Cortex™-M3 clock frequencies. For example, when the C28x is configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex™-M3 will be 75 MHz. See Figure 2-10 and Figure 2-11 to see the internal clocks and clock divider options. Lower LSPCLK will reduce device power consumption. This is the default reset value if C28SYSCLK = 150 MHz. Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 117 PRODUCT PREVIEW Table 5-8. PLL Lock Times F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 5.4.3 www.ti.com Output Clock Frequency and Switching Characteristics Table 5-10 provides the frequency of the output clock from the F28M35x devices. Table 5-11 shows the switching characteristics of the output clock from the F28M35x devices, XCLKOUT. Table 5-10. Output Clock Frequency NO. C14 f(XCO) Frequency, XCLKOUT MIN MAX UNIT 2 37.5 MHz Table 5-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2) over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN TYP MAX UNIT C15 tf(XCO) Fall time, XCLKOUT 5 ns C16 tr(XCO) Rise time, XCLKOUT 5 ns C17 tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns C18 tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns (1) (2) A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) PRODUCT PREVIEW 118 Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 5.5 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO135, are glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. VDDIO, VDDA (3.3 V) VDD12, VDD18 X1/X2 tOSCST (B) XCLKOUT PRODUCT PREVIEW (A) User-code dependent tw(RSL1) XRS (D) Address/data valid, internal boot-ROM code execution phase Address/Data/ Control (Internal) td(EX) th(boot-mode)(C) Boot-Mode Pins User-code execution phase User-code dependent GPIO pins as input Peripheral/GPIO function Based on boot code Boot-ROM execution starts (E) I/O Pins GPIO pins as input (state depends on internal PU/PD) User-code dependent A. B. C. D. E. Upon power up, PLLSYSCLK is OSCCLK/8. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. The internal pullup or pulldown will take effect when BOR is driven high. Figure 5-2. Power-On Reset Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 119 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 5-12. Reset (XRS) Timing Requirements MIN th(boot-mode) (1) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset (1) MAX UNIT 14000tc(M3C) cycles 32tc(OCK) cycles The minimum hold time for boot mode pins is 23 times longer for silicon revision 0 devices. Table 5-13. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN tw(RSL1) Pulse duration, XRS driven by device tw(WDRS) Pulse duration, reset pulse generated by watchdog td(EX) Delay time, address/data valid after XRS high tINTOSCST Start up time, internal zero-pin oscillator tOSCST (1) On-chip crystal-oscillator start-up time (1) TYP MAX UNIT μs 600 1 512tc(OCK) cycles 32tc(OCK) cycles 3 μs 10 ms Dependent on crystal/resonator and board design. X1/X2 PRODUCT PREVIEW XCLKOUT User-Code Dependent tw(RSL2) XRS Address/Data/ Control (Internal) td(EX) User-Code Execution Boot-ROM Execution Starts Boot-Mode Pins User-Code Execution Phase Peripheral/GPIO Function GPIO Pins as Input th(boot-mode)(A) Peripheral/GPIO Function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled. Figure 5-3. Warm Reset 120 Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 5.5.1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Changing the Frequency of the Main PLL Figure 5-4 shows how to change the frequency of the Main PLL. The three steps are described below: 1. The PLL must first be placed in bypass mode (by writing to the SYSPLLCTL register) before any changes are made to the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT Register. Figure 54 shows that before being placed in bypass mode, the internal PLLSYSCLK clock was operating at 100 MHz. After entering the bypass mode, the PLLSYSCLK becomes 10 MHz, which is the frequency of OSCCLK, the input clock to the PLL 2. Once the PLL is placed in bypass mode, the SYSPLLMULT register can be modified to increase the PLLSYSCLK frequency to 150 MHz. See Figure 5-4 for the settings of the SPLLIMULT (integer) and SPLLFMULT (fractional) multiply fields of the SYSPLLMULT register for this step, and see Figure 2-8 for the functional description of the Main PLL. The PLL bypass mode must be maintained for at least 2000 OSCCLK cycles in order for the PLL to properly lock to the new frequency. 3. Finally, the SYSPLLCTL register is written to again, this time to take the PLL out of the bypass mode. Following this step, the PLLSYSCLK switches over from 10 MHz to the new frequency of 150 MHz. STEP 2 WRITE TO SYSPLLCTL REGISTER TO PUT PLL IN BYPASS MODE WRITE TO SYSPLLMULT REGISTGER TO CHANGE PLL MULTIPLIER CONFIGURATION STEP 3 WRITE TO SYSPLLCTL REGISTER TO TAKE PLL OUT OF BYPASS MODE PRODUCT PREVIEW STEP 1 PLLSYSCLK 10 MHz 100 MHz 150 MHz (MINIMUM 2000 OSCCLK CYCLES) INPUT CLK TO PLL IS OSCCLK OSCCLK BYPASSES THE PLL INPUT CLK TO PLL IS OSCCLK SYSPLLMULT REG 10 MHz 10 MHz 10 MHz SYSPLLMULT REG SPLLIMULT = 40 10 MHz x 40 = 10 MHz x 60 = SPLLIMULT = 60 SPLLFMULT = 2 400 MHz / 2 = 600MHz / 2 = SPLLFMULT = 2 PLL OUTPUT / 2 200 MHz / 2 = 300 MHz / 2 = PLL OUTPUT / 2 SYSDIVSEL = 0 100 MHz / 1 = 100 MHz / 1 = 150 MHz / 1 = SYSDIVSEL = 0 SYSDIVSEL REG 100 MHz 10 MHz 150 MHz SYSDIVSEL REG PLLSYSCLK BEFORE THE CHANGE PLLSYSCLK DURING THE CHANGE PLLSYSCLK AFTER THE CHANGE Figure 5-4. Changing the Frequency of the Main PLL Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 121 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 5.5.2 www.ti.com Power Management and Supervisory Circuit Solutions Table 5-14 lists the power management and supervisory circuit solutions for F28M35x devices. LDO selection depends on the total power consumed in the end application. Go to www.ti.com and click on Power Management for a complete list of TI power ICs or select the Power Management Selection Guide link for specific power reference designs. Table 5-14. Power Management and Supervisory Circuit Solutions SUPPLIER PRODUCT PREVIEW TYPE PART Texas Instruments DC/DC TPS62160/170 1/0.5-A, 3–17-V input, step-down converter in 2x2 QFN package Texas Instruments DC/DC TPS62140/150 2/1-A, 3–17-V input, step-down converter in 3x3 QFN package Texas Instruments LDO TPS7A8001 Low-noise, high-bandwidth PSRR, 1A low-dropout linear regulator Texas Instruments LDO TPS7A7001 2A, single-output, very-low input, adjustable low-dropout linear regulator Texas Instruments LDO/SVS TPS75005 Dual, 500-mA, low-dropout regulators and triple-voltage rail monitor Texas Instruments DC/DC LM22672/1 1/0.5-A, 4.5–42-V input SIMPLE SWITCHER®, step-down voltage regulator with features Texas Instruments DC/DC TPS54160/060 Texas Instruments Module LMZ10501 1A SIMPLE SWITCHER® Nano Module with 5.5-V maximum input voltage Texas Instruments SVS TPS386000/040 Quad supply voltage supervisors with programmable delay and watchdog timer Texas Instruments LDO TPS73719 Single-output LDO, 1-A, fixed (1.9-V), reverse-current protection Texas Instruments LDO TPS73534 Single-output LDO, 500-mA, fixed (3.4-V), low-quiescent current, low-noise, high PSRR 122 DESCRIPTION 3.5-V to 60-V input, 1.5/0.5-A step-down converter with Eco-Mode Electrical Specifications Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6 Peripheral Information and Timings 6.1 Analog and Shared Peripherals Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem. The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six Comparator + DAC (10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other analog registers, such as the ADC Configuration and Comparator Registers, are accessible by the C28x CPU only. The Digital Shared Peripherals include the Inter-Processor Communications (IPC) peripheral and the External Peripheral Interface (EPI). IPC is accessible by both CPUs; EPI is accessible by both CPUs and both DMAs. IPC is used for sending and receiving synchronization events between Master and Control subsystems to coordinate execution of software running on both processors, or exchanging of data between the two processors. EPI is used by this device to communicate with external memory and other devices. Analog-to-Digital Converter (ADC) Figure 6-1 shows the internal structure of each of the two ADC peripherals that are present on Concerto. Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read 16 result registers. The 16 ADC channels can be used independently or in pairs, based on the assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be sampled simultaneously—thereby, increasing the overall conversion performance. 6.1.1.1 Sample Mode Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential mode. Both the SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and 5 to independently perform analog-to-digital conversions with results being stored in the RESULT4 and RESULT5 registers. "Independently" means that channel 4 may use a different Start-Of-Conversion (SOC) trigger, different analog input, and different sampling window than the trigger, input, and window assigned to channel 5. The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and the SOC5CTL register is ignored. While channel 4 and channel 5 are still using dedicated analog inputs (now selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC trigger and Sampling Window, with the results being stored in the RESULT4 and RESULT5 registers. The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each sample-and-hold unit has its own mux for selecting analog inputs (see Figure 6-1). By programming the SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels, 8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous pairs). Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 123 PRODUCT PREVIEW 6.1.1 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com TRIGS(8:1) ADC_INT(8:1) INTSOCSEL1 REG INTSOCSEL2 REG ADCINT1 ACIB SOC0CTL REG ADCINT2 SOC1CTL REG ACIB (ANALOG COMMON INTERFACE BUS) SOC2CTL REG INTSEL1N2 REG INTSEL3N4 REG ADC INTERUPT CONTROL INTSEL5N6 REG INTSEL7N8 REG INTFLG REG SOCFLG REG INTFLGCLR REG SOCFRC REG INTOVF REG SOCOVF REG INTOVFCLR REG SOCOVFCLR REG SOC3CTL REG SOC4CTL REG SOCx TRIGGER CONTROL SOC5CTL REG SOC6CTL REG SOC7CTL REG SOC8CTL REG PRODUCT PREVIEW SOC9CTL REG SOCPRICTL REG EOC(15:0) SOC(15:0) AIO_MUX SAMPLEMODE REG SOC10CTL REG SOC11CTL REG SOC12CTL REG SOC13CTL REG SOC14CTL REG GPIO ADC CONTROL 4 ASEL ADC_INA0 SOC15CTL REG SHSEL SOC REGSEL ANALOG BUS 0 N/C ADC_INA2 ADC_INA3 ADC_INA4 N/C ADC_INA6 1 2 RESULT0 REG 3 RESULT1 REG 4 RESULT2 REG 5 RESULT3 REG 6 ADC_INA7 RESULT4 REG 7 A S/H A RESULT5 REG RESULT6 REG MUX 12-BIT ADC CONVERTER ADCCTL1 REG BSEL VREFLOCONV ADC_INB3 N/C 1 N/C 2 3 ADC_INB4 4 VREFLO 1 ADC_INB7 RESULT7 REG RESULT8 REG RESULT9 REG 0 ADC_INB0 STORE RESULT N/C 5 6 B S/H B RESULT10 REG RESULT11 REG ADCCTL1 REG REFTRIM REG OFFTRIM REG REV REG RESULT12 REG RESULT13 REG RESULT14 REG RESULT15 REG 7 (1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGISTER TO CONNECT TO VREFLO Figure 6-1. ADC 124 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.1.1.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Start-of-Conversion (SOC) Triggers There are eight external SOC triggers that go to each of the two ADC modules (from the Control Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers derived from End-Of-Conversion (EOC) interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1 and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-to-digital conversion priority is managed according to the state of the PRICTL register. 6.1.1.3 Analog Inputs 6.1.1.4 ADC Result Registers and EOC Interrupts Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be read by a CPU or DMA (see Figure 2-3). 6.1.2 Comparator + DAC Units Figure 6-2 shows the internal structure of the six analog Comparator + DAC units present in Concerto devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs and two B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be programmed to select the source of the B input, to enable or disable the comparator circuit, to invert comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification period (number of clock cycles). All six output signals from the six comparators can be routed out to the device pins via GPIO_MUX2 pin mux. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 125 PRODUCT PREVIEW Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group having a dedicated mux and sample-and-hold unit (see Figure 6-1). Mux A selects one of six possible analog inputs via AIO MUX. Mux B selects one of five possible analog inputs—four external inputs via AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units according to the sampling window chosen in the SOCxCTL register for the corresponding channel. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com GPIO_MUX2 AIO_MUX1 COMPA(1) COMPOUT(1) GPIO GPIO COMP1 DAC1 N/C 4 4 COMP2 COMPCTL REG COMPSOURCE COMPDACE COMPINV QUALSEL SYNCSEL 1 COMPA(2) + 10 1 COMPB(2) MUX VDDA VSSA V 10-BIT DAC2 PRODUCT PREVIEW DACVAL(8:0) DACVAL REG 0 0 COMP2 _ COMPOUT(2) 1 SYNC / QUAL 0 V = ( DACVAL * ( VDDA-VSSA ) ) / 1023 C28SYSCLK COMP = 0 WHEN VOLTAGE A < VOLTAGE B COMP = 1 WHEN VOLTAGE A > VOLTAGE B COMPSTS COMPSTS REG COMPA(3) N/C DAC3 COMP3 COMPOUT(3) 8 MUX AIO_MUX2 COMPA(4) GPIO N/C DAC4 COMP4 COMPOUT(4) 4 COMPA(5) 10 COMPB(5) DAC5 COMP5 COMPOUT(5) MUX COMPA(6) N/C DAC6 COMP6 COMPOUT(6) Figure 6-2. Comparator + DAC Units 126 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.1.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Inter-Processor Communications (IPC) The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS (1), and MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels through which the Cortex™-M3 CPU can send up to 32 events to the C28x CPU via software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event via channel 2 from Cortex™-M3 to C28x, for example, the Cortex™-M3 and C28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The handshake starts with the Cortex™-M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is ‘0’. Next, the Cortex™-M3 writes a ‘1’ into bit 2 of the MTOCIPCSET register to start the handshake. In the mean time, the C28x is continually polling the MTOCIPCSTS register while waiting for the message. As soon as the Cortex™-M3 writes ‘1’ to bit 2 of the MTOCIPCSET register, bit 2 of MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the C28x. As soon as the C28x CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should acknowledge by writing a ‘1’ to bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS register, enabling the Cortex™-M3 to send another message. Since the first four channels (bits 0, 1, 2, 3) are backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of polling to increase performance. A similar handshake is also used when sending data (not just event) from the Master Subsystem to the Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the Cortex™-M3 should first load the MTOC Message RAM with a block of data that is to be made available to the C28x. In the second additional step, the C28x should read the data before setting a bit in the MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of the message RAM. The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET, CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC IPC communication above. (1) Note that physically MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register when the Cortex™M3 CPU reads it, and as the MTOCIPCSTS register when the C28x CPU reads it. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 127 PRODUCT PREVIEW Figure 6-3 shows the internal structure of the IPC peripheral used to synchronize program execution and exchange of data between the Cortex™-M3 and the C28x CPU. IPC can be used by itself when synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating data transfers between processors. In either case, the operation of the IPC is the same. There are two independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master). F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com INTRS M3 CPU WRDATA (31:0) SET(31:0) CTOM IPC INT (3:0) NVIC STS(3:0) STS(31:0) FLG(31:0) ACK(31:0) RDDATA (31:0) M3 SYSTEM BUS M3 32 MTOC IPC CHANNELS 3 4 MTOC_CH0 MTOC_CH1 MTOC_CH2 MTOC_CH29 MTOC_CH30 MTOC_CH31 ACK FLG STS SET MTOC MTOC IPC MTOCIPCFLG REG MTOCIPCSTS REG 31 ... FLG REG 31 ... 0 STS REG 31 ... 0 ACK REG 0 C28 PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE M3 AND STS FOR THE C28 M3 1 2 SYNC HANDSHAKE FOR ONE OF 32 MTOC CHANNELS PHYSICALLY THIS IS ONE REGISTER WITH TWO DIFFERENT NAMES – FLG FOR THE C28 AND STS FOR THE M3 SYNC HANDSHAKE FOR ONE OF 32 MTOC CHANNELS 2 1 CTOMIPCSTS REG CTOMIPCSFLG REG 31 ... 0 ACK REG FLG REG 31 ... 0 STS REG SET REG 31 ... 0 MTOCIPCACK REG CTOM MTOC MTOC MSG RAM CTOMIPCSACK REG SET REG CTOM PRODUCT PREVIEW MTOCIPCSET REG CTOM IPC CTOM MSG RAM CTOMIPCSET REG STS ACK C28 3 CTOM_CH2 CTOM_CH1 CTOM_CH0 FLG CTOM_CH31 CTOM_CH30 CTOM_CH29 SET 4 32 CTOM IPC CHANNELS C28 CPU BUS RDDATA (31:0) ACK(31:0) FLG(31:0) STS(31:0) STS(3:0) MTOC IPC INT (3:0) INTRS PIE SET(31:0) WRDATA (31:0) C28x CPU Figure 6-3. Interprocessor Communications (IPC) 128 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.1.4 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 External Peripheral Interface (EPI) The External Peripheral Interface (EPI) provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation conform to standard microprocessor address/data bus protocols, while others are tailored to support a variety of fast custom interfaces, such as those communicating with fieldprogrammable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). NOTE The Control Subsystem has no direct access to EPI in silicon revision 0 devices. Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration between the Cortex™-M3 and C28x bus cycles is fixed-priority with Cortex™-M3 having higher priority than C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively stalling all Cortex™-M3 accesses during that time. Another EPI register inside the Cortex™-M3 Bus Matrix is the Memory Protection Register, which enables assignments of chip-select spaces to Cortex™-M3 or C28x EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor) that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is configurable only by the Cortex™-M3 CPU, as are all configuration registers inside the EPI peripheral. Figure 6-4 shows the EPI registers and how they relate to individual blocks within the EPI. Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO; therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes full. Read cycles can be handled in two different ways: blocking read cycles and non-blocking read cycles. Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall the CPU or DMA until the bus transaction completes. Non-blocking read cycles are triggered when a nonzero value is written into a Read Data Register. A non-zero value being written into a Read Data register triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or DMA) according to values stored inside the Read Address Register and the Read Size Register. The incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of nonblocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the other end of the NBR FIFO. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 129 PRODUCT PREVIEW The EPI peripheral can be accessed by the Cortex™-M3 CPU, the Cortex™-M3 DMA, the C28x CPU, and the C28x DMA over the high-performance AHB bus. The Cortex™-M3 CPU and the µDMA drive AHB bus cycles directly through the Cortex™-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex™-M3 Bus Matrix, but not directly. Before entering the Cortex™-M3 Bus Matrix, the native C28x CPU and DMA bus cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex™-M3 Bus Matrix, the Cortex™-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus on the way to the EPI peripheral. See Figure 6-4 to see how EPI interfaces to the Concerto Master Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com EPI 42 PINS EPI MUX GENERAL PURPOSE INTERFACE SDRAM INTERFACE HOST BUS INTERFACE GP GPIOCSEL CONFIGREG REG GP GPIOCSEL CONFIG2REG REG SDRAM GPIOCSEL CFGREG REG 4X32 WR FIFO EPI INTERRUPT PRODUCT PREVIEW INT MASK REG GPIOCSEL REG HB-16 CONFIG REG EPI CONFIG REG HB-8 GPIOCSEL CONFIG2 REG REG GPIOCSEL REGREG HB-16 CONFIG2 EPI STATUS REG 8-BIT MODE 16-BIT MODE 8X32 NBR FIFO WR FIFO CNT REG MASK INT STAT REG HB-8 GPIOCSEL CONFIGREG REG READ FIFO ALIAS 1 READ FIFO ALIAS 2 READ FIFO CNT REG READ FIFO ALIAS 3 READ FIFO ALIAS 4 RAW INT STAT REG ERR INT STAT/CLR FIFO LEVEL SEL REG READ FIFO ALIAS 5 READ FIFO REG READ FIFO ALIAS 6 INTERRUPT SOURCES READ FIFO ALIAS 7 FIFO READ (NON-BLOCKING) WRITE NON-FIFO READ (BLOCKING) GPIO_MUX1 EPI RD SIZE0 REG EPI RD ADDR0 REG EPI RD DATA0 REG EPI NON-BLOCKING ACCESS REGISTERS EPI RD SIZE0 REG EPI RD ADDR0 REG EPI RD DATA1 REG EPI CLK EPI RST BAUD RATE CONTROL AHB BUS INTERFACE AHB BUS APB BUS EPIGPIOCSEL ADDR MAP REG REG MEMORY PROTECTION LOGIC ASSIGNS CS SPACES TO C28 ONLY, M3 ONLY, OR BOTH EPI REQ EPI BAUD REG M3SSCLK M3SYSRST M3 CLOCKS RESETS MEMPROT REG M3 uDMA M3 BUS MATRIX M3 CPU NVIC EPI CHAN 20 CHAN 22 VECT# 69 FREQ GASKET MEM32 TO AHB BUS BRIDGE CONVERTS C28 CPU/DMA BUS CYCLES TO M3 AHB BUS CYCLES C28 DMA MEM32 TO AHB BUS BRIDGE INT12/INTx.6 RTWEPIREG REG RTWEPICNTR REG RTWEPIWD REG CEPISTATUS REG REAL-TIME WINDOW MODE ALLOWS UN-INTERRUPTED ACCESS TO EPI FROM C28 CPU/DMA, WHILE STALLING M3 CPU/DMA CYCLES EPI C28 CPU PIE THE M3 FREQUENCY GASKET REDUCES AHB BUS ACCESS FREQUENCY FOR C28 CPU/DMA CYCLES BY FACTOR OF 2 OR FACTOR OF 4 Figure 6-4. External Peripheral Interface (EPI) 130 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 EPI can directly interrupt the Cortex™-M3 CPU, the Cortex™-M3 uDMA, and the C28x CPU (but not the C28x DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt generation, clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex™-M3 CPU is interrupted by Nested Vectored Interrupt Controller (NVIC) vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE. During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be remapped to different addresses according to values stored in the EPI Address Map Register in conjunction with the most significant bit of the incoming address. The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the Host Bus Mode (including 8-bit and 16-bit versions). EPI General-Purpose Mode The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose Mode from the 8-bit and 16-bit Host Bus Modes. Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The slave device responding to the bus cycles may use this signal to recognize related words of data and to speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks, depending on the clocking mode used. Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. These and numerous other aspects of the General-Purpose Mode are controlled through the GeneralPurpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block. See Figure 6-5 for a snapshot of the General-Purpose Mode registers, modes, and features. For more detailed maps of the General-Purpose Mode, see Table 6-1. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 131 PRODUCT PREVIEW 6.1.4.1 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 EPI CONFIG REG www.ti.com GP CONFIG REG MODE = GEN PURP ASIZE = 3 ADDRESS RANGE DATA SIZE FRAME SIGNAL READY SIGNAL RDYEN = 1 A0 – A18 8 YES YES RDYEN = 0 A0 – A18 8 YES NO RDYEN = 1 A0 – A19 8 NO YES RDYEN = 0 A0 – A19 8 NO NO RDYEN = 1 A0 – A10 16 YES YES RDYEN = 0 A0 – A10 16 YES NO RDYEN = 1 A0 – A11 16 NO YES RDYEN = 0 A0 – A11 16 NO NO RDYEN = 1 A0 – A2 24 YES YES RDYEN = 0 A0 – A2 24 YES NO RDYEN = 1 A0 – A3 24 NO YES RDYEN = 0 A0 – A3 24 NO NO RDYEN = X N/A 32 NO NO DSIZE = 0 FRMPIN = 1 FRMPIN = 1 ASIZE = 2 DSIZE = 1 FRMPIN = 1 PRODUCT PREVIEW FRMPIN = 1 ASIZE = 1 DSIZE = 2 FRMPIN = 1 FRMPIN = 1 ASIZE = 0 DSIZE = 3 FRMPIN = X Figure 6-5. EPI General-Purpose Modes 132 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 EPI PORT NAME Accessible by Cortex™-M3 Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN General-Purpose General-Purpose General-Purpose General-Purpose Signal Signal Signal Signal (D8, A20) (D16, A12) (D24, A4) (D30, No Addr) (Available GPIOMUX_1 Muxing Choices for EPI) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 D8 D8 D8 PE0_GPIO24 EPI0S9 A1 D9 D9 D9 PE1_GPIO25 EPI0S10 A2 D10 D10 D10 PH4_GPIO52 EPI0S11 A3 D11 D11 D11 PH5_GPIO53 EPI0S12 A4 D12 D12 D12 PF4_GPIO36 EPI0S13 A5 D13 D13 D13 PG0_GPIO40 EPI0S14 A6 D14 D14 D14 PG1_GPIO41 EPI0S15 A7 D15 D15 D15 PF5_GPIO37 EPI0S16 A8 A0 D16 D16 PJ0_GPIO56 EPI0S17 A9 A1 D17 D17 PJ1_GPIO57 EPI0S18 A10 A2 D18 D18 PJ2_GPIO58 EPI0S19 A11 A3 D19 D19 PD4_GPIO20 EPI0S20 A12 A4 D29 D29 PD2_GPIO18 EPI0S21 A13 A5 D21 D21 PD3_GPIO19 EPI0S22 A14 A6 D22 D22 PB5_GPIO13 EPI0S23 A15 A7 D23 D23 PB4_GPIO12 EPI0S24 A16 A8 A0 D24 PE2_GPIO26 EPI0S25 A17 A9 A1 D25 PE3_GPIO27 EPI0S26 A18 A10 A2 D26 PH6_GPIO54 EPI0S27 A19/RDY A11/RDY A3/RDY D27 PH7_GPIO55 EPI0S28 WR WR WR D28 PD5_GPIO21 PJ4_GPIO60 EPI0S29 RD RD RD D29 PD6_GPIO22 PJ5_GPIO61 EPI0S30 FRAME FRAME FRAME D30 PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK CLK CLK D31 PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 PJ3_GPIO59 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 133 PRODUCT PREVIEW Table 6-1. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0) F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.1.4.2 www.ti.com EPI SDRAM Mode The EPI SDRAM Mode combines high performance, low cost, and low pin utilization to access up to 512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are: • Supports x16 (single data rate) SDRAM • Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb] • Includes automatic refresh and access to all banks, rows • Includes Sleep/Standby Mode to keep contents active with minimal power drain • Multiplexed address/data interface for reduced pin count See Figure 6-6 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more detailed maps of the SDRAM Mode, see Table 6-2. EPI CONFIG REG SDRAM CFG REG SDRAM SIZE DATA SIZE SIZE = 0 16 MBit 16 SIZE = 1 128 MBit 16 SIZE = 2 256 MBit 16 SIZE = 3 512 MBit 16 MODE = SDRAM PRODUCT PREVIEW Figure 6-6. EPI SDRAM Mode 134 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-2. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1) Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN (Available GPIOMUX_1 Muxing Choices for EPI) Column/Row Address Data EPI0S0 A0 D0 PH3_GPIO51 EPI0S1 A1 D1 PH2_GPIO50 EPI0S2 A2 D2 PC4_GPIO68 EPI0S3 A3 D3 PC5_GPIO69 EPI0S4 A4 D4 PC6_GPIO70 EPI0S5 A5 D5 PC7_GPIO71 EPI0S6 A6 D6 PH0_GPIO48 EPI0S7 A7 D7 PH1_GPIO49 EPI0S8 A8 D8 PE0_GPIO24 EPI0S9 A9 D9 PE1_GPIO25 EPI0S10 A10 D10 PH4_GPIO52 EPI0S11 A11 D11 PH5_GPIO53 EPI0S12 A12 D12 PF4_GPIO36 EPI0S13 BA0 D13 PG0_GPIO40 EPI0S14 BA1 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S16 DQML PJ0_GPIO56 EPI0S17 DQMH PJ1_GPIO57 EPI0S18 CAS PJ2_GPIO58 EPI0S19 RAS PD4_GPIO20 PJ3_GPIO59 EPI0S28 WE PD5_GPIO21 PJ4_GPIO60 EPI0S29 CS PD6_GPIO22 PJ5_GPIO61 EPI0S30 CKE PD7_GPIO23 PJ6_GPIO62 EPI0S31 CLK PG7_GPIO47 EPI0S20 x PD2_GPIO18 EPI0S21 x PD3_GPIO19 EPI0S22 x PB5_GPIO13 EPI0S23 x PB4_GPIO12 EPI0S24 x PE2_GPIO26 EPI0S25 x PE3_GPIO27 EPI0S26 x PH6_GPIO54 EPI0S27 x PH7_GPIO55 EPI0S32 x PF2_GPIO34 PC0_GPIO64 EPI0S33 x PF3_GPIO35 PC1_GPIO65 EPI0S34 x PE4_GPIO28 EPI0S35 x PE5_GPIO29 EPI0S36 x PB7_GPIO15 PC3_GPIO67 EPI0S37 x PB6_GPIO14 PC2_GPIO66 EPI0S38 x PF6_GPIO38 PE4_GPIO28 EPI0S39 x PG2_GPIO42 EPI0S40 x PG5_GPIO45 EPI0S41 x PG6_GPIO46 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW EPI PORT NAME Accessible by Cortex™-M3 135 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.1.4.3 www.ti.com EPI Host Bus Mode There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16). Section 6.1.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 6.1.4.3.2 discusses the EPI 16-Bit Host Bus Mode. 6.1.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence, more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip selects, and other options. These registers are the HB-8 Configuration Register and the HB-8 Configuration2 Register. See Figure 6-7 for a snapshot of HB-8 registers, modes, and features. EPI CONFIG REG HP8 CONFIG REG HB8 CONFIG2 REG MODE = HB-8 PRODUCT PREVIEW MODE = MUXED ADDRESS RANGE DATA SIZE READY SIGNAL CSCFG = ALE A0 – A27 8 NO CSCFG = 1 CS A0 – A27 8 NO CSCFG = 2 CS A0 – A26 8 NO CSCFG = ALE + 2 CS A0 – A25 8 NO MODE = NOMUX CSCFG = ALE A0 – A19 8 NO CSCFG = 1 CS A0 – A19 8 NO CSCFG = 2 CS A0 – A18 8 NO CSCFG = ALE + 2 CS A0 – A17 8 NO CSCFG = 2 CS N/A 8 NO CSCFG = ALE + 2 CS N/A 8 NO MODE = FIFO Figure 6-7. EPI 8-Bit Host Bus Mode 6.1.4.3.1.1 HB-8 Muxed Address/Data Mode The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 Chip Select (CS) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 63. 136 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-3. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Muxed (EPIHB16CFG/MODE = 0x0) EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 A8 A8 A8 A8 PE0_GPIO24 EPI0S9 A9 A9 A9 A9 PE1_GPIO25 EPI0S10 A10 A10 A10 A10 PH4_GPIO52 EPI0S11 A11 A11 A11 A11 PH5_GPIO53 EPI0S12 A12 A12 A12 A12 PF4_GPIO36 EPI0S13 A13 A13 A13 A13 PG0_GPIO40 EPI0S14 A14 A14 A14 A14 PG1_GPIO41 EPI0S15 A15 A15 A15 A15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PJ3_GPIO59 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 137 PRODUCT PREVIEW EPI PORT NAME F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 6.1.4.3.1.2 HB-8 Non-Muxed Address/Data Mode The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the NonMuxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; and 1–4 Chip Select (CS) signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see Table 6-4. Table 6-4. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) EPI PORT NAME DEVICE PIN With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 A0 A0 A0 A0 PE0_GPIO24 EPI0S9 A1 A1 A1 A1 PE1_GPIO25 EPI0S10 A2 A2 A2 A2 PH4_GPIO52 EPI0S11 A3 A3 A3 A3 PH5_GPIO53 EPI0S12 A4 A4 A4 A4 PF4_GPIO36 EPI0S13 A5 A5 A5 A5 PG0_GPIO40 EPI0S14 A6 A6 A6 A6 PG1_GPIO41 EPI0S15 A7 A7 A7 A7 PF5_GPIO37 EPI0S16 A8 A8 A8 A8 PJ0_GPIO56 EPI0S17 A9 A9 A9 A9 PJ1_GPIO57 EPI0S18 A10 A10 A10 A10 PJ2_GPIO58 EPI0S19 A11 A11 A11 A11 PD4_GPIO20 EPI0S20 A12 A12 A12 A12 PD2_GPIO18 EPI0S21 A13 A13 A13 A13 PD3_GPIO19 EPI0S22 A14 A14 A14 A14 PB5_GPIO13 EPI0S23 A15 A15 A15 A15 PB4_GPIO12 EPI0S24 A16 A16 A16 A16 PE2_GPIO26 EPI0S25 A17 A17 A17 A17 PE3_GPIO27 EPI0S26 A18 A18 A18 CS0 PH6_GPIO54 Accessible by Cortex™-M3 PRODUCT PREVIEW 138 EPI SIGNAL FUNCTION With Address Latch Enable (CSCFG = 0x0) Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PJ3_GPIO59 EPI0S27 A19 A19 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-4. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see Table 6-5. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 139 PRODUCT PREVIEW 6.1.4.3.1.3 HB-8 FIFO Mode F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 6-5. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI PORT NAME Accessible by Cortex™-M3 PRODUCT PREVIEW 140 EPI SIGNAL FUNCTION DEVICE PIN With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S8 x x PE0_GPIO24 EPI0S9 x x PE1_GPIO25 EPI0S10 x x PH4_GPIO52 EPI0S11 x x PH5_GPIO53 EPI0S12 x x PF4_GPIO36 EPI0S13 x x PG0_GPIO40 EPI0S14 x x PG1_GPIO41 EPI0S15 x x PF5_GPIO37 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S32 x x PF2_GPIO34 EPI0S31 x x PG7_GPIO47 EPI0S33 x x PF3_GPIO35 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46 Accessible by C28x Peripheral Information and Timings (Available GPIOMUX_1 Muxing Choices for EPI) PJ6_GPIO62 PJ3_GPIO59 PC0_GPIO64 PC1_GPIO65 Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.1.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence, more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the HB16 Configuration2 Register. See Figure 6-8 for a snapshot of HB-16 registers, modes, and features. EPI CONFIG REG HP16 CONFIG REG HB16 CONFIG2 REG MODE = HB-16 MODE = MUXED ADDRESS RANGE DATA SIZE READY SIGNAL CSCFG = ALE A0 – A25 16 NO CSCFG = 1 CS A0 – A25 16 NO CSCFG = 2 CS A0 – A24 16 NO CSCFG = ALE + 2 CS A0 – A23 16 NO PRODUCT PREVIEW BSEL = YES BSEL = NO CSCFG = ALE A0 – A27 16 NO CSCFG = 1 CS A0 – A27 16 NO CSCFG = 2 CS A0 – A26 16 NO CSCFG = ALE + 2 CS A0 – A25 16 NO MODE = NOMUX BSEL = YES CSCFG = ALE A0 – A9 16 NO CSCFG = 1 CS A0 – A9 16 YES CSCFG = 2 CS A0 – A8 16 YES CSCFG = ALE + 2 CS A0 – A7 16 YES CSCFG = 3 CS A0 – A16 16 YES CSCFG = 4 CS A0 – A14 16 YES BSEL = NO CSCFG = ALE A0 – A11 16 NO CSCFG = 1 CS A0 – A11 16 YES CSCFG = 2 CS A0 – A10 16 YES CSCFG = ALE + 2 CS A0 – A9 16 YES CSCFG = 3 CS A0 – A18 16 YES CSCFG = 4 CS A0 – A16 16 YES CSCFG = 2 CS N/A 16 NO CSCFG = ALE + 2 CS N/A 16 NO MODE = FIFO BSEL = DON’T CARE Figure 6-8. EPI 16-Bit Host Bus Mode Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 141 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com 6.1.4.3.2.1 HB-16 Muxed Address/Data Mode The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 Chip Select (CS) signals to enable one of four external peripherals; and two Byte Select (BSEL) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see Table 6-6. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 6-7. Table 6-6. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME DEVICE PIN With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 A24 PE2_GPIO26 EPI0S25 A25 A25 A25 A25 PE3_GPIO27 EPI0S26 A26 A26 A26 CS0 PH6_GPIO54 Accessible by Cortex™-M3 PRODUCT PREVIEW 142 EPI SIGNAL FUNCTION With Address Latch Enable (CSCFG = 0x0) Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PJ3_GPIO59 EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-6. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PRODUCT PREVIEW Accessible by Cortex™-M3 Table 6-7. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51 EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50 EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68 EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69 EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70 EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71 EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48 EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49 EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24 EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25 EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52 EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53 EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36 EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40 EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41 EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37 EPI0S16 A16 A16 A16 A16 PJ0_GPIO56 EPI0S17 A17 A17 A17 A17 PJ1_GPIO57 EPI0S18 A18 A18 A18 A18 PJ2_GPIO58 EPI0S19 A19 A19 A19 A19 PD4_GPIO20 EPI0S20 A20 A20 A20 A20 PD2_GPIO18 EPI0S21 A21 A21 A21 A21 PD3_GPIO19 EPI0S22 A22 A22 A22 A22 PB5_GPIO13 EPI0S23 A23 A23 A23 A23 PB4_GPIO12 EPI0S24 A24 A24 A24 BSEL0 PE2_GPIO26 EPI0S25 A25 A25 BSEL0 BSEL1 PE3_GPIO27 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PJ3_GPIO59 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 143 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 6-7. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S31 x x x x PG7_GPIO47 EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64 EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PRODUCT PREVIEW 6.1.4.3.2.2 HB-16 Non-Muxed Address/Data Mode The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the NonMuxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the address until the data phase); RD and WR data strobes; 1–4 Chip Select (CS) signals to enable one of four external peripherals; and two Byte Select (BSEL) signals to accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 10 additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without Byte Selects, see Table 6-8 and Table 6-9. For detailed maps of HB-16 Non-Muxed Modes with Byte Selects, see Table 6-10 and Table 6-11. 144 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 A8 PE2_GPIO26 EPI0S25 A9 A9 A9 A9 PE3_GPIO27 EPI0S26 A10 A10 A10 CS0 PH6_GPIO54 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PRODUCT PREVIEW EPI PORT NAME PJ3_GPIO59 EPI0S27 A11 A11 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 PC1_GPIO65 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 145 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 6-9. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI PORT NAME Accessible by Cortex™-M3 PRODUCT PREVIEW 146 Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN With Three Chip Selects (CSCFG = 0x7) (Available GPIOMUX_1 Muxing Choices for EPI) EPI PORT NAME Accessible by Cortex™-M3 Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN With Four Chip Selects (CSCFG = 0x5) (Available GPIOMUX_1 Muxing Choices for EPI) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 EPI0S19 A3 PD4_GPIO20 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S25 A9 PE3_GPIO27 EPI0S25 A9 PE3_GPIO27 EPI0S26 A10 PH6_GPIO54 EPI0S26 A10 PH6_GPIO54 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S40 A15 PG5_GPIO45 EPI0S35 A16 PE5_GPIO29 EPI0S41 A16 PG6_GPIO46 EPI0S40 A17 PG5_GPIO45 EPI0S30 CS0 PD7_GPIO23 EPI0S41 A18 PG6_GPIO46 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 PJ3_GPIO59 PJ6_GPIO62 Peripheral Information and Timings PJ3_GPIO59 PJ6_GPIO62 Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Table 6-10. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With Address Latch Enable (CSCFG = 0x0) With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) With ALE and Two Chip Selects (CSCFG = 0x3) EPI0S0 D0 D0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 D15 D15 PF5_GPIO37 EPI0S16 A0 A0 A0 A0 PJ0_GPIO56 EPI0S17 A1 A1 A1 A1 PJ1_GPIO57 EPI0S18 A2 A2 A2 A2 PJ2_GPIO58 EPI0S19 A3 A3 A3 A3 PD4_GPIO20 EPI0S20 A4 A4 A4 A4 PD2_GPIO18 EPI0S21 A5 A5 A5 A5 PD3_GPIO19 EPI0S22 A6 A6 A6 A6 PB5_GPIO13 EPI0S23 A7 A7 A7 A7 PB4_GPIO12 EPI0S24 A8 A8 A8 BSEL0 PE2_GPIO26 EPI0S25 A9 A9 BSEL0 BSEL1 PE3_GPIO27 EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54 EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55 EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62 EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x RDY RDY RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x x x x PG7_GPIO47 EPI0S33 x x x x PF3_GPIO35 EPI0S34 x x x x PE4_GPIO28 EPI0S35 x x x x PE5_GPIO29 EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x x x PG2_GPIO42 EPI0S40 x x x x PG5_GPIO45 EPI0S41 x x x x PG6_GPIO46 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PJ3_GPIO59 PC1_GPIO65 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback PRODUCT PREVIEW Accessible by Cortex™-M3 147 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 6-11. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3), Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0), and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7) EPI PORT NAME Accessible by Cortex™-M3 PRODUCT PREVIEW 148 Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN With Three Chip Selects (CSCFG = 0x7) (Available GPIOMUX_1 Muxing Choices for EPI) EPI PORT NAME Accessible by Cortex™-M3 Accessible by C28x EPI SIGNAL FUNCTION DEVICE PIN With Four Chip Selects (CSCFG = 0x5) (Available GPIOMUX_1 Muxing Choices for EPI) EPI0S0 D0 PH3_GPIO51 EPI0S0 D0 PH3_GPIO51 EPI0S1 D1 PH2_GPIO50 EPI0S1 D1 PH2_GPIO50 EPI0S2 D2 PC4_GPIO68 EPI0S2 D2 PC4_GPIO68 EPI0S3 D3 PC5_GPIO69 EPI0S3 D3 PC5_GPIO69 EPI0S4 D4 PC6_GPIO70 EPI0S4 D4 PC6_GPIO70 EPI0S5 D5 PC7_GPIO71 EPI0S5 D5 PC7_GPIO71 EPI0S6 D6 PH0_GPIO48 EPI0S6 D6 PH0_GPIO48 EPI0S7 D7 PH1_GPIO49 EPI0S7 D7 PH1_GPIO49 EPI0S8 D8 PE0_GPIO24 EPI0S8 D8 PE0_GPIO24 EPI0S9 D9 PE1_GPIO25 EPI0S9 D9 PE1_GPIO25 EPI0S10 D10 PH4_GPIO52 EPI0S10 D10 PH4_GPIO52 EPI0S11 D11 PH5_GPIO53 EPI0S11 D11 PH5_GPIO53 EPI0S12 D12 PF4_GPIO36 EPI0S12 D12 PF4_GPIO36 EPI0S13 D13 PG0_GPIO40 EPI0S13 D13 PG0_GPIO40 EPI0S14 D14 PG1_GPIO41 EPI0S14 D14 PG1_GPIO41 EPI0S15 D15 PF5_GPIO37 EPI0S15 D15 PF5_GPIO37 EPI0S16 A0 PJ0_GPIO56 EPI0S16 A0 PJ0_GPIO56 EPI0S17 A1 PJ1_GPIO57 EPI0S17 A1 PJ1_GPIO57 EPI0S18 A2 PJ2_GPIO58 EPI0S18 A2 PJ2_GPIO58 EPI0S19 A3 PD4_GPIO20 EPI0S19 A3 PD4_GPIO20 EPI0S20 A4 PD2_GPIO18 EPI0S20 A4 PD2_GPIO18 EPI0S21 A5 PD3_GPIO19 EPI0S21 A5 PD3_GPIO19 EPI0S22 A6 PB5_GPIO13 EPI0S22 A6 PB5_GPIO13 EPI0S23 A7 PB4_GPIO12 EPI0S23 A7 PB4_GPIO12 EPI0S24 A8 PE2_GPIO26 EPI0S24 A8 PE2_GPIO26 EPI0S40 A9 PG5_GPIO45 EPI0S40 A9 PG5_GPIO45 EPI0S41 A10 PG6_GPIO46 EPI0S41 A10 PG6_GPIO46 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S36 A11 PB7_GPIO15 PC3_GPIO67 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S37 A12 PB6_GPIO14 PC2_GPIO66 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S38 A13 PF6_GPIO38 PE4_GPIO28 EPI0S39 A14 PG2_GPIO42 EPI0S39 A14 PG2_GPIO42 EPI0S27 A15 PH7_GPIO55 EPI0S25 BSEL0 PE3_GPIO27 EPI0S35 A16 PE5_GPIO29 EPI0S26 BSEL1 PH6_GPIO54 EPI0S25 BSEL0 PE3_GPIO27 EPI0S30 CS0 PD7_GPIO23 EPI0S26 BSEL1 PH6_GPIO54 EPI0S27 CS1 PH7_GPIO55 EPI0S30 CS0 PD7_GPIO23 EPI0S34 CS2 PE4_GPIO28 EPI0S34 CS2 PE4_GPIO28 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S33 CS3 PF3_GPIO35 PC1_GPIO65 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S29 WR PD6_GPIO22 PJ5_GPIO61 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S28 RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S32 RDY PF2_GPIO34 PC0_GPIO64 EPI0S31 x PG7_GPIO47 EPI0S31 x PG7_GPIO47 EPI0S35 x PE5_GPIO29 PJ3_GPIO59 PJ6_GPIO62 Peripheral Information and Timings PJ3_GPIO59 PJ6_GPIO62 Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.1.4.3.2.3 HB-16 FIFO Mode The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 612. Table 6-12. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) EPI SIGNAL FUNCTION DEVICE PIN With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) EPI0S0 D0 D0 PH3_GPIO51 EPI0S1 D1 D1 PH2_GPIO50 EPI0S2 D2 D2 PC4_GPIO68 EPI0S3 D3 D3 PC5_GPIO69 EPI0S4 D4 D4 PC6_GPIO70 EPI0S5 D5 D5 PC7_GPIO71 EPI0S6 D6 D6 PH0_GPIO48 EPI0S7 D7 D7 PH1_GPIO49 EPI0S8 D8 D8 PE0_GPIO24 EPI0S9 D9 D9 PE1_GPIO25 EPI0S10 D10 D10 PH4_GPIO52 EPI0S11 D11 D11 PH5_GPIO53 EPI0S12 D12 D12 PF4_GPIO36 EPI0S13 D13 D13 PG0_GPIO40 EPI0S14 D14 D14 PG1_GPIO41 EPI0S15 D15 D15 PF5_GPIO37 EPI0S25 x CS1 PE3_GPIO27 EPI0S30 CS0 CS0 PD7_GPIO23 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PRODUCT PREVIEW EPI PORT NAME PJ6_GPIO62 EPI0S27 FFULL FFULL PH7_GPIO55 EPI0S26 FEMPTY FEMPTY PH6_GPIO54 EPI0S29 WR WR PD6_GPIO22 EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60 EPI0S32 x x PF2_GPIO34 PC0_GPIO64 EPI0S16 x x PJ0_GPIO56 EPI0S17 x x PJ1_GPIO57 EPI0S18 x x PJ2_GPIO58 EPI0S19 x x PD4_GPIO20 EPI0S20 x x PD2_GPIO18 EPI0S21 x x PD3_GPIO19 EPI0S22 x x PB5_GPIO13 EPI0S23 x x PB4_GPIO12 EPI0S24 x x PE2_GPIO26 EPI0S31 x x PG7_GPIO47 PJ5_GPIO61 PJ3_GPIO59 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 149 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com Table 6-12. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3), FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued) EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN With One Chip Select (CSCFG = 0x1) With Two Chip Selects (CSCFG = 0x2) EPI0S33 x x PF3_GPIO35 EPI0S34 x x PE4_GPIO28 EPI0S35 x x PE5_GPIO29 EPI0S36 x x PB7_GPIO15 PC3_GPIO67 EPI0S37 x x PB6_GPIO14 PC2_GPIO66 EPI0S38 x x PF6_GPIO38 PE4_GPIO28 EPI0S39 x x PG2_GPIO42 EPI0S40 x x PG5_GPIO45 EPI0S41 x x PG6_GPIO46 Accessible by Cortex™-M3 Accessible by C28x (Available GPIOMUX_1 Muxing Choices for EPI) PC1_GPIO65 PRODUCT PREVIEW 150 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Master Subsystem Peripherals Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the Cortex™-M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB peripherals include EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG, and a µCRC module (Cyclic Redundancy Check). The Cortex™-M3 CPU/µDMA also have access to Analog (Result Registers only) and Shared peripherals (see Section 6.1). 6.2.1 Synchronous Serial Interface (SSI) This device has four Synchronous Serial Interface (SSI) modules. Each SSI has a Master or Slave interface for synchronous serial communication with peripheral devices that have Texas Instruments™ Synchronous Serial interfaces, SPI, MICROWIRE®, or Freescale™ serial format. The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by setting the appropriate bit or bits in the SSIDMACTL register. 6.2.1.1 Bit Rate Generation The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk is defined by: SSIClk = SysClk / [CPSDVSR * (1 + SCR)] NOTE For master mode, the system clock must be at least four times faster than SSIClk, with the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times faster than SSIClk. 6.2.1.2 Transmit FIFO The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data to the FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit FIFO. If less than eight values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or an µDMA request when the FIFO is empty. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 151 PRODUCT PREVIEW Figure 6-9 shows the SSI peripheral. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com SSIxIRQ INTR M3 NVIC M3 CPU M3 CLOCKS M3SSCLK M3CLKENBx REGISTER ACCESS SSI CLOCK PRESCALER DMA CONTROL DMAxREQ M3 uDMA SSICPSR REG SSIDMACTL REG PRODUCT PREVIEW TX/RX FIFO ACCESS SSIxCLK SSITX TX FIFO ( 8 x 16 ) CONTROL / STATUS PIN SSIRX RX FIFO STAT SSICR0 REG SSICR1 REG TRANSMIT / RECEIVE LOGIC SSIDR REG SSISR REG GPIO_MUX1 TX FIFO STAT PIN SSICLK PIN RX FIFO ( 8 x 16 ) SSIFSS PIN INTxREQ SSIIM REG SSIPCELLID0 REG SSIPERIPHLD0 REG SSIPERIPHLD4 REG SSIMIS REG SSIPCELLID1 REG SSIPERIPHLD1REG SSIPERIPHLD5 REG SSIRIS REG SSIPCELLID2 REG SSIPERIPHLD2 REG SSIPERIPHLD6 REG SSIICR REG SSIPCELLID3 REG SSIPERIPHLD3 REG SSIPERIPHLD7 REG IDENTIFICATION REGISTERS INTR CONTROL Figure 6-9. SSI 152 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.1.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Receive FIFO The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 6.2.1.4 Interrupts The SSI can generate interrupts when the following conditions are observed: • Transmit FIFO service (when the transmit FIFO is half full or less) • Receive FIFO service (when the receive FIFO is half full or more) • Receive FIFO time-out • Receive FIFO overrun • End of transmission The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt service routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers. The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily. The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to complete. 6.2.1.5 Frame Formats Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. Three basic frame types can be selected: • Texas Instruments™ Synchronous Serial • Freescale™ SPI • MICROWIRE® For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive time-out indication that occurs when the receive FIFO still contains data after a time-out period. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 153 PRODUCT PREVIEW All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.2.2 www.ti.com Universal Asynchronous Receiver/Transmitter (UART) This device has five Universal Asynchronous Receiver/Transmitter (UART) modules. The CPU accesses data, control, and status information. The UART also supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not register-compatible. The UART is configured for transmit and receive via the TXE bit and the RXE bit, respectively, of the UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. Figure 6-10 shows the UART peripheral. 6.2.2.1 Baud-Rate Generation PRODUCT PREVIEW The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD, and BRDF is the fractional part, separated by a decimal place). BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. 6.2.2.2 Transmit and Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. 154 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 UARTxIRQ INTR M3 NVIC M3 CPU M3 CLOCKS M3SSCLK UARTCLKENBx REGISTER ACCESS UART UARTxCLK DMA CONTROL BAUDE RATE GENERATOR M3 uDMA UARTIBRD REG UARTDMACTL REG UARTFBRD REG TX/RX FIFO ACCESS PRODUCT PREVIEW DMAxREQ XCLK RX FIFO STAT UARTCR0 REG UARTCR1 REG UARTDR REG UARTSR REG RECEIVER RX FIFO ( 8 x 16 ) UARTIFLS REG UARTIM REG INTxREQ UARTMIS REG UARTRIS REG UARTICR REG UxTX (WITH SIR TRANSMIT ENCODER) PIN GPIO_MUX1 TX FIFO STAT TRANSMITTER TX FIFO ( 8 x 16 ) CONTROL / STATUS (WITH SIR RECEIVE DECODER) UARTPCELLID0 UARTPERIPHLD0 UARTPERIPHLD4 UARTPCELLID1 UARTPERIPHLD1 UARTPERIPHLD5 UARTPCELLID2 UARTPERIPHLD2 UARTPERIPHLD6 UARTPCELLID3 UARTPERIPHLD3 UARTPERIPHLD7 UxRX PIN IDENTIFICATION REGISTERS INTR CONTROL Figure 6-10. UART Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 155 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.2.2.3 www.ti.com Data Transmission and Reception Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL). PRODUCT PREVIEW The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later), according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word. 6.2.2.4 Interrupts The UART can generate interrupts when the following conditions are observed: • Overrun Error • Break Error • Parity Error • Framing Error • Receive Time-out • Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer) • Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register. The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register. Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the corresponding bit in the UART Interrupt Clear (UARTICR) register. The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a "1" is written to the corresponding bit in the UARTICR register. 156 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Cortex™-M3 Inter-Integrated Circut (I2C) The two Cortex™-M3 I2C modules include the following features: • Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation • Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive • Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) • Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected • Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode Figure 6-11 shows the Cortex™-M3 I2C peripheral. 6.2.3.1 Functional Overview Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals. The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 6.2.3.2 Available Speed Modes The I2C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode should match the speed of the other I2C devices on the bus. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 157 PRODUCT PREVIEW This device has two Cortex™-M3 I2C peripherals. The Cortex™-M3 Inter-Integrated Circuit (I2C) bus provides bidirectional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with other I2C devices on the bus. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 I2CxIRQ M3 NVIC www.ti.com INTR M3 CPU M3 CLOCKS M3SSCLK M3CLKENBx REGISTER ACCESS I2CxCLK I2C (M3) I2C CONTROL I2CSCL_M I2C MASTER CORE I2CMCS REG I2CMTPR REG I2CSOAR REG I2CMCR REG I2CSCSR REG I2CxSCL I2CSDA_M PIN I2C I/O SELECT I2CMDR REG I2CSDR REG I2CMIMR REG I2CSIMR REG I2CMRISREG I2CSRISREG I2CMMIS REG I2CSMIS REG I2CMICR REG I2CSICR REG I2CSCL_S I2C SLAVE CORE I2CSDA_S GPIO_MUX1 PRODUCT PREVIEW I2CMSA REG I2CxSDA PIN Figure 6-11. I2C (Cortex™-M3) 158 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.4 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Cortex™-M3 Controller Area Network (CAN) CAN implements the following features: • CAN protocol version 2.0 part A, B • Bit rates up to 1 Mbit/s • Multiple clock sources • 32 message objects • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Software module reset • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM parity check mechanism • Two interrupt lines • Global power down and wakeup support Figure 6-12 shows the Cortex™-M3 CAN peripheral. 6.2.4.1 Functional Overview CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver hardware is required for the connection to the physical layer (CAN bus). For communication on a CAN network, individual message objects can be configured. The message objects and identifier masks are stored in the Message RAM. All functions concerning the handling of messages are implemented in the message handler. Those functions are: acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests. The register set of the CAN is accessible directly by the CPU via the module interface. These registers are used to control/configure the CAN Core and the message handler, and to access the message RAM. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 159 PRODUCT PREVIEW This device has two Cortex™-M3 Controller Area Network (CAN) peripherals. CAN is a serial communications protocol that efficiently supports distributed real-time control with a high level of security. The CAN module supports bit rates up to 1 Mbit/s and is compliant with the CAN 2.0B protocol specification. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 CANxIRQ www.ti.com M3 NVIC INTR M3 CPU M3 CLOCKS M3SSCLK M3CLKENBx REGISTER ACCESS CAN (M3) CANxCLK PRODUCT PREVIEW CANxTX MODULE INTERFACE PIN MESSAGE RAM CAN CORE GPIO_MUX1 REGISTERS AND MESSAGE OBJECT ACCESS (IFX) 32 MESSAGE OBJECTS MESSAGE RAM INTERFACE CANxRX MESSAGE HANDLER PIN Figure 6-12. CAN (Cortex™-M3) 160 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.5 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Cortex™-M3 Universal Serial Bus (USB) Controller The USB controller includes the following features: • Complies with USB-IF certification standards • USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation • Integrated PHY • Four transfer types: Control, Interrupt, Bulk, and Isochronous • 32 endpoints: – One dedicated control IN endpoint and one dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints • 4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size • VBUS droop and valid ID detection and interrupt • Efficient transfers using direct memory access controller (DMA): – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data Figure 6-13 shows the USB peripheral. 6.2.5.1 Functional Description The USB controller provides full OTG negotiation by supporting both the Session Request Protocol (SRP) and the Host Negotiation Protocol (HNP). The SRP allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used after the initial session request protocol has powered the bus and provides a method to determine which end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the Host controller or the Device controller. This indication and the mode of operation are handled automatically by the USB controller. This autodetection allows the system to use a single A/B connector instead of having both A and B connectors in the system, and supports full OTG negotiations with other OTG devices. In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. NOTE When the USB is used in the system, the minimum system frequency is 20 MHz. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 161 PRODUCT PREVIEW This device has one Cortex™-M3 USB controller. The USB controller operates as a full-speed or lowspeed function controller during point-to-point communications with the USB Host, Device, or OTG functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty-two endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support multiple packet queuing. DMA access to the FIFO allows minimal interference from system software. Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller complies with the OTG standard's Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 M3 NVIC INTR www.ti.com M3 CPU M3 CLOCKS M3SSCLK USBCLKENB USBPLLCLK REGISTER ACCESS USBMAC_IRQ USB CPU INTERFACE ENDPOINT CONTROL EP REGISTER DECODER TRANSMIT PRODUCT PREVIEW EP 0-31 CONTROL USB0EPEN RECEIVE COMMON REGS PIN USB0PFLT CYCLE CONTROL HOST TRANSACTION SCHEDULER PIN COMBINE ENDPOINTS FIFO DECODER GPIO_MUX1 PHY USB0VBUS INTERRUPT CONTROL DMAxREQ M3 uDMA FIFO RAM CONTROLLER TX BUFF RX BUFF PACKET ENCODE / DECODE UTM SYNCHRONIZATION PACKET ENCODE DATA SYNC TX BUFF RX BUFF (5V TOLERANT) PIN USB0ID PACKET DECODE HNP / SRP CRC GEN/CHECK TIMERS (5V TOLERANT) PIN USB0DM PIN TX/RX FIFO ACCESS CYCLE CONTROL USB0DP PIN USBMAC REQ Figure 6-13. USB 162 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.6 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Cortex™-M3 Ethernet Media Access Controller (EMAC) The EMAC module has the following features: • Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant • Multiple operational modes – Full- and half-duplex 100-Mbps – Full- and half-duplex 10-Mbps – Power-saving and power-down modes • Highly configurable: – Programmable MAC address – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts • IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets • Efficient transfers using the Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO Figure 6-14 shows the EMAC peripheral. 6.2.6.1 Functional Overview The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the external PHY layer via an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 163 PRODUCT PREVIEW The Cortex™-M3 Ethernet Media Access Controller (EMAC) conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. This device has one Ethernet Media Access Controller. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 EMAC_IRQ www.ti.com M3 NVIC INTR M3 CPU M3 CLOCKS M3SSCLK EMACCLKENB REGISTER ACCESS EMAC MII_TXCLK DMAxREQ M3 uDMA INTR CONTROL TX/RX FIFO ACCESS RECEIVE CONTROL PIN MII_TXEN MACRIS REG PIN PRODUCT PREVIEW MACIACK REG MACRCTL REG MACIM REG MACNP REG MII_TXD(3:0) TRANSMIT FIFO PIN EMACRX_REQ EMACTX_REQ MII_CRS DATA ACCESS PIN MII_COL GPIO_MUX1 MACDDATA REG TIMER SUPPORT MACTS REG PIN MII_RXCLK TRANSMIT CONTROL MACTCTL REG PIN RECEIVE FIFO MII_RXDV PIN MACTHR REG MII_RXER MACTR REG PIN MII_RXD(3:0) INDIVIDUAL ADDRESS MII CONTROL PIN MACMCTL REG MACMDV REG MACIA0 REG MACIA1 REG MDIO_CK MACMTXD REG MACMRXD REG MADIX REG MACMAR REG PIN MDIO MDIO_D PIN Figure 6-14. EMAC 164 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.2.6.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 MII Signals The individual EMAC and MDIO signals for the MII interface are summarized in Table 6-13. TYPE (1) DESCRIPTION MII_TXCK I Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MII_TXD and MII_TXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MII_TXD[3-0] O Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MII_TXCLK and are valid only when MII_TXEN is asserted. MII_TXEN O Transmit enable. The transmit enable signal indicates that the MII_TXD pins are generating nibble data for use by the PHY. MII_TXEN is driven synchronously to MII_TXCLK. MII_COL I Collision detected. In half-duplex operation, the MII_COL pin is asserted by the PHY when the PHY detects a collision on the network. The MII_COL pin remains asserted while the collision condition persists. This signal is not necessarily synchronous to MII_TXCLK or MII_RXCLK. In full-duplex operation, the MII_COL pin is used for hardware transmit flow control. Asserting the MII_COL pin will stop packet transmissions; packets in the process of being transmitted when MII_COL is asserted will complete transmission. The MII_COL pin should be held low if hardware transmit flow control is not used. MII_CRS I Carrier sense. In half-duplex operation, the MII_CRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is deasserted when both transmit and receive are idle. This signal is not necessarily synchronous to MII_TXCLK or MII_RXCLK. In full-duplex operation, the MII_CRS pin should be held low. MII_RXCK I Receive clock. The receive clock is a continuous clock that provides the timing reference for receive operations. The MII_RXD, MII_RXDV, and MII_RXER signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MII_RXD[3-0] I Receive data. The receive data pins are a collection of four data signals comprising 4 bits of data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MII_RXCLK and are valid only when MII_RXDV is asserted. MII_RXDV I Receive data valid. The receive data valid signal indicates that the MII_RXD pins are generating nibble data for use by the EMAC. MII_RXDV is driven synchronously to MII_RXCLK. MII_RXER I Receive error. The receive error signal is asserted for one or more MII_RXCLK periods to indicate that an error was detected in the received frame. The MII_RXER signal being asserted is meaningful only during data reception when MII_RXDV is active. MDIO_CK O Management data clock. The MDIO data clock is sourced by the MDIO module on the system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control Register (CONTROL). MDIO_D I/O Management data input output. The MDIO data pin drives PHY management data into and out of the PHY by way of an access frame that consists of start-of-frame, read/write indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles, at which time the pin is an input for read operations. SIGNAL (1) I = Input, O = Output, I/O = Input/Output Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 165 PRODUCT PREVIEW Table 6-13. EMAC and MDIO Signals for MII Interface F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.3 www.ti.com Control Subsystem Peripherals Control Subsystem peripherals are accessible from the C28x CPU via the C28x Memory Bus, and from the C28x DMA via the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP). Additionally, the C28x CPU/DMA also have access to the External Peripheral Interface (EPI), and to Analog and Shared peripherals (see Section 6.1). 6.3.1 High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules There are nine PWM modules in the Concerto device. Eight of these are of the High-Resolution PWM (HRPWM) type with high-resolution control on both A and B signal outputs, and one is of the Enhanced PWM (ePWM) type. The HRPWM modules have all the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on the order of 150 ps). Figure 6-15 shows the eight HRPWM modules (PWM 1–8) and one ePWM module (PWM 9). PRODUCT PREVIEW The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1), EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x CPU). There are 9 SOCA PWM outputs and 9 SOCB PWM outputs—a pair from each PWM module. The 9 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCAO signal. The 9 SOCB outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from PWM1–PWM9 also go to the Analog Subsystem, where they can be selected to become conversion triggers to ADC modules. The nine PWM modules also drive two other sets of outputs which can interrupt the C28x CPU via the C28x PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See Figure 6-16 for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution blocks. 166 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 ANALOG SUBSYSTEM SOCA (9:1) PULSE STRETCH 32 HSPCLK CYCLES SOCAO SOCB(9:1) PULSE STRETCH 32 HSPCLK CYCLES SOCBO GPTRIP6 EPWM (9:1) A C28x DMA GPTRIP1 GPTRIP2 GPTRIP3 GPTRIP4 GPTRIP5 GPTRIP6 GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ‘0’ ECCDBLERR PIEERR TRIPIN1 TRIPIN2 TRIPIN3 TRIPIN4 TRIPIN5 TRIPIN6 TRIPIN7 TRIPIN8 TRIPIN9 TRIPIN10 TRIPIN11 TRIPIN12 TRIPIN13 TRIPIN14 TRIPIN15 PWM 1 PWM 2 PWM 3 SYNCO PWM 4 PWM 5 TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 PWM 6 PWM 7 GPTRIP1 GPTRIP2 GPTRIP3 EQEPERR CLOCKFAIL EMUSTOP PWM 9 PWM 8 EPWM (9:1) B GPIO_MUX1 EPWM TBCLKSYNC EPWM (9:1) TZINT C28X PIE PRODUCT PREVIEW SYNCI EPWM (9:1) INT SYNCO PULSE STRETCH 8 HSPCLK CYCLES SYNCO1 CPCLKCR0 REG EQEP(3:1)INT ECAP(6:1)INT SYNCI GPTRIP7 GPTRIP8 GPTRIP9 GPTRIP10 GPTRIP11 GPTRIP12 ECAP 1 ECAP1INP ECAP2INP ECAP3INP ECAP4INP ECAP5INP ECAP6INP ECAP 2 ECAP 3 EQEP 1 EQEP1A EQEP1B EQEP1S EQEP1I EQEP2A EQEP2B EQEP2S EQEP2I EQEP3A EQEP3B EQEP3S EQEP3I SYNCO EQEP 2 ECAP 4 ECAP ECAP 5 ECAP 6 EQEP EQEP3 ECAP(6:1) LEGEND: PWM 1-8 EPWM + HiRES PWM PWM 9 EPWM ONLY GPTRIP(1-12) GPIO_MUX1 ECCDBLERR C28x LOCAL RAM PIEERR SHARED RAM EMUSTOP C28x CPU EQEPERR CLOCKFAIL C28x CLOCKS Figure 6-15. PWM, eCAP, eQEP Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 167 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com C28SYSCLK TBCLKSYNC TRIPIN(15:1) SYNCO (1) SYNCI TIME BASE DCAEVT1.SYNC DCAEVT1.SOC DCBEVT1.SYNC DCBEVT1.SOC PHS (TB) TBCLK PRD DIGITAL COMPARE CTR=ZER CTR= CMPB CTR=PRD TBCTR (15:0) CTR=ZER CTR=PRD CTR_DIR TBCLK TBCTR (15:0) HiRES CONTROL PRODUCT PREVIEW DCAEVT1.SYNC COUNTER COMPARE CMPA CAL CMPB CNTRL RED (DC) FED DCBEVT1.SYNC (CC) DCAEVT1.FORCE DCAEVT2.FORCE DCBEVT1.FORCE DCBEVT2.FORCE DCAEVT1.INTER DCAEVT2.INTER DCBEVT1.INTER DCBEVT2.INTER CTR=ZER CTR=PRD EPWM_A CTR_DIR CTR=CMPA ACTION QUALIFIER DEAD BAND PWM CHOPPER TRIP ZONE HiRES PWM (AQ) (DB) (PC) (TZ) (HRPWM) CTR=CMPB EPWM_B SWFSYNC SYNCI CTR=ZER CTR=PRD C28SYSCLK CTR=CMPA CTR=CMPB CTR=CMPC CTR=CMPD DCAEVT1.SOC EVENT TRIGGER SYNCI DCBEVT1.SOC (ET) EPWM_TZINT EPWM_INT SOCA SOCB EPWM_INT (1) NOTE THAT SYNCO OUTPUTS FROM PWM MODULES 3,6 AND 9 ARE NOT CONNECTED, THUS THEY ARE NOT USEABLE TZ (6:1) Figure 6-16. Internal Structure of PWM 168 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.2 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Enhanced Capture (eCAP) Module There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module represents one complete capture channel. Its main function is to accurately capture the timings of external events. One can also use eCAP modules for PWM, when they are not being used for input captures. This secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function, the counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM) waveforms. The CAP1 and CAP2 registers become the period and compare registers, respectively; while the CAP3 and CAP4 registers become the shadow registers of the main period and capture registers, respectively. The left side of Figure 6-17 shows internal components associated with the capture block, and the right side depicts the PWM block. The two blocks share a set of four registers that are used in both Capture and PWM modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT ports to synchronize with other modules; and the Interrupt Trigger and Flag Control block that sends Capture, PWM, and Counter events to the C28x PIE block via the ECAPxINT output. There are six ECAPxINT interrupts—one for each eCAP module. PRODUCT PREVIEW The eCAP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 169 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 EPWM1 OR OTHER ECAP PERIPHERALS www.ti.com SYNCIN SYNC IN COUNTER SYNCOUT CTRPHS REG SYNC OUT TSCTR REG RST OTHER ECAP PERIPHERALS DELTA MODE CAPTURE MODE MASTER SUBSYSTEM ECAPx CTR_OVF CTR(31:0) PWM MODE LD1 POLARITY SELECT CAP1/PERIOD REG PRD(31:0) C28CLKIN LD2 PRODUCT PREVIEW POLARITY SELECT C28SYSCLK ECAPxENCLK CMP(31:0) POLARITY SELECT LD3 REGISTER ACCESS POLARITY SELECT LD4 CAP3/PER SHDW PWM COMPARE LOGIC SYSTEM CONTROL REGISTERS C28x CPU CAP2/COMP REG CAPTURE EVENT QUALIFIER 4 CAP4/CMP SHDW 4 CTR=PER EVENT PRE-SCALE CAPTURE CONTROL CEVT (4:1) (CAPTURE EVENTS) PIN GPIO_MUX1 ECAPx INTERRUPT TRIGGER AND FLAG CONTROL CTR=CMP CTR_OVF MODE SELECT ECCTL2 REG ECAPxINT C28x PIE Figure 6-17. eCAP 170 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.3 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Enhanced Quadrature Encoder Pulse (eQEP) Module The Enhanced Quadrature Encoder Pulse (eQEP) module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and position-control systems. There are three Type 0 eQEP modules in each Concerto device. Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The C28x CPU controls and communicates with these modules through a set of associated registers (see Figure 6-18). The eQEP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers. PRODUCT PREVIEW Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins are always inputs, while the other two can be inputs or outputs, depending on the operating mode. The PCCU block of each eQEP also drives one interrupt to the C28x PIE. There is a total of three EQEPxINT interrupts—one from each of the three eQEP modules. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 171 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com MASTER SUBSYSTEM EQEPx QCPRD REG QCAPCTL REG QCTMR REG 16 C28CLKIN 16 C28SYSCLK QUADRATURE CAPTURE UNIT OCTMRLAT REG QCPRDLAT REG EQEPxENCLK ( QCAP ) 16 SYSTEM CONTROL REGISTERS PRODUCT PREVIEW REGISTER ACCESS REGISTERS USED BY MULTIPLE UNITS QUTMR REG QWDTMR REG QUPRD REG QWDPRD REG 32 QEPCTL REG 16 QDECCTL REG UTOUT QEPSTS REG C28x CPU UTIME QWDOG 16 QFLG REG WDTOUT EQEPxAIN EQEPxA /XCLK PIN C28x PIE QCLK EQEPxINT QDIR QI POSITION COUNTER/CONTROL UNIT QS PHE PCSOUT QPOSSLAT REG QPOSILAT REG 16 /XDIR ( QDU ) EQEPxIIN EQEPxIOUT GPIO_MUX1 ( PCCU ) QPOSLAT REG EQEPxB EQEPxBIN QUADRATURE DECODER PIN EQEPxI EQEPxIOE 32 32 QEINT REG EQEPxSIN QPOSINIT REG QFRC REG EQEPxSOUT QPOSMAX REG QCLR REG EQEPxSOE QPOSCNT REG QPOSCMP REG PIN 16 QPOSCTL REG EQEPxS PIN Figure 6-18. eQEP 172 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.4 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 C28x Inter-Integrated Circuit Module (I2C) This device has one C28x inter-integrated circuit (I2C) peripheral. The I2C provides an interface between a Concerto device and devices compliant with the Philips® I2C-Bus Specification Version 2.1 and connected by way of an I2C Bus®. External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data to and receive 1-bit to 8-bit data from the device through the I2C module . NOTE The I2C module has the following features: • Compliance with the Philips® I2C-Bus Specification Version 2.1: – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit-and-receive and receive-and-transmit mode – Data transfer rate of from 10 Kbps up to 400 Kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable or disable capability • Free data format mode The I2C module does not support: • High-speed mode (Hs-mode) • CBUS-compatibility mode Figure 6-19 shows the C28x I2C peripheral. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 173 PRODUCT PREVIEW A unit of data transmitted or received by the I2C module can have fewer than 8 bits; however, for convenience, a unit of data is called a data byte in this section. The number of bits in a data byte is selectable via the BC bits of the mode register, I2CMDR. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com I2C (C28) MASTER SUBSYSTEM REGISTER ACCESS CLK C28CLKIN C28SYSCLK I2CA_ENCLK I2CPSC REG I2CCLK I2CCLK MASTER CLOCK DIVIDER I2CCLKH REG CLOCK PRESCALER I2CCLKL REG SYSTEM CONTROL REGISTERS SLAVE CLOCK SYNCHRONIZER I2CASCL MODE AND STATUS REGISTERS REGISTER ACCESS PIN I2CFFTX REG I2CMDR REG GPIO_MUX1 PRODUCT PREVIEW C28x CPU I2CSTR REG I2CDXR REG TX FIFO INTR I2CXSR REG I2CINT2A C28x PIE I2COAR REG I2CINT1A I2CSAR REG I2CCNT REG I2CASDA PIN I2CIER REG I2CISRC REG INTERRUPT CONTROL AND ARBITRATION I2CRXR REG I2CDRR REG RX FIFO TX/RX LOGIC I2CFFRX REG Figure 6-19. I2C (C28x) 174 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.4.1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Functional Overview Each device connected to an I2C Bus is recognized by a unique address. Each device can operate as either a transmitter or a receiver, depending on the function of the device. A device connected to the I2C Bus can also be considered as the master or the slave when performing data transfers. A master device is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. During this transfer, any device addressed by this master is considered a slave. The I2C module supports the multi-master mode, in which one or more devices capable of controlling an I2C Bus can be connected to the same I2C Bus. The I2C module consists of the following primary blocks: • A serial interface: one data pin (SDA) and one clock pin (SCL) • Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the SDA pin and the CPU • Control and status registers • A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs. 6.3.4.2 Clock Generation The device clock generator receives a signal from an external clock source and produces an I2C input clock with a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then divided twice more inside the I2C module to produce the module clock and the master clock. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 175 PRODUCT PREVIEW For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL). These two pins carry information between the C28x device and other devices connected to the I2C Bus. The SDA and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using a pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain configuration to perform the required wired-AND function. There are two major transfer techniques: 1. Standard Mode: Send exactly n data values, where n is a value you program in an I2C module register. 2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new START condition. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.3.5 www.ti.com C28x Serial Communications Interface (SCI) This device has one serial communication interface (SCI) peripheral. SCI is a two-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit baud-select register. PRODUCT PREVIEW Features of the SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates • Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits • Four error-detection flags: parity, overrun, framing, and break detection • Two wake-up multiprocessor modes: idle-line and address bit • Half- or full-duplex operation • Double-buffered receive and transmit functions • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) • Separate enable bits for transmitter and receiver interrupts (except BRKDT) • NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect. • • Auto baud-detect hardware logic 4-level transmit and receive FIFO Figure 6-20 shows the C28x SCI peripheral. 176 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 MASTER SUBSYSTEM SCI (C28) SCICTL2 REG SCICTL1A REG TX INTERRUPT LOGIC AUTO-BAUD DETECT LOGIC SCIFFTXA REG SCEFFCT REG TX FIFO TX DELAY C28SYSCLK REGISTER ACCESS SCITXBUF REG PRODUCT PREVIEW C28CLKIN SCIA_ENCLK /1 /2 /4 … /14 C28LSPCLK BAUD-RATE GEN SCITXDA TXSHF REG GPIO_MUX1 SYSTEM CONTROL REGISTERS SCIHBAUD REG SCILBAUD REG C28x CPU SCICCRA REG REGISTER ACCESS RXSHF REG PIN SCIRXDA PIN SCIRXEMUA REG SCIRXBUF REG TX/RX LOGIC RX FIFO INTR SCIFFRXA REG SCIPRI REG SCIRXINA RX INTERRUPT LOGIC C28x PIE SCRXST REG SCITXINA Figure 6-20. SCI (C28x) Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 177 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.3.5.1 www.ti.com Architecture The major elements used in full-duplex operation include: • A transmitter (TX) and its major registers: – SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be transmitted – TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto the SCITXD pin, one bit at a time • A receiver (RX) and its major registers: – RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, one bit at a time – SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU registers • A programmable baud generator • Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and FIFOs. The SCI receiver and transmitter can operate either independently or simultaneously. PRODUCT PREVIEW 6.3.5.2 Multiprocessor and Asynchronous Communication Modes The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit multiprocessor mode. These protocols allow efficient data transfer between multiple processors. The SCI offers the universal asynchronous receiver/transmitter (UART) communications mode for interfacing with many popular peripherals. The asynchronous mode requires two lines to interface with many standard devices such as terminals and printers that use RS-232-C formats. Data transmission characteristics include: • One start bit • One to eight data bits • An even/odd parity bit or no parity bit • One or two stop bits with a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then divided twice more inside the I2C module to produce the module clock and the master clock. 178 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.6 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 C28x Serial Peripheral Interface (SPI) The SPI module features include: • SPISOMI: SPI slave-output/master-input pin • SPISIMO: SPI slave-input/master-output pin • SPISTE: SPI slave transmit-enable pin • SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO, if the SPI module is not used. • Two operational modes: master and slave • Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the maximum speed of the I/O buffers used on the SPI pins. • Data word length: 1 to 16 data bits • Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. • Simultaneous receive-and-transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • Twelve SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (bits 7−0), and the upper byte (bits 15−8) is read as zeros. Writing to the upper byte has no effect. • • 16-level transmit and receive FIFO Delayed transmit control Figure 6-21 shows the C28x SPI peripheral. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 179 PRODUCT PREVIEW This device has one C28x serial peripheral interface (SPI). The serial peripheral interface (SPI) is a highspeed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-to-digital converters (ADCs). Multi-device communications are supported by the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit FIFO for reducing CPU servicing overhead. F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com MASTER SUBSYSTEM SPI (C28) TX INTERRUPT LOGIC C28CLKIN SPICTL REG SPIFFTX REG SPISIMOA SPIFFCT REG C28SYSCLK REGISTER ACCESS SPITXBUF REG TX FIFO (1) PIN TX DELAY SPISOMIA SPIA_ENCLK C28LSPCLK GPIO_MUX1 PRODUCT PREVIEW SYSTEM CONTROL REGISTERS /1 /2 /4 … /14 SPI BIT RATE SPIDAT REG SPIBRR REG PIN SPISTEA SPICCR REG PIN C28x CPU REGISTER ACCESS SPIRXBUF REG TX/RX LOGIC RX FIFO (1) SPIRXEMU REG INTR SPICLKA PIN SPIFFRX REG SPIPRI REG SPITXINA SPIST REG C28x PIE SPIRXINA RX INTERRUPT LOGIC (1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIFFENA OF THE SPIFFTX REGISTER Figure 6-21. SPI (C28x) 180 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com 6.3.6.1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Functional Overview The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive data simultaneously. The application software determines whether the data is meaningful or dummy data. There are three possible methods for data transmission: • Master sends data; slave sends dummy data • Master sends data; slave sends data • Master sends dummy data; slave sends data PRODUCT PREVIEW The master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 181 F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 6.3.7 www.ti.com C28x Multichannel Buffered Serial Port (McBSP) This device provides one high-speed multichannel buffered serial port (McBSP) that allows direct interface to codecs and other devices. The CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers. The McBSP consists of a data-flow path and a control path connected to external devices by six pins. Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for transmission and via the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization). The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers (RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows simultaneous movement of internal and external data communications. PRODUCT PREVIEW DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits. The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads instead of the CLKR and FSR pins. 182 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 McBSP features include: • Full-duplex communication • Double-buffered transmission and triple-buffered reception, allowing a continuous data stream • Independent clocking and framing for reception and transmission • The capability to send interrupts to the CPU and to send DMA events to the DMA controller • 128 channels for transmission and reception • Multichannel selection modes that enable or disable block transfers in each of the channels • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices • Support for external generation of clock signals and frame-synchronization signals • A programmable sample rate generator for internal generation and control of clock signals and frame synchronization signals • Programmable polarity for frame-synchronization pulses and clock signals • Direct interface to: – T1/E1 framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multi-phase frame capability is provided) – I2S compliant devices – SPI devices • A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits NOTE A value of the chosen data size is referred to as a serial word or word in this section. Elsewhere, word is used to describe a 16-bit value. • • • • µ-law and A-law companding The option of transmitting/receiving 8-bit data with the LSB first Status bits for flagging exception/error conditions ABIS mode is not supported Figure 6-22 shows the C28x McBSP peripheral. Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 183 PRODUCT PREVIEW www.ti.com F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com MASTER SUBSYSTEM MCBSP MCR2 REG MCR1 REG C28CLKIN C28SYSCLK REG ACCESS MCBSPA_ENCLK PRODUCT PREVIEW SYSTEM CONTROL REGISTERS /1 /2 /4 … /14 C28LSPCLK XCERA REG RCERA REG XCERB REG RCERB REG XCERC REG RCERC REG XCERD REG RCERD REG XCERE REG RCERE REG XCERF REG RCERF REG XCERG REG RCERG REG XCERH REG RCERH REG MULTI CHANNEL SELECTION (128 CHAN) PERIPH LOGIC MCLKXA SPCR2 REG SPCR1 REG PIN C28x CPU ALL REG ACCESS MFSXA XCR2 REG XCR1 REG PIN GENERATION AND CONTROL OF CLOCK AND FRAME SYNC SPCR2 REG INTR MDXA SPCR1 REG PIN SRGR1 REG GPIO_MUX1 SRGR2 REG PCR REG C28x PIE MCLKRA MXINTA MRINTA MFFINT REG RX/TX INTERRUPT LOGIC PIN MFSRA PIN DXR2 REG DXR1 REG COMPRESS DRR1 REG DRR2 REG EXPAND XSR REG C28 DMA DRR / DXR REG ACCESS RBR REG RSR REG MDRA PIN Figure 6-22. McBSP (C28x) 184 Peripheral Information and Timings Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 7 Device and Documentation Support 7.1 7.1.1 Device Support Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). The following products support development of processor applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (SYS/BIOS), which provides the basic run-time target software needed to support any processor application. For a complete listing of development-support tools for the processor platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 7.1.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all Concerto™ MCU devices and support tools. Each Concerto™ MCU commercial family member has one of three prefixes: x, p, or no prefix (for example, xF28M35H52C1RFPT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (with prefix x for devices and TMDX for tools) through fully qualified production devices/tools (with no prefix for devices and TMDS, instead of TMDX, for tools). xF28M35... Experimental device that is not necessarily representative of the final device's electrical specifications pF28M35... Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification F28M35... Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product Devices with prefix x or p and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. Device and Documentation Support Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 185 PRODUCT PREVIEW Hardware Development Tools: Extended Development System ( XDS™) Emulator F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RFP) and temperature range (for example, T). For device part numbers and further ordering information of F28M35x devices in the RFP package type, see the TI website (www.ti.com) or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU Silicon Errata (literature number SPRZ357). F28M3 x 5 5 H 2 C 1 RFP T PREFIX TEMPERATURE RANGE T = −40°C to 105°C S = −40°C to 125°C Q = −40°C to 125°C (Q refers to Q100 qualification for automotive applications.) = experimental device x = prototype device p no prefix = qualified device DEVICE FAMILY F28M3 = Concerto TM PACKAGE TYPE TM 144-Pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) SERIES NUMBER PRODUCT PREVIEW PINS 1 = 144 pins PERFORMANCE (C28x TM TM Speed / Cortex -M3 Speed) H = 150 / 75 MHz or 100 / 100 MHz M = 75 / 75 MHz E = 60 / 60 MHz PERIPHERALS C = Connectivity B = Base FLASH 2 = 256KB each core 3 = additional 256KB to one core 5 = 512KB each core A. (A) RAM 0 = 72KB 2 = additional 64KB of masterable RAM The additional 256KB is added to the Cortex™-M3 core (Connectivity Devices) or to the C28x™ core (Base Devices). Figure 7-1. Device Nomenclature 7.2 Documentation Support The following documents describe the MCU. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box. 7.3 SPRUH22 Concerto F28M35x Technical Reference Manual SPRZ357 F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU Silicon Errata Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 186 Device and Documentation Support Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 8 Mechanical Packaging and Orderable Information 8.1 Thermal Data for Package Table 8-1 shows the thermal data. See Section 5.2 for more information on thermal design considerations. Table 8-1. Thermal Model 144-Pin RFP Results AIR FLOW 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 18.8 11.5 10.0 8.6 ΨJT [°C/W] 0.3 0.2 0.3 0.3 ΨJB 4.8 4.6 4.5 4.4 θJC 6.3 θJB 4.4 Packaging Information The following packaging information and addendum reflect the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. Copyright © 2011–2012, Texas Instruments Incorporated Mechanical Packaging and Orderable Information Submit Documentation Feedback 187 PRODUCT PREVIEW 8.2 PARAMETER PACKAGE OPTION ADDENDUM www.ti.com 20-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) F28M35H20B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H20C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H22C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H32C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H50C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52B1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPQ PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPS PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI F28M35H52C1RFPT PREVIEW HTQFP RFP 144 60 TBD Call TI Call TI Addendum-Page 1 (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device XF28M35H52C1RFPT 20-Jun-2012 Status (1) ACTIVE Package Type Package Drawing HTQFP RFP Pins 144 Package Qty Eco Plan 1 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated