DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com 2-Vrms DirectPath™ Line Driver With Programmable-Fixed Gain Check for Samples: DRV612 FEATURES DESCRIPTION • The DRV612 is a single-ended, 2-Vrms stereo line driver designed to reduce component count, board space and cost. It is ideal for single-supply electronics where size and cost are critical design parameters. 1 2 • • • • • • • DirectPath™ – Eliminates Pops/Clicks – Eliminates Output DC-Blocking Capacitors – 3-V to 3.6-V Supply Voltage Low Noise and THD – SNR > 105 dB at –1× Gain – Typical Vn < 12 μVms 20 Hz–20 kHz at –1× Gain – THD+N < 0.003% at 10-kΩ Load and –1× Gain 2-Vrms Output Voltage Into 600-Ω Load Single-Ended Input and Output Programmable Gain Select Reduces Component Count – 13× Gain Values Active Mute With More Than 80 dB Attenuation Short Circuit and Thermal Protection ±8-kV HBM ESD-Protected Outputs Designed using TI’s patented DirectPath technology, which integrates a charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased output. The DRV612 is capable of driving 2 Vms into a 600-Ω load. DirectPath technology also allows the removal of the costly output dc-blocking capacitors. The device has fixed-gain single-ended inputs with a gain-select pin. Using a single resistor on this pin, the designer can choose from 13 internal programmable gain settings to match the line driver with the codec output level. It also reduces the component count and board space. Line outputs have ±8 kV HBM ESD protection, enabling a simple ESD protection circuit. The DRV612 has built-in active mute control with more that 80 dB attenuation for pop-free mute on/off control. APPLICATIONS • • • • The DRV612 does not require a power supply greater than 3.3 V to generate its 5.6-VPP output, nor does it require a split-rail power supply. PDP / LCD TV DVD Players Mini/Micro Combo Systems Soundcards The DRV612 is available in a 14-pin TSSOP and 16-pin QFN. For a footprint-compatible stereo headphone driver, see TPA6139A2 (SLOS700). DAC - LEFT + Programmable Gain SOC DAC -1x to -10x DRV612 - Line Driver RIGHT + 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION TERMINAL ASSIGNMENT The DRV612 is available in package: • 14-pin TSSOP package (PW) or 16-pin QFN package (RGT) GND 11 5 VSS VDD 10 6 CN CP 9 7 NC NC 8 2 13 MUTE OUT_L -IN_R 4 1 OUT_R 12 GND GAIN 11 3 GND GND 10 4 MUTE VDD 9 CP 12 8 GAIN 14 GND NC 3 NC 13 7 OUT_R 15 OUT_L NC 2 CN 14 6 -IN_R VSS -IN_L 5 1 RGT PACKAGE QFN (TOP VIEW) -IN_L 16 PW PACKAGE TSSOP (TOP VIEW) PIN FUNCTIONS FUNCTION (1) PIN DESCRIPTION NAME PW NO. RGT NO. -IN_L 1 16 I Negative input, left channel OUT_L 2 1 O Output, left channel 3, 11 2, 3, 10 P Ground MUTE 4 4 I MUTE, active low VSS 5 5 O Change Pump negative supply voltage CN 6 6 I/O Charge Pump flying capacitor negative connection NC 7, 8 7. 14, 15 CP 9 8 I/O VDD 10 9 P Supply voltage, connect to positive supply GAIN 12 11 I Gain set programming pin; connect a resistor to ground. See Table 1 for recommended resistor values OUT_R 13 12 O Output, right channel -IN_R 14 13 I Negative input, right channel Thermal Pad n/a Thermal Pad P Connect to ground GND (1) 2 No internal connection Charge Pump flying capacitor positive connection I = input, O = output, P = power Copyright © 2010–2011, Texas Instruments Incorporated DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com SYSTEM BLOCK DIAGRAM Current Limit Left GAIN Control De Pop Current Limit Right Charge Pump Thermal Limit Power Management ORDERING INFORMATION (1) TA –40°C to 85°C (1) PACKAGE DESCRIPTION DRV612PW 14-pin TSSOP DRV612RGT 16-pin QFN For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. THERMAL INFORMATION THERMAL METRIC (1) DRV612 DRV612 RGT (16-Pin) PW (14-Pin) θJA Junction-to-ambient thermal resistance 52 130 θJCtop Junction-to-case (top) thermal resistance 71 49 θJB Junction-to-board thermal resistance 26 63 ψJT Junction-to-top characterization parameter 3.0 3.6 ψJB Junction-to-board characterization parameter 26 62 θJCbot Junction-to-case (bottom) thermal resistance n/a n/a (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 3 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN Temperature 4 VSS – 0.3 VDD + 0.3 MUTE to GND –0.3 VDD + 0.3 Maximum operating junction temperature range, TJ –40 150 Storage temperature –65 150 VI , Input voltage Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A) (1) MAX –0.3 VDD to GND Voltage range UNIT OUT_L, OUT_R 8 All other pins 2 V °C kV Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range unless otherwise noted VDD Supply voltage DC supply voltage VIL Low-level input voltage MUTE VIH High-level input voltage MUTE TA Free-air temperature RL 4 Submit Documentation Feedback MIN NOM MAX 3.0 3.3 3.6 UNIT V 600 10k 38 40 43 %VDD 57 60 66 %VDD –0 25 85 °C Ω Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 3.3V, RLD = 5 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, unless otherwise noted. PARAMETER TEST CONDITIONS |VOS| Output offset voltage PSRR Power-supply rejection ratio VOH High-level output voltage VDD = 3.3 V VOL Low-level output voltage VDD = 3.3 V Vuvp_on VDD, undervoltage detection MIN VDD = 3.3 V, input ac-coupled 70 TYP MAX 0.5 1 80 UNIT mV dB 3.1 V –3.05 2.8 V V Vuvp_hysteresis VDD, undervoltage detection, hysteresis 200 mV FCP Charge-pump switching frequency 350 kHz |IIH| High-level input current, MUTE VDD = 3.3 V, VIH = VDD 1 |IIL| Low-level input current, MUTE VDD = 3.3 V, VIL = 0 V 1 I(VDD) Supply current, no load VDD, MUTE = 3.3 V Supply current, MUTED VDD = 3.3 V, MUTE = GND TSD Thermal shutdown Thermal shutdown hysteresis µA µA 18 mA 18 mA 150 °C 15 °C ELECTRICAL CHARACTERISTICS, LINE DRIVER VDD = 3.3 V, RLOAD = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 µF, 1× gain select (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage, outputs in phase 1% THD+N, f = 1 kHz, 10 -kΩ load 2.2 THD+N Total harmonic distortion plus noise f = 1 kHz, 10-kΩ load, VO = 2 Vrms 0.007% SNR Signal-to-noise ratio A-weighted, AES17 filter, 2 Vrms ref 105 DNR Dynamic range A-weighted, AES17 filter, 2 Vrms ref 105 dB Vn Noise voltage A-weighted, AES17 filter 12 μV Zo Output impedance when muted MUTE = GND Input-to-output attenuation when muted 1 Vrms, 1-kHz input Slew rate GBW Ilimit Unity-gain bandwidth Crosstalk – Line L-R and R-L 10-kΩ load, VO = 2 Vrms Current limit VDD = 3.3 V 0.07 Vrms dB 1 80 dB 4.5 V/μs 8 MHz –91 dB 25 mA Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 Ω 5 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com PROGRAMMABLE GAIN SETTINGS (1) (2) VDD = 3.3 V, Rload = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, 1× gain select, unless otherwise noted PARAMETER R_Tol Gain programming resistor tolerance ΔAV Gain matching TEST CONDITIONS 6 TYP MAX UNIT 2% Between left and right channels 0.25 dB 0.1 dB Gain steps Gain resistor 2% tolerance 249k or higher 82k5 51k1 34k8 27k4 20k5 15k4 11k5 9k09 7k50 6k19 5k11 4k22 A –2 –1 –1.5 –2.3 –2.5 –3 –3.5 –4 –5 –5.6 –6.4 –8.3 –10 V/V Input impedance Gain resistor 2% tolerance 249k or higher 82k5 51k1 34k8 27k4 20k5 15k4 11k5 9k09 7k50 6k19 5k11 4k22 A 37 55 44 33 31 28 24 22 18 17 15 12 10 kΩ Gain step tolerance (1) (2) MIN If the GAIN pin is left floating, an internal pullup sets the gain to –2×. Gain setting is latched during power up. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS, LINE DRIVER VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, Gain = -2V/V (unless otherwise noted) THD+N vs OUTPUT VOLTAGE 3.3 V, 10 kΩ, 1 kHz THD+N vs OUTPUT VOLTAGE 3.3 V, 600 Ω load, 1 kHz 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 5 1 0.5 0.1 0.01 0.005 0.001 40m 100m 200m 500m 1 2 VO - Output Voltage - Vrms 4 5 1 0.5 0.1 0.01 0.005 0.001 40m 100m 200m 500m 1 2 VO - Output Voltage - Vrms Figure 1. Figure 2. THD+N vs FREQUENCY 3.3 V, 10 kΩ load, 2 Vrms CHANNEL SEPARATION 3.3 V, 5 kΩ load, 2 Vrms, Blue L to R, Red R to L 4 +0 5 -10 1 -20 0.5 -30 Attenuation - dBr THD+N - Total Harmonic Distortion + Noise - % 10 0.1 3.3 V, 5 kW, 2Vrms -40 -50 -60 -70 0.01 Left to Right -80 0.005 -90 0.001 20 Right to Left 50 100 200 500 1k 2k 5k VO - Output Voltage - Vrms 20k -100 20 Blue: 10-µF ceramic ac-coupling capacitor. Red: 10-µF electrolytic ac-coupling capacitor Figure 3. 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k Figure 4. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 7 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS, LINE DRIVER (continued) VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, Gain = -2V/V (unless otherwise noted) Gain vs Frequency For the Different Gain Settings Mute to Play +22 +20 +18 +16 Gain - dBr +14 +12 +10 +8 +6 +4 +2 -0 -2 20 50 100 200 500 1k 2k 5k 10k 20k 50k f - Frequency - Hz 200k Figure 5. Figure 6. Play to Mute Figure 7. 8 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 8 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal. 9-12V Conventional solution VDD + Mute Circuit Co + + OPAMP Output VDD/2 GND MUTE 3.3V DRV 612 Solution DirectPath VDD - DRV612 Output GND VSS MUTE Figure 8. Conventional and DirectPath Line Driver The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click- and pop-reduction circuit, the DirectPath amplifier requires no output dc-blocking capacitors. The bottom block diagram and waveform of Figure 8 illustrate the ground-referenced line-driver architecture. This is the architecture of the DRV612. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 9 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com COMPONENT SELECTION Charge Pump Flying Capacitor and VSS Capacitor The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The VSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Decoupling Capacitors The DRV612 is a DirectPath line-driver amplifier that requires adequate power-supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the DRV612 is important for the performance of the amplifier. For filtering lower-frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier also helps, but it is not required in most applications because of the high PSRR of this device. Gain-Setting The gain setting is programmed with the GAIN pin. Gain setting is latched durning power on. Table 1 lists the gain settings. NOTE: If gain pin is left unconnected (open) default gain of –2× is selected. Table 1. Gain Settings Gain_set RESISTOR GAIN GAIN (dB) INPUT RESISTANCE 249 kΩ (1) –2× 6 37 kΩ 82k5 –1× 0.0 55 kΩ 51k1 –1.5× 3.5 44 kΩ 34k8 –2.3× 7.2 33 kΩ 27k4 –2.5× 8 31 kΩ 20k5 –3× 9.5 28 kΩ 15k4 –3.5× 10.9 24 kΩ 11k5 –4.0× 12 22 kΩ 9k09 –5× 14 18 kΩ 7k5 –5.6× 15 17 kΩ 6k19 –6.4× 16.1 15 kΩ 5k11 –8.3× 18.4 12 kΩ 4k22 –10× 20 10 kΩ (1) or higher Internal Undervoltage Detection The DRV612 contains an internal precision band-gap reference voltage and a comparator used to monitor the supply voltage, VDD. The internal VDD monitor is set at 2.8 V with 200-mV hysteresis. 1.25 V Bandgap AMP Enable VDD Comparator Internal VDD 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV612. These capacitors block the dc portion of the audio source and allow the DRV612 inputs to be properly biased to provide maximum performance. The input blocking capacitors also limit the dc gain to 1, limiting the dc-offset voltage at the output. These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input resistor chosen from Table 2. Then the frequency and/or capacitance can be determined when one of the two values is given. 1 1 fc IN + or C IN + 2p fc R 2p RIN C IN IN IN (1) For a fixed cutoff frequency of 2 Hz, the size of the input capacitance is shown in Table 2 with the capacitors rounded up to nearest E6 values. For 20-Hz cutoff, simply divide the capacitor values with 10; e.g., for 1× gain, 150 nF is needed. Table 2. Input Capacitor for Different Gain and Cutoff Gain_set RESISTOR GAIN Gain (dB) INPUT RESISTANCE 2 Hz Cutoff 249 kΩ –2 × 6 37 kΩ 2.2 µF 82k5 –1 × 0.0 55 kΩ 1.5 µF 51k1 –1.5× 3.5 44 kΩ 2.2 µF 34k8 –2.3× 7.2 33 kΩ 3.3 µF 27k4 –2.5× 8 31 kΩ 3.3 µF 20k5 –3× 9.5 28 kΩ 3.3 µF 15k4 –3.5× 10.9 24 kΩ 3.3 µF 11k5 –4× 12 22 kΩ 4.7 µF 9k09 –5× 14 18 kΩ 4.7 µF 7k5 –5.6× 15 17 kΩ 4.7 µF 6k19 –6.4× 16.1 15 kΩ 6.8 µF 5k11 –8.3× 18.4 12 kΩ 6.8 µF 4k22 –10× 20 10 kΩ 10 µF Pop-Free Power Up Pop-free power up is ensured by keeping the MUTE pin low during power-supply ramp-up and -down. The pins should be kept low until the input ac-coupling capacitors are fully charged before asserting the MUTE pin high, this way proper pre-charge of the ac-coupling is performed and pop-less power up is achieved. Figure 9 illustrates the preferred sequence. Supply Supply ramp MUTE _ Time for ac -coupling capasitors to charge Figure 9. Power-Up/Down Sequence Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 11 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com CAPACITIVE LOAD The DRV612 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be accepted by adding a series resistor of 47 Ω or larger for the line driver output. LAYOUT RECOMMENDATIONS A proposed layout for the DRV612 can be seen in the DRV612EVM User's Guide (SLOU248), and the Gerber files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/DRV612evm.html. To access this information, open the DRV612 product folder and look in the Tools and Software folder. Ground traces are recommended to be routed as a star ground to minimize hum interference. VDD, VSS decoupling capacitors and the charge-pump capacitors should be connected with short traces. 12 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com FOOTPRINT COMPATIBLE WITH TPA6139A2 The DRV612 stereo line driver is pin compatible with the headphone amplifier TPA6139A2. Therefore, a single PCB layout can be used with stuffing options for different board configurations. 1 14 14 DRV612 TPA6139A2 1 APPLICATION CIRCUIT 1 C11 1 2.2 mF 2 OUT_LEFT 3 4 MUTE 1 2 U11 2 5 C13 1 mF 6 7 GND -IN_L 14 -IN_R OUT_L OUT_R DRV612PW 2 IN_LEFT GND MUTE VSS GND VDD CN CP NC NC 2 IN_RIGHT C12 2.2 mF 13 OUT_RIGHT 12 GAIN 1 1 2 11 R11 10 1 9 49 kW 2 C15 1 mF GND 8 +3.3 V 1 C14 1 mF 2 13 -IN_R VDD C23 1 mF 1 +3.3 V C25 1 mF R21 49 kW GND GND 1 2 GND 1 CN 6 2 5 9 2 MUTE 10 2 14 nc GND OUT_RIGHT 11 1 4 DRV612RGT GND VSS MUTE GAIN 12 CP 3 GND IN_RIGHT C22 2.2 mF OUT_R GND 1 8 2 OUT_L nc 1 OUT_LEFT nc U21 -IN_L C21 2.2 mF 15 1 7 2 16 IN_LEFT C24 1 mF GND Figure 10. Single-Ended Input and Output, Gain Set to –1.5× Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 13 DRV612 SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 www.ti.com REVISION HISTORY Changes from Original (December 2010) to Revision A Page • Added the QFN pinout drawing ............................................................................................................................................ 2 • Added the QFN device To the PIN FUNCTIONS table ........................................................................................................ 2 • Changed the Abs Max Storage Temp From: MIN = -40 To: MIN = -65 ............................................................................... 4 • Changed the Gain resistor 2% tolerance values in the Programmable Gain Settings table For Gain Steps and Input Impedance ............................................................................................................................................................................ 6 • Changed Note 1 of the PROGRAMMABLE GAIN SETTINGS table From: If pin 12, GAIN, is left floating To: If the GAIN pin is left floating ......................................................................................................................................................... 6 • Changed From: CPUMP = C(VSS) = 10 µF To: CPUMP = C(VSS) = 1 µF in the Typical Characteristics condition text ................ 7 • Changed the Gain_set RESISTOR values in Table 1 ........................................................................................................ 10 • Changed the Gain_set RESISTOR values in Table 2 ........................................................................................................ 11 • Removed references to DRV614 from the FOOTPRINT COMPATIBLE WITH TPA6139A2 secton ................................. 13 Changes from Revision A (February 2011) to Revision B Page • Deleted the Product Preview note from the RGT package .................................................................................................. 3 • Changed RIN = 10 kΩ, Rfb = 20 kΩ To Gain = -2V/V in the Typical Characteristics condition text ...................................... 7 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :DRV612 PACKAGE OPTION ADDENDUM www.ti.com 29-Apr-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV612PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV612 DRV612PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV612 DRV612RGTR ACTIVE QFN RGT 16 3000 TBD Call TI Call TI -40 to 85 D612 DRV612RGTT ACTIVE QFN RGT 16 250 TBD Call TI Call TI -40 to 85 D612 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV612PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV612PWR TSSOP PW 14 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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