EtronTech EM565161 512K x 16 Low Power SRAM Preliminary, Rev 0.9 01/2002 Features Pin Assignment • Single Power Supply Voltage, 2.3 ~ 3.6 V • Power Down Features Using CE1#, CE2, LB# and UB# • Low Power Dissipation 48-Ball BGA (CSP), Top View 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CE2 • Data retention Supply Voltage: 1.0V to 3.6V • Direct TTL Compatibility for All Input and Output B DQ8 UB# A3 A4 CE1# DQ 0 • Wide Operating Temperature Range: -40°C to 85°C • Standby current (maximum) @ VDD = 3.6 V C DQ9 DQ 10 A5 A6 DQ1 DQ 2 D GND DQ 11 A17 A7 DQ3 VDD E VDD DQ 12 GND A16 DQ4 GND F DQ 14 DQ 13 A14 A15 DQ5 DQ 6 G DQ 15 NC A12 A13 W E# DQ 7 H A18 A8 A9 A10 A11 NC Part Number Typical IDDS2 Maximum EM565161BA/BJ-55 2 µA 35 µA EM565161BA/BJ-70 2 µA 25 µA EM565161BA/BJ-55E/70E 14 µA 80 µA Ordering Information Part Number Speed IDDS2 Package EM565161BJ-70 70 ns 25 µA 6x9 BGA EM565161BA-70 70 ns 25 µA 8x10 BGA EM565161BA-70E 70 ns 80 µA 8x10 BGA EM565161BJ-55 55 ns 35 µA 6x9 BGA Pin Names EM565161BA-55 55 ns 35 µA 8x10 BGA EM565161BA-55E 55 ns 80 µA 8x10 BGA Symbol A0 – A18 DQ0-DQ15 CE1#,CE2 OE# WE# LB#,UB# GND VDD NC Function Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Read/Write Control Input Data Byte Control Inputs Ground Power Supply No Connection Overview The EM565161 is an 8M-bit SRAM organized as 512K words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from –40°C to 85°C, the EM565161 can be used in environments exhibiting extreme temperature conditions. Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM565161 Block Diagram A0 VDD M EMO RY CELL ARRAY 5 12 k x 1 6 GND A18 D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7 SENSE AMP D Q8 D Q9 D Q1 0 D Q1 1 D Q1 2 D Q1 3 D Q1 4 D Q1 5 C OL U M N ADD R ES S D EC OD ER W E# UB# LB# OE# CE1# CE2 P OW ER D OW N C IR C UIT Preliminary 2 Rev 0.9 Jan 2002 EtronTech EM565161 Operating Mode Mode Read Write CE1# CE2 L L H H OE# L X WE# LB# UB# DQ0~DQ7 DQ8~DQ15 Power L L DOUT DOUT IDDO H L High-Z DOUT IDDO L H DOUT High-Z IDDO L L DIN DIN IDDO H L High-Z DIN IDDO L H DIN High-Z IDDO H L L H H H X X High-Z High-Z IDDO L H X X H H High-Z High-Z IDDO H X X X X X X L X X X X High-Z High-Z IDDS X X X X H H Output Disabled Standby Note:X=don’t care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD -0.3 to +4.6V Input voltages, VIN -0.3 to +4.6V Input and output voltages, VI/O -0.5 to VDD +0.5V Operating temperature, TOPR -40 to +85°C Storage temperature, TSTRG -55 to +150°C Soldering Temperature (10s), TSOLDER 240°C Power dissipation, PD Preliminary 1W 3 Rev 0.9 Jan 2002 EtronTech EM565161 DC Recommended Operating Conditions (Ta=-40°C to 85°C) Symbol Parameter Min Typ Max VDD Power Supply Voltage 2.3 3.0 3.6 VIH Input High Voltage VIL Input Low Voltage − 2.2 (2) -0.3 VDR Data Retention Supply Voltage Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns (2) Undershoot : -2.0V in case of pulse width ≤ 20ns 1.0 Unit V VDD + 0.3 − 0.6 − 3.6 (1) DC Characteristics (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) Parameter Input low current Symbol IIL Test Conditions Min IIN = 0V to VDD Typ* Max Unit -1 − 1 µA Output low voltage VOL IOL = 2.1 mA − − 0.4 V Output high voltage VOH IOH = -1.0 mA VDD – 0.15 − − V Operating current IDD1 − 12 35 Standby current CE1# = VIL and Cycle time = min CE2 = VIH and mA IDD2 IOUT = 0mA Other Input = VIH / VIL IDDS1 CE1# = VIH or CE2 = VIL Cycle time = 1µs -55 CE1# = VDD – 0.2V or IDDS2 − − 5 − − 0.3 − 2 35 mA µA UB# and LB# = VDD-0.2V or -70 − 2 25 -55E/70E − 14 80 CE2 = 0.2V Notes: * Typical value are measured at Ta = 25°C. Capacitance (Ta = 25°C; f = 1 MHz) Parameter Input capacitance Symbol Min Max Unit CIN − 8 pF VIN = GND pF VIO = GND CIO 10 − Notes: This parameter is periodically sampled and is not 100% tested. Input/Output capacitance Preliminary 4 Rev 0.9 Test Conditions Jan 2002 EtronTech EM565161 AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V) Read Cycle EM565161 Symbol -55 Parameter -70 Unit Min Max Min Max tRC Read cycle time 55 − 70 − tAA Address access time − 55 − 70 tCO1 Chip Enable (CE1#) Access Time − 55 − 70 tCO2 Chip Enable (CE2) Access Time − 55 − 70 tOE Output enable access time − 25 − 35 tBA Data Byte Control Access Time − 55 − 70 tLZ Chip Enable Low to Output in Low-Z 10 − 10 − tOLZ Output enable Low to Output in Low-Z 5 − 5 − tBLZ Data Byte Control Low to Output in Low-Z 10 − 10 − tHZ Chip Enable High to Output in High-Z − 20 − 25 tOHZ Output Enable High to Output in High-Z − 20 − 25 tBHZ Data Byte Control High to Output in High-Z − 20 − 25 tOH Output Data Hold Time 10 − 10 − ns Write Cycle EM565161 Symbol -55 Parameter -70 Unit Min Max Min Max tWC Write cycle time 55 − 70 − tWP Write pulse width 45 − 55 − tCW Chip Enable to end of write 45 − 60 − tBW Data Byte Control to end of Write 45 − 60 − tAS Address setup time 0 − 0 − tWR Write Recovery time 0 − 0 − tWHZ WE# Low to Output in High-Z − 20 − 20 tOW WE# High to Output in Low-Z 5 − 5 − tDS Data Setup Time 25 − 30 − tDH Data Hold Time 0 − 0 − ns AC Test Condition • Output load : 60pF + one TTL gate • Input pulse level : 0.4V, 2.4V • Timing measurements : 0.5 x VDD • tR, tF : 5ns Preliminary 5 Rev 0.9 Jan 2002 EtronTech EM565161 Read Cycle (See Note 1) tR C Address tO H tA A tC O 1 CE1# CE2 tC O 2 tH Z tO E OE# tO H Z tB A UB # , LB# tB L Z tB H Z tO L Z tL Z DOUT Preliminary V A L ID D A T A O U T 6 Rev 0.9 Jan 2002 EtronTech EM565161 Write Cycle1 (WE# Controlled)(See Note 4) tW C Address tA S tW P tW R W E# tC W CE1# CE2 tC W tB W UB# , LB# tW H Z DOUT tO W (S e e N o te 2 ) (S e e N o te 3 ) tD S D IN Preliminary V A L ID D A T A IN (S e e N ote 5 ) 7 Rev 0.9 tD H (S e e N ote 5 ) Jan 2002 EtronTech EM565161 Write Cycle 2 (CE1# Controlled)(See Note 4) tW C A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tBW UB# , LB# tB L Z tW H Z DOUT tL Z tD S D IN Preliminary (S e e N o te 5 ) tD H V A L ID D A T A IN 8 Rev 0.9 Jan 2002 EtronTech EM565161 Write Cycle 3 (CE2 Controlled)(See Note 4) tW C A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tW H Z DOUT tL Z tD S D IN Preliminary (S e e N o te 5 ) tD H V A L ID D A T A IN 9 Rev 0.9 Jan 2002 EtronTech EM565161 Write Cycle4 (UB#, LB# Controlled)(See Note 4) tW C A ddres s tAS tW P tW R W E# tC W CE1# CE2 tC W tBW UB# , LB# tB L Z tW H Z DOUT tL Z tD S D IN (S e e N o te 5 ) tD H V A L ID D A T A IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 0.9 Jan 2002 EtronTech EM565161 Data Retention Characteristics (Ta = -40°C to 85°C) Symbol Parameter Min Typ Max Unit 1.0 − 3.6 V 0 − − ns tRC − − ns CE1# ≥ VDD – 0.2V VDR Data Retention Supply Voltage or UB# = LB# ≥ VDD – 0.2V or CE2 ≤ 0.2V, VIN ≥ VDD – 0.2V or VIN ≤ 0.2V tSDR Chip Deselect to Data Retention Mode Time tRDR Recovery Time CE1# or UB#/LB# Controlled Data Retention Mode tS D R D a ta R e te n tio n M o d e tR D R VDD 2 .7 V 2 .2 V VDR N o te 1 CE1#, U B # /L B # GND CE2 Controlled Data Retention Mode Data Reten tion M ode VDD 2.7 V CE2 tRD R tSDR VDR 0.4 V Note 2 GND Note: 1. CE1# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V 2. CE2 ≤ 0.2V Preliminary 11 Rev 0.9 Jan 2002 EtronTech EM565161 Package Diagrams 48-Ball (8mm x 10mm) BGA Units in mm BO T T O M V IE W T O P VIEW 2 C 0.25 S C 0.30 P IN 1 C O R N E R 1 0.10 S 3 4 5 6 6 5 4 P IN 1 C O R N E R A B 0.05(48X) 3 2 1 A B B C C D D 10 .0 E 0.1 5.25 A F 0.75 F E G G H H -B 0.75 0.52 0.02 3.75 -A 8.0 0.03 D D 0.23 -C - 0.1 0.20(4X) 0.15 SE AT IN G PLA NE 0.36 0.02 0.05 1.20 MA X Preliminary 12 Rev 0.9 Jan 2002 EtronTech EM565161 Package Diagrams 48-Ball (6mm x 9mm) BGA Units in mm T O P V IE W BOT TO M VIEW 0.10 S C P IN 1 C O R N E R 0.25 S C A 0 .3 0 (4 8 X ) P IN 1 C O R N E R 6 1 2 3 4 5 6 B 5 4 3 2 1 7 8 9 10 11 12 L -B0 .7 5 3 .7 5 -A0 . 2 0 (4 X ) 0 .1 0 -C - Preliminary SEA TING P LA NE 13 Rev 0.9 Jan 2002