Elpida EDD2516AETA-7B-E 256m bits ddr sdram Datasheet

DATA SHEET
256M bits DDR SDRAM
EDD2508AETA (32M words × 8 bits)
EDD2516AETA (16M words × 16 bits)
Specifications
Features
• Density: 256M bits
• Organization
 8M words × 8 bits × 4 banks (EDD2508AETA)
 4M words × 16 bits × 4 banks (EDD2516AETA)
• Package: 66-pin plastic TSOP (II)
 Lead-free (RoHS compliant)
• Power supply:
 DDR400:
VDD, VDDQ = 2.6V ± 0.1V
 DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 400Mbps/333Mbps/266Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
 Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5, 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
 Average refresh period: 7.8µs
• Operating ambient temperature range
 TA = 0°C to +70°C
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E0859E50 (Ver. 5.0)
Date Published September 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007
EDD2508AETA, EDD2516AETA
Ordering Information
Part number
EDD2508AETA-5B-E
EDD2508AETA-5C-E
Mask
version
E
Organization
(words × bits)
32M × 8
Internal
banks
4
EDD2508AETA-6B-E
EDD2508AETA-7A-E
EDD2508AETA-7B-E
EDD2516AETA-5B-E
EDD2516AETA-5C-E
Data rate
Mbps (max.)
JEDEC speed bin
(CL-tRCD-tRP)
Package
400
DDR400B (3-3-3)
DDR400C (3-4-4)
66-pin Plastic
TSOP (II)
333
DDR333B (2.5-3-3)
266
16M × 16
400
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR400B (3-3-3)
DDR400C (3-4-4)
EDD2516AETA-6B-E
333
DDR333B (2.5-3-3)
EDD2516AETA-7A-E
EDD2516AETA-7B-E
266
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Part Number
E D D 25 08 A E TA - 5B - E
Elpida Memory
Type
D: Monolithic Device
Environment Code
E: Lead Free
(RoHS compliant)
Product Family
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Organization
08: x8
16: x16
Power Supply, Interface
A: 2.5V, SSTL_2
Package
TA: TSOP (II)
Die Rev.
Speed Grade Compatibility
Operating Frequencies
Speed bin
CL2
CL2.5
CL3
DDR400B
133MHz
166MHz
200MHz
DDR400C
133MHz
166MHz
200MHz
DDR333B
133MHz
166MHz
166MHz
DDR266A
133MHz
133MHz
133MHz
DDR266B
100MHz
133MHz
133MHz
Data Sheet E0859E50 (Ver. 5.0)
2
EDD2508AETA, EDD2516AETA
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
VDD
DQ0
DQ0
VDDQ VDDQ
NC
DQ1
DQ1
DQ2
VSSQ VSSQ
NC
DQ3
DQ2
DQ4
VDDQ VDDQ
NC
DQ5
DQ3
DQ6
VSSQ VSSQ
NC
DQ7
NC
NC
VDDQ VDDQ
NC LDQS
NC
NC
VDD
VDD
NC
NC
NC
LDM
/WE
/WE
/CAS
/CAS
/RAS
/RAS
/CS
/CS
NC
NC
BA0
BA0
BA1
BA1
A10(AP) A10(AP)
A0
A0
A1
A1
A2
A2
A3
A3
VDD
VDD
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC
NC
VSSQ VSSQ
UDQS DQS
NC
NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK
CK
CKE CKE
NC
NC
A12 A12
A11 A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS VSS
X 16
X8
(Top view)
Pin name
Function
Pin name
Function
A0 to A12
Address inputs
CK
Clock input
BA0, BA1
Bank select address
/CK
Differential Clock input
DQ0 to DQ15
Data-input/output
CKE
Clock enable
DQS, LDQS, UDQS
Input and output data strobe
VREF
Input reference voltage
/CS
Chip select
VDD
Power for internal circuit
/RAS
Row address strobe command
VSS
Ground for internal circuit
/CAS
Column address strobe command
VDDQ
Power for DQ circuit
/WE
Write enable
VSSQ
Ground for DQ circuit
DM, UDM, LDM
Input mask
NC
No connection
Data Sheet E0859E50 (Ver. 5.0)
3
EDD2508AETA, EDD2516AETA
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Speed Grade Compatibility............................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................13
Pin Function.................................................................................................................................................14
Command Operation ...................................................................................................................................16
Simplified State Diagram .............................................................................................................................23
Operation of the DDR SDRAM ....................................................................................................................24
Timing Waveforms.......................................................................................................................................43
Package Drawing ........................................................................................................................................49
Recommended Soldering Conditions..........................................................................................................50
Data Sheet E0859E50 (Ver. 5.0)
4
EDD2508AETA, EDD2516AETA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VT
–1.0 to +3.6
V
Supply voltage relative to VSS
VDD
–1.0 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
Parameter
Symbol
Speed
min.
typ.
max.
Unit
Notes
Supply voltage
VDD,VDDQ
DDR400
2.5
2.6
2.7
V
1
VDD, VDDQ
DDR333, 266
1
2.3
2.5
2.7
V
VSS,
VSSQ
0
0
0
V
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ
0.51 × VDDQ
V
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V
3
–0.3
—
VDDQ + 0.3
V
4
0.5 × VDDQ −
0.2V
0.5 × VDDQ
0.5 × VDDQ +
0.2V
V
0.36
—
VDDQ + 0.6
V
Input voltage level,
VIN (DC)
CK and /CK inputs
Input differential cross point
VIX (DC)
voltage, CK and /CK inputs
Input differential voltage,
VID (DC)
CK and /CK inputs
Notes: 1.
2.
3.
4.
5.
6.
5, 6
VDDQ must be lower than or equal to VDD.
VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (DC) specifies the allowable DC excursion of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0859E50 (Ver. 5.0)
5
EDD2508AETA, EDD2516AETA
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
Parameter
Symbol
Grade
max.
Unit
Operating current (ACT-PRE)
IDD0
110
mA
Operating current
(ACT-READ-PRE)
IDD1
140
mA
5
mA
Idle power down standby current IDD2P
Floating idle standby current
IDD2F
35
mA
Quiet idle standby current
IDD2Q
35
mA
Active power down standby
current
IDD3P
30
mA
Active standby current
IDD3N
80
mA
IDD4R
215
mA
IDD4W
215
mA
Auto-refresh current
IDD5
225
mA
Self-refresh current
IDD6
5
mA
Operating current
(4 banks interleaving)
IDD7A
350
mA
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Test condition
CKE ≥ VIH,
tRC = tRC (min.)
CKE ≥ VIH, BL = 4,CL = 3,
tRC = tRC (min.)
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 3
CKE ≥ VIH, BL = 2,
CL = 3
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
BL = 4
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
Grade
max.
Operating current (ACT-PRE)
IDD0
-6B
-7A, -7B
Operating current
(ACT-READ-PRE)
IDD1
-6B
-7A, -7B
100
90
130
120
Idle power down standby current IDD2P
Unit
Test condition
Notes
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
mA
CKE ≥ VIH, BL = 4,
CL = 2.5, tRC = tRC (min.)
1, 2, 5
mA
CKE ≤ VIL
4
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 5
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 10
mA
CKE ≤ VIL
3
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
5
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
300
250
mA
BL = 4
5
Floating idle standby current
IDD2F
-6B
-7A, -7B
Quiet idle standby current
IDD2Q
-6B
-7A, -7B
Active power down standby
current
IDD3P
Active standby current
IDD3N
-6B
-7A, -7B
Operating current
(Burst read operation)
IDD4R
-6B
-7A, -7B
Operating current
(Burst write operation)
IDD4W
-6B
-7A, -7B
Auto-refresh current
IDD5
-6B
-7A, -7B
Self-refresh current
IDD6
Operating current
(4 banks interleaving)
IDD7A
35
30
30
25
30
-6B
-7A, -7B
75
70
185
155
185
155
200
175
Data Sheet E0859E50 (Ver. 5.0)
6
5, 6, 7
EDD2508AETA, EDD2516AETA
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–2
2
µA
VDD ≥ VIN ≥ VSS
Output leakage current
ILO
–5
5
µA
VDDQ ≥ VOUT ≥ VSS
Output high current
IOH
–15.2
—
mA
VOUT = 1.95V
Output low current
IOL
15.2
—
mA
VOUT = 0.35V
Note
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
Pins
min.
typ.
max.
Unit
Input capacitance
CI1
CK, /CK
2.0
—
3.0
pF
1
CI2
All other input pins
2.0
—
3.0
pF
1
Delta input capacitance
Cdi1
CK, /CK
—
—
0.25
pF
1
Cdi2
All other input-only pins
—
—
0.5
pF
1
Data input/output capacitance
CI/O
DQ, DM, DQS
4.0
—
5
pF
1, 2
Delta input/output capacitance
Cdio
DQ, DM, DQS
—
—
0.5
pF
1
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. DOUT circuits are disabled.
Data Sheet E0859E50 (Ver. 5.0)
7
Notes
EDD2508AETA, EDD2516AETA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
-5B
-5C
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Clock cycle time
tCK
5
8
5
8
ns
10
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from CK, /CK
tAC
–0.7
0.7
–0.7
0.7
ns
2, 11
DQS output access time from CK, /CK
tDQSCK
–0.55
0.55
–0.55
0.55
ns
2, 11
DQS to DQ skew
tDQSQ
—
0.4
—
0.4
ns
3
CK half period
DQ/DQS output hold time from DQS
tQH
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.5
—
0.5
ns
tHZ
—
0.7
—
0.7
ns
5, 11
tLZ
–0.7
0.7
–0.7
0.7
ns
6, 11
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time
from CK, /CK
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.4
—
0.4
—
ns
8
DQ and DM input hold time
tDH
0.4
—
0.4
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
0.72
1.28
0.72
1.28
tCK
Write command to first DQS latching transition tDQSS
9
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
tCK
Address and control input setup time
tIS
0.6
—
0.6
—
ns
8
Address and control input hold time
tIH
0.6
—
0.6
—
ns
8
7
Address and control input pulse width
tIPW
2.2
—
2.2
—
ns
Mode register set command cycle time
tMRD
2
—
2
—
tCK
Active to Precharge command period
tRAS
40
120000
40
120000
ns
Active to Active/Auto-refresh command period tRC
55
—
60
—
ns
Auto-refresh to Active/Auto-refresh command
period
tRFC
70
—
70
—
ns
Active to Read/Write delay
tRCD
15
—
18
—
ns
Precharge to active command period
tRP
15
—
18
—
ns
Active to Autoprecharge delay
tRAP
tRCD min.
—
tRCD min.
—
ns
Active to active command period
tRRD
10
—
10
—
ns
Write recovery time
tWR
15
—
15
—
ns
Auto precharge write recovery and precharge
time
tDAL
(tWR/tCK)+
—
(tRP/tCK)
(tWR/tCK)+
—
(tRP/tCK)
tCK
Internal write to Read command delay
tWTR
2
—
2
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
µs
Data Sheet E0859E50 (Ver. 5.0)
8
13
EDD2508AETA, EDD2516AETA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
-6B
Parameter
Symbol
min.
Clock cycle time
(CL = 2)
tCK
7.5
-7A
-7B
max.
min.
max
min.
max.
Unit Notes
12
7.5
12
10
12
ns
(CL = 2.5)
tCK
6
12
7.5
12
7.5
12
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
CK half period
DQ output access time from CK, /CK tAC
10
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
2, 11
DQS output access time from CK,
/CK
tDQSCK –0.6
0.6
–0.75
0.75
–0.75
0.75
ns
2, 11
DQS to DQ skew
tDQSQ
0.45
—
0.5
—
0.5
ns
3
—
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
ns
tHZ
—
0.7
—
0.75
—
0.75
ns
5, 11
tLZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input hold time
tDH
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
0.25
—
tCK
Write postamble
tWPST
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching
tDQSS
transition
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
tCK
Address and control input setup time tIS
0.75
—
0.9
—
0.9
—
ns
8
Address and control input hold time
tIH
0.75
—
0.9
—
0.9
—
ns
8
tIPW
2.2
—
2.2
—
2.2
—
ns
7
tMRD
2
—
2
—
2
—
tCK
42
120000
45
120000
45
120000
ns
tRC
60
—
65
—
65
—
ns
tRFC
72
—
75
—
75
—
ns
tRCD
Address and control input pulse
width
Mode register set command cycle
time
Active to Precharge command period tRAS
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
Active to Read/Write delay
0.35
9
18
—
20
—
20
—
ns
Precharge to active command period tRP
18
—
20
—
20
—
ns
Active to Autoprecharge delay
tRAP
tRCD min.
—
tRCD min.
—
tRCD min.
—
ns
Active to active command period
tRRD
12
—
15
—
15
—
ns
Data Sheet E0859E50 (Ver. 5.0)
9
EDD2508AETA, EDD2516AETA
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max
min.
max.
Unit Notes
Write recovery time
tWR
15
—
15
—
15
—
ns
tDAL
(tWR/tCK)+
(tRP/tCK)
tWTR
1
tREF
—
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
Average periodic refresh interval
(tWR/tCK)+
—
(tRP/tCK)
(tWR/tCK)+
—
(tRP/tCK)
tCK
—
1
—
1
—
tCK
7.8
—
7.8
—
7.8
µs
13
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.6V ± 0.1V (DDR400), 2.5V ± 0.2V (DDR333, 266). VDD power supply variation
per cycle expected to be less than 0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,
tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)
tDAL = 7 clocks
Data Sheet E0859E50 (Ver. 5.0)
10
EDD2508AETA, EDD2516AETA
Test Conditions
Parameter
Symbol
Value
Unit
Input reference voltage
VREF
VDDQ/2
V
Termination voltage
VTT
VREF
V
Input high voltage
VIH (AC)
VREF + 0.31
V
Input low voltage
VIL (AC)
VREF − 0.31
V
VID (AC)
0.62
V
VIX (AC)
VREF
V
SLEW
1
V/ns
Input differential voltage, CK and /CK
inputs
Input differential cross point voltage,
CK and /CK inputs
Input signal slew rate
tCK
VDD
CK VID
VREF
/CK
VSS
tCL
tCH
VIX
VDD
VIH
VIL
VREF
VSS
∆t
SLEW = (VIH (AC) – VIL (AC))/∆t
VTT
Measurement point
RT = 50Ω
DQ
CL = 30pF
Input Waveforms and Output Load
Data Sheet E0859E50 (Ver. 5.0)
11
EDD2508AETA, EDD2516AETA
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
Parameter
5ns
6ns
7.5ns
Symbol
min.
max.
min.
max.
min.
max.
Unit
tWPD
1 + BL/2
+ tWR
—
1 + BL/2
+ tWR
—
1 + BL/2
+ tWR
—
tCK
tRPD
BL/2
—
BL/2
—
BL/2
—
tCK
tWRD
1 + BL/2
+ tWTR
—
1 + BL/2
+ tWTR
—
1 + BL/2
+ tWTR
—
tCK
tBSTW
—
—
—
—
2
—
tCK
(CL = 2.5)
tBSTW
—
—
3
—
3
—
tCK
(CL = 3)
tBSTW
3
—
3
—
3
—
tCK
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
—
—
—
—
2
2
tCK
(CL = 2.5)
tBSTZ
—
—
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tBSTZ
3
3
3
3
3
3
tCK
Read command to write command
delay (to output all data)
(CL = 2)
tRWD
—
—
—
—
2 + BL/2
—
tCK
(CL = 2.5)
tRWD
—
—
3 + BL/2
—
3 + BL/2
—
tCK
(CL = 3)
tRWD
3 + BL/2
—
3 + BL/2
—
3 + BL/2
—
tCK
Pre-charge command to High-Z
(CL = 2)
tHZP
—
—
—
—
2
2
tCK
(CL = 2.5)
tHZP
—
—
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tHZP
3
3
3
3
3
3
tCK
Write command to data in latency
tWCD
1
1
1
1
1
1
tCK
Write recovery
tWR
3
—
3
—
2
—
tCK
DM to data in latency
tDMD
0
0
0
0
0
0
tCK
Self-refresh exit to non-read
command
tSNR
15
—
12
—
10
—
tCK
Self-refresh exit to read command
tSRD
200
—
200
—
200
—
tCK
Power down entry
tPDEN
1
1
1
1
1
1
tCK
Power down exit to command input
tPDEX
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 2)
1
—
1
—
1
—
tCK
Active to Precharge command period tRAS
8

7

6

tCK
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
tRC
11 (-5B)
12 (-5C)

10

9

tCK
tRFC
14

12

10

tCK

3

3

tCK

3

3

tCK
Active to Read/Write delay
tRCD
Precharge to active command period tRP
3 (-5B)
4 (-5C)
3 (-5B)
4 (-5C)
Data Sheet E0859E50 (Ver. 5.0)
12
EDD2508AETA, EDD2516AETA
Clock
generator
Block Diagram
Bank 3
Bank 2
Bank 1
A0 to A12, BA0, BA1
Mode
register
Row
address
buffer
and
refresh
counter
Row decoder
CK
/CK
CKE
Memory cell array
Bank 0
Control logic
/CS
/RAS
/CAS
/WE
Command decoder
Sense amp.
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
DLL
CK, /CK
Input & Output buffer
DQ
Data Sheet E0859E50 (Ver. 5.0)
13
DQS
DM
EDD2508AETA, EDD2516AETA
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A8, and A9 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD2508AETA
AX0 to AX12
AY0 to AY9
EDD2516AETA
AX0 to AX12
AY0 to AY8
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0859E50 (Ver. 5.0)
14
EDD2508AETA, EDD2516AETA
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is
low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when
the CKE is driven low and exited when it resumes to high. CKE must be maintained high throughout read or write
access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM, UDM, LDM (input pin)
DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. In × 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data. When DM = high, the data input at the same timing are
masked while the internal burst counter will be count up.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins (DQ0 to DQ7; EDD2508AETA, DQ0 to DQ15; EDD2516AETA).
DQS, UDQS, LDQS (input and output pin)
DQS provide the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the
lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0859E50 (Ver. 5.0)
15
EDD2508AETA, EDD2516AETA
Command Operation
Command Truth Table
DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other
combinations than those in the table below are illegal.
CKE
Command
Symbol
n–1
n
/CS
/RAS /CAS /WE
BA1
BA0
AP
Address
Ignore command
DESL
H
H
H
×
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
×
×
×
×
Burst stop in read command
BST
H
H
L
H
H
L
×
×
×
×
Column address and read command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto-precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto-precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank active
ACT
H
H
L
L
H
H
V
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
V
L
×
Precharge all bank
PALL
H
H
L
L
H
L
×
×
H
×
Refresh
REF
H
H
L
L
L
H
×
×
×
×
SELF
H
L
L
L
L
H
×
×
×
×
MRS
H
H
L
L
L
L
L
L
L
V
EMRS
H
H
L
L
L
L
L
H
L
V
Mode register set
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is high at the cross point of the CK rising edge and the VREF level, every input are neglected and internal
status is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data
input are neglected and internal status is held.
Burst stop in read operation [BST]
This command stops a burst read operation, which is not applicable for a burst write operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Data Sheet E0859E50 (Ver. 5.0)
16
EDD2508AETA, EDD2516AETA
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode
register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE
Current state
Command
n–1
n
/CS
/RAS
/CAS
/WE
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
2
Idle
Power down entry (PDEN)
H
L
L
H
H
H
×
H
L
H
×
×
×
×
Self-refresh
Self-refresh exit (SELFX)
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Power down
Power down exit (PDEX)
Remark: H: VIH. L: VIL. ×: VIH or VIL.
Notes: 1. All the banks must be in IDLE before executing this command.
2. The CKE level must be kept for 1 CK cycle at least.
Data Sheet E0859E50 (Ver. 5.0)
17
EDD2508AETA, EDD2516AETA
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state
Precharging*
1
/CS
/RAS
/CAS /WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL*
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
ILLEGAL*
11
—
11
—
L
Idle*
2
Activating*
4
Active*
L
L
BA, CA, A10
WRIT/WRITA
L
H
H
BA, RA
ACT
ILLEGAL*
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
L
L
L
×
×
ILLEGAL
—
ldle
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
H
H
L
×
BST
ldle
ILLEGAL*
11
—
—
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
L
L
H
H
BA, RA
ACT
Activating
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
ldle/
Self-refresh
Active
L
L
L
H
×
REF, SELF
Refresh/
12
Self-refresh*
L
L
L
L
MODE
MRS
Mode register set*
ldle
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
×
×
ILLEGAL
—
L
L
×
×
×
ILLEGAL
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
12
Active
L
H
H
L
×
BST
ILLEGAL*
11
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
ILLEGAL*
11
—
—
—
L
5
H
—
L
L
Refresh
3
(auto-refresh)*
ldle
11
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11
L
L
L
×
×
ILLEGAL
—
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
Active
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation Read/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting write
operation
L
L
H
H
BA, RA
ACT
ILLEGAL*
L
L
H
L
BA, A10
PRE, PALL
Pre-charge
Idle
L
L
L
×
×
ILLEGAL
—
Data Sheet E0859E50 (Ver. 5.0)
18
11
Write
recovering/
precharging
—
EDD2508AETA, EDD2516AETA
Current state
Read*
6
/CS
/RAS
/CAS /WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
BST
Active
L
H
L
H
BA, CA, A10
READ/READA
Interrupting burst read
operation to
Active
start new read
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
13
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
Interrupting burst
read operation to
start pre-charge
Precharging
ILLEGAL
—
NOP
Precharging
L
L
L
×
×
Read with auto-preH
7
charge*
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
—
Write*
8
Write recovering*
9
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
—
ILLEGAL*
11, 14
—
L
L
H
L
BA, A10
PRE, PALL
L
L
L
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
ILLEGAL
—
Write
recovering
Write
recovering
—
Interrupting burst write
operation to
Read/ReadA
start read operation.
Interrupting burst write
operation to
Write/WriteA
start new write
operation.
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
PRE, PALL
Interrupting write
operation to start precharge.
Idle
ILLEGAL
—
NOP
Active
11
—
L
L
H
L
BA, A10
L
L
L
×
×
H
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL*
11
—
L
L
L
×
×
Starting read
operation.
Starting new write
operation.
ILLEGAL
Data Sheet E0859E50 (Ver. 5.0)
19
Read/ReadA
Write/WriteA
—
EDD2508AETA, EDD2516AETA
Current state
/CS
/RAS
/CAS /WE
Address
Command
Operation
Next state
Write with auto10
pre-charge*
H
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
—
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
—
ILLEGAL*
11, 14
—
L
L
H
L
BA, A10
L
L
L
×
×
PRE, PALL
ILLEGAL
—
H: VIH. L: VIL. ×: VIH or VIL
The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
The DDR SDRAM is in "Active" state after "Activating" is completed.
The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or
a write with auto-precharge enabled, may be followed by any column command to other banks, as long as
that command does not interrupt the read or write data transfer, and all other related limitations apply.
(E.g. Conflict between READ data and WRITE data must be avoided.)
Remark:
Notes: 1.
2.
3.
4.
5.
6.
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
From command
To command (different bank, noninterrupting command)
Read w/AP
Write w/AP
Minimum delay
(Concurrent AP supported)
Units
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL(rounded up)+ (BL/2)
tCK
Precharge or Activate
1
tCK
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
Data Sheet E0859E50 (Ver. 5.0)
20
EDD2508AETA, EDD2516AETA
Command Truth Table for CKE
Current State
CKE
n–1 n
Self-refresh
Self-refresh recovery
Power down
All banks idle
Row active
/CS
/RAS /CAS /WE Address
Operation
H
×
×
×
×
×
×
INVALID, CK (n-1) would exit self-refresh
L
H
H
×
×
×
×
Self-refresh recovery
L
H
L
H
H
×
×
Self-refresh recovery
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
Maintain self-refresh
H
H
H
×
×
×
×
Idle after tRC
H
H
L
H
H
×
×
Idle after tRC
H
H
L
H
L
×
×
ILLEGAL
H
H
L
L
×
×
×
ILLEGAL
H
L
H
×
×
×
×
ILLEGAL
H
L
L
H
H
×
×
ILLEGAL
H
L
L
H
L
×
×
ILLEGAL
H
L
L
L
×
×
×
ILLEGAL
EXIT power down → Idle
H
×
×
×
×
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
×
Note
INVALID, CK (n – 1) would exit power down
L
L
×
×
×
×
H
H
H
×
×
×
Refer to operations in Function Truth Table
H
H
L
H
×
×
Refer to operations in Function Truth Table
H
H
L
L
H
×
H
H
L
L
L
H
×
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
×
×
Refer to operations in Function Truth Table
H
L
L
H
×
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
Refer to operations in Function Truth Table
H
L
L
L
L
H
×
H
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
H
×
×
×
×
×
×
Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
Maintain power down mode
Refer to operations in Function Truth Table
CBR (auto) refresh
Self-refresh
1
1
1
Remark: H: VIH. L: VIL. ×: VIH or VIL
Note: 1. Self-refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
Data Sheet E0859E50 (Ver. 5.0)
21
EDD2508AETA, EDD2516AETA
Auto-refresh command [REF]
This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The average refresh cycle is 7.8 µs. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can
be issued tRFC after the last auto-refresh command.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held low. No internal refresh operation occurs during the power down mode. [PDEN] do not
disable DLL.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.
To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After
the exit, input auto-refresh command within 7.8 µs.
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Data Sheet E0859E50 (Ver. 5.0)
22
EDD2508AETA, EDD2516AETA
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
POWER
DOWN
CKE_
CKE
ROW
ACTIVE
BST
WRITE
Write
READ
WRITE
WITH
AP
WRITE
READ
WITH
AP
READ
READ
READ
WITH AP
WRITE
WITH AP
Read
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically
and enter the IDLE state.
Data Sheet E0859E50 (Ver. 5.0)
23
EDD2508AETA, EDD2516AETA
Operation of the DDR SDRAM
Power-up Sequence
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
(4)
(5)
PALL
EMRS
(6)
(7)
MRS
PALL
(8)
(9)
CK
/CK
Command
2 cycles (min.)
2 cycles (min.) 2 cycles (min.)
DLL enable
REF
REF
tRP
REF
tRFC
DLL reset with A8 = High
Any
command
MRS
tRFC
2 cycles (min.)
Disable DLL reset with A8 = Low
200 cycles (min)
Power-up Sequence after CKE Goes High
Data Sheet E0859E50 (Ver. 5.0)
24
EDD2508AETA, EDD2516AETA
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command
[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are
set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine
which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode
register must be set.
Remind that no other parameters shown in the table bellow are allowed to input to the registers.
BA0
BA1
A12
0
0
0
A11 A10 A9
0
0
0
A8
A7
DR
0
A6
A5
A4
LMODE
A3
A2
A1
BT
A0
BL
MRS
A8 DLL Reset A6 A5 A4 CAS Latency
0 0 0 Reserved
0 No
1 Yes
A3 Burst Type
A2 A1 A0 Burst Length
0 Sequential
0
0
0
Reserved
1 Interleave
0
0
1
2
4
0
0
0
1
1
0
Reserved
2
0
1
0
0
1
1
0
1
0
3
Reserved
0
1
1
8
1
0
0
Reserved
1
0
1
0
1
Reserved
1
0
Reserved
2.5
1
1
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
BA0 BA1
1
0
A12 A11 A10 A9
0
0
0
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
DS
DLL
EMRS
A1 Driver Strength
A0 DLL Control
0 Normal
0 DLL Enable
1 Weak
1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0)
Data Sheet E0859E50 (Ver. 5.0)
25
EDD2508AETA, EDD2516AETA
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequence
Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequence
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequence
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
Data Sheet E0859E50 (Ver. 5.0)
26
EDD2508AETA, EDD2516AETA
Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
t0
t1
t5
t6
t7
t8
t9
t10
t11
CK
/CK
tRCD
Command
Address
NOP
ACT
NOP
Row
READ
NOP
Column
tRPRE
out0 out1
BL = 2
tRPST
DQS
DQ
out0 out1 out2 out3
BL = 4
out0 out1 out2 out3 out4 out5 out6 out7
BL = 8
CL = 3
BL: Burst length
Read Operation (Burst Length)
Data Sheet E0859E50 (Ver. 5.0)
27
;; ;;;
EDD2508AETA, EDD2516AETA
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
Command
READ
NOP
tRPRE
tRPST
VTT
DQS
CL = 3
tAC,tDQSCK
out0
DQ
out1
out2
VTT
out3
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
t0
tn tn+0.5 tn+1
t1
tn+2
tn+3
tn+4
tn+5
CK
/CK
Command
tRCD
NOP
Address
ACT
NOP
Row
WRITE
NOP
Column
tWPRE
tWPRES
BL = 2
in0
in1
tWPST
DQS
DQ
BL = 4
BL = 8
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
BL: Burst length
Write Operation
Data Sheet E0859E50 (Ver. 5.0)
28
EDD2508AETA, EDD2516AETA
Burst Stop
Burst stop command during burst read
The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst
read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become
High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred
when this command is executed.
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
Command
READ
BST
NOP
tBSTZ
3 cycles
DQS
CL = 3
out0
DQ
out1
CL: /CAS latency
Burst Stop during a Read Operation
Data Sheet E0859E50 (Ver. 5.0)
29
EDD2508AETA, EDD2516AETA
Auto Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2)
cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column
command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge
command does not limit row commands execution for other bank. Refer to ‘Function truth table and related
note(Notes.*14).
CK
/CK
tRPD
tRAP (min) = tRCD (min)
Command
ACT
tRP (min)
BL/2 cycles
ACT
NOP
READA
DQS
tAC,tDQSCK
DQ
out0
Note: Internal auto-precharge starts at the timing indicated by "
out1
out2
out3
".
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started (1 + BL/ 2 + tWR) cycles after WRITA command issued. A column command to the other banks can be
issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not
limit row commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with AutoPrecharge Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14)‘.
CK
/CK
tRAS (min)
tRP
tRCD (min)
Command
ACT
NOP
NOP
WRITA
ACT
1 + BL/2 + tWR cycles
DM
DQS
DQ
in1
in2
in3
Note: Internal auto-precharge starts at the timing indicated by "
in4
".
Burst Write (BL = 4)
Data Sheet E0859E50 (Ver. 5.0)
30
BL = 4
EDD2508AETA, EDD2516AETA
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
IDLE
t0
t4
t5
READ
READ
t6
t7
t8
t9
t10
CK
/CK
Command
ACT
Address
Row
NOP
NOP
Column A Column B
BA
out out
A0 A1
DQ
Column = A Column = B
Read
Read
out
B0
Column = A
Dout
out
B1
out
B2
out
B3
Column = B
Dout
DQS
CL = 3
BL = 4
Bank0
Bank0
Active
READ to READ Command Interval (same ROW address in the same bank)
Data Sheet E0859E50 (Ver. 5.0)
31
t11
EDD2508AETA, EDD2516AETA
t0
t1
t2
ACT
NOP
ACT
t5
t6
READ
READ
t7
t8
t9
t10
t11
CK
/CK
Command
Address
Row0
Row1
NOP
NOP
Column A Column B
BA
out out
A0 A1
DQ
Column = A Column = B
Read
Read
Bank0
Dout
out out out out
B0 B1 B2 B3
Bank3
Dout
DQS
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
READ to READ Command Interval (different bank)
Data Sheet E0859E50 (Ver. 5.0)
32
CL = 3
BL = 4
;;;;;
EDD2508AETA, EDD2516AETA
A Write command to the consecutive Write command Interval
Destination row of the consecutive write
command
Bank
address
1.
Same
2.
Same
3.
Different
Row address State
Operation
Same
ACTIVE
Different
—
Any
ACTIVE
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive write command can be issued.
IDLE
t0
CK
/CK
Command
Address
BA
DQ
ACT
Row
tn
NOP
WRIT
tn+1
tn+2
tn+4
tn+5
tn+6
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Column = A
Write
DQS
tn+3
Column = B
Write
Bank0
Active
BL = 4
Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
Data Sheet E0859E50 (Ver. 5.0)
33
;;; ;;;
EDD2508AETA, EDD2516AETA
CK
/CK
Command
Address
BA
DQ
t0
t1
t2
ACT
NOP
ACT
Row0
Row1
tn
NOP
WRIT
tn+1
tn+3
tn+4
tn+5
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Bank0
Write
DQS
tn+2
Bank0
Active
Bank3
Write
Bank3
Active
BL = 4
Bank0, 3
WRITE to WRITE Command Interval (different bank)
Data Sheet E0859E50 (Ver. 5.0)
34
EDD2508AETA, EDD2516AETA
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
IDLE
t0
t1
READ
BST
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
NOP
tBSTW (≥ tBSTZ)
DM
tBSTZ (= CL)
DQ
out0 out1
in0
in1
in2
in3
High-Z
DQS
OUTPUT
INPUT
READ to WRITE Command Interval
Data Sheet E0859E50 (Ver. 5.0)
35
BL = 4
CL = 3
EDD2508AETA, EDD2516AETA
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= 1 + BL/2 + tWTR) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= 1 + BL/2 + tWTR) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
IDLE
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
tWRD (min)
1 + BL/2 + tWTR cycles
tWTR*
DM
DQ
in0
in1
in2
out0
in3
out1
out2
DQS
INPUT
OUTPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
Data Sheet E0859E50 (Ver. 5.0)
36
BL = 4
CL = 3
EDD2508AETA, EDD2516AETA
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1.
Same
Same
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
2.
Same
Different
—
—*
3.
Different
Any
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
IDLE
—*
1
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
WRIT
READ
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
CL=3
1 cycle
DM
DQ
in0
in1
out0 out1 out2 out3
in2
High-Z
High-Z
DQS
BL = 4
CL = 3
Data masked
[WRITE to READ delay = 1 clock cycle]
Data Sheet E0859E50 (Ver. 5.0)
37
;;;;;
EDD2508AETA, EDD2516AETA
t0
t1
t2
WRIT
NOP
READ
t3
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
2 cycle
CL=3
DM
in0
DQ
in1
in2
High-Z
out0 out1 out2 out3
in3
High-Z
DQS
Data masked
BL = 4
CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
3 cycle
CL=3
tWTR*
DM
DQ
in0
in1
in2
out0 out1 out2 out3
in3
DQS
BL = 4
CL = 3
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
Data Sheet E0859E50 (Ver. 5.0)
38
EDD2508AETA, EDD2516AETA
A Read command to the consecutive Precharge command interval (same bank): To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0
t1
t2
t3
NOP
READ
NOP
PRE/
PALL
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
DQ
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP
(= CL) after the precharge command.
t0
t1
t2
t3
t4
READ
PRE/PALL
t5
t6
t7
t8
CK
/CK
Command
NOP
NOP
CL = 3
High-Z
DQ
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 2, 4, 8)
Data Sheet E0859E50 (Ver. 5.0)
39
;;;;;;;
;; ;
EDD2508AETA, EDD2516AETA
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
PRE/PALL
NOP
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
PRE/PALL
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Data masked
Precharge Termination in Write Cycles (same bank) (BL = 4)
Data Sheet E0859E50 (Ver. 5.0)
40
NOP
EDD2508AETA, EDD2516AETA
Bank active command interval
Destination row of the consecutive ACT
command
Bank
address
Row address
State
1.
Same
Any
ACTIVE
2.
Different
Any
ACTIVE
IDLE
Operation
Two successive ACT commands can be issued at tRC interval. In between two
successive ACT operations, precharge command should be executed.
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
tRRD after an ACT command, the next ACT command can be issued.
CK
/CK
Command
Address
ACTV
ACT
ACT
ROW: 0
ROW: 1
Bank0
Active
Bank3
Active
PRE
NOP
NOP
ACT
NOP
ROW: 0
BA
tRRD
Bank0
Precharge
Bank0
Active
tRC
Bank Active to Bank Active
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK
/CK
Command
MRS
Address
CODE
NOP
ACT
BS and ROW
Mode Register Set
tMRD
Data Sheet E0859E50 (Ver. 5.0)
41
Bank3
Active
NOP
EDD2508AETA, EDD2516AETA
DM Control
DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data,
respectively. By setting DM to low, data can be written. When DM is set to High, the corresponding data is not
written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1
t2
t3
t4
t5
t6
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Self-Refresh
The self-refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered
down. When in the self-refresh mode, the DDR SDRAM retains data without external clocking. The self-refresh
command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled
upon entering self-refresh, and is automatically enabled upon exiting self-refresh. Any time the DLL is enabled a
DLL reset must follow and 200 clock cycles should occur before a read command can be issued. Input signals
except CKE are “Don’t care” during self-refresh. Since CKE is an SSTL2 input, VREF must be maintained during
self-refresh.
The procedure for exiting self-refresh requires a sequence of commands. First, CK must be stable prior to CKE
going back high. Once CKE is high, the DDR SDRAM must have NOP commands issued for tSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before applying any other command.
The use of self-refresh mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self-refresh mode. Upon exit from self-refresh an extra auto-refresh command is recommended.
t0
t1
t2
t3
t4
t5
t6
tm
tn
tCK
tCH tCL
/CK
CK
≥ tSNR*3
tRP*1
tIS
tIS
≥ tSRD*2
CKE
tIS tIH
Command
SELF
NOP
NOP
NOP
Valid
Notes: 1. Device must be in the “All banks idle” state prior to entering self-refresh mode.
2. tSRD is applied for a read or a read with autoprecharge command.
3. tSNR is applied for any command except a read or a read with autoprecharge command.
Self-Refresh
Data Sheet E0859E50 (Ver. 5.0)
42
;;;;;;
EDD2508AETA, EDD2516AETA
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
tIS
Command
(/RAS, /CAS,
/WE, /CS)
tIH
VREF
tIS
tIH
VREF
Address
Read Timing Definition
tCK
/CK
CK
tCL
tCH
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
DQS
tDQSQ
tLZ
DQ
(Dout)
tAC
tDQSQ
tQH
tAC
tAC
tQH
tHZ
tDQSQ
tDQSQ tQH
tQH
Write Timing Definition
tCK
/CK
CK
tDQSS
DQS
tDSH
tDSS
tDSS
VREF
tWPRES
tDQSL
tWPRE
DQ
(Din)
tWPST
VREF
tDS
DM
tDQSH
tDIPW
tDH
VREF
tDS
tDH
tDIPW
Data Sheet E0859E50 (Ver. 5.0)
43
tDIPW
EDD2508AETA, EDD2516AETA
Read Cycle
;
;
;
;
;
;;; ;
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRCD
tRP
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
;
;;
;;
;
;
BA
A10
tIS tIH
tIS tIH
tIS tIH
Address
DM
DQS
DQ (output)
tRPRE
High-Z
tRPST
High-Z
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
Data Sheet E0859E50 (Ver. 5.0)
44
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
;
;
;;;;;
;
EDD2508AETA, EDD2516AETA
Write Cycle
tCK
tCH
tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRP
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
tDQSS
DQS
(input)
tDQSL
tWPST
tDQSH
tDS
tDS
tDH
DM
tDS
tDH
DQ (input)
tWR
tDH
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
Data Sheet E0859E50 (Ver. 5.0)
45
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
EDD2508AETA, EDD2516AETA
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
code
Address
C: b
R: b
code
valid
DM
High-Z
DQS
High-Z
b
DQ (output)
tMRD
tRP
Mode
register
set
Precharge
If needed
Bank 3
Read
Bank 3
Active
Bank 3
Precharge
CL = 2
BL = 4
= VIH or VIL
Read/Write Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:a
R:b
C:b''
C:b
DM
DQS
a
DQ (output)
b’’
High-Z
DQ (input)
b
tRWD
Bank 0
Active
tWRD
Bank 0 Bank 3
Read Active
Bank 3
Write
Data Sheet E0859E50 (Ver. 5.0)
46
Bank 3
Read
Read cycle
CL = 2
BL = 4
=VIH or VIL
EDD2508AETA, EDD2516AETA
Auto-refresh Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
b
DQ (output)
High-Z
DQ (input)
tRP
Precharge
If needed
tRFC
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 2
BL = 4
= VIH or VIL
Data Sheet E0859E50 (Ver. 5.0)
47
EDD2508AETA, EDD2516AETA
Self-refresh Cycle
/CK
CK
tIS
tIH
CKE
CKE = low
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ (output)
High-Z
DQ (input)
tSNR
tRP
tSRD
Precharge
If needed
Self
refresh
entry
Self refresh
exit
Bank 0
Active
Bank 0
Read
CL = 2.5
BL = 4
= VIH or VIL
Data Sheet E0859E50 (Ver. 5.0)
48
EDD2508AETA, EDD2516AETA
Package Drawing
66-pin Plastic TSOP (II)
Solder plating: Lead free (Sn-Bi)
Unit: mm
22.22 ± 0.10 *1
A
11.76 ± 0.20
34
10.16
66
PIN#1 ID
1
0.65
0.17 to 0.32
33
B
0.13 M S A B
0.80
Nom
0.91 max.
0.25
0.10 +0.08
−0.05
0.10 S
0.09 to 0.20
S
1.20 max
1.0 ± 0.05
0 to 8°
0.60 +0.15
−0.20
Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or
gate burrs shall not exceed 0.20mm per side.
ECA-TS2-0143-01
Data Sheet E0859E50 (Ver. 5.0)
49
EDD2508AETA, EDD2516AETA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD2508AETA, EDD2516AETA.
Type of Surface Mount Device
EDD2508AETA, EDD2516AETA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) >
Data Sheet E0859E50 (Ver. 5.0)
50
EDD2508AETA, EDD2516AETA
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0859E50 (Ver. 5.0)
51
EDD2508AETA, EDD2516AETA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Data Sheet E0859E50 (Ver. 5.0)
52