Product Folder Order Now Support & Community Tools & Software Technical Documents ESD224 SLVSEB4 – FEBRUARY 2018 1 Features 3 Description • The ESD224 is a bidirectional TVS ESD protection diode array for high speed applications such as USB 3.0 and HDMI 2.0. The ESD224 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). The ESD224 employs on-chip differentially matched series elements to enhance down-stream ESD clamping performance while maintaining the signal compliance for high speed interfaces. The ultra-low clamping performance and high differential bandwidth provided by the ESD224 on-chip ESD protection network enables the device to be HDMI 2.0 compliant while providing robust protection to downstream HDMI devices. 1 • • • • • • • • • IEC 61000-4-2 Level 4 ESD Protection – ±12-kV Contact Discharge – ±15-kV Air Gap Discharge IEC 61000-4-4 EFT Protection – 80 A (5/50 ns) IEC 61000-4-5 Surge Protection – 2 A (8/20 µs) IO Capacitance: – 0.5 pF (Typical) HDMI 2.0 Compliant Ultra-Low Leakage Current: 0.1 nA (Typical) Ultra-Low ESD Clamping Voltage: 8 V at 16-A TLP (System Side) Supports High Speed Interfaces up to 6 Gbps Industrial Temperature Range: –40°C to +125°C Industry Standard DQA Package The ESD224 is offered in the industry standard USON-10 (DQA) package. The package features 0.5mm pin pitch easing implementation and reducing design time. Device Information(1) PART NUMBER 2 Applications • • PACKAGE BODY SIZE (NOM) USON (10) 2.50 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic ESD224 TMDS D2+ TMDS D2- TMDS D1+ TMDS D1- To System ESD224 TMDS D0+ TMDS D0TMDS CLK+ TMDS CLK- TPD4E05U06 CEC UTILITY HDMI 2.0 Connector End Equipment – Set-Top Boxes – TV and Monitors – Laptops and Desktops – DVD, Blue-ray, Multimedia Players Interfaces – HDMI 2.0/1.4 – Ethernet 10/100/1000 Mbps – USB 3.0 ESD224 DDC_CLK DDC_DAT GND P 5V0 HOTPLUG TPD1E05U06 Copyright © 2018, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION ESD224 Low Clamping 4-Channel ESD Protection Device for HDMI Interface ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings -JEDEC Specifications ........................ ESD Ratings - IEC Specifications ............................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 7.4 Device Functional Modes.......................................... 8 8 Application and Implementation .......................... 9 8.1 Application Information.............................................. 9 8.2 Typical Application ................................................... 9 9 Power Supply Recommendations...................... 11 10 Layout................................................................... 11 10.1 Layout Guidelines ................................................. 11 10.2 Layout Examples ................................................. 12 11 Device and Documentation Support ................. 13 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 7 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 13 12 Mechanical, Packaging, and Orderable Information ........................................................... 13 ADVANCE INFORMATION 4 Revision History 2 DATE REVISION NOTES February 2018 * Initial release. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 5 Pin Configuration and Functions ADVANCE INFORMATION DQA Package 10-Pin USON Top View Pin Functions PIN NAME NO. TYPE GND 3 GND 8 IO1_C 1 IO2_C 2 IO3_C 4 IO4_C 5 IO4_S 6 System Side I/O Pin corresponding to IO4_C IO3_S 7 System Side I/O Pin corresponding to IO3_C IO2_S 9 System Side I/O Pin corresponding to IO2_C IO1_S 10 System Side I/O Pin corresponding to IO1_C Ground Connector Side I/O DESCRIPTION Ground. Connect to ground. These pins are shorted internally. ESD protected channel to be connected to the connector To be connected to the system side Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 3 ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Electrical Fast Transient Peak Pulse MAX UNIT IEC 61000-4-4 Peak Current at 25°C 80 A IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25°C 17 W IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25°C 2 A TA Operating free-air temperature -40 125 °C Tstg Storage temperature -65 155 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings -JEDEC Specifications VALUE ADVANCE INFORMATION V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings - IEC Specifications VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 Contact Discharge, all pins ±12000 IEC 61000-4-2 Air Discharge, all pins ±15000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage -3.6 3.6 V TA Operating Free Air Temperature -40 125 °C 6.5 Thermal Information ESD224 THERMAL METRIC (1) DQA (USON) UNIT 10 RθJA Junction-to-ambient thermal resistance 348.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 214.1 °C/W RθJB Junction-to-board thermal resistance 270.7 °C/W ΨJT Junction-to-top characterization parameter 81.7 °C/W ΨJB Junction-to-board characterization parameter 270.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 6.6 Electrical Characteristics At TA = 25°C unless otherwise noted TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 10 nA, across operating temperature range VBRF Breakdown voltage, Pin 1, 2, 4, 5 to 3 (GND) (1) IIO = 1 mA VBRR Reverse breakdown voltage, pin 1, 2, 4, 5 to 3 (GND) (1) IIO = -1 mA, VHOLD Holding voltage, pin1, 2, 4, 5 to 3 (GND) and 3 (GND) to pin 1, 2, 4, 5 IIO = 1 mA 6.3 V VHOLD-NEG Breakdown voltage, pin1, 2, 4, 5 to 3 (GND) (2) IIO = -1 mA -6.3 V IPP = 1 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 7 V IPP = 5 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 9 V IPP = 16 A, pin 1, 2, 4, 5 to 3 or 8(GND), GND to pin 1, 2, 4, 5 14 V 8 V -5 V VCLAMP VCLAMP-IECSYS TLP Clamping voltage (Intrinsic) (2) 8-kV Contact discharge on pin 1, 2, 4, 5 with pin3 grounded. Voltage waveform measured at pin 6, 7, 9, 10 with respect to GND IEC 61000-4-2 30 ns Clamping voltage (system side) assuming system draws at least 3 A of current at -8-kV Contact discharge on pin 1, 2, 4, 8V 5 with pin3 grounded. Voltage waveform measured at pin 6, 7, 9, 10 with respect to GND -3.6 3.6 V 5.5 7.5 V -5.5 -7.5 V Pin 1, 2, 4, 5 to GND, 100 ns TLP 0.5 GND to Pin 1, 2, 4, 5 , 100 ns TLP 0.5 Line capacitance, any IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.5 0.6 pF ΔCLINE Variation of line capacitance CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.02 0.07 pF S21dd-6GHz Differential Insertion Loss at 6GHz Differential insertion loss at Ch1, Ch2, Ch3, Ch4 at 6GHz Ileakage Leakage Current VIO=±3.6 V, Pin 1,2,4,5 to Pin 3 RDYN Dynamic resistance CLINE (1) (2) Ω 2 0.1 ADVANCE INFORMATION PARAMETER dB 10 nA VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 5 ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com 55 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -10 ns 10 5 0 -5 -10 Voltage (V) Voltage (V) 6.7 Typical Characteristics -20 -25 -30 -35 -40 -45 10 ns 30 ns 50 ns Time (ns) 70 ns -50 -10 ns 90 ns ESD_ Pin Connected to Broadcom HDMI Driver BCM7250 with 8 kV IEC. Contact Stress on the Connector Side Pin ADVANCE INFORMATION Figure 1. Clamping Voltage Waveform at the System Side 6 -15 10 ns 30 ns 50 ns Time (ns) 70 ns 90 ns ESD_ Pin Connected to Broadcom HDMI Driver BCM7250 with –8 kV IEC. Contact Stress on the Connector Side Pin Figure 2. Clamping Voltage Waveform at the System Side Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 7 Detailed Description 7.1 Overview The ESD224 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low capacitance makes this device ideal for protecting any super high-speed signal pins. 7.2 Functional Block Diagram IO1_C IO2_C IO2_S IO3_C IO3_S IO4_C IO4_S Copyright © 2018, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 IEC 61000-4-2 ESD Protection The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD-surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-4 EFT Protection The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground. 7.3.3 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground. 7.3.4 IO Capacitance The capacitance between each I/O pin to ground is 0.5 pF (typical). This device supports data rates up to 6 Gbps. 7.3.5 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±3.6 V. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 7 ADVANCE INFORMATION IO1_S ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com Feature Description (continued) 7.3.6 Ultra Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V. 7.3.7 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8 V (IPP = 16 A TLP) on the system side pins when the system draws at least 3 A. 7.3.8 Supports High Speed Interfaces This device is capable of supporting high speed interfaces up to 6 Gbps, because of the extremely low IO capacitance. 7.3.9 Industrial Temperature Range This device features an industrial operating range of –40°C to +125°C. 7.4 Device Functional Modes ADVANCE INFORMATION The ESD224 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of ESD224 (usually within 100s of nano-seconds) the device reverts to passive. 8 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ESD224 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on highspeed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. Part of this voltage drop across the diode drops across the series element between the connector side pin and the system-side pin. Therefore, the effective voltage drop across the protected IC is smaller than the voltage drop across the diode. It is recommended to avoid through-routing for this ESD diode (single trace connecting both the connector side pin and the system side pin) for the best ESD performance. ESD224 ADVANCE INFORMATION 8.2 Typical Application TMDS D2+ TMDS D2- TMDS D1+ TMDS D1- ESD224 TMDS CLK+ TMDS CLKTPD4E05U06 CEC UTILITY HDMI 2.0 Connector To System TMDS D0+ TMDS D0- DDC_CLK DDC_DAT GND P 5V0 HOTPLUG TPD1E05U06 Copyright © 2018, Texas Instruments Incorporated Figure 3. ESD224 Protecting the HDMI Interface Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 9 ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com Typical Application (continued) 8.2.1 Design Requirements In this design example, two ESD224 devices, one TPD4E05U06 and one TPD1E05U06 device are used to protect an HDMI 2.0 interface. For HDMI 2.0 application design parameters listed in Table 1 are known. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on high speed differential data lines 0 to 3.6 V Operating frequency of high speed data lines 3 GHz (First Harmonic) Signal range on control lines (CEC, UTILITY, DDC_CLK and DDC_DAT) 0 to 5 V 8.2.2 Detailed Design Procedure 8.2.2.1 Signal Range ADVANCE INFORMATION ESD224 supports signal ranges between –3.6 V and 3.6 V, which supports the high-speed lines on the HDMI 2.0 application. The TPD4E05U06 and TPD1E05U06 support signal ranges between 0 V and 5.5 V, which supports the HDMI control lines. 8.2.2.2 Operating Frequency The ESD224 has a 0.5 pF (typical) capacitance, which supports the HDMI 2.0 rate of 6 Gbps. The TPD4E05U06 and TPD1E05U06 have a typical capacitance of 0.5 pF and 0.42 pF respectively, which easily support the control lines. The ESD224 has 4 identical protection channels for the differential HDMI high-speed signal lines. The symmetrical pin out of the device with a ground pin between the two differential signal pins makes it suitable for this application. 10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 9 Power Supply Recommendations This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly. 10 Layout • • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. For the best ESD performance, do not use through-routing for the data channels. Connecting pins 1 and 10, 2 and 9, 4 and 7, 5 and 6 together with through routing will reduce the clamping voltage performance of ESD224. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 11 ADVANCE INFORMATION 10.1 Layout Guidelines ESD224 SLVSEB4 – FEBRUARY 2018 www.ti.com 10.2 Layout Examples ADVANCE INFORMATION Figure 4. HDMI Type-A Transmitter Port Layout. Note That There is no Through-Routing for the ESD224 Pins Connecting to the High Speed Data Lines. 12 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 ESD224 www.ti.com SLVSEB4 – FEBRUARY 2018 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: ESD224 13 ADVANCE INFORMATION The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Device Marking (4/5) ESD224DQAR PREVIEW USON DQA 10 ESD224DQAT PREVIEW USON DQA 10 250 TBD Call TI Call TI -40 to 125 PESD224DQAT ACTIVE USON DQA 10 3000 TBD Call TI Call TI -40 to 125 1AR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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