Very Low Power CMOS SRAM 128K X 16 bit BS616LV2016 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 30mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.1uA (Typ.) at 25 OC VCC = 5.0V Operation current : 62mA (Max.) at 55ns 8mA (Max.) at 1MHz Standby current : 0.6uA (Typ.) at 25OC Ÿ High speed access time : -55 55ns(Max.) at VCC=3.0~5.5V -70 70ns(Max.) at VCC=2.7~5.5V Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ I/O Configuration x8/x16 selectable by LB and UB pin. Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V The BS616LV2016 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 by 16 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.1uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616LV2016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2016 is available in DICE form, JEDEC standard 44-pin TSOP II package and 48-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY STANDBY OPERATING TEMPERATURE VCC=5.0V VCC=3.0V Commercial +0OC to +70OC 6.0uA 0.7uA Industrial -40OC to +85OC 20uA BS616LV2016DC BS616LV2016EC BS616LV2016AI BS616LV2016EI Operating (ICCSB1, Max) 1MHz fMax. 7mA 39mA 60mA A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1MHz VCC=3.0V 10MHz fMax. 1.5mA 14mA 29mA DICE TSOP II-44 BGA-48-0608 2.0uA 8mA 40mA 62mA 2mA 15mA 30mA TSOP II-44 n PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12 PKG TYPE (ICC, Max) VCC=5.0V 10MHz n BLOCK DIAGRAM A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BS616LV2016EC BS616LV2016EI 1 2 3 4 5 6 LB OE A0 A1 A2 NC B D8 UB A3 A4 CE D0 C D9 D10 A5 A6 D1 D2 D VSS D11 NC A7 D3 VCC E VCC D12 NC A16 D4 VSS F D14 D13 A14 A15 D5 D6 G D15 NC A12 A13 WE D7 H NC A8 A9 A10 A11 NC A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Address 1024 10 Input Row Buffer Decoder Memory Array 1024 x 2048 2048 DQ0 . 16 . . . . . . . . . . DQ15 CE WE OE UB LB 16 . Data Input Buffer Data Output Buffer 16 Column I/O Write Driver Sense Amp 16 128 Column Decoder 7 Control Address Input Buffer A12 A13 A14 A15 A16 A0 A1 VCC VSS 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS66LV2016 1 Revision 1.4 Nov. 2006 BS616LV2016 n PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit in the RAM CE Chip Enable Input CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0-DQ15 Data Input/Output There 16 bi-directional ports are used to read data from or write data into the RAM. Ports VCC Power Supply VSS Ground n TRUTH TABLE MODE CE WE OE LB UB IO0~IO7 IO8~IO15 VCC CURRENT Chip De-selected (Power Down) H X X X X High Z High Z ICCSB, ICCSB1 X X X H H High Z High Z ICCSB, ICCSB1 L H H L X High Z High Z ICC L H H X L High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC Output Disabled Read Write L L H L L X NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BS616LV2016 2 Revision 1.4 Nov. 2006 BS616LV2016 (1) n ABSOLUTE MAXIMUM RATINGS RATING UNITS RANG AMBIENT TEMPERATURE VCC Terminal Voltage with Respect to GND Temperature Under Bias -0.5(2) to 7.0 V Commercial 0OC to + 70OC 2.4V ~ 5.5V -40 to +125 O C Industrial -40OC to + 85OC 2.4V ~ 5.5V Storage Temperature -60 to +150 O C SYMBOL VTERM TBIAS TSTG n OPERATING RANGE PARAMETER PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA n CAPACITANCE (1) O (TA = 25 C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. O O n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS 2.4 -- 5.5 V VCC Power Supply VIL Input Low Voltage -0.5(2) -- 0.8 V VIH Input High Voltage 2.2 -- VCC+0.3(3) V IIL Input Leakage Current -- -- 1 uA ILO Output Leakage Current -- -- 1 uA VOL Output Low Voltage V CC = Max, IOL = 2.0mA -- -- 0.4 V VOH Output High Voltage V CC = Min, IOH = -1.0mA 2.4 -- -- V ICC(5) Operating Power Supply Current CE = VIL, VCC=3.0V IIO = 0mA, f = FMAX(4) -- -- VCC=5.0V Operating Power Supply Current CE = VIL, VCC=3.0V IIO = 0mA, f = 1MHz VCC=5.0V CE = VIH, VCC=3.0V IIO = 0mA VCC=5.0V CE≧VCC-0.2V VCC=3.0V VIN≧V CC-0.2V or VIN≦0.2V VCC=5.0V ICC1 ICCSB ICCSB1(6) VIN = 0V to VCC CE= VIH VI/O = 0V to V CC, CE= VIH or OE = VIH Standby Current – TTL Standby Current – CMOS 30 mA 62 -- -- 2 mA 8 -- -- 0.5 mA 1.0 -- 0.1 2.0 0.6 20 uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICC(MAX.) is 29mA/60mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 0.7uA/6.0uA at VCC=3.0V/5.0V and TA=70OC. R0201-BS616LV2016 3 Revision 1.4 Nov. 2006 BS616LV2016 O O n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL VDR (3) ICCDR PARAMETER TEST CONDITIONS TYP. (1) MAX. UNITS VCC for Data Retention CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V 1.5 -- -- V Data Retention Current CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V -- 0.05 1.0 uA 0 -- -- ns tRC (2) -- -- ns Chip Deselect to Data Retention Time tCDR MIN. See Retention Waveform tR Operation Recovery Time 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 0.5uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (CE Controlled) Data Retention Mode VCC VDR≧1.5V VCC tCDR tR CE≧VCC - 0.2V VIH CE VCC n AC TEST CONDITIONS VIH n KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 90% 10% → ← Rise Time: 1V/ns 90% 10% → ← Fall Time: 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. R0201-BS616LV2016 4 Revision 1.4 Nov. 2006 BS616LV2016 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC=3.0~5.5V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. TYP. MAX. UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tELQV tACS Chip Select Access Time (CE) -- -- 55 -- -- 70 ns tBLQV tBA Data Byte Control Access Time (LB, UB) -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns tELQX tCLZ Chip Select to Output Low Z (CE) 10 -- -- 10 -- -- ns tBLQX tBE Data Byte Control to Output Low Z (LB, UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns tEHQZ tCHZ Chip Select to Output High Z (CE) -- -- 30 -- -- 35 ns tBHQZ tBDO Data Byte Control to Output High Z (LB, UB) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT R0201-BS616LV2016 5 Revision 1.4 Nov. 2006 BS616LV2016 READ CYCLE 2 (1,3,4) CE tACS tBA LB, UB tCHZ tBE tCLZ DOUT READ CYCLE 3 (5) tBDO (5) (1, 4) tRC ADDRESS tAA OE tOH tOE tOLZ CE tCLZ tOHZ (5) tCHZ (5) (1,5) tBA LB, UB tBE tBDO DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS616LV2016 6 Revision 1.4 Nov. 2006 BS616LV2016 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (VCC=3.0~5.5V) CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tELWH tCW Chip Select to End of Write (CE) 55 -- -- 70 -- -- ns tBLWH tBW Data Byte Control to End of Write (LB, UB) 25 -- -- 30 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR Write Recovery Time 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (CE, WE) n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1 (3) OE tCW (11) (5) CE tBW LB, UB tWR2 tAW WE tWP tAS tOHZ (3) (2) (4,10) DOUT tDH tDW DIN R0201-BS616LV2016 7 Revision 1.4 Nov. 2006 BS616LV2016 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW CE (5) LB, UB (12) (11) tBW tAW tWP WE tAS tWHZ tWR2 (2) (4,10) (3) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write. 12. The change of Read/Write cycle must accompany with CE or address toggled. R0201-BS616LV2016 8 Revision 1.4 Nov. 2006 BS616LV2016 n ORDERING INFORMATION BS616LV2016 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE A: BGA-48-0608 D: DICE E: TSOP II-44 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS TSOP II-44 R0201-BS616LV2016 9 Revision 1.4 Nov. 2006 BS616LV2016 n PACKAGE DIMENSIONS (continued) NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.2 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8mm) R0201-BS616LV2016 10 Revision 1.4 Nov. 2006 BS616LV2016 n Revision History Revision No. History Draft Date 1.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 30uA to 20uA at 5.0V 5.0uA to 2.0uA at 3.0V C-grade from 10uA to 6.0uA at 5.0V 3.0uA to 0.7uA at 3.0V Jan. 13, 2006 1.3 Change I-grade operation temperature range - from –25OC to –40OC May. 25, 2006 1.4 Add 48-ball BGA package Nov. 02, 2006 R0201-BS616LV2016 11 Remark Revision 1.4 Nov. 2006