Multimedia ICs Audio digital delay (KARAOKE echo) BU9252S / BU9252F The BU9252S and BU9252F are digital delays specifically for Karaoke systems. Each has an internal sample hold circuit, an 8-bit A / D and D / A converter and 2kB SRAM, and allows for the selection of one of eight delay times just by attaching an inexpensive ceramic resonator. A digital echo system can be formed by using either of these ICs together with the BA7725S or BA7725FS. Applications •Karaoke echo system Electronic circuits that require signal delays •1)Features Internal digital delay circuit. 4) Internal 8-bit D / A converter. 5) CMOS design for low power consumption. 6) Internal sample hold circuit. 7) Internal feedback resistors and capacitors for oscillator circuits. 2) Internal 8-bit A / D converter. Sample rate. (14.22kHz when fOSC = 455kHz). 3) Internal 2k bytes data SRAM. OSCI OSCO 10 TDO0 13 11 TDIN 14 TDO1 TST2 15 12 TST1 TST0 17 16 VDD 18 •Block diagram TEST CIRCUIT ADDRESS COUNTER AND MAIN TIMING 1 2 3 4 5 6 7 8 9 S/H AIN AGND AOUT AVDD DCNT0 DCNT1 DCNT2 GND S/H 8bit A/D 8bit D/A 8 × 2k SRAM 1 Multimedia ICs BU9252S / BU9252F •Pin descriptions Pin No. Pin name 1 S/H 2 AIN 3 AGND Analog circuit ground 4 AOUT Analog output 5 AVDD Analog circuit power supply 6 DCNT0 7 DCNT1 8 DCNT2 9 GND 2 Function Pin No. Pin name For attaching sample-and-hold capacitor 10 OSCO Oscillator pin 2 Analog input 11 OSCI Oscillator pin 1 12 TDO1 Test pin (output) 13 TDO0 Test pin (output) 14 TDIN Test pin (input) Delay setting input 15 TST2 Test mode setting Delay setting input 16 TST1 Test mode setting Delay setting input 17 TST0 Test mode setting Digital circuit ground 18 VDD Function Digital circuit power supply Multimedia ICs BU9252S / BU9252F •Input / output circuits Pin name Pin No. S/H 1 AIN 2 TDIN 14 DCNT0 6 DCNT1 7 DCNT2 8 TDO0 13 TDO1 12 Internal equivalent circuit Pin name Pin No. OSCI 11 OSCO 10 AOUT 4 Internal equivalent circuit + TST0 17 TST1 16 TST2 15 D/A – Built-in 0.875x amplifier as output buffer. 3 Multimedia ICs BU9252S / BU9252F •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit VDD – 0.3 ~ + 7.0 V Power supply voltage Power dissipation BU9252S 600∗1 450∗2 mW – 55 ~ + 125 °C Pd BU9252F Storage temperature Tstg Input voltage Output voltage VIN – 0.3 ~ VDD + 0.3 V VOUT – 0.3 ~ VDD + 0.3 V ∗1 IC only. Reduce by – 6mW / °C for each in Ta of 1°C over 25°C. ∗2 IC only. Reduce by – 4.5mW / °C for each in Ta of 1°C over 25°C. •Recommended operating conditions Parameter Symbol Limits Unit VDD 4.5 ~ 5.5 V VDD V Power supply voltage AVDD Analog power supply voltage VIL Input "L" voltage Input "H" voltage VIH Analog input voltage VAIN 0.0 ~ 0.2VDD V 0.8VDD ~ VDD V 0 ~ AVDD V Clock frequency fOSC 200 ~ 1000 kHz Operating temperature Topr – 10 ~ + 70 °C •Electrical characteristics (unless otherwise noted, Ta = 25°C, V DD Parameter Supply current Symbol Min. Typ. Max. Unit IDD — 3.5 12 mA VAIN = AVDD, fOSC = 455kHz 1 4 — mA VAOUT = 1V, VAIN = 0V 0.3 0.8 — mA VAOUT = 0.5VDD, VAIN = VDD 12 25 60 kΩ ∗ Analog output current IAOUT Analog input impedance RAIN Conditions A / D to D / A precision RES — 2 — LSB OSCO output "L" voltage VLOSC — 0.6 1.2 V OSCO output "H" voltage VHOSC 3.8 4.4 — V IOH = – 100µA IOSCI 1 6 20 µA VOSCI = VDD — — 150 — pF OSCI feedback loop current Oscillation capacity ∗ The bias circuit is impedance. 4 = AVDD = 5V) IOL = 100µA Multimedia ICs BU9252S / BU9252F operation •(1)Circuit External capacitor for signal input pin Audio signals compressed by the BA7725S or BA7725FS have their DC component removed by an AC coupling capacitor and are then input to pin 2 of BU9252S or BU9252F. At this stage, level deviations occur because the input signal is capacitor-divided by this AC coupling capacitor C28 and by sampling hold capacitor C27 connected to pin 1. To prevent this, make sure that C27 is much lower than C28. (3) Delay timer settings The delay time (i.e., the length of time the signal is stored in the SRAM) can be set to any of eight settings between the maximum and minimum delay times by setting pins 6, 7 and 8 to the combination of logic signal inputs that results in the corresponding number of counts. The maximum and minimum delay times are determined by the oscillation frequency of the attached ceramic resonator. (dB) (Note: The numbers of external components are the numbers used in the system application example.) C27 1 C28 2 S/H (t) C The sample-held analog signal is converted to digital by the serial 8-bit A / D converter and then temporarily stored in the internal SRAM (2k bytes). C C C : Delay time (ms) (2) Relationship between oscillation frequency (CLK) and delay time Sample rate F = fOSC / 32 (fosc: oscillation frequency) F = 14.22kHz at fosc = 455kHz Sample period T = 1 / F Delay time Dtime = T × number of counts The delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals DCNT0 through DCNT2. Count Delay time (ms) (when fOSC = 455kHz) DCNT1 Logic input DCNT2 DCNT0 BU9252S / F BU9252S / F 0 0 0 256 18.00 0 0 1 512 36.01 0 1 0 768 54.01 0 1 1 1024 72.02 1 0 0 1280 90.02 1 0 1 1536 108.03 1 1 0 1792 126.03 1 1 1 2048 144.04 5 Multimedia ICs BU9252S / BU9252F Maximum and minimum delay times when using 300kHz, 375kHz and 455kHz ceramic oscillators Delay time (ms) 300kHz 375kHz 455kHz Max. Min. Max. Min. Max. Min. 218.45 27.30 174.76 21.85 144.04 18.00 (4) Peripheral components of the ceramic oscillator An oscillator circuit can be configured simply by attaching a 455kHz ceramic resonator. OSCI Rf Rd OSCO •External dimensions (Units: mm) BU9252F 11.2 ± 0.2 19.4 ± 0.3 1 9 1.778 0.5 ± 0.1 SDIP18 6 7.8 ± 0.3 1.8 ± 0.1 0.11 0.51Min. 3.95 ± 0.3 3.4 ± 0.2 7.62 0.3 ± 0.1 18 10 1 9 5.4 ± 0.2 10 6.5 ± 0.3 18 1.27 0.4 ± 0.1 0.15 ± 0.1 BU9252S 0.3Min. 0° ~ 15° 0.15 SOP18