AMD AM79C974KCW Pcnettm-scsi combination ethernet and scsi controller for pci system Datasheet

PRELIMINARY
Am79C974
PCnetTM-SCSI Combination Ethernet and SCSI Controller
for PCI Systems
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
PCI Features
SCSI Features
■ Direct glueless interface to 33 MHz, 32-bit PCI
local bus
■ Compliant to ANSI standards X3.131 – 1986
(SCSI-1) and X3.131 – 199X (SCSI-2)
■ 132 Mbyte/s burst DMA transfer rate
■ Fast 8-bit SCSI-2 10 Mbyte/s synchronous or
7 Mbyte/s asynchronous data transfer rate
■ Compliant to PCI local bus Specification
Revision 2.0
Ethernet Features
■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet Standards
■ High-performance Bus Master architecture with
integrated DMA Buffer Management Unit for
low CPU and bus utilization
■ Individual 136-byte transmit and 128-byte
receive FIFOs provide frame buffering for
increased system latency
■ MicrowireTM EEPROM interface supports
jumperless design
■ Integrated Manchester Encoder/Decoder
■ Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with automatic
port selection
■ Automatic Twisted-Pair receive polarity detection and automatic correction of the receive
polarity
■ Dynamic transmit FCS generation programmable on a frame-by-frame basis
■ Internal/external loopback capabilities
■ Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium
■ SCSI specific Bus Mastering DMA engine
(32-bit address/data)
■ 96-byte DMA FIFO for low bus latency
■ On-chip state machine to control the SCSI
sequences in hardware
■ Integrated industry standard Fast SCSI-2 core
■ Single-Ended 48 mA outputs to drive the SCSI
bus directly
■ Support for Scatter-Gather DMA data transfers
■ Hooks in silicon and software to enable disk
drive spin down for power savings
General Features
■ Software compatible with AMD’s Am79C960
PCnet-ISA, Am79C961 PCnet-ISA+, Am79C965
PCnet-32, Am79C970 PCnet-PCI register and
descriptor architecture
■ Plug-in and software compatible with AMD’s
PCSCSI family of SCSI controllers for PCI
■ NAND Tree test mode for connectivity testing
on printed circuit boards
■ Single +5 V power supply operation
■ Low-power, CMOS design with sleep modes for
both Ethernet and SCSI controllers allows reduced power consumption for critical battery
powered applications and ‘Green PCs’
■ Fully static design for low frequency and
power operation
■ 132-pin PQFP package
GENERAL DESCRIPTION
The PCnet-SCSI combination Ethernet and 8-bit Fast
SCSI controller with a 32-bit PCI bus interface is a highly
integrated Ethernet-Fast SCSI system solution designed to address high-performance system application
requirements. This single-chip is a flexible bus-mastering device that can be used in many applications, including network- and SCSI-ready PCs, printers, fax
modems, and bridge/router designs. The bus-master
architecture provides high data throughput in the system and low CPU and system bus utilization. The
PCnet-SCSI controller is fabricated with AMD’s advanced low-power CMOS process to provide low operating and standby current for power sensitive
applications.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 18681 Rev. B
Issue Date: October 1994
Amendment /1
AMD
PRELIMINARY
The PCnet-SCSI is part of AMD’s PCI product family of
plug-in and software compatible SCSI and Ethernet
controllers. This product compatibility ensures a low
cost system upgrade path and lower motherboard
manufacturing costs.
Ethernet Specific
The PCnet-SCSI controller includes a complete Ethernet node integrated into a single VLSI device. It contains
a bus interface unit, a DMA buffer management unit, an
IEEE 802.3-defined Media Access Control (MAC) function, individual 136-byte transmit and 128-byte receive
FIFOs, an IEEE 802.3-defined Attachment Unit Interface (AUI) and Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), and a Microwire EEPROM
interface. The PCnet-SCSI controller is also register
compatible with the LANCE (Am7990) Ethernet controller, the C-LANCE (Am79C90) Ethernet controller, the
ILACC (Am79C900) Ethernet controller, and all Ethernet controllers in the PCnet Family, including the PCnetISA controller (Am79C960), the PCnet-ISA+ controller
(Am79C961),
and
the
PCnet-32
controller
(Am79C965). The buffer management unit supports the
LANCE, ILACC, and PCnet descriptor software models.
The PCnet-SCSI controller is software compatible with
the Novell NE2100 and NE1500 Ethernet adapter card
architectures. In addition, a Sleep function has been incorporated to provide low standby current, excellent for
notebooks and Green PCs.
overhead, providing sufficient latency during frame
transmission and reception, and minimizing intervention
during normal network error recovery. The integrated
Manchester encoder/decoder (MENDEC) eliminates
the need for an external Serial Interface Adapter (SIA) in
the system. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity or jabber status.
SCSI Specific
The PCnet-SCSI controller also includes a highperformance Fast SCSI controller with a glueless interface to the PCI local bus. The PCnet-SCSI integrates its
own 32-bit bus mastering DMA engine with an industry
standard Fast SCSI-2 block. The DMA engine and accompanying 96 byte DMA FIFO allow 32-bit burst data
transfers across the high bandwidth PCI bus at speeds
of up to 132 Mbyte/s. Full support for scatter-gather
DMA transfers optimize performance in multi-tasking
system applications.
The PCnet-SCSI’s on-chip state machine controls SCSI
bus sequences in hardware and is coupled with the bus
mastering DMA engine to eliminate the need for an onchip RISC processor. This results in a smaller die size
giving the Am79C974 superior price/performance versus competitive offerings.
AMD supports the Am79C974 with a total system solution which includes:
The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus applications, simplifying the design of an Ethernet node in a PC system. With
its built-in support for both little and big endian byte
alignment, this controller also addresses proprietary
non-PC applications.
A full suite of licensable SCSI drivers and utilities
fully tested under the following operating system
environments:
— DOS 5.0 – 6.0
— Windows 3.1
— Windows NT
— OS/2 2.x
— Netware 3.x, 4.x
— SCO UNIX 3.2.4, ODT 2.0
An INT13h Compatible SCSI ROM BIOS
The PCnet-SCSI controller supports auto configuration
in the PCI configuration space. Additional PCnet-SCSI
controller configuration parameters, including the
unique IEEE physical address, can be read from an external non-volatile memory (serial EEPROM) immediately following system RESET.
The controller also has the capability to automatically
select either the AUI port or the Twisted-Pair transceiver. Only one interface is active at any one time. The
individual transmit and receive FIFOs optimize system
2
ASPI Compatibility
Complete hardware reference design kit
For more detailed information on the PCnet-SCSI refer
to the technical manual, PID #18738A.
Am79C974
AMD
PRELIMINARY
HIGH LEVEL BLOCK DIAGRAM
SCSI Data
SCSI Control
10Base-T, AUI Ports
SCSI Sequences,
SCSI Control,
SCSI Registers
SCSI FIFO
DMA
FIFO
96 Bytes
802.3 MAC Core
DMA Registers
RCV
FIFO
FIFO &
DMA Control
FIFO
Control
XMT
FIFO
DMA Registers
DMA Control
PCI Host Control and Interface
18681A-1
PCI Data/Address
PCI Host Control
Am79C974
3
AMD
PRELIMINARY
Cache
SRAM
DRAM
Memory
PCnet-SCSI
(Am79C974)
Video
Control
Control
CPU
Address
Core
Logic
Data
PCI
to
ISA
PCI Bus
PC-AT ISA Bus
Super I/O
IDE/Floppy
Ser/Par
Keyboard
Control
18681A-2
Am79C974 in a PCI System
4
Am79C974
PRELIMINARY
AMD
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
HIGH LEVEL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quick Reference Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
16
17
LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ethernet Controller Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted-Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
24
24
SCSI Controller Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
25
25
BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
System Bus Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
26
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
29
31
32
37
40
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Buffer Management Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Am79C974
43
43
43
43
44
46
46
48
5
AMD
PRELIMINARY
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
52
52
53
53
53
54
54
54
54
55
55
55
Twisted-Pair Transceiver (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Twisted-Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted-Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted-Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
55
56
56
56
57
57
57
57
57
Ethernet Power Savings Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Ethernet PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Hardware Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PCnet-SCSI Controller Master Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Slave Access to I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
EEPROM Microwire Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
69
70
70
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
71
72
72
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6
Am79C974
PRELIMINARY
AMD
H_RESET, S_RESET, and STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SCSI Specific DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DMA FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Blast Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Funneling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI DMA Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDL Based DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Scatter-Gather Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
76
76
76
76
78
Memory Descriptor List (MDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DMA Scatter-Gather Operation (4k aligned elements) . . . . . . . . . . . . . . . . . . . . . . . . 78
DMA Scatter-Gather Operation (Non-4k aligned elements MDL not set) . . . . . . . . . . 80
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
The Fast SCSI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SCSI Block ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REQ/ACK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
81
81
82
Parity Checking on the SCSI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Parity Generating on the SCSI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reset Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Hard Reset: (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Soft Reset: (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Disconnected Reset: (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Command Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Invalid Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
84
84
84
Information Transfer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiator Command Complete Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Accepted Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Pad Bytes Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set ATN Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset ATN Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
85
85
85
85
86
Idle State Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Select Without ATN Steps Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select With ATN Steps Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select With ATN and Stop Steps Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Selection/Reselection Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disable Selection/Reselection Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select With ATN3 Steps Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
86
86
86
87
87
General Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear FIFO Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Device Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset SCSI Bus Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Am79C974
87
87
87
87
7
AMD
PRELIMINARY
SCSI Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SCSI Activity Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reduced Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power Down Pin (PWDN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Software Disk Spin-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DC CHARACTERISTICS: PCI Bus and Board Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DC CHARACTERISTICS: Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DC CHARACTERISTICS: 10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DC CHARACTERISTICS: SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DC CHARACTERISTICS: Capacitance, ESD, and Latch Up . . . . . . . . . . . . . . . . . . . . . . . . 95
AC SWITCHING CHARACTERISTICS: PCI Bus and Board Interface . . . . . . . . . . . . . . . . . 96
AC SWITCHING CHARACTERISTICS: 10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC SWITCHING CHARACTERISTICS: Attachment Unit Interface . . . . . . . . . . . . . . . . . . . 98
AC SWITCHING CHARACTERISTICS: SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC SWITCHING WAVEFORMS: System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
AC SWITCHING WAVEFORMS: 10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
AC SWITCHING WAVEFORMS: Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . 107
AC SWITCHING WAVEFORMS: SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
APPENDIX A – Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Ethernet Controller
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
BCR —Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SCSI Controller
SCSI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
DMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
APPENDIX B – PCnet-SCSI Compatible Media Interface Modules . . . . . . . . . . . . . . . . . . 119
APPENDIX C – Recommendation for Power and Ground Decoupling . . . . . . . . . . . . . . . 121
APPENDIX D – Alternative Method for Initialization of Ethernet Controller . . . . . . . . . . . 123
APPENDIX E – SCSI System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
APPENDIX F – Designing a Single Motherboard for AMD PCI Family . . . . . . . . . . . . . . . 132
8
Am79C974
PRELIMINARY
AMD
LIST OF FIGURES
Figure 1. Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. Slave I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. Slave I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. Non-Burst Read Cycles With Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Non-Burst Read Cycles Without Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Non-Burst Read Cycles With and Without Wait States . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Burst Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Burst Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. Preemption When FRAME is Deasserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. Preemption When FRAME is Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. 16-Bit Data Structures: Initialization Block and Descriptor Rings . . . . . . . . . . . . . . . 44
Figure 18. 32-Bit Data Structures: Initialization Block and Descriptor Rings . . . . . . . . . . . . . . . 45
Figure 19. Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. Differential Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 21. 10BASE-T Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 22. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 23. 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. PCI BIU – DMA Engine – SCSI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26. DMA FIFO to SCSI FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27. Am79C974 NAND Tree Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 28. NAND Tree Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 29. SCSI Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 30. Asynchronous Initiator Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31. Asynchronous Initiator Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 32. Synchronous Initiator Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 33. Synchronous Initiator Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure E-1. Ideal Routing Scheme for SCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure E-2. A Poor Routing Scheme for SCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure E-3. Motherboard Layout – Approach #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure E-4. Motherboard Layout – Approach #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure E-5. Decoupling Capacitor Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure E-6. Regulated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure F-1. PCI Family Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Am79C974
9
AMD
PRELIMINARY
LIST OF TABLES
Table 1. Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 2. Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 3. Bus Master Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 4. Bus Slave Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 5. EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 6. The DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 7. Summary of SCSI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 8. NAND Tree Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10
Am79C974
PRELIMINARY
AMD
RELATED PRODUCTS
Part No.
Description
Am33C93A
Synchronous SCSI Controller
Am386
High-Performance 32-Bit Microprocessor
Am486TM
High-Performance 32-Bit Microprocessor
Am53C94/96
High-Performance SCSI Controller
Am53C974
PCSCSITM Bus Mastering Fast SCSI Controller for PCI Systems
Am53CF94/96
Enhanced Fast SCSI-2 Controller
Am79C90
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98
Twisted-Pair Ethernet Transceiver (TPEX)
Am79C100
Twisted-Pair Ethernet Transceiver Plus (TPEX+)
Am79C900
Integrated Local Area Communications ControllerTM (ILACCTM)
Am79C940
Media Acces Controller for Ethernet (MACETM)
Am79C960
PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961
PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support)
Am79C965
PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses)
Am79C970
PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus
Am79C981
Integrated Multiport Repeater PlusTM (IMR+TM)
Am79C987
Hardware Implemented Management Information BaseTM (HIMIBTM)
Am7990
Local Area Network Controller for Ethernet (LANCE)
Am7996
IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am85C30
Enhanced Serial Communication Controller
Am79C974
11
AMD
PRELIMINARY
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
AD28
AD29
VSSB
AD30
AD31
REQA
REQB
VSS
GNTA
GNTB
VDD
CLK
RST
VSS
INTB
INTA
RESERVE
SLEEP
EECS
DVSS
EESK/LED1
EEDI/LNKST
EEDO/LED3
DVDD
AVDD2
CI+
CIDI+
DIAVDD1
DO+
DOAVSS1
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Am79C974
PCnet-SCSI
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXDTXPAVDD4
RXD+
RXDDVSS
I/O
C/D
MSG
VDD
ACK
VSSBS
REQ
SEL
DVSS
SDP
SD7
VDDBS
SD6
SD5
SD4
VSSBS
SD3
SD2
SD1
SD0
VSSBS
PAR
C/BE1
AD15
VSSB
AD14
AD13
AD12
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
VSSB
AD5
AD4
AD3
AD2
VSSB
AD1
AD0
PWDN
VDD
SCSICLK
VSS
BUSY
VSS
BSY
ATN
SCSI^RST
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
IDSELA
IDSELB
VSS
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
18681A-3
Pin 1 is marked for orientation.
RESERVE = Don’t Connect.
12
Am79C974
AMD
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C974
K
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and Formed in a Tray
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
PACKAGE TYPE (per Prod. Nomenclature)
K = Plastic Quad Flat Pack Trimmed and Formed
(PQB132)
SPEED OPTION
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C974
PCnet-SCSI Combination Ethernet and
SCSI Controller for PCI Systems
Valid Combinations
Valid Combinations
AM79C974
KC\W
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Am79C974
13
AMD
PRELIMINARY
PIN DESIGNATIONS
Listed by Pin Number
14
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
VDDB
34
PAR
67
VSSBS
100
AVSS1
2
AD27
35
C/BE1
68
SD0
101
DO–
3
AD26
36
AD15
69
SD1
102
DO+
4
VSSB
37
VSSB
70
SD2
103
AVDD1
5
AD25
38
AD14
71
SD3
104
DI–
6
AD24
39
AD13
72
VSSBS
105
DI+
7
C/BE3
40
AD12
73
SD4
106
CI–
8
VDD
41
AD11
74
SD5
107
CI+
9
IDSELA
42
AD10
75
SD6
108
AVDD2
10
IDSELB
43
VSSB
76
VDDBS
109
DVDD
11
VSS
44
AD9
77
SD7
110
EEDO/LED3
12
AD23
45
AD8
78
SDP
111
EEDI/LNKST
13
AD22
46
VDDB
79
DVSS
112
EESK/LED1
14
VSSB
47
C/BE0
80
SEL
113
DVSS
15
AD21
48
AD7
81
REQ
114
EECS
16
AD20
49
AD6
82
VSSBS
115
SLEEP
17
VDDB
50
VSSB
83
ACK
116
RESERVE
18
AD19
51
AD5
84
DVDD
117
INTA
19
AD18
52
AD4
85
MSG
118
INTB
20
VSSB
53
AD3
86
C/D
119
VSS
21
AD17
54
AD2
87
I/O
120
RST
22
AD16
55
VSSB
88
DVSS
121
CLK
23
C/BE2
56
AD1
89
RXD–
122
VDD
24
FRAME
57
AD0
90
RXD+
123
GNTB
25
IRDY
58
PWDN
91
AVDD4
124
GNTA
26
TRDY
59
VDD
92
TXP–
125
VSS
27
DEVSEL
60
SCSICLK
93
TXD–
126
REQB
28
STOP
61
VSS
94
TXP+
127
REQA
29
LOCK
62
BUSY
95
TXD+
128
AD31
30
VSS
63
VSS
96
AVDD3
129
AD30
31
PERR
64
BSY
97
XTAL1
130
VSSB
32
SERR
65
ATN
98
AVSS2
131
AD29
33
VDDB
66
SCSI^RST
99
XTAL2
132
AD28
Am79C974
AMD
PRELIMINARY
PIN DESIGNATIONS
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
ACK
83
ATN
65
GNTB
123
STOP
28
AD0
57
AVDD1
103
IDSELA
9
TRDY
26
AD1
56
AVDD2
108
IDSEL
10
XTAL1
97
AD2
54
AVDD3
96
INTA
117
XTAL2
99
AD3
53
AVDD4
91
INTB
118
TXD–
93
AD4
52
AVSS1
100
I/O
87
TXD+
95
AD5
51
AVSS2
98
IRDY
25
TXP–
92
AD6
49
BSY
64
LOCK
29
TXP+
94
AD7
48
BUSY
62
MSG
85
VDD
8
AD8
45
C/BE0
47
PAR
34
VDD
59
AD9
44
C/BE1
35
PERR
31
VDD
122
AD10
42
C/BE2
23
PWDN
58
VDDB
1
AD11
41
C/BE3
7
REQ
81
VDDB
17
AD12
40
C/D
86
REQA
127
VDDB
33
AD13
39
CLK
121
REQB
126
VDDB
46
AD14
38
CI–
106
RESERVE
116
VDDBS
76
AD15
36
CI+
107
RST
120
VSS
11
AD16
22
DEVSEL
27
RXD–
89
VSS
30
AD17
21
DI–
104
RXD+
90
VSS
61
AD18
19
DI+
105
SCSICLK
60
VSS
63
AD19
18
DO–
101
SCSI^RST
66
VSS
119
AD20
16
DO+
102
SD0
68
VSS
125
AD21
15
DVDD
84
SD1
69
VSSB
4
AD22
13
DVDD
109
SD2
70
VSSB
14
AD23
12
DVSS
79
SD3
71
VSSB
20
AD24
6
DVSS
88
SD4
73
VSSB
37
AD25
5
DVSS
113
SD5
74
VSSB
43
AD26
3
EECS
114
SD6
75
VSSB
50
AD27
2
EEDI/LNKST
111
SD7
77
VSSB
55
AD28
132
EEDO/LED3
110
SDP
78
VSSB
130
AD29
131
EESK/LED1
112
SEL
80
VSSBS
67
AD30
129
FRAME
24
SERR
32
VSSBS
72
AD31
128
GNTA
124
SLEEP
115
VSSBS
82
Am79C974
15
AMD
PRELIMINARY
PIN DESIGNATIONS
Quick Reference Pin Description
Pin Name
Description
Type
Driver
# Pins
PCI Bus Interface
AD[31:00]
Address/Data Bus
IO
TS3
32
C/BE[3:0]
Bus Command/Byte Enable
IO
TS3
4
CLK
Bus Clock
I
NA
1
DEVSEL
Device Select
IO
TS6
1
FRAME
Cycle Frame
IO
TS6
1
GNTA, GNTB
Bus Grant
I
NA
1
IDSELA, IDSELB
Initialization Device Select
I
NA
1
INTA, INTB
Interrupt
IO
OD6
1
IRDY
Initiator Ready
IO
TS6
1
LOCK
Bus Lock
IO
TS6
1
PAR
Parity
IO
TS6
1
PERR
Parity Error
IO
TS6
1
REQA, REQB
Bus Request
IO
TS3
1
RST
Reset
I
NA
1
SERR
System Error
IO
OD6
1
STOP
Stop
IO
TS6
1
TRDY
Target Ready
IO
TS6
1
O
O8
1
1
ETHERNET SPECIFIC
Board Interface
EECS
Microwire Serial PROM Chip Select
EEDI/LNKST
Microwire Serial EEPROM Data In/Link Status
O
LED
EEDO/LED3
Microwire APROM Data Out/LED predriver
IO
LED
1
EESK/LED1
Microwire Serial PROM Clock/LED1
IO
LED
1
SLEEP
Sleep Mode
XTAL1–2
Crystal Input/Output
I
NA
1
IO
NA
2
I
NA
2
Attachment Unit Interface (AUI)
CI+/CI–
AUI Collision Differential Pair
DI+/DI–
AUI Data In Differential Pair
I
NA
2
DO+/DO–
AUI Data Out Differential Pair
O
DO
2
10BASE-T Interface
RXD+/RXD–
Receive Differential Pair
I
NA
2
TXD+/TXD–
Transmit Differential Pair
O
TDO
2
TXP+/TXP–
Transmit Pre-distortion Differential Pair
O
TPO
2
LNKST/EEDI
Link Status/Microwire Serial EEPROM Data In
O
LED
1
16
Am79C974
AMD
PRELIMINARY
PIN DESIGNATIONS (continued)
Quick Reference Pin Description
Pin Name
Description
Type
Driver
# Pins
SCSI SPECIFIC
SCSI Interface
SD [7:0]
SCSI Data
IO
OD48
8
SDP
SCSI Data Parity
IO
OD48
1
MSG
Message
C/D
Command/Data
I
1
I/O
Input/Output
I
1
ATN
Attention
O
OD48
1
BSY
Busy
IO
OD48
1
SEL
Select
IO
OD48
1
SCSI^RST
SCSI Bus Reset
IO
OD48
1
REQ
Request
I
ACK
Acknowledge
O
SCSI CLK
SCSI Core Clock
I
1
RESERVE
Reserved, DO NOT CONNECT
I
1
Power Down Indicator
I
1
NAND Tree Test Output
O
O3
1
AVDD
Analog Power
P
NA
4
AVSS
Analog Ground
P
NA
2
VDD/DVDD
Digital Power
P
NA
5
VSS/DVSS
Digital Ground
P
NA
9
VDDB/VDDBS
I/O Buffer Power
P
NA
5
VSSB/VSSBS
I/O Buffer Ground
P
NA
11
I
1
1
OD48
1
Miscellaneous
Power Management
PWDN
Test Interface
BUSY
Power Supplies
Listed by Driver Type
The following table describes the various types of drivers that are implemented in the PCnet-SCSI controller. Current
is given as milliamperes:
Name
Type
TM
IOL (mA)
IOH (mA)
pF
TS3
Tri-State
3
–2.0
50
TS6
Tri-State
6
–2.0
50
O3
Totem Pole
3
–0.4
50
O6
Totem Pole
6
–0.4
50
O8
Totem Pole
8
–0.4
50
OD6
Open Drain
6
NA
50
OD48
Open Drain
48
NA
—
LED
12
–0.4
50
LED
Am79C974
17
AMD
PRELIMINARY
LOGIC SYMBOL
CI+/–
AD [31:0]
DI+/–
XTAL1
C/BE [3:0]
XTAL2
DO+/–
PAR
RXD+/–
FRAME
Ethernet
TXD+/–
TRDY
TXP+/–
EEDI/LINKST
IRDY
EECS
STOP
EESK/LED1
EEDO/LED3
DEVSEL
PCI Interface
IDSELA
SD [7:0]
IDSELB
REQA
SDP
PCnet-SCSI
(Am79C974)
MSG
C/D
REQB
I/O
GNTA
ATN
BSY
GNTB
SCSI
SEL
CLK
SCSI^RST
RST
REQ
INTA
ACK
INTB
SCSI CLK
RESERVE
LOCK
PERR
SERR
PWDN
Power
Management
Signals
BUSY
Test Interface
18248B-4
VDD
18
VSS
Am79C974
PRELIMINARY
AMD
with respect to this edge. The PCnet-SCSI controller operates over a range of 0 to 33 MHz.
PIN DESCRIPTION
PCI Bus Interface
AD[31:00]
When RST is active, CLK is an input for NAND tree
testing.
Address and Data
Input/Output, Active High
DEVSEL
These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subsequent clocks AD[31:00] contain data. Byte ordering is little endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnetSCSI controller can be programmed for big endian byte
ordering. See CSR3, bit 2 (BSWP) for more details.
During the address phase of the transaction, when the
PCnet-SCSI controller is a bus master, AD[31:2] will address the active DWORD (double-word). The PCnetSCSI controller always drives AD[1:0] to ‘00’ during the
address phase indicating linear burst order. When the
PCnet-SCSI controller is not a bus master, the
AD[31:00] lines are continuously monitored to determine if an address match exists for I/O slave transfers.
During the data phase of the transaction, AD[31:00] are
driven by the PCnet-SCSI controller when performing
bus master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-SCSI controller when
performing bus master reads and slave write
operations.
When RST is active, AD[31:0] are inputs for NAND tree
testing.
C/BE [3:0]
Device Select
Input/Output, Active Low
This signal when actively driven by the PCnet-SCSI
controller as a slave device signals to the master device
that the PCnet-SCSI controller has decoded its address
as the target of the current access. As an input it indicates whether any device on the bus has been selected.
When RST is active, DEVSEL is an input for NAND tree
testing.
FRAME
Cycle Frame
Input/Output, Active Low
This signal is driven by the PCnet-SCSI controller when
it is the bus master to indicate the beginning and duration of the access. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted when the
transaction is in the final data phase.
When RST is active, FRAME is an input for NAND tree
testing.
GNTA
Bus Grant
Input, Active Low
This signal indicates that the access to the bus has been
granted to the Am79C974’s SCSI controller.
Bus Command and Byte Enables
Input/Output, Active Low
These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/BE[3:0]
define the bus command. During the data phase
C/BE[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/BE0 applies to byte 0 (AD[07:00]) and C/BE3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND tree
testing.
CLK
Clock
Input
This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-SCSI controller. All bus signals are sampled on
the rising edge of CLK and all parameters are defined
The Am79C974 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNTA
without an active REQA from the Am79C974 controller,
the controller will actively drive the AD[31:00], C/
BE[3:0], and PAR lines.
When RST is active, GNTA is an input for NAND tree
testing.
GNTB
Bus Grant
Input, Active Low
This signal indicates that the access to the bus has been
granted to the Am79C974’s Ethernet controller. The
Am79C974 controller supports bus parking. When the
PCI bus is idle and the system arbiter asserts GNTB
without an active REQB from the Am79C974 controller,
the controller will actively drive the AD, C/BE and PAR
lines.
Am79C974
19
AMD
PRELIMINARY
When RST is active, GNTB is an input for NAND tree
testing.
IDSELA
Initialization Device Select
Input, Active High
This signal is used as a SCSI controller selection for the
Am79C974
during
configuration
read
and
write transaction.
When RST is active, IDSELA is an input for NAND tree
testing.
IDSELB
Initialization Device Select
Input, Active High
This signal is used as an Ethernet controller selection for
the PCnet-SCSI controller during configuration read
and write transaction.
When RST is active, IDSELB is an input for NAND tree
testing.
INTA
Interrupt Request
Input/Output, Active Low, Open Drain
IRDY
Initiator Ready
Input/Output, Active Low
This signal indicates PCnet-SCSI controller’s ability, as
a master device, to complete the current data phase of
the transaction. IRDY is used in conjunction with the
TRDY. A data phase is completed on any clock when
both IRDY and TRDY are asserted. During a write IRDY
indicates that valid data is present on AD[31:00]. During
a read IRDY indicates that data is accepted by the
PCnet-SCSI controller as a bus master. Wait states are
inserted until both IRDY and TRDY are asserted simultaneously.
When RST is active, IRDY is an input for NAND tree
testing.
LOCK
Lock
Input, Active Low
LOCK is used by the current bus master to indicate an
atomic operation that may require multiple transfers.
As a slave device, the PCnet-SCSI controller can be
locked by any master device. When another master attempts to access the PCnet-SCSI while it is locked, the
PCnet-SCSI controller will respond by asserting
DEVSEL and STOP with TRDY deasserted (PCI retry).
This signal combines the interrupt requests from both
the SCSI DMA engine and the SCSI core. The interrupt
source can be determined by reading the SCSI DMA
Status Register. It is cleared when the Status Register is
read.
The PCnet-SCSI controller will never assert LOCK as a
master.
When RST is active, INTA is an input for NAND tree testing. This is the only time INTA is an input.
When RST is active, LOCK is an input for NAND tree
testing.
INTB
PAR
Interrupt Request
Input/Output, Active Low, Open Drain
Parity
Input/Output, Active High
An asynchronous attention signal which indicates that
one or more of the following status flags is set: BABL,
MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB,
MPCO, or TXSTRT. Each status flag has a mask bit
which allows for suppression of INTB assertion. The
flags have the following meaning:
BABL
RCVCCO
RPCO
JAB
MISS
MERR
MPCO
RINT
IDON
TXSTRT
Babble
Receive Collision Count Overflow
Runt Packet Count Overflow
Jabber
Missed Frame
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
When RST is active, INTB is an input for NAND tree
testing. This is the only time INTB is an input.
20
Parity is even parity across AD[31:00] and C/BE[3:0].
When the PCnet-SCSI controller is a bus master, it
generates parity during the address and write data
phases. It checks parity during read data phases. When
the PCnet-SCSI controller operates in slave mode and
is the target of the current cycle, it generates parity during read data phases. It checks parity during address
and write data phases.
When RST is active, PAR is an input for NAND tree
testing.
PERR
Parity Error
Input/Output, Active Low, Open Drain
This signal is asserted for one CLK by the PCnet-SCSI
controller when it detects a parity error during any data
phase when its AD[31:00] lines are inputs. The PERR
pin is only active when PERREN (bit 6) in the PCI command register is set.
Am79C974
PRELIMINARY
The PCnet-SCSI controller monitors the PERR input
during a bus master write cycle. It will assert the Data
Parity Reported bit in the Status register of the Configuration Space when a parity error is reported by the target
device.
When RST is active, PERR is an input for NAND tree
testing.
REQA
Bus Request
Input/Output, Active Low
AMD
When RST is active, SERR is an input for NAND tree
testing.
STOP
Stop
Input/Output, Active Low
In the slave role, the PCnet-SCSI controller drives the
STOP signal to inform the bus master to stop the current
transaction. In the bus master role, the PCnet-SCSI
controller receives the STOP signal and stops the current transaction.
The Am79C974’s SCSI controller asserts REQA pin as
a signal that it wishes to become a bus master. Once asserted, REQA remains active until GNTA has become
active.
When RST is active, STOP is an input for NAND tree
testing.
When RST is active, REQA is an input for NAND tree
testing. This is the only time REQA is an input.
Target Ready
Input/Output, Active Low
REQB
Bus Request
Input/Output, Active Low
The Am79C974’s Ethernet controller asserts REQB pin
as a signal that it wishes to become a bus master. Once
asserted, REQB remains active until GNT has become
active, independent of subsequent assertion of SLEEP
or setting of the STOP bit or access to the S_RESET
port (offset 14h).
When RST is active, REQB is an input for NAND tree
testing. This is the only time REQB is an input.
TRDY
This signal indicates the PCnet-SCSI controller’s ability
as a selected device to complete the current data phase
of the transaction. TRDY is used in conjunction with the
IRDY. A data phase is completed on any clock both
TRDY and IRDY are asserted. During a read TRDY indicates that valid data is present on AD[31:00]. During a
write, TRDY indicates that data has been accepted.
Wait states are inserted until both IRDY and TRDY are
asserted simultaneously.
When RST is active, TRDY is an input for NAND tree
testing.
RST
Ethernet Controller Pins
Reset
Input, Active Low
Board Interface
When RST is asserted low, then the PCnet-SCSI controller performs an internal system reset of the type
H_RESET (HARDWARE_RESET). RST must be held
for a minimum of 30 CLK periods. While in the H_RESET state, the PCnet-SCSI controller will disable or
deassert all outputs. RST may be asynchronous to the
CLK when asserted or deasserted. It is recommended
that the deassertion be synchronous to guarantee a
clean and bounce free edge.
LED1
Output
When RST is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the BUSY output
(pin 62).
SERR
System Error
Input/Output, Active Low, Open Drain
This signal is asserted for one CLK by the PCnet-SCSI
controller when it detects a parity error during the address phase when its AD[31:00] lines are inputs.
The SERR pin is only active when SERREN (bit 8) and
PERREN (bit 6) in the PCI command register are set.
LED1
This pin is shared with the EESK function. As LED1, the
function and polarity of this pin are programmable
through BCR5. By default, LED1 is active LOW and it indicates receive activity on the network. The LED1 output
from the PCnet-SCSI controller is capable of sinking the
12 mA of current necessary to drive an LED directly.
The LED1 pin is also used during EEPROM Auto-detection to determine whether or not an EEPROM is present
at the PCnet-SCSI controller Microwire interface. At the
trailing edge of the RST pin, LED1 is sampled to determine the value of the EEDET bit in BCR19. A sampled
HIGH value means that an EEPROM is present, and
EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection section for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in order to resolve the EEDET setting.
Am79C974
21
AMD
PRELIMINARY
LED3
LED3
Output
This pin is shared with the EEDO function of the
Microwire serial EEPROM interface. When functioning
as LED3, the signal on this pin is programmable through
BCR7. By default, LED3 is active LOW and it indicates
transmit activity on the network. Special attention must
be given to the external circuitry attached to this pin. If
an LED circuit were directly attached to this pin, it would
create an IOL requirement that could not be met by the
serial EEPROM that would also be attached to this pin.
Therefore, if this pin is to be used as an additional LED
output while an EEPROM is used in the system, then
buffering is required between the LED3 pin and the LED
circuit. If no EEPROM is included in the system design,
then the LED3 signal may be directly connected to an
LED without buffering. The LED3 output from the
PCnet-SCSI controller is capable of sinking the 12 mA of
current necessary to drive an LED in this case. For more
details regarding LED connection, see the section on
LEDs.
LNKST
LINK Status
Output
This pin provides 12 mA for driving an LED. By default, it
indicates an active link connection on the 10BASE-T interface. This pin can also be programmed to indicate
other network status (see BCR4). The LNKST pin
polarity is programmable, but by default, it is active
LOW. Note that this pin is multiplexed with the EEDI
function.
SLEEP
Sleep
Input
When SLEEP is asserted (active LOW), the PCnetSCSI controller performs an internal system reset of the
S_RESET type and then proceeds into a power savings
mode. (The reset operation caused by SLEEP assertion
will not affect BCR registers.) The PCI interface section
is not effected by SLEEP. In particular, access to the
PCI configuration space remains possible. None of the
configuration registers will be reset by SLEEP. All I/O
accesses to the PCnet-SCSI controller will result in a
PCI target abort response. The PCnet-SCSI controller
will not assert REQ while in sleep mode. When SLEEP
is asserted, all non-PCI interface outputs will be placed
in their normal S_RESET condition. All non-PCI interface inputs will be ignored except for the SLEEP pin itself. De-assertion of SLEEP results in wake-up. The
system must refrain from starting the network operations of the PCnet-SCSI device for 0.5 seconds following the deassertion of the SLEEP signal in order to allow
internal analog circuits to stabilize.
22
Both CLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP command to take
effect. If SLEEP is asserted while REQ is asserted, then
the PCnet-SCSI controller will wait for the assertion of
GNT. When GNT is asserted, the REQ signal will be deasserted and then the PCnet-SCSI controller will proceed to the power savings mode.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the assertion of SLEEP until three CLK cycles after the completion of a valid pin RST operation.
The SLEEP pin does not affect the SCSI section.
XTAL1
Crystal Oscillator Input
Input
XTAL2
Crystal Oscillator Output
Output
The crystal frequency determines the network data rate.
The PCnet-SCSI controller supports the use of quartz
crystals to generate a 20 MHz frequency compatible
with the ISO 8802-3 (IEEE/ANSI 802.3) network frequency tolerance and jitter specifications. See the section External Crystal Characteristics (in section
Manchester Encoder/Decoder) for more detail.
The network data rate is one-half of the crystal frequency. XTAL1 may alternatively be driven using an external CMOS level source, in which case XTAL2 must
be left unconnected. Note that when the PCnet-SCSI
controller is in coma mode, there is an internal 22 KΩ resistor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resistor. If XTAL1 is driven LOW at this time power consumption will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of SLEEP
and deassertion of REQ.
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
Input/Output
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EESK is connected to the Microwire EEPROM’s Clock pin. It is controlled by either the PCnet-SCSI controller directly
during a read of the entire EEPROM, or indirectly by the
host system by writing to BCR19, bit 1.
The EESK pin is also used during EEPROM Auto-detection to determine whether or not an EEPROM is present
Am79C974
PRELIMINARY
at the PCnet-SCSI controller Microwire interface. At the
trailing edge of the RST signal, EESK is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present,
and EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection section for more details.
EESK is shared with the LED1 function. If no LED circuit
is to be attached to this pin, then a pull up or pull down
resistor must be attached instead, in order to resolve the
EEDET setting.
EEDO
EEPROM Data Out
Input
The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EEDO is connected to the Microwire EEPROM’s Data Output pin. It
is controlled by the EEPROM during reads. It may be
read by the host system by reading BCR19 bit 0.
EEDO is shared with the LED3 function.
AMD
Attachment Unit Interface
CI±
Collision In
Input
A differential input pair signaling the PCnet-SCSI controller that a collision has been detected on the network
media, indicated by the CI± inputs being driven with a
10 MHz pattern of sufficient amplitude and pulse width
to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at pseudo ECL levels.
DI±
Data In
Input
A differential input pair to the PCnet-SCSI controller carrying Manchester encoded data from the network. Operates at pseudo ECL levels.
DO±
Data Out
Output
A differential output pair from the PCnet-SCSI controller
for transmitting Manchester encoded data to the network. Operates at pseudo ECL levels.
Twisted-Pair Interface
EECS
RXD±
EEPROM Chip Select
Output
The function of the EECS signal is to indicate to the
Microwire EEPROM device that it is being accessed.
The EECS signal is active high. It is controlled by either
the PCnet-SCSI controller during command portions of
a read of the entire EEPROM, or indirectly by the host
system by writing to BCR19 bit 2.
10BASE-T Receive Data
Input
10BASE-T port differential receivers.
TXD±
10BASE-T Transmit Data
Output
10BASE-T port differential drivers.
EEDI
EEPROM Data In
Output
The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions as an output. This pin is designed to directly interface to a serial EEPROM that uses the Microwire
interface protocol. EEDI is connected to the Microwire
EEPROM’s Data Input pin. It is controlled by either the
PCnet-SCSI controller during command portions of a
read of the entire EEPROM, or indirectly by the host system by writing to BCR19 bit 0.
TXP±
10BASE-T Pre-Distortion Control
Output
These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.
EEDI is shared with the LNKST function.
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SCSI Controller Pins
SCSI^RST
SCSI Bus Interface Signals
SCSI Bus Pins
Reset
Input/Output, Active Low, Schmitt Trigger,
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
SD [7:0]
SCSI Data
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger
These pins are defined as bi-directional SCSI data bus.
SDP
SCSI Data Parity
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger
This pin is defined as bi-directional SCSI data parity.
MSG
Message
Input, Active Low, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
Request
Input, Active Low, Schmitt Trigger
This is a SCSI input signal with a Schmitt trigger in the
initiator mode.
ACK
Acknowledge
Output, Active Low, Open Drain/Active Negation
This is a SCSI output signal with a 48 mA drive in the
initiator mode.
SCSI CLK
SCSI Clock
Input
The SCSI clock signal is used to generate all internal device timings. The maximum frequency of this input is
40 MHz and a minimum of 10 MHz is required to maintain the SCSI bus timings.
C/D
Command/Data
Input, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
I/O
Input/Output
Input, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
Note:
A 40 MHz clock must be supplied at this input to achieve
10 Mbyte/s Synchronous Fast SCSI transfers.
ATN
PWDN
Attention
Output, Active Low, Open Drain
This signal is a 48 mA output in the initiator mode. This
signal will be asserted when the device detects a parity
error; also, it can be asserted via certain commands.
BSY
Busy
Input/Output, Active Low, Schmitt Trigger,
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
SEL
Select
Input/Output, Active Low, Schmitt Trigger,
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
24
REQ
Power Down Indicator
Input, Active High
This signal, when asserted, sets the PWDN status bit in
the DMA status register and sends an interrupt to
the host.
Test Interface
BUSY
NAND Tree Out
Output, Active Low
This signal is logically equivalent to the SCSI bus signal
BSY. It is duplicated so that external logic can be
connected to monitor SCSI bus activity.
The results of the NAND tree testing can be observed on
the BUSY pin where RST is asserted; otherwise, BUSY
will reflect the state of the SCSI Bus Signal line BSY
(pin 64).
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Miscellaneous
RESERVED
Digital Power Supply Pins
Reserved_DO NOT CONNECT
Input
This pin (#116) is reserved for internal test logic. It
MUST NOT BE CONNECTED to anything for proper
chip operation. It’s use is subject to change in future
products.
Digital Power (5 Pins)
Power
Power Supply Pins
Analog Power Supply Pins
AVDD
VDDB/VDDB
AMD
VDD/DVDD
There are 5 power supply pins that are used by the internal digital circuitry. All VDD pins must be connected to a
+5 V supply.
I/O Buffer Power (5 Pins)
Power
There are 5 power supply pins that are used by the PCI
bus Input/Output buffer drivers. All VDDB pins must be
connected to a +5 V supply.
Analog Power (4 Pins)
Power
There are four analog +5 V supply pins. Special attention should be paid to the printed circuit board layout to
avoid excessive noise on these lines. Refer to
Appendix C and the Technical Manual (PID #18738A)
for details.
VSS/DVSS
Digital Ground (9 Pins)
Ground
AVSS
There are 9 ground pins that are used by the internal
digital circuitry.
Analog Ground (2 Pins)
Power
VSSB/VSSBS
There are two analog ground pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on these lines. Refer to Appendix C and
the Technical Manual (PID #18738A) for details.
I/O Buffer Ground (11 Pins)
Ground
There are 11 ground pins that are used by the PCI bus
Input/Output buffer drivers.
Am79C974
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registers are used to set up controller operating modes,
to enable or disable various features, to start certain operations, and to monitor operating status.
BASIC FUNCTIONS
System Bus Interface Function
During normal operations the Am79C974 operates as a
bus master with a few slave l/O accesses for status and
control functions.
The Ethernet controller is initialized through a combination of PCI Configuration Space accesses, I/O space
Bus Slave accesses, Memory Space Bus Master accesses, and optional reads of an external serial
EEPROM. The EEPROM is read through the Microwire
interface either automatically by the Am79C974 or indirectly by a series of bus slave accesses to one of the
Ethernet Bus Configuration Registers (BCRs). The
EEPROM normally contains the ISO 8802-3 (IEEE/
ANSI 802.3) Ethernet node address and data to be
loaded into some of the Ethernet BCRs.
The SCSI controller is initialized by bus slave writes to
SCSI Core and SCSI DMA registers.
Software Interface
The Am79C794 uses four address spaces: Ethernet
PCI configuration space, SCSI PCI configuration space,
I/O space, and memory space.
SCSI PCI configuration space is selected when the
IDSELA pin is active. Ethernet PCI configuration space
is selected when the IDSELB pin is active. The way that
IDSELA and IDSELB are controlled depends on external hardware. Section 3.6.4.1 of the PCI Specification
recommends two methods of generating configuration
cycles called Configuration Mechanism #1 and Configuration Mechanism #2.
The PCI Configuration Spaces are used by system software to identify the SCSI and Ethernet controllers and to
set up device configuration without the use of jumpers.
Certain PCI configuration registers have read-only information about the devices resource requirements. Other
registers are used as mail boxes that system configuration software uses to inform other software what resources have been allocated to the device. The only PCI
Configuration Registers that affect the operation of the
Am79C794 are the SCSI and Ethernet Base Address
Registers, which are found at offset 10h in each of the
two configuration spaces, and the Command Registers
at offset 4. Writing to these registers establishes the
base address of the SCSI l/O space and the base address of the Ethernet I/O space.
The SCSI controller registers occupy 96 bytes of l/O
space that starts on whatever 128-byte boundary that is
programmed into the Base Address Register at offset
10h in the SCSI PCI Configuration Space. The Ethernet
controller registers occupy 32 bytes of l/O space that
starts on whatever 32-byte boundary that is programmed into the Base Address Register at offset 10h
in the Ethernet PCI Configuration Space. These
26
In addition to the registers in the l/O space, the Ethernet
controller uses certain data structures that are set up
(typically by the host computer) in normal memory
space. These data structures are (1) the initialization
block that contains configuration data that the Ethernet
controller automatically loads into its Configuration and
Status Registers (CSRs), (2) the Receive and Transmit
Descriptor Rings, that contain pointers to receive and
transmit buffers and status and control information
about these buffers, and (3) the receive and transmit
buffers. The Ethernet controller uses bus master accesses to read the locations of the buffers, to store
frames received from the network into the receive buffers, and to transmit the contents of the transmit buffers.
Ethernet Interfaces
The Am79C974 controller can be connected to an 802.3
network via one of two network interfaces. The Attachment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection.
SCSI Interfaces
The Am79C974 acts as a bridge between the PCI and
SCSI buses. As the maximum data transfer rate on the
PCI bus is a very high 132 Mbyte/s compared with the
SCSI bus 10 Mbyte/s, buffering is required between the
two buses. The buffering is provided by two FIFOs: a
16-byte (16X8 bits) SCSI Core FIFO and an additional
96-byte (24X32 bits) DMA FIFO. These FIFOs provide a
temporary storage for all command, data, status and
message bytes as they are transferred between the
32-bit PCI bus and the 8-bit SCSI bus.
The Am79C974’s SCSI Core and DMA registers are addressed using the value in the Base Address Register
(offset 10h in the PCI Configuration Space). The SCSI
registers occupy 16 double words and the DMA engine
registers occupy 8 double word locations. The I/O address map is as follows:
Start Offset
End Offset
Block Name
Size
0x0000
0x003F
SCSI Core Reg
16 DW/64B
0x0040
0x005F
PCI DMA CCB
8 DW/32B
The PCI configuration space, Ethernet controller and
SCSI controller are described in detail in the following
sections.
Am79C974
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space with a configuration read or write command. The
Am79C974 controller will assert DEVSEL if the IDSEL
input is asserted during the address phase and if the access is a configuration cycle. DEVSEL is asserted two
clock cycles after the host has asserted FRAME. All
configuration cycles are of fixed length. The Am79C974
controller will assert TRDY on the 3rd clock of the
data phase.
DETAILED FUNCTIONS
Bus Interface Unit (BIU)
The bus interface unit is built of several state machines
that run synchronously to CLK. One bus interface unit
state machine handles accesses where the Am79C974
controller is the bus slave, and another handles accesses where the Am79C974 controller is the bus master. All inputs are synchronously sampled. All outputs
are synchronously generated on the rising edge of CLK.
Slave Configuration Read
The Slave Configuration Read command is used by the
host CPU to read the configuration space in the
Am79C974 controller. This provides the host CPU with
information concerning the device and its capabilities.
This is a single cycle, non-burst 8-bit, 16-bit, or 32-bit
transfer.
In the descriptions that follow, GNT, REQ, INT, and
IDSEL are used to refer to the set of GNTA, REQA,
INTA, and IDSELA for the SCSI controller and to the set
of GNTB, REQB, INTB, and IDSELB for the Ethernet
Controller, respectively.
Slave Configuration Transfers
The host can access the Am79C974 PCI configuration
CLK
1
2
3
4
5
6
FRAME
AD
ADDR
C/BE
1010
PAR
DATA
BE's
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
IDSEL
18681A-5
Figure 1. Slave Configuration Read
Am79C974
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Slave Configuration Write
control basic activity of the device, such as enable/disable, change I/O location, etc. This is a single cycle,
non-burst 8-bit, 16-bit, or 32-bit transfer.
The Slave Configuration Write command is used by the
host CPU to write the configuration space in the
Am79C974 controller. This allows the host CPU to
CLK
1
2
3
4
5
6
FRAME
AD
ADDR
C/BE
1011
PAR
DATA
BE's
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
IDSEL
18681A-6
Figure 2. Slave Configuration Write
28
Am79C974
AMD
PRELIMINARY
Slave I/O Transfers
After the Am79C974 controller is configured as I/O device (by setting IOEN in the PCI Command register), it
starts monitoring the PCI bus for access to its internal
registers. The Am79C974 controller will look for an address that falls within its I/O address space. The
Am79C974 controller will assert DEVSEL if it detects an
address match and the access is an I/O cycle. DEVSEL
is asserted two clock cycles after the host has asserted
FRAME. The Am79C974 controller will not assert DEVSEL if it detects an address match, but the PCI command is not of the type I/O read or I/O write. The
Am79C974 controller will suspend looking for I/O cycles
while being a bus master.
Slave I/O Read
The Slave I/O Read command is used by the host CPU
to read the Am79C974’s CSRs, BCRs and EEPROM locations and SCSI and CCB registers. It is a single cycle,
non-burst 8-bit,16-bit or 32-bit transfer which is initiated
by the host CPU. The typical number of wait states
added to a slave I/O read access on the part of the
Am79C974 controller is 6 to 7 clock cycles. The
Am79C974 controller will not produce Slave I/O Read
commands while being a bus master.
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
ADDR
C/BE
0010
PAR
DATA
BE's
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
18681A-7
Figure 3. Slave I/O Read
Am79C974
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Slave I/O Write
The Slave I/O Write command is used by the host CPU
to write to the Am79C974’s CSRs, BCRs and EEPROM
locations and SCSI and CCB registers. It is a single cycle, non-burst 8-bit, 16–bit, or 32-bit transfer which is
initiated by the host CPU. The typical number of wait
states added to a slave I/O write access on the part of
the Am79C974 controller is 6 to 7 clock cycles. The
Am79C974 controller will not produce Slave I/O write
commands while being a bus master.
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
ADDR
C/BE
0011
PAR
DATA
BE's
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
18681A-8
Figure 4. Slave I/O Write
30
Am79C974
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PRELIMINARY
Bus Acquisition
The Am79C974 microcode (in the buffer management
section) will determine when a DMA transfer should be
initiated. The first step in any Am79C974 bus master
transfer is to acquire ownership of the bus. This task is
handled by synchronous logic within the BIU. Bus ownership is requested with the REQ signal and ownership
is granted by the arbiter through the GNT signal.
CLK
1
2
3
4
5
FRAME
Figure 5 shows the Am79C974 controller bus acquisition. GNT is asserted at clock 3. The Am79C974 controller starts driving AD[31:00] and C/BE[3:0] prior to clock
4. FRAME is asserted at clock 5 indicating a valid address and command on AD[31:00] and C/BE[3:0].
ADSTEP (bit 7) in the PCI Command register is set to
ONE to indicated that the Am79C974 controller uses address stepping. Address stepping is only used for the
first address phase of a bus master period.
AD
ADDR
C/BE
CMD
REQ
GNT
18681A-9
Figure 5. Bus Acquisition
Am79C974
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Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C974 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Cycles
All Am79C974 controller non-burst read accesses are of
the PCI command type Memory Read (type 6). Note that
during all non-burst read operations, the Am79C974
controller will always activate all byte enables, even
though some byte lanes may not contain valid data as
indicated by a buffer pointer value. In such instances,
the Am79C974 controller will internally discard unneeded bytes.
Figure 6 shows a typical non-burst read access. The
Am79C974 controller asserts IRDY at clock 5 immediately after the address phase and starts sampling
DEVSEL. The target extends the cycle by asserting
DEVSEL not until clock 6. Additionally, the target inserts
one wait state by asserting its ready (TRDY) at clock 8.
CLK
1
2
3
4
5
6
7
8
9
FRAME
AD
C/BE
PAR
ADDR
0110
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-10
Figure 6. Non-Burst Read Cycles With Wait States
32
Am79C974
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Figure 7 shows two non-burst read access within one arbitration cycle. The Am79C974 controller will drop
FRAME between two consecutive non-burst read cycles. The Am79C974 controller will re-request the bus
right again if it is preempted before starting the second
access. The example below also shows a target that can
respond to the Am79C974 controller read cycles without
wait states.
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
PAR
ADDR
0110
DATA
ADDR
0000
PAR
0110
PAR
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-11
Figure 7. Non-Burst Read Cycles Without Wait States
Am79C974
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immediately if it is preempted before starting the second
access. The example below shows an extended cycle
for the first access. The target asserts DEVSEL 2 clock
cycles after the address phase (FRAME asserted) and
adds one extra wait state by asserting TRDY only on
clock 7. The second write cycle in the example shows a
ZERO wait state access.
Basic Non-Burst Write
All Am79C974 controller non-burst write accesses are
of the PCI command type Memory Write (type 7).
Figure 8 shows two non-burst write access within one
arbitration cycle. The Am79C974 controller will drop
FRAME between two consecutive non-burst write cycles. The Am79C974 controller will re-request the bus
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
PAR
ADDR
DATA
ADDR
DATA
0111
BE's
0111
BE's
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-12
Figure 8. Non-Burst Write Cycles With and Without Wait States
34
Am79C974
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Basic Burst Read Cycles
mode.
All Am79C974 controller burst read transfers are of the
PCI command type Memory Read Line (type14).
AD[1:0] will both be ZERO during the address phase indicating a linear burst order. All four byte enable signals
will be ZERO during the data phase as the Am79C974
controller always reads a full 32-bit word when in burst
Figure 9 shows a typical burst read access. The
Am79C974 controller arbitrates for the bus, is granted
access, and reads four 32-bit words (DWORD) from
system memory and then releases the bus. All four data
phases in this example take two clock cycles each,
which is determined by the timing of TRDY.
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
AD
C/BE
PAR
ADDR
1110
DATA
DATA
DATA
DATA
0000
PAR
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-13
Figure 9. Burst Read Cycles
Am79C974
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Basic Burst Write Cycles
Am79C974 controller arbitrates for the bus, is granted
access, and writes four 32-bit words (DWORDs) from
system memory and then releases the bus. In this example, the memory system extends the data phase of
the first access by one wait state. The following three
data phases take one clock cycle each, which is determined by the timing of TRDY.
All Am79C974 controller burst write transfers are of the
PCI command type Memory Write (type 7). AD[1:0] will
both be ZERO during the address phase indicating a linear burst order. All four byte enable signals will be ZERO
during the data phase as the Am79C974 controller always writes a full 32-bit word when in burst mode.
Figure 10 shows a typical burst write access. The
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
DATA
DATA
DATA
PAR
PAR
0000
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-14
Figure 10. Burst Write Cycles
36
Am79C974
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Transaction Termination
Disconnect With Data Transfer
Termination of a PCI transaction may be initiated by
either the master or the target. During termination, the
master remains in control to bring all PCI transactions to
an orderly and systematic conclusion regardless of what
caused the termination. All transactions are concluded
when FRAME and IRDY are both deasserted, indicating
an IDLE cycle.
Figure 11 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP is
asserted on clock 4 to start the termination sequence.
Data is still transferred during this cycles, since both
IRDY and TRDY are asserted. The Am79C974 controller terminates the current transfer with the deassertion
of FRAME on clock 5 and then one clock cycle later with
the deassertion of IRDY. It finally releases the bus on
clock 6. The Am79C974 controller will re-request the
bus after 2 clock cycles, if it wants to transfer more data.
The starting address of the new transfer will be the address of the next untransferred data.
Target Initiated Termination
When the Am79C974 controller is a bus master, the cycles it produces on the PCI bus may be terminated by
the target in one of three different ways: Disconnect with
data transfer, disconnect without data transfer, and target abort.
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
PAR
ADDR i
0111
DATA
ADDR i+8
DATA
0000
PAR
0111
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-15
Figure 11. Disconnect with Data Transfer
Am79C974
37
AMD
PRELIMINARY
Disconnect Without Data Transfer
Figure 12 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C974 controller terminates the current transfer
with the deassertion of FRAME on clock 5 and one clock
cycle later with the deassertion of IRDY. It finally releases the bus on clock 6. The Am79C974 controller will
re-request the bus after 2 clock cycles to retry the last
transfer. The starting address of the new transfer will be
the same address as of the last untransferred data.
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
PAR
ADDRi
0111
ADDRi
DATA
0000
PAR
0111
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-16
Figure 12. Disconnect Without Data Transfer
38
Am79C974
AMD
PRELIMINARY
Target Abort
Since data integrity is not guaranteed, the Am79C974
controller cannot recover from a target abort event. For
Ethernet, the Am79C974 controller will reset all CSR
and BCR locations to their H_RESET values. Any ongoing network activity will be stopped immediately. The
PCI configuration registers will not be cleared. For
SCSI, when target aborts, INTA will not be asserted, but
the ABORT bit (bit 2 of the DMA status register at offset
54h), is set. For either Ethernet or SCSI a target abort
causes RTABORT (bit 12) of the status register in the
appropriate PCI configuration space to be set.
Figure 13 shows a target abort sequence. The target asserts DEVSEL for one clock. It then deasserts DEVSEL
and asserts STOP on clock 4. A target can use the target
abort sequence to indicate that it cannot service the data
transfer and that it does not want the transaction to be
retried. Additionally, the Am79C974 controller cannot
make any assumption about the success of the previous
data transfers in the current transaction. The
Am79C974 controller terminates the current transfer
with the deassertion of FRAME on clock 5 and one clock
cycle later with the deassertion of IRDY. It finally releases the bus on clock 6.
CLK
1
2
3
4
5
6
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-17
Figure 13. Target Abort
Am79C974
39
AMD
PRELIMINARY
when transferring data. FRAME is deasserted in between two address phases. While FRAME is deasserted, the central arbiter can remove GNT to the
Am79C974 controller at any time to service another
master. When GNT is removed, the Am79C974 controller will finish the current transfer and then release the
bus. It will keep REQ asserted to regain bus ownership
as soon as possible.
Master Initiated Termination
There are three scenarios besides normal completion of
a transaction where the Am79C974 controller will terminate the cycles it produces on the PCI bus. These are
Preemption with and without FRAME assertion and
Master Abort.
Preemption When FRAME is Deasserted
The Am79C974 controller can generate multiple address phases during a single bus ownership period
CLK
1
2
3
4
5
6
7
8
FRAME
AD
C/BE
PAR
ADDR
DATA
0111
BE's
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-18
Figure 14. Preemption When FRAME is Deasserted
40
Am79C974
AMD
PRELIMINARY
Preemption When FRAME is Asserted
troller will finish the current transfer and then immediately release the bus. The Latency Timer in PCI
configuration space of the Am79C974 controller is always set to ZERO. The Am79C974 controller will keep
REQ asserted to regain bus ownership as soon as possible.
The central arbiter can take GNT to the Am79C974 controller away if the current bus operation takes too long.
This may happen, for example, when the Am79C974
controller tries to fill the whole Ethernet transmit FIFO
and the target inserts extra wait states for every data
phase. When GNT is taken away, the Am79C974 con-
CLK
1
2
3
4
5
6
7
8
9
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
DATA
DATA
0000
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-19
Figure 15. Preemption When FRAME is Asserted
Am79C974
41
AMD
PRELIMINARY
Master Abort
The PCI configuration registers will not be cleared. For
SCSI, when the master aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at offset 54h), is set. For either Ethernet or SCSI
master abort causes RMABORT (bit 13) of the status
register in the appropriate PCI configuration space to
be set.
The Am79C974 controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted within
4 clocks after FRAME is asserted. Master Abort is
treated as a fatal error by the Am79C974 controller. For
the Ethernet, the Am79C974 controller will reset all CSR
and BCR locations to their H_RESET values. Any
on-going network activity will be stopped immediately.
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A-20
Figure 16. Master Abort
42
Am79C974
PRELIMINARY
AMD
the detection of certain error conditions (MERR, UFLO,
TX BUFF error).
Ethernet Controller
Buffer Management Unit (BMU)
The buffer management unit is a micro-coded state machine which implements the initialization procedure and
manages the descriptors and buffers. The buffer management unit operates at half the speed of the
CLK input.
Initialization
Am79C974 initialization includes the reading of the initialization block in memory to obtain the operating parameters. The initialization block is read when the INIT
bit in CSR0 is set. The INIT bit should be set before or
concurrent with the STRT bit to insure correct operation.
Two DWORDs are read during each period of bus mastership. When SSIZE32 = 1 (BCR20, bit 8), this results
in a total of 4 arbitration cycles (3 arbitration cycles if
SSIZE32 = 0). Once the initialization block has been
completely read in and internal registers have been updated, IDON will be set in CSR0, and an interrupt generated (if IENA is set). At this point, the BMU knows where
the receive and transmit descriptor rings and hence,
normal network operations will begin.
The Am79C974 controller obtains the start address of
the Initialization Block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most significant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The block contains the
user defined conditions for Am79C974 operation, together with the base addresses and length information
of the transmit and receive descriptor rings.
There is an alternative method to initialize the
Am79C974 controller. Instead of initialization via the initialization block in memory, data can be written directly
into the appropriate registers. Either method may be
used at the discretion of the programmer. If the registers
are written to directly, the INIT bit must not be set, or the
initialization block will be read in, thus overwriting the
previously written information. Please refer to Appendix
C for details on this alternative method.
If initialization is done by writing directly to registers, the
Polling Interval register (CSR47) must be initialized in
addition to those registers that can be loaded automatically from the initialization block.
Re-Initialization
The transmitter and receiver sections of the Am79C974
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
states of the transmitter and receiver are monitored by
the host through CSR0 (RXON, TXON bits). The
Am79C974 controller should be reinitialized if the transmitter and/or the receiver were not turned on during the
original initialization, and it was subsequently required
to activate them or if either section was shut off due to
Reinitialization may be done via the initialization block or
by setting the STOP bit in CSR0, followed by writing to
CSR15, and then setting the START bit in CSR0. Note
that this form of restart will not perform the same in the
Am79C974 controller as in the LANCE. In particular,
upon restart, the Am79C974 controller reloads the
transmit and receive descriptor pointers with their respective base addresses. This means that the software
must clear the descriptor own bits and reset its descriptor ring pointers before the restart of the Am79C974
controller. The reload of descriptor base addresses is
performed in the LANCE only after initialization, so a restart of the LANCE without initialization leaves the
LANCE pointing at the same descriptor locations as before the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in memory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4
DWORDs, or 16 bytes, when SSIZE32 = 1. The size of a
message descriptor entry is 4 words, or 8 bytes, when
SSIZE32 = 0.
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the Am79C974 controller reads the user-defined base address for the transmit and receive descriptor rings, as well as the number of entries contained in
the descriptor rings. Descriptor ring base addresses
must be on a 16-byte boundary when SSIZE32=1, and
8-byte boundary when SSIZE=0. A maximum of 128 (or
512, depending upon the value of SSIZE32) ring entries
is allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. However, the
ring lengths can be set beyond this range (up to 65535)
by writing the transmit and receive ring length registers
(CSR76, CSR78) directly.
Each ring entry contains the following information:
1. The address of the actual message data buffer in
user or host memory
2. The length of the message buffer
3. Status information indicating the condition of the
buffer
To permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the
Am79C974 controller or the host. The OWN bit within
the descriptor status information, either TMD or RMD
(see section on TMD or RMD), is used for this purpose.
OWN = “1” signifies that the Am79C974 controller cur-
Am79C974
43
AMD
PRELIMINARY
rently has ownership of this ring descriptor and its
associated buffer. Only the owner is permitted to relinquish ownership or to write to any field in the descriptor
entry. A device that is not the current owner of a descriptor entry cannot assume ownership or change any field
in the entry. A device may, however, read from a descriptor that it does not currently own. Software should
always read descriptor entries in sequential order.
When software finds that the current descriptor is owned
by the Am79C974 controller, then the software must not
read “ahead” to the next descriptor. The software should
wait at the unOWNed descriptor until ownership has
been granted to the software (when LAPPEN = 1
(CSR3, bit 5), then this rule is modified. See the LAPPEN description). Strict adherence to these rules insures that “Deadly Embrace” conditions are avoided.
Descriptor Ring Access Mechanism
base address of both the transmit and receive descriptor
rings into CSRs for use by the Am79C974 controller during subsequent operations.
As the final step in the self-initialization process, the
base address of each ring is loaded into each of the current descriptor address registers and the address of the
next descriptor entry in the transmit and receive rings is
computed and loaded into each of the next descriptor
address registers.
When SSIZE32 = 0, software data structures are 16 bits
wide. The following diagram, Figure 17, illustrates the
relationship between the Initialization Base Address,
the Initialization Block, the Receive and Transmit Descriptor Ring Base Addresses, the Receive and Transmit Descriptors and the Receive and Transmit Data
Buffers, for the case of SSIZE32 = 0.
At initialization, the Am79C974 controller reads the
N
N
24-Bit Base Address
Pointer to
Initialization Block
CSR2
RES
N
N
•
•
•
Rcv Descriptor
Ring
1st desc.
start
CSR1
2nd desc.
start
IADR[15:0]
IADR[23:16]
RMD0
RMD0
RMD1 RMD2
RMD3
Initialization
Block
PADR[31:16]
PADR[47:32]
Data
Buffer
1
Rcv
Buffers
LADRF[15:0]
LADRF[31:16]
M
LADRF[47:32]
LADRF[63:48]
RES
RDRA[23:16]
TDRA[15:0]
TLEN
RES
Data
Buffer
N
M
M
M
•
RX DESCRIPTOR RINGS
RDRA[15:0]
RLEN
Data
Buffer
2
•
•
•
MODE
PADR[15:0]
•
Xmt Descriptor
RX DESCRIPTOR
RINGS
Ring
2nd desc.
start
1st desc.
start
TDRA[23:16]
TMD0
TMD0
TMD1
Data
Buffer
1
TMD2
Data
Buffer
2
TMD3
•
•
•
Xmt
Buffers
Data
Buffer
M
Figure 17. 16-Bit Data Structures: Initialization Block and Descriptor Rings
44
•
Am79C974
18681A-21
AMD
PRELIMINARY
When SSIZE32 = 1, software data structures are 32 bits
wide. The following diagram illustrates, Figure 18, the
relationship between the Initialization Base Address,
the Initialization Block, the Receive and Transmit
Descriptor Ring Base Addresses, the Receive and
Transmit Descriptors and the Receive and Transmit
Data Buffers, for the case of SSIZE32 = 1.
N
N
32-Bit Base Address
Pointer to
Initialization Block
CSR2
CSR1
IADR[31:16]
N
N
•
•
•
Rcv Descriptor
Ring
1st desc.
start
2nd desc.
start
IADR[15:0]
RMD0
RMD0
RMD1 RMD2 RMD3
Initialization
Block
TLEN RES
Rcv
Buffers
Data
Buffer
1
Data
Buffer
2
M
Data
Buffer
N
•
•
•
RLEN RES
MODE
PADR[31:0]
PADR[47:32]
RES
LADRF[31:0]
LADRF[63:32]
RDRA[31:0]
TDRA[31:0]
M
M
M
RX DESCRIPTOR RINGS
•
•
•
Xmt Descriptor
RX DESCRIPTOR
RINGS
Ring
2nd desc.
start
1st desc.
start
TMD0
Data
Buffer
1
Data
Buffer
2
TMD3
•
•
•
Xmt
Buffers
TMD0
TMD1 TMD2
Data
Buffer
M
18681A-22
Figure 18. 32-Bit Data Structures: Initialization Block and Descriptor Rings
Am79C974
45
AMD
PRELIMINARY
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity being performed by the Am79C974 controller, then the
Am79C974 controller will periodically poll the current receive and transmit descriptor entries in order to ascertain their ownership. If the DPOLL bit in CSR4 is set,
then the transmit polling function is disabled.
A typical polling operation consists of the following: The
Am79C974 controller will use the current receive descriptor address stored internally to vector to the appropriate Receive Descriptor Table Entry (RDTE). It will
then use the current transmit descriptor address (stored
internally) to vector to the appropriate Transmit Descriptor Table Entry (TDTE). The accesses will be made in
the following order: RMD1, then RMD0 of the current
RDTE during one bus arbitration, and after that, TMD1,
then TMD0 of the current TDTE during a second bus arbitration. All information collected during polling activity
will be stored internally in the appropriate CSRs. (i.e.
CSR18, CSR19, CSR20, CSR21, CSR40, CSR42,
CSR50, CSR52). UnOWNed descriptor status will be internally ignored.
A typical receive poll is the product of the following
conditions:
1. Am79C974 controller does not possess ownership
of the current RDTE and the poll time has elapsed
and RXON=1 (CSR0, bit 5), or
2. Am79C974 controller does not possess ownership
of the next RDTE the poll time has elapsed and
RXON=1.
If RXON=0 the Am79C974 controller will never poll
RDTE locations.
The ideal system should always have at least one RDTE
available for the possibility of an unpredictable receive
event. (This condition is not a requirement. If this condition is not met, it simply means that frames will be
missed by the system because there was no buffer
space available.) But the typical system usually has at
least one or two RDTEs available for the possibility of an
unpredictable receive event. Given that this condition is
satisfied, the current and next RDTE polls are rarely
seen and hence, the typical poll operation simply consists of a check of the status of the current TDTE. When
there is only one RDTE (because the RLEN was set to
ZERO), then there is no “next RDTE” and ownership of
“next RDTE” cannot be checked. If there is at least one
RDTE, the RDTE poll will rarely be seen and the typical
poll operation simply consists of a check of the
current TDTE.
A typical transmit poll is the product of the following
conditions:
1. Am79C974 controller does not possess ownership
of the current TDTE and
46
DPOLL=0 (CSR4, bit 2) and
TXON=1 (CSR0, bit 4) and
the poll time has elapsed, or
2. Am79C974 controller does not possess ownership
of the current TDTE and
DPOLL=0 and
TXON=1 and
a frame has just been received, or
3. Am79C974 controller does not possess ownership
of the current TDTE and
DPOLL=0 and
TXON=1 and
a frame has just been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll. If the microcode is
not executing the poll counting code when the TDMD bit
is set, then the demanded poll of the TDTE will be delayed until the microcode returns to the poll
counting code.
The user may change the poll time value from the default of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47). Note that if a non–
default value is desired, then a strict sequence of setting
the INIT bit in CSR0, waiting for the IDON bit in CSR0,
then writing to CSR47, and then setting STRT in CSR0
must be observed, otherwise the default value will not
be overwritten. See the CSR47 section for details.
Transmit Descriptor Table Entry (TDTE)
If, after a TDTE access, the Am79C974 controller finds
that the OWN bit of that TDTE is not set, then the
Am79C974 controller resumes the poll time count and
reexamines the same TDTE at the next expiration of the
poll time count.
If the OWN bit of the TDTE is set, but Start of Frame
(STP) bit is not set, the Am79C974 controller will immediately request the bus in order to reset the OWN bit of
this descriptor. (This condition would normally be found
following a LCOL or RETRY error that occurred in the
middle of a transmit frame chain of buffers.) After resetting the OWN bit of this descriptor, the Am79C974 controller will again immediately request the bus in order to
access the next TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP = 1 or
STP = 1 and ENP = 1. It is not acceptable to have 0
length buffer with STP = 0 and ENP =1.
If the OWN bit is set and the start of frame (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO. The
Am79C974
PRELIMINARY
Am79C974 controller will look ahead to the next transmit descriptor after it has performed at least one transmit data transfer from the first buffer. (More than one
transmit data transfer may possibly take place, depending upon the state of the transmitter.) The contents of
TMD0 and TMD1 will be stored in Next Xmt Buffer Address (CSR64 and CSR65), Next Xmt Byte Count
(CSR66) and Next Xmt Status (CSR67) regardless of
the state of the OWN bit. This transmit descriptor
lookahead operation is performed only once.
If the Am79C974 controller does not own the next TDTE
(i.e. the second TDTE for this frame), then it will complete transmission of the current buffer and then update
the status of the current (first) TDTE with the BUFF and
UFLO bits being set. This will cause the transmitter to be
disabled (CSR0, TXON=0). The Am79C974 controller
will have to be re-initialized to restore the transmit function. The situation that matches this description implies
that the system has not been able to stay ahead of the
Am79C974 controller in the transmit descriptor ring and
therefore, the condition is treated as a fatal error. (To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.)
If the Am79C974 controller does own the second TDTE
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit operation), perform a single-cycle DMA transfer to update the
status of the first descriptor (reset the OWN bit in
TMD1), and then it may perform one data DMA access
on the second buffer in the chain before executing another lookahead operation. (i.e. a lookahead to the third
descriptor.)
The Am79C974 controller can queue up to two frames in
the transmit FIFO. Call them frame “X” and frame “Y”,
where “Y” is after “X”. Assume that frame “X” is currently
being transmitted. Because the Am79C974 controller
can perform lookahead data transfer past the ENP of
frame “X”, it is possible for the Am79C974 controller to
completely transfer the data from a buffer belonging to
frame “Y” into the FIFO even though frame “X” has not
yet been completely transmitted. At the end of this “Y”
buffer data transfer, the Am79C974 controller will write
intermediate status (change the OWN bit to a ZERO) for
the “Y” frame buffer, if frame “Y” uses data chaining.
The last TDTE for the “X” frame (containing ENP) has
not yet been written, since the “X” frame has not yet
been completely transmitted. Note that the Am79C974
controller has, in this instance, returned ownership of a
TDTE to the host out of a “normal” sequence.
AMD
For this reason, it becomes imperative that the host system should never read the Transmit DTE ownership bits
out of order. Software should always process buffers in
sequence, waiting for the ownership before proceeding.
There should be no problems for software which processes buffers in sequence, waiting for ownership before
proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; In
such a case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1 update,
the Am79C974 controller will go to the next transmit
frame, if any, skipping over the rest of the frame which
experienced an error, including chained buffers. This is
done by returning to the polling microcode where
Am79C974 controller will immediately access the next
descriptor and find the condition OWN=1 and STP=0 as
described earlier. As described for that case, the
Am79C974 controller will reset the own bit for this descriptor and continue in like manner until a descriptor
with OWN=0 (no more transmit frames in the ring) or
OWN=1 and STP=1 (the first buffer of a new frame)
is reached.
At the end of any transmit operation, whether successful
or with errors, immediately following the completion of
the descriptor updates, the Am79C974 controller will always perform another poll operation. As described earlier, this poll operation will begin with a check of the
current RDTE, unless the Am79C974 controller already
owns that descriptor. Then the Am79C974 controller will
proceed to polling the next TDTE. If the transmit descriptor OWN bit has a ZERO value, then the Am79C974
controller will resume poll time count incrementing. If the
transmit descriptor OWN bit has a value of ONE, then
the Am79C974 controller will begin filling the FIFO with
transmit data and initiate a transmission. This end–of–
operation poll coupled with the TDTE lookahead operation allows the Am79C974 controller to avoid inserting
poll time counts between successive transmit frames.
Whenever the Am79C974 controller completes a transmit frame (either with or without error) and writes the
status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the IENA
bit of CSR0 has been set and the TINTM bit of CSR3
is reset.
Am79C974
47
AMD
PRELIMINARY
Receive Descriptor Table Entry (RDTE)
If the Am79C974 controller does not own both the current and the next Receive Descriptor Table Entry then
the Am79C974 controller will continue to poll according
to the polling sequence described above. If the receive
descriptor ring length is 1, then there is no next descriptor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the Am79C974 controller then additional poll accesses are not necessary. Future poll operations will not include RDTE accesses as long as the
Am79C974 controller retains ownership of the current
and the next RDTE.
When receive activity is present on the channel, the
Am79C974 controller waits for the complete address of
the message to arrive. It then decides whether to accept
or reject the frame based on all active addressing
schemes. If the frame is accepted the Am79C974 controller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the current buffer.
If ownership is lacking, then the Am79C974 controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the Am79C974
controller has no buffer in which to store the incoming
message. The Missed Frame Count register (CSR112)
will be incremented and the MISS bit will be set in CSR0
and an interrupt will be generated if IENA=1 (CSR0) and
MISSM=0 (CSR3). Another poll of the current RDTE will
not occur until the frame has finished.
If the Am79C974 controller sees that the last poll (either
a normal poll, or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid ownership, then it proceeds to a poll of the next RDTE. Following this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descriptor, the Am79C974 controller will continue to perform receive data DMA transfers to the first buffer. If the frame
length exceeds the length of the first buffer, and the
Am79C974 controller does not own the second buffer,
ownership of the current descriptor will be passed back
to the system by writing a ZERO to the OWN bit of
RMD1 and status will be written indicating buffer
(BUFF=1) and possibly overflow (OFLO=1) errors.
If the frame length exceeds the length of the first (current) buffer, and the Am79C974 controller does own the
second (next) buffer, ownership will be passed back to
the system by writing a ZERO to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the Am79C974 controller proceeds to look ahead to the ownership of the third
buffer. Such action will depend upon the state of the
FIFO when the status has been updated on the first de48
scriptor. In any case, lookahead will be performed to the
third buffer and the information gathered will be stored in
the chip, regardless of the state of the ownership bit. As
in the transmit flow, lookahead operations are performed only once.
This activity continues until the Am79C974 controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The Am79C974 controller will subsequently update the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) of the complete frame into RMD2 and overwrite
the “current” entries in the CSRs with the “next” entries.
Media Access Control
The Media Access Control engine incorporates the essential protocol requirements for operation of a compliant Ethernet/802.3 node, and provides the interface
between the FIFO sub-system and the Manchester Encoder/Decoder (MENDEC).
The MAC engine is fully compliant to Section 4 of ISO/
IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition)
and ANSI/IEEE 802.3 (1985).
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post- message processing.
These include the ability to disable retries after a collision, dynamic FCS generation on a frame-by-frame basis, and automatic pad field insertion and deletion to
enforce minimum frame size attributes, automatic
retransmission without reloading the FIFO, automatic
deletion of collision fragments, and reduces bus
bandwidth use.
The two primary attributes of the MAC engine are:
Transmit and receive message data encapsulation.
— Framing (frame boundary delimitation, frame
synchronization).
— Addressing (source and destination address
handling).
— Error detection (physical medium transmission
errors).
Media access management.
— Medium allocation (collision avoidance).
— Contention resolution (collision handling).
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforcement for transmit and receive frames. When
APAD_XMT = 1 (CSR, bit 11), transmit messages will
be padded with sufficient bytes (containing 00h) to ensure that the receiving station will observe an information field (destination address, source address,
length/type, data and FCS) of 64-bytes. When
Am79C974
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ASTRP_RCV = 1 (CSR4, bit 10), the receiver will
automatically strip pad bytes from the received message by observing the value in the length field, and stripping excess bytes if this value is below the minimum
data size (46 bytes). Both features can be independently over-ridden to allow illegally short (less than 64
bytes of frame data) messages to be transmitted and/or
received. The use of this feature reduces bus utilization
because the pad bytes are not transferred into or out of
main memory.
Framing (Frame Boundary Delimitation, Frame
Synchronization)
The MAC engine will autonomously handle the construction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the channel
is currently permitted, the MAC engine will commence
the 7 byte preamble sequence (10101010b, where first
bit transmitted is a 1). The MAC engine will subsequently append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
Transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the frame. The data portion of the frame consists of destination address, source address, length/type, and
frame data.
Addressing (Source and Destination Address
Handling)
The first 6-bytes of information after SFD will be interpreted as the destination address field. The MAC engine
provides facilities for physical, logical (multicast) and
broadcast address reception.
Error Detection (Physical Medium Transmission
Errors)
The MAC engine provides several facilities which report
and recover from errors on the medium. In addition, the
network is protected from gross errors due to inability of
the host to keep pace with the MAC engine activity.
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
The exact number of transmission retry attempts
(ONE, MORE, RTRY or TRC).
Whether the MAC engine had to Defer (DEF) due
to channel activity.
Excessive deferral (EXDEF), indicating that the
transmitter has experienced Excessive Deferral on
this transmit frame, where Excessive Deferral is
defined in ISO 8802-3 (IEEE/ANSI 802.3).
Loss of Carrier (LCAR), indicating that there was
an interruption in the ability of the MAC engine to
monitor its own transmission. Repeated
LCAR errors indicate a potentially faulty transceiver or network connection.
The user is responsible for the correct ordering and content in each of the fields in the frame.
The receive section of the MAC engine will detect an incoming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8-bits of information before searching for the SFD sequence. Once the SFD is detected, all
subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the Receive FIFO to the host. If pad stripping is performed, the
MAC engine will also strip the received FCS bytes, although the normal FCS computation and checking will
occur. Note that apart from pad stripping, the frame will
be passed unmodified to the host. If the length field has
a value of 46 or greater, the MAC engine will not attempt
to validate the length against the number of bytes contained in the message.
If the frame terminates or suffers a collision before
64-bytes of information (after SFD) have been received,
the MAC engine will automatically delete the frame from
the Receive FIFO, without host intervention. The
Am79C974 controller has the ability to accept runt packets for diagnostics purposes and proprietary networks.
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Late Collision (LCOL) indicates that the transmission suffered a collision after the slot time. This is
indicative of a badly configured network. Late collisions should not occur in a normal operating network.
Collision Error (CERR) indicates that the transceiver did not respond with an SQE Test message
within the predetermined time after a transmission
completed. This may be due to a failed transceiver,
disconnected or faulty transceiver drop cable, or
the fact the transceiver does not support this feature (or it is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keep the Transmit FIFO filled sufficiently, causing an underflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
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The status of each receive message is available in the
appropriate RMD and CSR areas. FCS and Framing errors (FRAM) are reported, although the received frame
is still passed to the host. The FRAM error will only be
reported if an FCS error is detected and there are a non
integral number of bytes in the message. The MAC engine will ignore up to 7 additional bits at the end of a message (dribbling bits), which can occur under normal
network operating conditions. The reception of 8 additional bits will cause the MAC engine to de-serialize the
entire byte, and will result in the received message and
FCS being modified.
The Am79C974 controller can handle up to 7 dribbling
bits when a received frame terminates. During the reception, the FCS is generated on every serial bit (including the dribbling bits) coming from the cable, although
the internally saved FCS value is only updated on the
eighth bit (on each byte boundary). The framing error is
reported to the user as follows:
The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier is
detected, the media is considered busy, and the MAC
should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard also allows optional two part deferral after a receive message.
See ANSI/IEEE Std 802.3 –1990 Edition, 4.2.3.2.1:
Note: It is possible for the PLS carrier sense indication
to fail to be asserted during a collision on the media. If
the deference process simply times the interFrame gap
based on this indication it is possible for a short interFrame gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system
robustness the following optional measures, as specified in 4.2.8, are recommended when InterFrameSpacingPart1 is other than ZERO:
If the number of dribbling bits are 1 to 7 and there
is no CRC (FCS) error, then there is no Framing
error (FRAM = 0).
1. Upon completing a transmission, start timing the
interpacket gap, as soon as transmitting and carrier Sense are both false.
If the number of dribbling bits are 1 to 7 and there
is a CRC (FCS) error, then there is also a Framing
error (FRAM = 1).
2. When timing an interFrame gap following reception, reset the interFrame gap timing if carrier
Sense becomes true during the first 2/3 of the interFrame gap timing interval. During the final 1/3 of
the interval the timer shall not be reset to ensure
fair access to the medium. An initial period shorter
than 2/3 of the interval is permissible including
ZERO.
If the number of dribbling bits = 0, then there is no
Framing error. There may or may not be a CRC
(FCS) error.
Counters are provided to report the Receive Collision
Count and Runt Packet Count for network statistics and
utilization calculations.
Note that if the MAC engine detects a received frame
which has a 00b pattern in the preamble (after the first 8
bits which are ignored), the entire frame will be ignored.
The MAC engine will wait for the network to go inactive
before attempting to receive additional frames.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The
802.3/Ethernet protocols define a media access mechanism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter Packet Gap internal) after the last activity, before transmitting
on the media. The channel is a multidrop communications media (with various topological configurations permitted) which allows a single station to transmit and all
other stations to receive. If two nodes simultaneously
contend for the channel, their signals will interact causing loss of data, defined as a collision. It is the responsibility of the MAC to attempt to avoid and recover from a
collision, to guarantee data integrity for the end-to-end
transmission to the receiving station.
50
Medium Allocation
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-spacing time of 6.0 µs. The second part of the inter-framespacing interval is therefore 3.6 µs.
The Am79C974 controller will perform the two part deferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6 µs InterFrameSpacing after the receive
carrier is de-asserted. During the first part deferral (InterFrameSpacingPart1 – IFS1) the Am79C974 controller will defer any pending transmit frame and respond to
the receive message. The IPG counter will be reset to
ZERO continuously until the carrier de-asserts, at which
point the IPG counter will resume the 9.6 µs count once
again. Once the IFS1 period of 6.0 µs has elapsed, the
Am79C974 controller will begin timing the second part
deferral (InterFrame Spacing Part 2 – IFS2) of 3.6 µs.
Once IFS1 has completed, and IFS2 has commenced,
the Am79C974 controller will not defer to a receive
frame if a transmit frame is pending. This means that the
Am79C974 controller will not attempt to receive the receive frame, since it will start to transmit, and generate a
collision at 9.6 µs. The Am79C974 controller will guarantee to complete the preamble (64-bit) and jam (32-bit)
Am79C974
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sequence before ceasing transmission and invoking the
random backoff algorithm.
This transmit two part deferral algorithm is implemented
as an option which can be disabled using the DXMT2PD
bit in CSR3. Two part deferral after transmission is useful for ensuring that severe IPG shrinkage cannot occur
in specific circumstances, causing a transmit message
to follow a receive message so closely as to make them
indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should generate the SQE Test message (a nominal 10 MHz burst of
5 –15 Bit Times duration) on the CI± pair (within 0.6 µs –
1.6 µs after the transmission ceases). During the time
period in which the SQE Test message is expected the
Am79C974 controller will not respond to receive carrier
sense.
See ANSI/IEEE Std 802.3—1990 Edition, 7.2.4.6 (1):
“At the conclusion of the output function, the DTE opens
a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when the
CARRIER_STATUS becomes CARRIER_OFF. If execution of the output function does not cause CARRIER_ON to occur, no SQE test occurs in the DTE. The
duration of the window shall be at least 4.0 µs but no
more than 8.0 µs. During the time window the Carrier
Sense Function is inhibited.”
The Am79C974 controller implements a carrier sense
“blinding” period within 0 µs – 4.0 µs from de-assertion
of carrier sense after transmission. This effectively
means that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6 µs
after a transmission. However, since IPG shrinkage below 4 µs will rarely be encountered on a correctly configured networks, and since the fragment size will be larger
than the 4 µs blinding window, then the IPG counter will
be reset by a worst case IPG shrinkage/fragment scenario and the Am79C974 controller will defer its transmission. In addition, the Am79C974 controller will not
restart the “blinding” period if carrier is detected within
the 4.0 µs – 6.0 µs IFS1 period, but will commence timing of the entire IFS1 period.
Contention Resolution (Collision Handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/Decoder (MENDEC). If a collision is detected before the
complete preamble/SFD sequence has been transmitted, the MAC Engine will complete the preamble/SFD
before appending the jam sequence. If a collision is detected after the preamble/SFD has been completed, but
prior to 512 bits being transmitted, the MAC Engine will
abort the transmission, and append the jam sequence
immediately. The jam sequence is a 32-bit all Zeros pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of collision will cause the transmission to be re-scheduled, dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit will
be set in the Transmit Frame Status. If more than one
retry was required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit will be set
(ONE and MORE will be clear), and the transmit message will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in CSR15, the MAC Engine will abandon transmission of the frame on detection
of the first collision. In this case, only the RTRY bit will be
set and the transmit message will be flushed from
the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the jam
sequence and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the transmit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a “truncated binary exponential backoff” algorithm which provides a controlled pseudo random
mechanism to enforce the collision backoff interval, before re-transmission is attempted.
See ANSI/IEEE Std 802.3—1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple of
slot Time. The number of slot times to delay before the
nth re-transmission attempt is chosen as a uniformly
distributed random integer r in the range:
0 £ r <2k
where
k = min (n,10).”
The Am79C974 controller provides an alternative algorithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes are
present, and numerous nodes can be in collision. It effectively accelerates the increase in the backoff time in
busy networks, and allows nodes not involved in the collision to access the channel whilst the colliding nodes
await a reduction in channel activity. Once channel activity is reduced, the nodes resolving the collision time
out their slot time counters as normal.
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Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) station. The MENDEC provides the encoding function for
data to be transmitted on the network using the high accuracy on-board oscillator, driven by either the crystal
oscillator or an external CMOS level compatible clock.
The MENDEC also provides the decoding function from
data received from the network. The MENDEC contains
a Power On Reset (POR) circuit, which ensures that all
analog portions of the Am79C974 controller are forced
into their correct state during power up, and prevents erroneous data transmission and/or reception during
this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the following
crystal specification may be used to ensure less than
±0.5 ns jitter at DO±. See Table 1 below.
Table 1. Crystal Specification
Parameter
Min
1. Parallel Resonant Frequency
Nom
Max
20
Unit
MHz
2. Resonant Frequency Error
–50
+50
PPM
3. Change in Resonant Frequency
With Respect to Temperature (0 – 70 C)
–40
+40
PPM
4. Crystal Load Capacitance
20
50
pF
5. Motional Crystal Capacitance (C1)
0.022
6. Series Resistance
pF
35
7. Shunt Capacitance
8. Drive Level
Ω
7
pF
TBD
mW
External Clock Drive Characteristics
When driving the oscillator from a CMOS level external
clock source, XTAL2 must be left floating (unconnected). An external clock having the following characteristics must be used to ensure less than ±0.5 ns jitter at
DO±. See Table 2.
Table 2. Clock Drive Characteristics
Clock Frequency:
20 MHz ±0.01%
Rise/Fall Time (tR/tF):
<= 6 ns from 0.5 V to VDD –0.5 V
XTAL1 HIGH/LOW Time (tHIGH/tLOW):
20 ns min
XTAL1 Falling Edge to Falling Edge Jitter:
< ±0.2 ns at 2.5 V input (VDD/2)
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO±) are designed to operate into terminated transmission lines.
When operating into a 78 Ω terminated transmission
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet and
IEEE-802.3.
Transmitter Timing and Operation
the basic timing reference for the MENDEC portion of
the Am79C974 controller. The crystal is divided by two,
to create the internal transmit clock reference. Both
clocks are fed into the MENDECs Manchester Encoder
to generate the transitions in the encoded data stream.
The internal transmit clock is used by the MENDEC to
internally synchronize the Internal Transmit Data
(ITXDAT) from the controller and Internal Transmit Enable (ITXEN). The internal transmit clock is also used as
a stable bit rate clock by the receive section of the MENDEC and controller.
A 20 MHz fundamental mode crystal oscillator provides
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The oscillator requires an external 0.01% timing reference. The accuracy requirements, if an external crystal
is used are tighter because allowance for the on-board
parasitics must be made to deliver a final accuracy of
0.01%.
Receiver Path
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO±. When the internal request is dropped by the controller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
The Receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is a
ZERO threshold, wide bandwidth line receiver. The carrier path is an offset threshold bandpass detecting line
receiver. Both receivers share common bias networks
to allow operation over a wide input common
mode range.
TSEL LOW:
The principal functions of the Receiver are to signal the
Am79C974 controller that there is information on the receive pair, and separate the incoming Manchester encoded data stream into clock and NRZ data.
The idle state of DO± yields “ZERO”
differential to operate transformercoupled loads.
TSEL HIGH: In this idle state, DO+ is positive with
respect to DO– (logical HIGH).
DI±
Data
Receiver
Manchester
Decoder
Noise
Reject
Filter
Carrier
Detect
Circuit
IRXDAT*
ISRDCLK*
IRXCRS*
*Internal signal
18681A-23
Figure 19. Receiver Block Diagram
Input Signal Conditioning
Clock Acquisition
Transient noise pulses at the input data stream are rejected by the Noise Rejection Filter. Pulse width rejection is proportional to transmit data rate, (which is fixed
at 10 MHz for Ethernet but could be different for proprietary networks). DC inputs more negative than minus
100 mV are also surpressed.
When there is no activity at DI± (receiver is idle), the receive oscillator is phase locked to internal transmit
clock. The first negative clock transition (bit cell center of
first valid Manchester “0”) after IRXCRS is asserted interrupts the receive oscillator. The oscillator is then restarted at the second Manchester “0” (bit time 4) and is
phase locked to it. As a result, the MENDEC acquires
the clock from the incoming Manchester bit pattern in
4 bit times with a 1010b Manchester bit pattern.
The Carrier Detection circuitry detects the presence of
an incoming data frame by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acquisition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI±, the internal enable signal from the MENDEC
to controller (IRXCRS) is asserted and a clock acquisition cycle is initiated.
The internal serial receive data clock, ISRDCLK and the
internal received data, IRXDAT, are enabled 1/4 bit time
after clock acquisition in bit cell 5. IRXDAT is at a HIGH
state when the receiver is idle (no ISRDCLK). IRXDAT
however, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
ISRDCLK is enabled. At 1/4 bit time through bit cell 5,
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the controller portion of the Am79C974 controller sees
the first ISRDCLK transition. This also strobes in the incoming fifth bit to the MENDEC as Manchester “1”.
IRXDAT may make a transition after the ISRDCLK rising
edge in bit cell 5, but its state is still undefined. The
Manchester “1” at bit 5 is clocked to IRXDAT output at
1/4 bit time in bit cell 6.
PLL Tracking
After clock acquisition, the phase-locked clock is compared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a correction circuit. This circuit ensures that the phaselocked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage Controlled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
Hence, input data jitter is reduced in ISRDCLK by
10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI± inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transition on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS de-assert allows the last bit
to be strobed by ISRDCLK and transferred to the controller section, but prevents any extra bit(s) at the end
of message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI± inputs. Input error is
less than ±35 mV to minimize sensitivity to input rise and
fall time. ISRDCLK strobes the data receiver output at
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
ISRDCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI±)
should be externally terminated by two 40.2 Ω ±1% resistors and one optional common-mode bypass capacitor, as shown in the Differential Input Termination
diagram below. The differential input impedance, ZIDF,
and the common-mode input impedance, ZICM, are
specified so that the Ethernet specification for cable termination impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39 Ω is the nearest
usable value. The CI± differential inputs are terminated
in exactly the same way as the DI± pair.
AUI Isolation
Transformer
DI+
Am79C974
DI-
40.2 Ω
40.2 Ω
0.01 µF
to
0.1 µF
18681A-24
Figure 20. Differential Input Termination
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Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI± inputs. This
collision signal passes through an input stage which detects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the internal collision
signal HIGH. The condition continues for approximately
1.5 bit times after the last LOW-to-HIGH transition on
CI±.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Since data is strobed at 1/4 bit time, Manchester transitions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of Jitter Handling is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which effectively connects the DTE to a MAU. The differential interface provided by the Am79C974 controller is fully
compliant to Section 7 of ISO 8802-3 (ANSI/IEEE
802.3).
After the Am79C974 controller initiates a transmission it
will expect to see data “looped-back” on the DI± pair
(when the AUI port is selected). This will internally generate a “carrier sense”, indicating that the integrity of the
data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted at least 6 bit times before the last
transmitted bit on DO± (when using the AUI port). If “carrier sense” does not become active in response to the
data transmission, or becomes inactive before the end
of transmission, the loss of carrier (LCAR) error bit will
be set in the Transmit Descriptor Ring (TMD2, bit 27) after the frame has been transmitted.
Twisted-Pair Transceiver (T-MAU)
The T-MAU implements the Medium Attachment Unit
(MAU) functions for the Twisted-Pair Medium, as specified by the supplement to ISO 8802-3 (IEEE/ANSI
802.3) standard (Type 10BASE-T). The T-MAU provides twisted pair driver and receiver circuits, including
on-board transmit digital predistortion and receiver
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squelch and a number of additional features including
Link Status indication, Automatic Twisted-Pair Receive
Polarity Detection/Correction and Indication, Receive
Carrier Sense, Transmit Active and Collision Present
indication.
Twisted-Pair Transmit Function
The differential driver circuitry in the TXD± and TXP±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted-Pair cable, as specified
by the 10BASE-T supplement to the ISO 8802-3 (IEEE/
ANSI 802.3) Standard. The transmit function for data
output meets the propagation delays and jitter specified
by the standard.
Twisted-Pair Receive Function
The receiver complies with the receiver specifications of
the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Standard, including noise immunity and received signal rejection criteria (‘Smart Squelch’). Signals meeting these
criteria appearing at the RXD± differential input pair are
routed to the MENDEC. The receiver function meets the
propagation delays and jitter requirements specified by
the standard. The receiver squelch level drops to half its
threshold value after unsquelch to allow reception of
minimum amplitude signals and to offset carrier fade in
the event of worst case signal attenuation and crosstalk
noise conditions.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Interface (MDI). Filter and transformer loss are not specified.
The T-MAU receiver squelch levels are defined to account for a 1 dB insertion loss at 10 MHz, which is typical
for the type of receive filters/transformers employed.
Normal 10BASE-T compatible receive thresholds are
employed when the LRT bit (CSR15[9]) is LOW. When
the LRT bit is set (HIGH), the Low Receive Threshold
option is invoked, and the sensitivity of the T-MAU receiver is increased. This allows longer line lengths to be
employed, exceeding the 100 m target distance of normal 10BASE-T (assuming typical 24 AWG cable). The
increased receiver sensitivity compensates for the increased signal attenuation caused by the additional
cable distance.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, primarily caused by coupling from co-resident services
(crosstalk). For this reason, it is recommended that
when using the Low Receive Threshold option that the
service should be installed on 4-pair cable only. Multipair cables within the same outer sheath have lower
crosstalk attenuation, and may allow noise emitted from
adjacent pairs to couple into the receive pair, and be of
sufficient amplitude to falsely unsquelch the T-MAU.
Am79C974
55
AMD
PRELIMINARY
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair
inactivity, ’Link beat pulses’ will be periodically sent over
the twisted pair medium to constantly monitor medium integrity.
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD± pair will cause the TMAU to go
into a link fail state. In the link fail state, data transmission, data reception, data loopback and the collision detection functions are disabled, and remain disabled until
valid data or >5 consecutive link pulses appear on the
RXD± pair. During link fail, the Link Status (LNKST pin)
signal is inactive. When the link is identified as functional, the Link Status signal is asserted. The LNKST
pin displays the Link Status signal by default.
Transmission attempts during Link Fail state will produce no network activity and will produce LCAR and
CERR error indications.
In order to inter-operate with systems which do not implement Link Test, this function can be disabled by setting the DLNKTST bit in CSR15. With link test disabled,
the data driver, receiver and loopback functions as well
as collision detection remain enabled irrespective of the
presence or absence of data or link pulses on the RXD±
pair. Link Test pulses continue to be sent regardless of
the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to invert
the polarity of the signals appearing at the RXD± pair if
the polarity of the received signal is reversed (such as in
the case of a wiring error). This feature allows data
frames received from a reverse wired RXD± input pair to
be corrected in the T-MAU prior to transfer to the MENDEC. The polarity detection function is activated following H_RESET or Link Fail, and will reverse the receive
polarity based on both the polarity of any previous link
beat pulses and the polarity of subsequent frames with a
valid End Transmit Delimiter (ETD).
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state is made due to the reception
of 5 – 6 consecutive link beat pulses of identical polarity.
On entry to the Link Pass state, the polarity of the last 5
link beat pulses is used to determine the initial receive
polarity configuration and the receiver is reconfigured to
subsequently recognize only link beat pulses of the previously recognized polarity.
Positive link beat pulses are defined as received signal
with a positive amplitude greater than 585 mV (LRT =
HIGH) with a pulse width of 60 ns – 200 ns. This positive
excursion may be followed by a negative excursion.
This definition is consistent with the expected received
56
signal at a correctly wired receiver, when a link beat
pulse which fits the template of Figure 14-12 of the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
Negative link beat pulses are defined as received signals with a negative amplitude greater than 585 mV with
a pulse width of 60 ns – 200 ns. This negative excursion
may be followed by a positive excursion. This definition
is consistent with the expected received signal at a reverse wired receiver, when a link beat pulse which fits
the template of Figure 14-12 in the 10BASE-T Standard
is generated at a transmitter and passed through 100 m
of twisted pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive frames with valid ETD of
identical polarity are detected. When “armed”, the receiver is capable of changing the initial or previous polarity configuration based on the ETD polarity.
On receipt of the first frame with valid ETD following
H_RESET or link fail, the T-MAU will utilize the inferred
polarity information to configure its RXD± input, regardless of its previous state. On receipt of a second frame
with a valid ETD with correct polarity, the detection/correction algorithm will “lock-in” the received polarity. If the
second (or subsequent) frame is not detected as confirming the previous polarity decision, the most recently
detected ETD polarity will be used as the default. Note
that frames with invalid ETD have no effect on updating
the previous polarity decision. Once two consecutive
frames with valid ETD have been received, the T-MAU
will disable the detection/correction algorithm until
either a Link Fail condition occurs or H_RESET
is activated.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when enabled by the LED control bits in the Bus Configuration
Registers (BCR4–BCR7).
Twisted-Pair Interface Status
Three internal signals (XMT, RCV and COL) indicate
whether the T-MAU is transmitting, receiving, or in a collision state with both functions active simultaneously.
These signals are internal signals and the behavior of
the LED outputs depends on how the LED output circuitry is programmed.
The T-MAU will power up in the Link Fail state and normal algorithm will apply to allow it to enter the Link Pass
state. In the Link Pass state, transmit or receive activity
will be indicated by assertion of RCV signal going active.
If T-MAU is selected using the PORTSEL bits in CSR15,
then when moving from AUI to T-MAU selection the
T-MAU will be forced into the LINK Fail state.
In the Link Fail state, XMT, RCV and COL are inactive.
Am79C974
AMD
PRELIMINARY
Collision Detect Function
Activity on both twisted pair signals RXD± and TXD±
constitutes a collision, thereby causing the COL signal
to be activated. (COL is used by the LED control circuits)
COL will remain active until one of the two colliding signals changes from active to idle. However, transmission
attempt in Link Fail state results in LCAR and CERR indication. COL stays active for 2 bit times at the end of
a collision.
Signal Quality Error (SQE) Test (Heartbeat)
Function
The SQE function is disabled when the 10BASE-T port
is selected.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the T-MAU TXD± is active for an excessive
period (20 ms – 150 ms). This prevents any one node
from disrupting the network due to a ‘stuck-on’ or faulty
transmitter. If this maximum transmit time is exceeded,
the T-MAU transmitter circuitry is disabled, the JAB bit is
set (CSR4, bit 1) the COL signal is asserted. Once the
transmit data stream to the T-MAU is removed, an “unjab” time of 250 ms – 750 ms will elapse before the
T-MAU COL and re-enables the transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into power savings mode. This feature is useful in battery powered or
low duty cycle systems. The T-MAU will go into power
down mode when H_RESET is active, coma mode is active, or the T-MAU is not selected. Refer to the Power
Savings Modes section for descriptions of the various
power down modes.
Any of the three conditions listed above resets the internal logic of the T-MAU and places the device into power
down mode. In this mode, the Twisted-Pair driver pins
(TXD±, TXP±) are driven LOW, and the internal T-MAU
status signals (LNKST, RCVPOL, XMT, RCV and COL)
signals are inactive.
Once H_RESET ends, coma mode is disabled, and the
T-MAU is selected. The T-MAU will remain in the reset
state for up to 10 µs. Immediately after the reset condition is removed, the T-MAU will be forced into the Link
Fail state. The T-MAU will move to the Link Pass state
only after 5 – 6 link beat pulses and/or a single received
message is detected on the RD± pair.
In snooze mode, the T-MAU receive circuitry will remain
enabled even while the SLEEP pin is driven LOW.
The T-MAU circuitry will always go into power down
mode if H_RESET is asserted, coma mode is enabled,
or the T-MAU is not selected.
10BASE-T Interface Connection
Figure 21 shows the proper 10BASE-T network interface design. Refer to the Technical Manual (PID
#18738A) for more design details, and refer to
Appendix B for a list of compatible 10BASE-T filter/
transformer modules.
Note that the recommended resistor values and filter
and transformer modules are the same as those used by
the IMR (Am79C980) and the IMR+ (Am79C981).
Filter &
Transformer
Module
61.9 Ω
TXD+
TXP+
TXD-
Am79C974
TXP-
1.21 KΩ
422 Ω
RJ45
Connector
1:1
XMT
Filter
61.9 Ω
422 Ω
TD+
1
TD-
2
RD+
3
RD-
6
1:1
RXD+
RCV
Filter
RXD100 Ω
18681A-25
Figure 21. 10BASE-T Interface Connection
Am79C974
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AMD
PRELIMINARY
Ethernet Power Savings Modes
The Am79C974’s Ethernet controller supports two hardware power savings modes. Both are entered by driving
the SLEEP pin LOW.
The PCI interface section is not effected by SLEEP. In
particular, access to the PCI configuration space remains possible. None of the configuration registers will
be reset by SLEEP. All I/O accesses to the Am79C974’s
Ethernet controller will result in a PCI target abort
response.
The first power saving mode is called coma mode. In
coma mode, the Am79C974 controller has no means to
use the network to automatically wake itself up. Coma
mode is enabled when the AWAKE bit in BCR2 is reset.
Coma mode is the default power down mode.
The second power saving mode is called snooze mode.
In snooze mode, enabled by setting the AWAKE bit in
BCR2 and driving the SLEEP pin LOW, the T-MAU receive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LNKST output is the only
one of the LED pins that continues to function. The
LNKSTE bit must be set in BCR4 to enable indication of
a good 10BASE-T link if there are link beat pulses or
valid frames present. This LNKST pin can be used to
drive an LED and/or external hardware that directly controls the SLEEP pin of the Am79C974 controller. This
configuration effectively wakes the system when there
is any activity on the 10BASE-T link. Snooze mode can
be used only if the T-MAU is the selected network port.
58
Link beat pulses are not transmitted during snooze
mode.
If the REQ output is active when the SLEEP pin is asserted, then the Am79C974 controller will wait until the
GNT input is asserted. Next, the Am79C974 controller
will deassert the REQ pin and finally, it will internally enter either the coma or snooze sleep mode.
Before the sleep mode is invoked, the Am79C974 controller will perform an internal S_RESET. This
S_RESET operation will not affect the values of the BCR
registers or the PCI configuration space.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the assertion of SLEEP until three CLK cycles after the completion of a valid pin RST operation.
Software Access
Ethernet PCI Configuration Registers
The Am79C974 controller supports the 64-byte header
portion of the configuration space as predefined by the
PCI specification revision 2.0. None of the device specific registers in locations 64 – 255 are used by the
Ethernet controller. The layout of the configuration registers in the header region is shown in the table below.
All registers required to identify the Am79C974 controller and its function are implemented. Additional registers are used to setup the configuration of the
Am79C974 controller in a system.
Am79C974
AMD
PRELIMINARY
31
24 23
16 15
8
Device ID
Status
Reserved
Header Type
Don’t Care
0 0
Latency Timer
Reserved
0Ch
14h
Reserved
18h
Reserved
1Ch
Reserved
20h
Reserved
24h
Reserved
28h
Reserved
2Ch
Reserved
30h
Reserved
34h
Reserved
38h
Interrupt Pin
2 1 0
DWORD Index
08h
10h
When the Am79C974 controller samples its IDSELA or
IDSELB input asserted during a configuration cycle, it
will acknowledge the cycle by asserting its DEVSEL output. The content of AD[31:00] during the address phase
of the configuration cycles must meet the format as
shown below:
Don’t
Care
Revision ID
Reserved
The configuration registers are accessible only by PCI
configuration cycles. They can be accessed right after
the Am79C974 controller is powered-on, even if the
read operation of the serial EEPROM is still on-going.
All multi-byte numeric fields follow little endian byte ordering. The Command register is the only register
cleared by H_RESET. S_RESET as well as asserting
SLEEP have no effect on the value of the PCI configuration registers. All write accesses to Reserved locations
have no effect, reads from these locations will return a
data value of ZERO.
8 7 6 5
04h
Programming IF
Base Address
Reserved
11 10
Offset
00h
Command
Sub-Class
31
0
Vendor ID
Base-Class
Reserved
7
0 0
AD[1:0] must both be ZEROs, since the Am79C974
controller is not a bridge device. It only recognizes configuration cycles of Type 0 (as defined by the PCI specification revision 2.0). AD[7:2] specify the selected
DWORD in the configuration space. AD[7:6] must both
be ZERO, since the Am79C974’s Ethernet controller
does not implement any of the device specific registers
in locations 64 – 255. Since AD[1:0] and AD[7:6] must all
be ZERO, the lower 8 bits of the address for a configuration cycle are equal to the offset of the DWORD counting
from the beginning of the PCI configuration space.
AD[10:8] specify one of eight possible functions of a PCI
Interrupt Line
3Ch
device. The Am79C974 controller functions as two single function devices, as indicated in the Header Type
registers of both PCI configuration spaces (bit 7,
FUNCT = 0). Therefore, the Am79C974 controller ignores AD[10:8] during the address phase of a configuration cycle. AD[31:11] are typically used to generate the
IDSELA or IDSELB signals. The Am79C974 controller
ignores all upper address bits.
PCI configuration registers can be accessed with 8-bit,
16-bit or 32-bit transfers. The active bytes within a
DWORD are determined by the byte enable signals.
E.G. a read of the Sub-Class register can be performed
by reading from offset 08h with only BE2 being active.
I/O Resources
The Am79C974 controller uses two separate blocks of
I/O space, one for the SCSI controller and one for the
Ethernet controller. This section discusses the I/O address block used by the Ethernet controller.
PCnet-SCSI’s Ethernet Controller I/O Resource
Mapping
The Am79C974’s Ethernet controller has several I/O resources. These resources use 32 bytes of I/O space
that begin at the Am79C974’s Ethernet controller I/O
base address.
The Ethernet controller allows two modes of slave access. Word I/O mode treats all Ethernet controller I/O
Resources as two-byte entities spaced at two-byte address intervals. Double Word I/O mode treats all Ethernet controller I/O Resources as four-byte entities
spaced at four-byte address intervals. The selection of
WIO or DWIO mode is accomplished in any of
several ways:
Am79C974
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AMD
PRELIMINARY
H_RESET function.
EEPROM programming of the DWIO mode bit of
BCR18.
Automatic determination of DWIO mode due to
DWORD (double-word) I/O write access to offset
10h.
The Ethernet controller I/O mode setting will default to
WIO after H_RESET (i.e. DWIO = 0).
Following the H_RESET operation, a PREAD operation
of the EEPROM will be executed. If the EEPROM is programmed with a ONE in the DWIO bit position and the
EEPROM checksum is correct, then the EEPROM read
will result in the setting of the DWIO mode to a ONE.
The DWIO mode setting is unaffected by the S_RESET
or setting the STOP bit.
WIO I/O Resource Map
When the Ethernet controller I/O space is mapped as
Word I/O, then the resources that are allotted to the
Ethernet controller occur on word boundaries that are
offset from the Ethernet controller I/O base address as
shown in the table below:
Offset
No. of
Bytes
Register
0h
2
APROM
2h
2
APROM
4h
2
APROM
6h
2
APROM
If the EEPROM programming was absent, failed, or contained a ZERO in the DWIO bit position, then the software may invoke DWIO mode by performing a Double
Word write access to the I/O location at offset 10h
(RDP). Note that even though the I/O resource mapping
changes when the I/O mode setting changes, the RDP
location offset is the same for both modes.
8h
2
APROM
Ah
2
APROM
Ch
2
APROM
Eh
2
APROM
1-, 2- and 3-byte accesses to Ethernet controller I/O resources are not allowed during DWIO mode.
10h
2
RDP
12h
2
RAP (shared by RDP and BDP)
The mapping of the Ethernet controller resources into
the 32-byte I/O space varies depending upon the setting
of the DWIO bit of BCR10. Depending upon the setting
of this variable, the 32-byte I/O space will be either Word
I/O mapped (WIO) or Double Word I/O mapped (DWIO).
A DWIO setting of 0 produces Word I/O mode, while a
DWIO setting of 1 produces Double Word I/O mapping.
14h
2
Reset Register
16h
2
BDP
18h
2
Vendor Specific Word
DWIO is automatically programmed as active when the
system attempts a DWORD write access to offset 10h of
the Ethernet controller I/O space. As long as no
DWORD write access to offset 10h of the Ethernet controller I/O space is performed, the Ethernet controller
will use the value of DWIO that was programmed from
the EEPROM read operation. If no EEPROM is used in
the system, then the power up reset value of DWIO will
be ZERO, and this value will be maintained until a
DWORD access is performed to Ethernet controller I/O
space.
Therefore, if DWIO mode is desired, it is imperative that
the first access to the Ethernet controller be a DWORD
write access to offset 10h, unless the EEPROM will be
used to program the DWIO bit.
Alternatively, if DWIO mode is not desired, then it is imperative that the software never executes a DWORD
write access to offset 10h of the Ethernet controller I/O
space, and the EEPROM programming of the DWIO bit
must be ZERO.
Once the DWIO bit has been set to a ONE, only a hardware H_RESET or a new read of the EEPROM can reset it to a ZERO.
60
1Ah
2
Reserved
1Ch
2
Reserved
1Eh
2
Reserved
When Ethernet controller I/O space is Word mapped, all
I/O resources fall on word boundaries and all I/O resources are word quantities. However, while in Word I/O
mode, APROM locations may also be accessed as individual bytes either on odd or even byte addresses.
Attempts to write to any Ethernet controller I/O resources (except to offset 10h, RDP) as 32 bit quantities
while in Word I/O mode are illegal and may cause unexpected reprogramming of the Ethernet controller control
registers. Attempts to read from any Ethernet controller
I/O resources as 32-bit quantities while in Word I/O
mode are illegal and will yield undefined values.
An attempt to write to offset 10h (RDP) as a 32 bit quantity while in Word I/O mode will cause the Ethernet controller to exit WIO mode and immediately thereafter, to
enter DWIO mode.
Word accesses to non word address boundaries are not
allowed while in WIO mode. (A write access may cause
unexpected reprogramming of the Ethernet controller
control registers. A read access will yield undefined
values.)
Am79C974
PRELIMINARY
Accesses of non word quantities to any I/O resource are
not allowed while in WIO mode, with the exception of a
read to APROM locations. (A write access may cause
unexpected reprogramming of the Ethernet controller
control registers; a read access will yield undefined
values.)
The Vendor Specific Word (VSW) is not implemented by
the Ethernet controller. This particular I/O address is reserved for customer use and will not be used by future
AMD Ethernet controller products.
DWIO I/O Resource Map
When the Ethernet controller I/O space is mapped as
Double Word I/O, then all of the resources that are allotted to the Ethernet controller occur on DWORD boundaries that are offset from the Ethernet controller I/O base
address as shown in the table below:
AMD
reserved and written as ZEROS and read as undefined,
except for the APROM locations and CSR88.
DWIO mode is exited by asserting the RST pin or by
forcing a re-read of the EEPROM when the EEPROM
will program a ZERO into the DWIO bit location of
BCR10. Assertion of S_RESET or setting the STOP bit
of CSR0 will have no effect on the DWIO mode setting.
I/O Space Comments
The following statements apply to both WIO and DWIO
mapping:
The RAP is shared by the RDP and the BDP.
The Ethernet controller does not respond to any addresses outside of the offset range 0h–17h when DWIO
= 0 or 0h–1Fh when DWIO = 1. I/O offsets 18h through
1Fh are not used by the Ethernet controller when programmed for DWIO = 0 mode; locations 1Ah through
1Fh are reserved for future AMD use and therefore
should not be implemented by the user if upward compatibility to future AMD devices is desired.
Offset
No. of
Bytes
Register
0h
4
APROM
4h
4
APROM
8h
4
APROM
Ch
4
APROM
10h
4
RDP
14h
4
RAP (shared by RDP and BDP)
18h
4
Reset Register
Note that APROM accesses do not directly access the
EEPROM, but are redirected to a set of shadow registers on board the Ethernet controller that contain a copy
of the EEPROM contents that was obtained during the
automatic EEPROM read operation that follows the
H_RESET operation.
1Ch
4
BDP
Am79C974’s Ethernet Controller I/O Base Address
When Ethernet I/O space is Double Word mapped, all
I/O resources fall on DWORD boundaries. APROM resources are DWORD quantities in DWIO mode. RDP,
RAP and BDP contain only two bytes of valid data; the
other two bytes of these resources are reserved for future use. (Note that CSR88 is an exception to this rule.)
The reserved bits must be written as ZEROs, and when
read, are considered undefined.
Accesses to non-doubleword address boundaries are
not allowed while in DWIO mode. (A write access may
cause unexpected reprogramming of the Ethernet controller control registers; a read access will yield undefined values.)
Accesses of less than 4 bytes to any I/O resource are
not allowed while in DWIO mode. (A write access may
cause unexpected reprogramming of the Ethernet controller control registers; a read access will yield undefined values.)
If an EEPROM is not used to program the value of
DWIO, then a DWORD write access to the RDP offset of
10h will automatically program DWIO mode.
Note that in all cases when I/O resource width is defined
as 32 bits, the upper 16 bits of the I/O resource is
The Ethernet PCI Configuration Space Base Address
register defines what I/O base address the Ethernet
controller uses. This register is typically programmed by
the PCI configuration utility after system power-up. The
PCI configuration utility must also set the IOEN bit in the
COMMAND register to enable I/O accesses to the
Ethernet controller.
The contents of the Ethernet I/O Base Address Registers (BCR16 and BCR17) are ignored.
I/O Register Access
All I/O resources are accessed with similar I/O bus
cycles.
I/O accesses to the Ethernet controller begin with a valid
FRAME signal, the C/BE[3:0] lines signaling an I/O read
or I/O write operation and an address on the AD[31:00]
lines that falls within the I/O space of the Ethernet controller. The Ethernet I/O space will be determined by the
Base Address Register in the PCI Configuration Space.
The Ethernet controller will respond to an access to its
I/O space by asserting the DEVSEL signal and eventually, by asserting the TRDY signal.
Typical I/O access times are 6 or 7 clock cycles.
Am79C974
61
AMD
PRELIMINARY
APROM Access
The APROM space is a convenient place to store the
value of the 48-bit IEEE station address. This space is
automatically loaded from the serial EEPROM, if an
EEPROM is present. It can be overwritten by the host
computer. Its contents have no effect on the operation of
the controller. The software must copy the station address from the APROM space to the initialization block
or to CSR12-14 in order for the receiver to accept
unicast frames directed to this station.
When programmed for WIO mode, any byte or word address from an offset of 0h to an offset of Fh may be read.
An appropriate byte or word of APROM contents will be
delivered by the Am79C974 controller in response to accesses that fall within the APROM range of 0h to Fh.
When programmed for DWIO mode, only DWORD addresses from an offset of 0h to an offset of Fh may be
read. An appropriate DWORD of APROM contents will
be delivered in response to accesses that fall within the
APROM range of 0h to Fh.
Accesses of non-DWORD quantities are not allowed in
DWIO mode, even though such an access may be properly aligned to a DWORD address boundary.
Write access to any of the APROM locations is allowed,
but only 4 bytes on DWORD boundaries in DWIO mode
or 2 bytes on word boundaries in WIO mode (only read
accesses to the APROM locations can be in 8-bit quantities while in WIO mode). The IESRWE bit (see BCR2)
must be set in order to enable a write operation to the
APROM. Only the Am79C974 controller on-board IEEE
Shadow registers are modified by writes to APROM locations. The EEPROM is unaffected by writes to
APROM locations.
Note that the APROM locations occupy 16 bytes of
space, yet the IEEE station address requirement is for 6
bytes. The 6 bytes of IEEE station address occupy the
first 6 locations of the APROM space. The next six bytes
are reserved. Bytes 12 and 13 should match the value of
the checksum of bytes 1 through 11 and 14 and 15.
Bytes 14 and 15 should each be ASCII W (57h). The
above requirements must be met in order to be compatible with AMD driver software.
RDP Access (CSR Register Space)
RDP = Register Data Port. The RDP is used with the
RAP to gain access to any of the Am79C974 controller
CSR locations.
Access to any of the CSR locations of the Am79C974
controller is performed through the Am79C974 controllers Register Data Port (RDP). In order to access a particular CSR location, the Register Address Port (RAP)
should first be written with the appropriate CSR address. The RDP now points to the selected CSR. A read
62
of the RDP will yield the selected CSRs data. A write to
the RDP will write to the selected CSR.
When programmed for WIO mode, the RDP has a width
of 16 bits, hence, all CSR locations have 16 bits of width.
Note that when accessing RDP, the upper two bytes of
the data bus will be undefined since the byte masks will
not be active for those bytes.
If DWIO mode has been invoked, then the RDP has a
width of 32 bits, hence, all CSR locations have 32 bits of
width and the upper two bytes of the data bus will be active, as indicated by the byte mask. In this case, note
that the upper 16 bits of all CSR locations (except
CSR88) are reserved and written as ZEROs and read as
undefined values. Therefore, during RDP write operations in DWIO mode, the upper 16 bits of all CSR locations should be written as ZEROs.
RAP Access
RAP = Register Address Port. The RAP is used with the
RDP and with the BDP to gain access to any of the CSR
and BCR register locations, respectively. The RAP contains the address pointer that will be used by an access
to either the RDP or BDP. Therefore, it is necessary to
set the RAP value before accessing a specific CSR or
BCR location. Once the RAP has been written with a
value, the RAP value remains unchanged until another
RAP write occurs, or until an H_RESET or S_RESET
occurs. RAP is set to all ZEROs when an H_RESET or
S_RESET occurs. RAP is unaffected by the STOP bit.
When programmed for WIO mode, the RAP has a width
of 16 bits. Note that when accessing RAP, the upper two
bytes of the data bus will be undefined since the byte
masks will not be active for those bytes
When programmed for DWIO mode, the RAP has a
width of 32 bits. In DWIO mode, the upper 16 bits of the
RAP are reserved and written as ZEROs and read as
undefined. These bits should be written as ZEROs.
BDP Access (BCR Register Space)
BDP = Bus Configuration Register Data Port. The BDP
is used with the RAP to gain access to any of the
Am79C974 controller BCR locations.
Access to any of the BCR locations of the Am79C974
controller is performed through the Am79C974 controllers BCR Data Port (BDP ); in order to access a particular BCR location, the Register Address Port (RAP)
should first be written with the appropriate BCR address. The BDP now points to the selected BCR.
A read of the BDP will yield the selected BCR s data. A
write to the BDP will write to the selected BCR.
When programmed for WIO mode, the BDP has a width
of 16 bits, hence, all BCR locations have 16 bits of width
in WIO mode. Note that when operating in WIO mode,
Am79C974
PRELIMINARY
the upper two bytes of the data bus will be undefined
since the byte mask will not be active for those bytes.
If DWIO mode has been invoked, then the BDP has a
width of 32 bits, hence, all BCR locations have 32 bits of
width and the upper two bytes of the data bus will be active, as indicated by the byte mask. In this case, note
that the upper 16 bits of all BCR locations are reserved
and written as ZEROs and read as undefined. Therefore, during BDP write operations in DWIO mode, the
upper 16 bits of all BCR locations should be written as
ZEROs.
RESET Register (S_RESET)
A read of the reset register creates an internal S_RESET pulse in the Am79C974 controller. This read access cycle must be 16 bits wide in WIO mode and 32 bits
wide in DWIO mode. The internal S_RESET pulse that
is generated by this access is different from both the assertion of the hardware RST pin (H_RESET) and from
the assertion of the software STOP bit. Specifically, the
reset registers S_RESET will be the equivalent of the
assertion of the RST pin (H_RESET) assertion for all
CSR locations, but S_RESET will have no effect at all on
the BCR or PCI configuration space locations, and
S_RESET will not cause a deassertion of the REQ pin.
The NE2100 LANCE based family of Ethernet cards requires that a write access to the reset register follows
each read access to the reset register. The Am79C974
controller does not have a similar requirement. The write
access is not required but it does not have any
harmful effects.
Write accesses to the reset register will have no effect
on the Am79C974 controller.
Note that a read access of the reset register will take
longer than the normal I/O access time of the
Am79C974 controller. This is because an internal
S_RESET pulse will be generated due to this access,
and the access will not be allowed to complete on the
system bus until the internal S_RESET operation has
been completed. This is to avoid the problem of allowing
a new I/O access to proceed while the S_RESET operation has not yet completed, which would result in erroneous data being returned by (or written into) the
Am79C974 controller. The length of a read of the Reset
register can be as long as 64 clock cycles.
AMD
Note that a read of the reset register will not cause a
deassertion of the REQ signal, if it happens to be active
at the time of the read of the reset register. The REQ signal will remain active until the GNT signal is asserted.
Following the read of the reset register, on the next clock
cycle after the GNT signal is asserted, the Am79C974
controller will deassert the REQ signal. No bus master
accesses will have been performed during this brief bus
ownership period.
Note that this behavior differs from that which occurs following the assertion of a minimum-width pulse on the
RST pin (H_RESET). A RST pin assertion will cause the
REQ signal to deassert within six clock cycles following
the assertion. In the RST pin case, the Am79C974 controller will not wait for the assertion of the GNT signal before deasserting the REQ signal.
Vendor Specific Word
This I/O offset is reserved for use by the system designer. The Am79C974 controller will not respond to accesses directed toward this offset. The Vendor Specific
Word is only available when the Am79C974 controller is
programmed to word I/O mode (DWIO = 0).
If more than one Vendor Specific Word is needed, it is
suggested that the VSW location should be divided into
a VSW Register Address Pointer (VSWRAP) at one location (e.g. VSWRAP at byte location 18h or word location 30h, depending upon DWIO state) and a VSW Data
Port (VSWDP) at the other location (e.g. VSWDP at byte
location 19h or word location 32h, depending upon
DWIO state). Alternatively, the system may capture
RAP data accesses in parallel with the Am79C974 controller and therefore share the Am79C974 controller
RAP to allow expanded VSW space. Am79C974 controller will not respond to access to the VSW I/O address.
Reserved I/O Space
These locations are reserved for future use by AMD.
The Am79C974 controller does not respond to accesses directed toward these locations, but future AMD
products that are intended to be upward compatible with
the Am79C974 controller device may decode accesses
to these locations. Therefore, the system designer may
not utilize these I/O locations.
Am79C974
63
AMD
PRELIMINARY
Hardware Access
data size and address information.
PCnet-SCSI Controller Master Accesses
The Am79C974 controller will support master accesses
only to 32-bit peripherals. The Am79C974 controller
does not support master accesses to 8-bit or 16-bit
memory. The Am79C974 controller is not compatible
with 8-bit systems, since there is no mode that supports
Am79C974 controller accesses to 8-bit peripherals.
The Am79C974 controller has a bus interface compatible with PCI specification revision 2.0.
Complete descriptions of the signals involved in bus
master transactions for each mode may be found in the
pin description section of this document. Timing diagrams for master accesses may be found in the block
description section for the Bus Interface Unit. This section simply lists the types of master accesses that will be
performed by the Am79C974 controller with respect to
Table 3 describes all possible bus master accesses that
the Am79C974 controller will perform. The right most
column lists all operations that may execute the given
access:
Table 3. Bus Master Accesses
Access
Mode
BE[3:0]
4-byte read
Read
0000
descriptor read
or initialization block read
or transmit data buffer read
4-byte write
Write
0000
descriptor write
or receive data buffer write
3-byte write
Write
1000
receive data buffer write
3-byte write
Write
0001
receive data buffer write
2-byte write
Write
1100
receive data buffer write
2-byte write
Write
1001*
receive data buffer write
2-byte write
Write
0011
receive data buffer write
1-byte write
Write
1110
receive data buffer write
1-byte write
Write
1101*
receive data buffer write
1-byte write
Write
1011*
receive data buffer write
1-byte write
Write
0111
descriptor write
or receive data buffer write
Operation
* Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte
buffer sizes, and therefore will not be seen under normal circumstances.
Note that all Am79C974 controller master read operations will always activate all byte enables. Therefore, no
one-, two- or three-byte read operations are indicated in
the table.
In the instance where a transmit buffer pointer address
begins on a non-DWORD boundary, the pointer will be
truncated to the next DWORD boundary address that
lies below the given pointer address and the first read
access from the transmit buffer will be indicated on the
byte enable signals as a four-byte read from this address. Any data from byte lanes that lie outside of the
boundary indicated by the buffer pointer will be discarded inside of the Am79C974 controller. Similarly, if
the end of a transmit buffer occurs on a non-DWORD
boundary, then all byte lanes will be indicated as active
by the byte enable signals, and any data from byte lanes
that lie outside of the boundary indicated by the buffer
pointer will be discarded inside of the Am79C974
controller.
64
Slave Access to I/O Resources
The Am79C974 device is always a 32-bit peripheral on
the system bus. However, the width of individual software resources on board the Am79C974 controller may
be either 16-bits or 32-bits. The Am79C974 controller
I/O resource widths are determined by the setting of the
DWIO bit as indicated in the following table:
Am79C974
Controller I/O
DWIO Setting Resource Width
Example Application
DWIO = 0
16-bit
Existing PCnet-ISA
driver that assumes
16-bit I/O mapping
and 16-bit resource
widths
DWIO = 1
32-bit
New drivers written
specifically for the
Am79C974 controller
Am79C974
AMD
PRELIMINARY
Note that when I/O resource width is defined as 32 bits
(DWIO mode), the upper 16 bits of the I/O resource is
reserved and written as ZEROS and read as undefined,
except for the APROM locations and CSR88. The
APROM locations and CSR88 are the only I/O resources for which all 32 bits will have defined values.
However, this is true only when the Am79C974 controller is in DWIO mode.
Configuring the Am79C974 controller for DWIO mode is
accomplished whenever there is any attempt to perform
a 32-bit write access to the RDP location (offset 10h).
See the DWIO section for more details.
Table 4 describes all possible bus slave accesses that
may be directed toward the Am79C974 controller. (i.e.,
the Am79C974 controller is the target device during the
transfer.) The first column indicates the type of slave access. RD stands for READ, WR for a WRITE operation.
The second column indicates the value of the C/BE[3:0]
lines during the data phase of the transfer. The four byte
columns (AD[31:24], AD[23:16], AD[15:8], AD[7:0]) indicate the value on the address/data bus during the data
phase of the access. “data” indicates the position of the
active bytes; “copy” indicates the positions of copies of
the active bytes; “undef” indicates byte locations that are
undefined during the transfer.
Table 4. Bus Slave Accesses
TYPE
BE[3:0]
AD
[31:24]
AD
[23:16]
AD
[15:8]
AD
[7:0]
RD
0000
data
data
data
data
DWORD access to DWORD address, e.g. 300h,
30Ch, 310h (DWIO mode only)
RD
1100
undef
undef
data
data
word access to even word address, e.g. 300h,
30Ch, 310h (WIO mode only)
RD
0011
data
data
copy
copy
word access to odd word address, e.g. 302h, 30Eh,
312h (WIO mode only)
RD
1110
undef
undef
undef
data
byte access to lower byte of even word address, e.g.
300h, 304h (WIO mode only, APROM accesses
only)
RD
1101
undef
undef
data
undef
byte access to upper byte of even word address,
e.g. 301h, 305h (WIO mode only, APROM accesses
only)
RD
1011
undef
data
undef
copy
byte access to lower byte of odd word address, e.g.
302h, 306h (WIO mode only, APROM accesses
only)
RD
0111
data
undef
copy
undef
byte access to upper byte of odd word address, e.g.
303h, 307h (WIO mode only, APROM accesses
only)
WR
0000
data
data
data
data
DWORD access to DWORD address, e.g. 300h,
30Ch, 310h (DWIO mode only)
WR
1100
undef
undef
data
data
word access to even word address, e.g. 300h,
30Ch, 310h (WIO mode only)
WR
0011
data
data
undef
undef
word access to odd word address, e.g. 302h, 30Eh,
312h (WIO mode only)
Am79C974
Comments
65
AMD
PRELIMINARY
EEPROM Microwire Access
The Am79C974 controller contains a built-in capability
for reading and writing to an external EEPROM. This
built-in capability consists of a Microwire interface for direct connection to a Microwire compatible EEPROM, an
automatic EEPROM read feature, and a user-programmable register that allows direct access to the Microwire
interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the RST pin, the
Am79C974 controller will read the contents of the
EEPROM that is attached to the Microwire interface.
Because of this automatic-read capability of the
Am79C974 controller, an EEPROM can be used to program many of the features of the Am79C974 controller
at power-up, allowing system-dependent configuration
information to be stored in the hardware, instead of inside of operating code.
If an EEPROM exists on the Microwire interface, the
Am79C974 controller will read the EEPROM contents at
the end of the H_RESET operation. The EEPROM contents will be serially shifted into a temporary register and
then sent to various register locations on board the
Am79C974 controller. The host can access the PCI
Configuration Space during the EEPROM read operations. Access to the Am79C974 I/O resources, however,
is not possible during the EEPROM read operation. The
Am79C974 controller will terminate these I/O accesses
with the assertion of DEVSEL and STOP while TRDY is
not asserted, signaling to the initiator to retry the access
at a later time.
A checksum verification is performed on the data that is
read from the EEPROM. If the checksum verification of
the EEPROM data fails, then at the end of the EEPROM
read sequence, the Am79C974 controller will force all
EEPROM-programmable BCR registers back to their
H_RESET default values. The content of the APROM
locations (offsets 0h – Fh from the I/O base address),
however, will not be cleared. The 8-bit checksum for the
entire 36 bytes of the EEPROM should be FFh.
the EEPROM-programmable registers on board the
Am79C974 controller. (The EEPROM-programmable
registers may also be reprogrammed directly, but only
information that is stored in the EEPROM will be preserved at system power-down.) When the PREAD bit of
BCR19 is set, it will cause the Am79C974 controller to
terminate further accesses to internal I/O resources with
the PCI retry cycle. Accesses to the PCI configuration
space is still possible.
EEPROM Auto-Detection
The Am79C974 controller uses the EESK/LED1 pin to
determine if an EEPROM is present in the system. At all
rising CLK edges during the assertion of the RST pin,
the Am79C974 controller will sample the value of the
EESK/LED1 pin. If the sampled value is a ONE, then the
Am79C974 controller assumes that an EEPROM is present, and the EEPROM read operation begins shortly
after the RST pin is deasserted. If the sampled value of
EESK/LED1 is a ZERO, then the Am79C974 controller
assumes that an external pulldown device is holding the
EESK/LED1 pin low, and therefore, there is no
EEPROM in the system. Note that if the designer creates a system that contains an LED circuit on the
EESK/LED1 pin but has no EEPROM present, then the
EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the system. However, this will not pose a problem for the Am79C974
controller, since it will recognize the lack of an EEPROM
at the end of the read operation, when the checksum
verification fails.
Systems Without an EEPROM
Some systems may be able to save the cost of an
EEPROM by storing the ISO 8802-3 (IEEE/ANSI 802.3)
station address and other configuration information
somewhere else in the system. There are several design choices:
If the LED1 is not needed in the system, then the system designer may connect the EESK/LED1 pin to a
resistive pulldown device. This will indicate to the
EEPROM auto-detection function that no EEPROM
is present.
If no EEPROM is present at the time of the automatic
read operation, then the Am79C974 controller will recognize this condition and will abort the automatic read
operation and reset both the PREAD and PVALID bits in
BCR19. All EEPROM-programmable BCR registers will
be assigned their default values after H_RESET. The
content of the Address PROM locations (offsets 0h – Fh
from the I/O base address) will be undefined.
If the user wishes to modify any of the configuration bits
that are contained in the EEPROM, then the seven command, data and status bits of BCR19 can be used to
write to the EEPROM. After writing to the EEPROM, the
host should set the PREAD bit of BCR19. This action
forces a Am79C974 controller re-read of the EEPROM
so that the new EEPROM contents will be loaded into
66
If the LED1 function is needed in the system, then the
system designer will connect the EESK/LED1 pin to
a resistive pullup device and the EEPROM auto-detection function will incorrectly conclude that an
EEPROM is present in the system. However, this will
not pose a problem for the Am79C974 controller,
since it will recognize the lack of an EEPROM at the
end of the read operation, when the checksum verification fails.
In either case, following the PCI configuration, additional information, including the ISO 8802-3 (IEEE/ANSI
802.3) station address, may be loaded into the
Am79C974 controller. Note that the IESRWE bit (bit 8 of
BCR2) must be set before the Am79C974 controller will
Am79C974
PRELIMINARY
accept writes to the APROM offsets within the
Am79C974 I/O resources map. Startup code in the system BIOS can perform the PCI configuration accesses,
the IESRWE bit write, and the APROM writes.
Direct Access to the Microwire Interface
4. BCR17
5. BCR18
The user may directly access the Microwire port through
the EEPROM register, BCR19. This register contains
bits that can be used to control the Microwire interface
pins. By performing an appropriate sequence of I/O accesses to BCR19, the user can effectively write to and
read from the EEPROM. This feature may be used by a
system configuration utility to program hardware configuration information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration information that will be programmed automatically during the
EEPROM read operation:
1. I/O offsets 0h – Fh
2. BCR2
3. BCR16
APROM locations
Miscellaneous Configuration
6. BCR21
AMD
register
not used in the Am79C974
controller
not used in the Am79C974
controller
Burst Size and Bus Control
Register
Not Used
If the PREAD bit (BCR19) is reset to ZERO and the
PVALID bit (BCR19) is reset to ZERO, then the
EEPROM read has experienced a failure and the contents of the EEPROM programmable BCR register will
be set to default H_RESET values. The content of the
APROM locations, however, will not be cleared.
Note that accesses to the APROM I/O locations do not
directly access the Address EEPROM itself. Instead,
these accesses are routed to a set of shadow registers
on board the Am79C974 controller that are loaded with
a copy of the EEPROM contents during the automatic
read operation that immediately follows the H_RESET
operation.
Am79C974
67
AMD
PRELIMINARY
EEPROM MAP
The automatic EEPROM read operation will access 18
words (i.e. 36 bytes) of the EEPROM. The format of the
EEPROM contents is shown in Table 5, beginning with
the byte that resides at the lowest EEPROM address:
Table 5. EEPROM Contents
EEPROM
WORD
Address
EEPROM Contents
Byte
Addr.
Byte
Addr.
Most Significant Byte
Least Significant Byte
00h
(lowest
EEPROM
address)
01h
2nd byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node
00h
first byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node, where “first byte”
refers to the first byte to appear on the
802.3 medium
01h
03h
4th byte of the node address
02h
3rd byte of the node address
02h
05h
6th byte of the node address
04h
5th byte of the node address
03h
07h
reserved location: must be 00h
06h
reserved location must be 00h
04h
09h
Hardware ID: must be 11h if
compatibility to AMD drivers is
desired
08h
reserved location must be 00h
05h
0Bh
user programmable space
0Ah
user programmable space
06h
0Dh
MSByte of two-byte checksum,
which is the sum of bytes 00h–0Bh
and bytes 0Eh and 0Fh
0Ch
LSByte of two-byte checksum, which is the
sum of bytes 00h–0Bh and bytes 0Eh and 0Fh
07h
0Fh
must be ASCII “W” (57h) if compatibility
to AMD driver software is desired
0Eh
must be ASCII “W” (57h) if compatibility
to AMD driver software is desired
08h
11h
BCR16[15:8] (not used)
10h
BCR16[7:0] (not used)
09h
13h
BCR17[15:8] (not used)
12h
BCR17[7:0] (not used)
0Ah
15h
BCR18[15:8] (Burst Size and Bus Control)
14h
BCR18[7:0] (Burst Size and Bus Control)
0Bh
17h
BCR2[15:8] (Misc. configuration)
16h
BCR2[7:0] (Misc. configuration)
0Ch
19h
BCR21[15:8] (Not Used)
18h
BCR21[7:0] (Not Used)
0Dh
1Bh
reserved location must be 00h
1Ah
reserved location must be 00h
0Eh
1Dh
reserved location must be 00h
1Ch
reserved location must be 00h
0Fh
1Fh
checksum adjust byte for the first 36 bytes
of the EEPROM contents; checksum of the
first 36 bytes of the EEPROM should total
to FFh
1Eh
reserved location must be 00h
10h
21h
reserved location must be 00h
20h
reserved location must be 00h
11h
23h
user programmable byte locations
22h
user programmable byte locations
Note that the first bit out of any WORD location in the
EEPROM is treated as the MSB of the register that is being programmed. For example, the first bit out of
EEPROM WORD location 08h will be written into
BCR16[15], the second bit out of EEPROM WORD location 08h will be written into BCR16[14], etc.
There are two checksum locations within the EEPROM.
The first is required for the EEPROM address. This
checksum will be used by AMD driver software to verify
that the ISO 8802-3 (IEEE/ANSI 802.3) station address
68
has not been corrupted. The value of bytes 0Ch and 0Dh
should match the sum of bytes 00h through 0Bh and
0Eh and 0Fh. The second checksum location – byte
1Fh – is not a checksum total, but is, instead, a checksum adjustment. The value of this byte should be such
that the total checksum for the entire 36 bytes of
EEPROM data equals the value FFh. The checksum adjust byte is needed by the Am79C974 controller in order
to verify that the EEPROM contents have not been
corrupted.
Am79C974
AMD
PRELIMINARY
Transmit Operation
The transmit operation and features of the Am79C974
controller are controlled by programmable options. The
Am79C974 controller offers a136-byte Transmit FIFO to
provide frame buffering for increased system latency,
automatic retransmission with no FIFO reload, and
automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initialization block.
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4. If APAD_XMT is set, automatic pad field insertion is enabled, the DXMTFCS feature is over-ridden, and the 4-byte FCS will be added to
the transmitted frame unconditionally. If APAD_XMT is
clear, no pad field insertion will take place and runt
packet transmission is possible.
The disable FCS generation/transmission feature can
be programmed dynamically on a frame by frame basis.
See the ADD_FCS description of TMD1.
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
point at which the BMU requests more data from the
transmit buffers for the FIFO. A minimum of XMTFW
empty spaces must be available in the transmit FIFO before the BMU will request the system bus in order to
transfer transmit packet data into the transmit FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes must
be written to the transmit FIFO for the current frame before transmission of the current frame will begin. (When
automatically padded packets are being sent, it is conceivable that the XMTSP is not reached when all of the
data has been transferred to the FIFO. In this case, the
transmission will begin when all of the packet data has
been placed into the transmit FIFO.)
When the entire frame is in the FIFO, attempts at transmission of preamble will commence regardless of the
value in XMTSP. The default value of XMTSP is 10b,
meaning there has to be 64 bytes in the Transmit FIFO
to start a transmission.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This allows
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed with no software intervention from the host/controlling process.
Setting the APAD_XMT bit in CSR4 enables the automatic padding feature. The pad is placed between the
LLC data field and FCS field in the 802.3 frame.FCS is
always added if the frame is padded, regardless of the
state of DXMTFCS. The transmit frame will be padded
by bytes with the value of 00h. The default value of
APAD_XMT is 0; this will disable auto pad generation after H_RESET.
Preamble
1010....1010
Sync
10101011
Destination
Address
Source
Address
Length
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
LLC
Data
Pad
FCS
4
Bytes
46 — 1500
Bytes
18681A-26
Figure 22. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes encapsulated in the packet (length field as defined in the
ISO 8802-3 (IEEE/ANSI 802.3) standard). The length
value contained in the message is not used by the
Am79C974 controller to compute the actual number of
pad bytes to be inserted. The Am79C974 controller will
append pad bytes dependent on the actual number of
bits transmitted onto the network. Once the last data
byte of the frame has completed, prior to appending the
FCS, the Am79C974 controller will check to ensure that
544 bits have been transmitted. If not, pad bytes are
added to extend the frame size to this value, and the
FCS is then added.
Am79C974
69
AMD
PRELIMINARY
ownership (resets the OWN bit to ZERO) for this frame,
and processes the next frame in the transmit ring for
transmission.
The 544 bit count is derived from the following:
Minimum frame
size (excluding
preamble,
including FCS)
64
bytes
512
bits
Preamble/SFD size
8
bytes
64
bits
FCS size
4
bytes
32
bits
Abnormal network conditions include:
Loss of carrier.
Late collision.
SQE Test Error. (does not apply to 10BASE-T port)
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
Preamble + (Min Frame Size + FCS) bits
Preamble + (Min Frame Size – FCS) bits
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be reset until the STP (the next frame)
is found.
64 + (512 – 32) bits
Loss of Carrier
At the point that FCS is to be appended, the transmitted
frame should contain:
A minimum length transmit frame from the Am79C974
controller will therefore be 576 bits, after the FCS is
appended.
The Ethernet specification assumes that minimum
length messages will be at least 64 bytes in length.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit in
CSR15. When DXMTFCS = 0 the transmitter will generate and append the FCS to the transmitted frame. If the
automatic padding feature is invoked (APAD_XMT is
set in CSR4), the FCS will be appended by the
Am79C974 controller regardless of the state of
DXMTFCS. Note that the calculated FCS is transmitted
most significant bit first. The default value of DXMTFCS
is 0 after H_RESET.
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories. Those which are the result of normal
network operation, and those which occur due to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the Am79C974 controller include collisions within the slot time with automatic retry. The
Am79C974 controller will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried with no
host intervention. The transmit FIFO ensures this by
guaranteeing that data contained within the FIFO will
not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length and data fields have been
transmitted onto the network without encountering
a collision.
If 16 total attempts (initial attempt plus 15 retries) fail, the
Am79C974 controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up
70
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
A loss of carrier condition will be reported if the
Am79C974 controller cannot observe receive activity
whilst it is transmitting on the AUI port. After the
Am79C974 controller initiates a transmission it will expect to see data “looped-back” on the DI± pair. This will
internally generate a “carrier sense”, indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This “carrier
sense” signal must be asserted about 6 bit times before
the last transmitted bit on DO±. If “carrier sense” does
not become active in response to the data transmission,
or becomes inactive before the end of transmission, the
loss of carrier (LCAR) error bit will be set in TMD2 after
the frame has been transmitted. The frame will not be
re-tried on the basis of an LCAR error.
When the 10BASE-T port is selected, LCAR will be reported for every packet transmitted during the Link
fail condition.
Late Collision
A late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
The Am79C974 controller will abandon the transmit
process for the particular frame, set Late Collision
(LCOL) in the associated TMD2, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be re-tried. Recovery from this condition
must be performed by upper layer software.
SQE Test Error
During the inter packet gap time following the completion of a transmitted message, the AUI CI± pair is asserted by some transceivers as a self-test. The integral
Manchester Encoder/Decoder will expect the SQE Test
Message (nominal 10 MHz sequence) to be returned via
the CI± pair, within a 40 network bit time period after DI±
goes inactive (this does not apply if the 10BASE-T port
is selected). If the CI± input is not asserted within the 40
Am79C974
PRELIMINARY
network bit time period following the completion of
transmission, then the Am79C974 controller will set the
CERR bit in CSR0. CERR will be asserted in 10BASE-T
mode after transmit if T-MAU is in Link Fail state. CERR
will never cause INTA to be activated. It will, however,
set the ERR bit CSR0.
Receive Operation
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promiscuous mode. In the promiscuous mode, all properly formed packets are received, regardless of the contents of their destination address fields. The
promiscuous mode overrides the Disable Receive
Broadcast bit (DRCVBC bit l4 in the MODE register) and
the Disable Receive Physical Address bit (DRCVPA, bit
13 MODE register).
The receive operation and features of the Am79C974
controller are controlled by programmable options.
The Am79C974 controller operates in promiscuous
mode when PROM (bit 15 in the MODE register) is set.
Address Matching
Receive Function Programming
The Am79C974 controller supports three types of address matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified by
programming three bits in the MODE register (PROM,
DRCVBC, and DRCVPA).
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the 802.3 frame
format.
If the first bit received after the start of frame delimiter
(the least significant bit of the first byte of the destination
address field) is 0, the frame is unicast, which indicates
that the frame is meant to be received by a single node.
If the first bit received is 1, the frame is multicast, which
indicates that the frame is meant to be received by a
group of nodes. If the destination address field contains
all ones, the frame is broadcast, which is a special type
of multicast. Frames with the broadcast address in the
destination address field are meant to be received by all
nodes on the local area network.
When a unicast frame arrives at the Am79C974 controller, the controller will accept the frame if the destination
address field of the incoming frame exactly matches the
6-byte station address stored in the PADR registers
(CSR12, CSR13, and CSR14). The byte ordering is
such that the first byte received from the network (after
the SFD) must match the least significant byte of CSR12
(PADR[7:0]), and the sixth byte received must match the
most significant byte of CSR14 (PADR[47:40]).
If DRCVPA (bit 13 in the MODE register) is set. the
Am79C974 controller will not accept unicast frames.
If the incoming frame is multicast the Am79C974 controller performs a calculation on the contents of the destination address field to determine whether or not to
accept the frame. This calculation is explained in the
section that describes the Logical Address Filter
(LADRF).
If all bits of the LADRF registers are 0 no multicast
frames are accepted, except for broadcast frames.
Although broadcast frames are classified as special
multicast frames, they are treated differently by the
Am79C974 controller hardware. Broadcast frames are
always accepted, except when DRCVBC (bit 14 in the
MODE register) is set.
None of the address filtering described above applies
when the Am79C974 controller is operating in the
All receive frames can be accepted by setting the PROM
bit in CSR15. When PROM is set, the Am79C974 controller will attempt to receive all messages, subject to
minimum frame enforcement. Promiscuous mode over
rides the effect of the Disable Receive Broadcast bit on
receiving broadcast frames.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established during H_RESET is 10b which sets the threshold flag at
64 bytes empty.
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. ASTRP_RCV (CSR4, bit 0) = 1
enables the automatic pad stripping feature. The pad
field will be stripped before the frame is passed to the
FIFO, thus preserving FIFO space for additional frames.
The FCS field will also be stripped, since it is computed
at the transmitting station based on the data and pad
field characters, and will be invalid for a receive frame
that has had the pad characters stripped.
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-3
(IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field (≥46), the
Am79C974 controller will not attempt to strip valid
Ethernet frames.
Note that for some network protocols, the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause
problems.
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Figure 23 shows the byte/bit ordering of the received
length field for an 802.3 compatible frame format.
46 — 1500
Bytes
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
Preamble
1010....1010
Sync
10101011
Destination
Address
Source
Address
Length
4
Bytes
LLC
Data
Pad
1 — 1500
Bytes
45 — 0
Bytes
FCS
Start of Frame
at Time = 0
Bit
0
Bit
7
Bit
0
Bit
7
Increasing Time
Most
Significant
Byte
Least
Significant
Byte
18681A-27
Figure 23. 802.3 Frame and Length Field Transmission Order
Receive FCS Checking
Reception and checking of the received FCS is performed automatically by the Am79C974 controller. Note
that if the Automatic Pad Stripping feature is enabled,
the FCS for padded frames will be verified against the
value computed for the incoming bit stream including
pad characters, but the FCS value for a padded frame
will not be passed to the host. If an FCS error is detected
in any frame, the error will be reported in the CRC bit
in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the Am79C974 controller are basically
collisions within the slot time and automatic runt packet
rejection. The Am79C974 controller will ensure that collisions which occur within 512 bit times from the start of
reception (excluding preamble) will be automatically deleted from the receive FIFO with no host intervention.
The receive FIFO will delete any frame which is composed of fewer than 64 bytes provided that the Runt
Packet Accept (RPA bit in CSR124) feature has not
been enabled. This criterion will be met regardless of
72
whether the receive frame was the first (or only) frame in
the FIFO or if the receive frame was queued behind a
previously received message.
Abnormal network conditions include:
FCS errors
Late Collision
Host related receive exception conditions include MISS,
BUFF, and OFLO. These are described in the BMU
section.
Loopback Operation
Loopback is a mode of operation intended for system diagnostics. In this mode, the transmitter and receiver are
both operating at the same time so that the controller receives its own transmissions. The controller provides
two types of internal loopback and one type of external
loopback. In internal loopback mode, the transmitted
data can be looped back to the receiver at one of two
places inside the controller without actually transmitting
any data to the external network. The receiver will move
the received data to the next receive buffer, where it can
be examined by software. Alternatively, in external loopback mode, data can be transmitted to and received
from the external network.
Am79C974
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There are restrictions on loopback operation. The
Am79C974 controller has only one FCS generator circuit. The FCS generator can be used by the transmitter
to generate the FCS to append to the frame, or it can be
used by the receiver to verify the FCS of the received
frame. It can not be used by the receiver and transmitter
simultaneously.
If the FCS generator is connected to the receiver, the
transmitter will not append an FCS to the frame, but the
receiver will check for one. The user can, however, calculate the FCS value for a frame and include this fourbyte number in the transmit buffer.
If the FCS generator is connected to the transmitter, the
transmitter will append an FCS to the frame, but the receiver will not check for the FCS. However, the user can
verify the FCS by software.
During loopback, the FCS logic can be allocated to the
receiver by setting DXMTFCS = 1 in CSR15.
If DXMTFCS=0, the MAC Engine will calculate and append the FCS to the transmitted message. The receive
message passed to the host will therefore contain an additional 4 bytes of FCS. In this loopback configuration,
the receive circuitry cannot detect FCS errors if
they occur.
If DXMTFCS=1, the last four bytes of the transmit message must contain the (software generated) FCS computed for the transmit data preceding it. The MAC
Engine will transmit the data without addition of an FCS
field, and the FCS will be calculated and verified at
the receiver.
The loopback facilities of the MAC Engine allow full operation to be verified without disturbance to the network.
Loopback operation is also affected by the state of the
Loopback Control bits (LOOP, MENDECL, and INTL) in
CSR15. This affects whether the internal MENDEC is
considered part of the internal or external
loopback path.
The multicast address detection logic uses the FCS
generator circuit. Therefore, in the loopback mode(s),
the multicast address detection feature of the MAC Engine, programmed by the contents of the Logical Address Filter (LADRF [63:0] in CSRs 8–11) can only be
tested when DXMTFCS=1, allocating the FCS generator to the receiver. All other features operate identically
in loopback as in normal operation, such as automatic
transmit padding and receive pad stripping.
When performing an internal loopback, no frame will be
transmitted to the network. However, when the
Am79C974 controller is configured for internal loopback
the receiver will not be able to detect network traffic. External loopback tests will transmit frames onto the
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network if the AUI port is selected, and the Am79C974
controller will receive network traffic while configured for
external loopback when the AUI port is selected. Runt
Packet Accept is automatically enabled when any loopback mode is invoked.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is invoked. This is to be backwards compatible to the
LANCE (Am7990) software.
When the 10BASE-T MAU is selected in external loopback mode, the collision detection is disabled. This is
necessary, because a collision in a 10BASE-T system is
defined as activity on the transmitter outputs and receiver inputs at the same time, which is exactly what occurs during external loopback.
Since a 10BASE-T hub does not normally feed the station’s transmitter outputs back into the station’s receiver
inputs, the use of external loopback in a 10BASE-T system usually requires some sort of external hardware that
connects the outputs of the 10BASE-T MAU to
its inputs.
LED Support
The Am79C974 controller can support up to 3 LEDs.
LED outputs LNKST and LED1 allow for direct connection of an LED and its supporting pullup device. LED output LED3 may require an additional buffer between the
Am79C974 controller output pin and the LED and its
supporting pullup device.
Because the LED3 output is multiplexed with other
Am79C974 controller functions, it may not always be
possible to connect an LED circuit directly to the LED3
pin. For example, when an LED circuit is directly connected to the EEDO/LED3 pin, then it is not possible for
most serial EEPROM devices to sink enough IOL to
maintain a valid low level on the EEDO input to the
Am79C974 controller. Therefore, in applications that require both an EEPROM and a third LED, then it is necessary to buffer the LED3 circuit from the
EEPROM-PCnet-SCSI connection. The LED registers
in the BCR resource space allow each LED output to be
programmed for either active high or active low operation, so that both inverting and non-inverting buffering
choices are possible.
In applications where an EEPROM is not needed, the
LED3 pin may be directly connected to an LED circuit.
The Am79C974 LED3 pin driver will be able to sink
enough current to properly drive the LED circuit.
By default, after H_RESET, the 3 LED outputs are configured in the following manner:
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LED
output
PRELIMINARY
Default
Default
Default
Interpretation Drive Enable Output Polarity
LNKST
Link Status
Enabled
Active LOW
LED1
Receive
Enabled
Active LOW
LED3
Transmit
Enabled
Active LOW
For each LED register, each of the status signals is
ANDed with its enable signal, and these signals are all
ORed together to form a combined status signal. Each
LED pins combined status signal runs to a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz (26 ms). The data input of each shift register is
normally at logic 0. The OR gate output for each LED
register asynchronously sets all three bits of its shift register when the output becomes asserted. The inverted
output of each shift register is used to control an LED
pin. Thus the pulse stretcher provides 2–3 clocks of
stretched LED output, or 52 ms to 78 ms.
LNK
LNK E
RCVM
RCVM E
To
Pulse
Stretcher
XMT
XMT E
RXPOL
RXPOL E
RCV
RCV E
JAB
JAB E
COL
COL E
18681A-28
Figure 24. LED Control Logic
H_RESET will RESET all of or some portions of CSR0,
3, 4, 15, 58, 80, 82, 100, 112, 114, 122, 124 and 126 to
default values. H_RESET will RESET all of or some portions of BCR 2, 4, 5, 6, 7, 18, 19, 20, 21 to default values.
H_RESET will reset the Command register in the PCI
configuration space. H_RESET will cause the
microcode program to jump to its RESET state. Following the end of the H_RESET operation, the Am79C974
controller will attempt to read the EEPROM device
through the EEPROM Microwire interface. H_RESET
resets the T-MAU into the link fail state.
S_RESET
S_RESET = SOFTWARE_RESET is an Ethernet controller RESET operation that has been created by a read
access to the RESET REGISTER which is located at offset 14hex from the Am79C974 I/O base address.
S_RESET will RESET all of or some portions of CSR0,
3, 4, 15, 80, 100 and 124 to default values. S_RESET
will not affect any of the BCR and PCI configuration
space locations. S_RESET will cause the microcode
program to jump to its RESET state. Following the end
of the S_RESET operation, the Am79C974 controller
will NOT attempt to read the EEPROM device.
S_RESET sets the T-MAU into the link fail state.
Note that S_RESET will not cause a deassertion of the
REQ signal, if it happens to be active at the time of the
read to the reset register. The REQ signal will remain
active until the GNT signal is asserted. Following the
read of the RESET register, on the next clock cycle after
the GNT signal is asserted, the Am79C974 controller
will deassert the REQ signal. No bus master accesses
will have been performed during this brief bus ownership period.
STOP
The diagram above shows the LED signal circuit that exists for each LED pin within the Am79C974 controller.
H_RESET, S_RESET, and STOP
There are three different types of RESET operations
that may be performed on the Am79C974 device,
H_RESET, S_RESET and STOP. These names have
been used throughout the document. The following is a
description of each type of RESET operation:
H_RESET
H_RESET= HARDWARE_RESET is a Am79C974 RESET operation that has been created by the proper assertion of the RST PIN of the Am79C974 device. When
the minimum pulse width timing as specified in the RST
74
pin description has been satisfied, then an internal RESET operation will be performed.
STOP is an Ethernet controller RESET operation that
has been created by the ASSERTION of the STOP bit in
CSR0. That is, a STOP RESET is generated by writing a
ONE to the STOP bit of CSR0 when the STOP bit currently has a value of ZERO. If the STOP bit value is currently a ONE and a ONE is rewritten to the STOP bit,
then NO STOP RESET will be generated.
STOP will RESET all or some portions of CSR0, 3, and 4
to default values. STOP will not affect any of the BCR
and PCI configuration space locations. STOP will cause
the microcode program to jump to its RESET state. Following the end of the STOP operation, the Am79C974
controller will NOT attempt to read the EEPROM device.
For the identity of individual CSRs and bit locations that
are affected by STOP, see the individual CSR register
descriptions. Setting the STOP bit does not affect
the T-MAU.
Am79C974
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SCSI Controller
The primary function of the PCnet-SCSI controller is to
transfer data between the 4 byte-wide PCI bus and 1
byte-wide SCSI bus. The controller consists of two
blocks: SCSI and DMA. The SCSI block sits between
the SCSI bus and the DMA block. It controls data flow
to/from SCSI bus. The DMA block is located between
the SCSI block and the PCI bus Interface Unit. It handles
data flow to/from PCI bus.
The operation of each block is governed by a set of control registers:
1. Channel Context Block (CCB) registers control the
DMA block
2. SCSI registers control the SCSI block
In a normal operation, both sets of registers must be programmed with the specifics of the transfer, such as starting address, transfer count, etc. (For more information,
refer to Technical Manual PID #18738A).
vides bus-mastering capabilities to allow flexibility and
performance advantages over slave PCI-SCSI devices.
Built into the engine is a 96-byte (24 DWORD) FIFO and
additional logic to handle the transition between the
32-bit PCI bus and the 8-bit SCSI bus.
Figure 25 illustrates the DMA Engine in relation to the
PCI interface and the SCSI block. As its most basic function, the DMA engine acts as the DMA controller in a bus
master capacity on the PCI bus, transferring data between memory and the SCSI block. All Command, Data,
Status, and Message bytes pass through the DMA FIFO
on their way to or from the SCSI bus. However, for programmed I/O (PIO) accesses to the SCSI registers, the
DMA FIFO is bypassed as data moves directly from the
SCSI block to the PCI interface. Since PIO operations
do not pass through the funneling logic and DMA FIFO,
data is transferred one byte at a time from the SCSI
block to the PCI interface via the least significant byte
lane. (The three most significant byte lanes will contain
null data.)
SCSI Specific DMA Engine
The SCSI Specific DMA Engine in the Am79C974 pro-
DMA
FIFO
(24x32)
32
Data
PCI^REQ
PCI^GNT
16
Data
SCSI
FIFO
(16x9)
Data
Funnel/Alignment
Logic
Empty
Full
PCI
Bus
Interface
Unit
32
DMA
CNTL
SCSI Block
DREQ
DMA
REG
DACK
DMA Engine
8 Data
AD (4:0)
PCI
Config
Space
C/BE(3:0)
SCSI REG
WR, RD,
AD(4:0), CS
AD(3:0)
CS
RD
Data
Path
Unit
WR
18681A-29
Figure 25. PCI BIU – DMA Engine – SCSI Block
Since the PCI bus is 4 bytes wide and the SCSI bus is
only 1 byte wide, funneling logic is included in this en-
gine to handle byte alignment and to ensure that data is
properly transferred between the SCSI bus and the
Am79C974
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wider PCI bus. All boundary conditions are handled
through hardware by the DMA Engine.
The DMA engine is also designed for block type (4
KByte page) transfers to support scatter-gather operations. Implementation of this feature is described further
in the DMA Scatter-Gather Mechanism section.
DMA FIFO
Data transfers from the SCSI FIFO to the DMA FIFO
take place each time the threshold of two bytes is
reached on the SCSI side. The transfer is initiated by the
SCSI block when the internal DREQ is asserted, and
continues with the DACK handshaking which typically
takes place in DMA accesses. Data is accumulated in
the DMA FIFO until a threshold of 16 DWORD (64 bytes)
is reached. Data is then burst across the PCI bus to
memory. Residue data which is less than the threshold
in each FIFO is sent in non-contiguous bursts. For memory read operations, data is sent in burst mode to the
DMA FIFO and continues through to the SCSI FIFO and
onto the SCSI bus.
DMA BLAST Command
This command is used to retrieve the contents of the
DMA FIFO when the Target disconnects during a DMA
Write operation. This could happen for example if a
SCSI disk drive detected the end of a sector and decided to give up the bus while it was looking for the next
sector. The Target Disconnect can leave some bytes of
data in the DMA FIFO and some in the SCSI FIFO, while
some bytes have yet to be transferred from the peripheral device. When this happens, the controller will assert
INTA to interrupt the processor, the SCSI state machine
will continue to empty its contents into the DMA FIFO,
but the DMA FIFO will not necessarily dump its contents
into memory (unless the 64-byte DMA threshold happens to have been exceeded at this time).
The BLAST command causes the contents of the DMA
FIFO to be emptied into memory. There are some restrictions on when this command should be used.
First, the command should be used only to recover
from an interrupted DMA write operation—not a
read operation.
Second, the command must not be issued until the
SCSI FIFO has finished dumping its contents into
the DMA FIFO.
Third, the command should never be issued when
the DMA FIFO has already been emptied. This is
indicated by the state of the DONE bit in the DMA
STATUS register at ((B)+54h).
(This is a test for a special case that can occur when a
Target Disconnect leaves only 1 byte left to be transferred from the SCSI peripheral. In this case, if the original transfer count was even, an odd number of bytes will
be left in the SCSI FIFO. Since the SCSI engine transfers data to the DMA FIFO two bytes at a time, the last
76
transfer consists of one byte of valid data and one byte
of garbage. The DMA engine treats this final invalid byte
as valid data and writes it to memory. When it does this,
it decrements its Working Byte Counter to zero and sets
the DONE bit, even though 1 byte still needs to be retrieved from the peripheral device.)
The following procedure outlines the use of the BLAST
command after an interrupt has occurred. Note that the
order of steps 2–4 is not critical. The order can be
changed to tune the performance. Also note that each
register is read only once in this procedure even though
several tests may be made on data from one register.
1. Verify that INT (bit 7 of the SCSI status register at
((B)+10h) is set to indicate that a SCSI interrupt is
pending.
2. Read the SCSI current FIFO count (bits 4:0 of the
Current FIFO/Internal State register at ((B)+1Ch).
If this value is not zero, wait for the SCSI FIFO to
empty its contents into the DMA FIFO.
3. If bit 4 of the SCSI status register (CTZ) is set,
stop here. The transfer is complete, and it is not
necessary to execute the BLAST command.
4. Verify that DIR (bit 7 of DMA command register at
((B)+40h) is set to one to indicate that the direction
of transfer is from SCSI to memory.
5. Test the error bits in the DMA status register and
the SCSI status register (STATREG at (B)+10h) to
verify that the contents of the DMA and SCSI
FIFOs are not invalid.
6. Test the DMA DONE bit in the DMA STATUS
register. If DONE is not set, write ‘01’ to the DMA
command register to issue the BLAST command.
This will move the remaining data from the DMA
FIFO into memory.
7. Wait until the BLAST complete (BCMPLT) in the
DMA STATUS register is set to indicate the completion of the BLAST operation.
8. Write ‘00’ to the DMA command register to issue
the IDLE command to the DMA engine. (Note
that the IDLE command does not generate an
interrupt.)
The above procedure insures that the data that has
been transferred from the SCSI peripheral does not get
lost in the DMA FIFO when a Target Disconnect occurs.
However, it does not complete the original transfer. The
software must now read the SCSI Current Transfer
Count register (CTCREG) to find out how many bytes
have yet to be transferred from the SCSI peripheral device and must start a new transfer operation to get the
rest of the data. (CTCREG consists of three bytes located at ((B)+00h, (B)+04h, and (B)+38h.)
Funneling Logic
Figure 26 shows the internal DMA logic interface with
the SCSI block. The DMA FIFO interfaces to the Funnel
Am79C974
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PRELIMINARY
Logic block via a 32-bit data bus, and the funnel logic
properly reduces this stream of data to a 16-bit stream to
32
96-Byte
DMA FIFO
properly interface with the SCSI FIFO.
Funnel
Logic
16
16-Byte
SCSI FIFO
18681A-30
Figure 26. DMA FIFO to SCSI FIFO Interface
SCSI DMA Programming Sequence
scatter-gather DMA operations:
The following section outlines the procedure for executing SCSI DMA operations:
1. Set up the MDL list
1. Issue IDLE command to the DMA Engine
2. Configure the SCSI block registers (e.g. synchronous operation, offset values, etc.)
3. Program the DMA registers to set up address and
transfer count
4. Issue a transfer command to the SCSI command
registers
5. Issue the START command to the DMA engine
6. At the end of the DMA transaction, issue the IDLE
command to the DMA engine
Memory Descriptor List (MDL) Based DMA
Programming
2. Use the programming sequence defined earlier for
initiating a SCSI DMA transfer
DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Configuration Base Address (B) and its corresponding offset
value. The Base address for the SCSI controller is
stored at register address (10h) in the SCSI PCI configuration space.
The following section outlines the use of the MDL for
Table 6. The DMA Registers
Register Acronym
Register Description
Type
CMD
Addr (Hex)
(B)+40
Command (bits 31:8 reserved, bits 7:0 used)
R/W
STC
(B)+44
Starting Transfer Count (bits 31:24 reserved, bits 23:0 used)
R/W
SPA
(B)+48
Starting Physical Address (bits 31:0 used)
R/W
WBC
(B)+4C
Working Byte Counter
R
WAC
(B)+50
Working Address Counter (bits 31:0 used)
R
STATUS
(B)+54
Status Register (bits 31:8 reserved, bits 7:0 used)
SMDLA
(B)+58
Starting Memory Descriptor List (MDL) Address
WMAC
(B)+5C
Working MDL Counter
Am79C974
R
R/W
R
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Command Register (CMD)
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Address (B)+40h, LSB
7
6
5
4
DIR
INTE_D
INTE_P
MDL
READ/WRITE
3
2
1
set, the ERROR or DONE condition will cause INTA to
be asserted.
INTE_P:
Page transfer active interrupt bit.
MDL:
0
Memory Descriptor List (MDL) SPA enable bit.
Reserved Reserved
CMD1
CMD0
RESERVED:
DIR:
Data transfer direction bit. When this bit is set, the direction of transfer is from SCSI to memory.
INTE_D:
DMA transfer active interrupt enable bit. When this bit is
Reserved for future expansion. The zero value must be
written in these bits.
CMD1-0:
These two bits are encoded to represent four commands: IDLE, BLAST, START, and ABORT.
CMD1
CMD0
Command
Description
0
0
IDLE
0
1
BLAST
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
1
0
ABORT
Terminates the current DMA transfer. Restores the DMA engine to the IDLE
state. Sets the ABORT bit (bit 2) in the status register.
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Note: This is only valid after a ‘START’ command is issued.
1
1
START
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note: This command should be issued only after all other
control bits have been initialized.
DMA Scatter-Gather Mechanism
The Am79C974 controller contains a scatter-gather
translation mechanism which facilitates faster data
transfers. This feature uses a Memory Descriptor List
which is stored in system memory. Use of the Memory
Descriptor List allows a single SCSI transfer to be read
from (or written to) non-contiguous physical memory locations. This mechanism avoids copying the transfer
data and MDL list, which was previously required for
conventional DMA operations.
assumes 4k page alignment and size for all MDL entries
except the first and last entry. This feature is enabled by
setting the MDL bit in the DMA Command register (Bit 4,
Address (B)+40h).
1. a) Prepare the Memory Descriptor List (MDL)
through software and store it in system
memory.
b) Load the address of the starting entry in the
Memory Descriptor List (MDL) into the Start
Memory Descriptor List Address (SMDLA)
register. This value is automatically copied into
the Working MDL Address Counter (WMAC).
Memory Descriptor List (MDL)
The MDL is a non-terminated (no End Of File marker)
list of 32-bit page frame addresses, which is always
aligned on a Double Word boundary. The format is
shown below:
31
12 11
Page Frame Address
0
Ignored
Note: The value in the SMDLA register must be double
word aligned. Therefore, read/write transactions will always begin on a double word boundary.
DMA Scatter-Gather Operation
(4k aligned elements)
The
78
scatter-gather
mechanism
described
c) Program the Starting Transfer Count (STC)
register with the total transfer length (i.e., # of
bytes). Also program the Starting Physical
Address (SPA) register (bits 11:0) with the
starting offset of the first entry.
below
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31
0
SMDLA
31
MDL
31
12
0
Page Frame Address #1
Ignored
Page Frame Address #2
Ignored
0
WMAC
Page Frame Address #3
Page Frame Address #4
Ignored
Ignored
Page Frame Address #n
Ignored
18681A/1-31
In this example, the contents of the WMAC register is
pointing to page frame address #1. When the first entry
in the MDL is read (page frame address #1), the WMAC
register is incremented to point to the next page entry
(page frame address #2).
the MDL entry and combines it with the first page
offset value in the Starting Physical Address (SPA)
register (bits 11:0). This 32-bit value is loaded into
the Working Address Counter (WAC) register and
becomes the physical address for page#1, as
shown below. The WMAC is then incremented to
point to the next entry in the MDL.
2. Issue the Start DMA Command. The SCSI controller reads the page frame address (bits 31:12) from
Programmed by
the software
31
SPA
12
XXXX
0
Starting Offset
From the MDL
31
WAC
4K Page #1
12
Page Frame Address #1
0
Starting Offset
Data
18681A/1-32
3. When the WAC register (bits 11:0) reaches the
first 4K byte boundary, the SCSI controller reads
the second MDL entry and combines the page
frame address (bits 31:12) from this entry of the
MDL with bits 11:00 of the WAC register. This becomes the physical address for page#2. Since the
WAC register (bits 11:0) has rolled over to ‘00h’,
the WAC now points to the beginning of the Page
Frame Address #2 as shown below. The WMAC
is then incremented to point to the next entry in
the MDL.
From the MDL
31
WAC
12
Page Frame Address #2
0
4K Page #2
0
Data
18681A/1-33
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When WAC (bits 11:0) again reaches the next 4K byte
boundary, the next MDL entry is read into the WAC. The
operation continues in this way until WMAC register
reaches the last MDL entry (Page Frame Address #n in
this example).
page and the DMA operation continues until the
byte count is exhausted in the Working Byte
Counter (WBC) register. When WBC=0, the chip
stops incrementing the WAC register. This is
shown below.
4. The WAC register points to the beginning of the last
From the MDL
31
WAC
12
0
4K Page #n
0
Page Frame Address #n
Data
WBC = 0
18681A/1-34
DMA Scatter-Gather Operation
(Non-4k aligned elements MDL not set)
There is another way to implement a scatter-gather operation which does not force the data elements to be
aligned on 4k boundaries. It assumes a “traditional”
scatter-gather list of the following format:
Element 0
Physical Address Byte Count
Element 1
Physical Address Byte Count
...
Element n
Physical Address Byte Count
This second implementation is described as follows:
1. Set the SCSI Start Transfer Count Register
((B)+00h, (B)+04h, (B)+38h) to the Byte count of
the first Scatter-Gather element.
8. Reprogram the DMA Starting Physical Address
Register ((B)+48h) to the Physical Address of the
next Scatter-Gather element.
9. Repeat steps 4–8 until the Scatter-Gather list is
completed.
Interrupts
Interrupts may come from two sources: the DMA engine
or the SCSI block. Upon receipt of an interrupt (INTA asserted), the DMA Status register should be serviced first
to identify the interrupt source(s). DMA engine related
interrupts are cleared when the related flags are read in
the DMA Status register. However, SCSI block interrupts will be cleared only when the SCSI Status, Internal
State, and Interrupt Status Registers are read.
Interrupts are caused by:
2. Program the DMA Starting Transfer Count Register ((B)+44h) to the Byte Count of the first ScatterGather element.
Successful completion of a DMA transfer request.
(Bit 6 in the DMA Command Register ((B+40h)
must be set to enable this interrupt)
3. Program the DMA Starting Physical Address Register ((B)+48h) to the Physical Address of the first
Scatter-Gather element.
An address error occurred on the PCI bus during a
DMA transfer (Bit 6 in the DMA Command Register ((B)+40h) must be set to enable this interrupt)
4. Start the SCSI operation by issuing a SCSI Information Transfer command.
The PWDN pin is first asserted
After completion of each page transfer during MDL
operations. (Bit 5 in the DMA Command Register
((B)+40h) must be set to enable this interrupt)
5. Start the DMA Engine with DMA Transfer Interrupt
Enable (Bit 6, (B)+40h).
6. When the Scatter-Gather element’s Byte Count
is exhausted, the DMA engine will generate an
interrupt.
7. Reprogram the next Scatter-Gather element’s Byte
Count into the SCSI Start Transfer Count Register
and the DMA Starting Transfer Count Register.
80
An interrupt from the SCSI block will automatically set
bit 4 (SCSIINT) in the DMA Status register (Address
(B)+54h). The SCSI block will generate an interrupt under the following conditions:
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Illegal command code issued
The target must be able to sustain Fast SCSI
timings.
The target disconnects from the SCSI bus
Bits 3 (FASTCLK) and 4 (FASTSCSI) in Control
Register Three must be set to ‘1.’
SCSI bus service request
Successful completion of a command
The lower three bits of Register ((B)+24h), the
Clock Conversion Factor Register must be
programmed to ‘000.’
The Am79C974 has been reselected
The Fast SCSI Block
The lower 5 bits of the Synchronous Transfer
Period Register ((B)+18h) must be set to a value
of ‘04h.’
The functionality of the SCSI block is described in the
following section. Topics to be covered are:
SCSI Block ID
The FASTCLK and FASTSCSI bits in Control Register
Three modify the SCSI state machine to produce both
FAST and Normal SCSI timings. Synchronous data
transmission rates are dependent on the input clock frequency selected, as well as the transfer period.
SCSI FIFO Threshold
Data Transmission
REQ/ACK Control
Parity
Reset Levels
SCSI Block ID
The Am79C974 contains a SCSI Block ID code which is
stored in the MSB of the Current Transfer Count Register. The code reflects the chip’s revision level and family
code. This 8-bit code may be read when the following
conditions are true.
After power up or a chip reset has occurred
Before the Current Transfer Counter ((B)+38h) is
loaded
The part-unique ID code in Register ((B)+38h) will read
as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
1
0
SCSI FIFO Threshold
The threshold value for the SCSI FIFO is two bytes (one
word). When this threshold is reached, the SCSI block
will indicate to the DMA engine that it is capable of receiving or sending data bytes.
Data Transmission
Data transmission rates will vary from system to system,
depending on the number of devices configured on the
SCSI bus, as well as the transfer rates that each individual device is capable of sustaining.
Transfer rates for the Am79C974 are controlled by the
FASTSCSI and FASTCLK bits in Control Register
Three, as well by the Extended Timing Feature in Control Register One.
Bits 4:0 in the Synchronous Transfer Period Register
((B)+18h) specify the period for synchronous data transfers. For programming information, refer to the Technical Manual.
REQ/ACK Control
The assertion and deassertion time for the REQ and
ACK signals may be controlled via the Synchronous Offset Register ((B)+1Ch). Bits 7:6 control REQ/ACK
deassertion delay with respect to the time that data is
valid, while bits 5:4 control REQ/ACK assertion delay.
The deassertion for REQ/ACK may be moved ahead .5
clock cycles, or it may be delayed for up to 1.5 clock cycles. Deassertion delay options depend on the status of
the FASTCLK bit in Control Register Three. Assertion
delay for REQ/ACK can vary from 0 to 1.5 clock cycles.
Parity
Parity on the SCSI bus is such that the total number of
logical ones on data bus including the parity bit must be
odd. Parity checking features are implemented via two
bits in the Status Register and Control Register One.
Parity checking can be implemented on data flowing in
from the SCSI bus. Parity is always generated internally
by the Am79C974 for data moving onto the SCSI bus.
Feature
Bit Name
Bit #
Register
Parity From
SCSI
Parity Error
Reporting
4
Control
Reg One
((B)+20h)
Parity Status
Parity Error
5
Status
Register
((B)+10h)
Parity Checking on the SCSI Bus
To achieve 10 Mbyte/s transmission rates, the following
conditions must be true:
A 40 MHz clock (50% duty cycle) must be supplied
to SCSICLK.
The Parity Error Reporting Bit (Bit 4, Control Register
One) enables parity checking on all incoming bytes from
the SCSI bus. This feature is cleared to ‘0’ by a hardware
reset.
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When this feature is enabled, the Am79C974 will check
parity on all data received from the SCSI bus. Any detected error will be flagged by setting bit 5 in the SCSI
Status Register, and ATN will be asserted on the SCSI
bus. However, no interrupt will be generated.
chines. It leaves the SCSI block in the disconnected
state. It leaves all SCSI registers in their default states.
In addition, if the Hard Reset is caused by the assertion
of the RST pin, the following actions occur:
The Command register in the PCI configuration
space is cleared to zero. (No other register in the
configuration space is affected.)
When this feature is disabled (bit 4 set to ‘0’), no parity
check is done on incoming bytes. Note that the parity on
the PCI bus is generated internally and is distinct from
the parity received from the SCSI bus.
The DMA CCB registers are set to their default
values.
Parity Generating on the SCSI Bus
For each byte transferred to the SCSI bus, parity generation is done automatically.
Reset Levels
The Am79C794 has two reset pins and two reset commands that affect the SCSI block. The RST pin resets
the whole chip including the SCSI controller, the Ethernet controller, and the PCI interface.
The Reset Device command causes almost the same
effect on the SCSI controller that the RST pin does.
However, the Reset Device command has no effect on
the Ethernet controller or the PCI interface. Also, after
the Reset Device command has been issued, the user
must issue a NOP command before another command
can be executed.
The action of the RST signal or the Reset Device command is called Hard Reset.
The SCSI^RST pin is a bidirectional signal on the SCSI
bus that resets a portion of the SCSI logic when it is asserted by a device on the SCSI bus. Similarly the
Am79C794 can assert the SCSI^RST signal to cause all
of the other devices on the SCSI bus to reset.
The Reset SCSI command causes the same effect on
the SCSI controller that the SCSI^RST pin does, except
that this command also causes the SCSI^RST pin to be
asserted so that all other (external) devices on the SCSI
bus are also reset. Once a SCSI Reset command has
been executed, the SCSI^RST signal will remain asserted until a Hard Reset has occurred.
The action of the SCSI^RST signal and the Reset SCSI
command is called Soft Reset.
In addition there is a third type of reset, called Disconnected Reset, that is caused by certain sequences on
the SCSI bus. These three types of reset are described
in the following sections.
Hard Resets: (H)
This reset occurs at power up, when the RST pin is asserted through external hardware, or when the Reset
Device command is issued by writing 02h to the SCSI
command register at ((B)+0Ch). Hard reset causes all
chip functions to halt and resets all internal state ma82
Soft Reset: (S)
This reset occurs either when the SCSI^RST pin on the
SCSI bus is asserted or when the Reset SCSI Bus command is issued (by writing 03h to the SCSI command
register at ((B) = 0ch)).
Soft reset causes the following actions to occur:
All SCSI bus signals except SCSI^RST are
released.
The chip is returned to the Disconnected state.
An interrupt is generated if bit 6 in Control Register
One is enabled.
Disconnected Reset: (D)
Disconnected reset occurs when either of the following
conditions occur:
The Am79C974 is the Initiator and the SCSI bus
moves to a Bus Free state
The Selection command terminates due to
selection time-out
Disconnected reset causes the following actions:
All SCSI signals except SCSI^RST are deasserted.
The SCSI Command Register is initialized to
empty.
The IS1 and IS0 bits in the Internal State Register,
((B)+18h), are cleared to 0.
Please refer to the Technical Manual (PID #18738A) for
the default values for all registers.
Device Commands
The device commands can be broadly divided into two
categories, DMA commands and non-DMA commands.
DMA commands are those which cause data movement
between the host memory and the SCSI bus while nonDMA commands are those that cause data movement
between the SCSI FIFO and the SCSI bus. The Most
Significant Bit of the command byte differentiates the
DMA from the non-DMA commands.
When a DMA command is issued, the contents of the
Start Transfer Count Register will be loaded into the
Current Transfer Count Register. Data transmission will
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continue until the Current Transfer Count Register decrements to zero.
Non-DMA commands do not modify the Current Transfer Count Register and are unaffected by the value in the
Current Transfer Count Register. For non-DMA commands, the number of bytes transmitted depends solely
on the operation in progress.
When non-DMA commands are used, the host computer must use programmed I/O to transfer the data between the SCSI FIFO and the host memory.
AMD
multiple interrupts can occur when commands are
stacked, it is recommended that the ENF bit in Control
Register Two (Bit 6) be set in order to latch the SCSI
phase bits in the SCSI Status Register ((B)+10h) at the
completion of a command. This allows the host to determine the phase of the interrupting command without
having to consider phase changes that occurred after
the stacked command began execution.
Note: Command stacking should only be used during
SCSI Data In or Data Out transfers.
Invalid Commands
Table 7. Summary of Commands
Code
(Hex.)
Command
NonDMA
Mode
DMA
Mode
Information Transfer
10
90
Initiator Command Complete Steps
11
91
Message Accepted
12
–
Transfer Pad Bytes
–
98
Set ATN*
1A
–
Reset ATN*
1B
–
Initiator Commands
When an illegal command is written to the Am79C974,
the Invalid Command Bit (Bit 6, Register (B)+14h) will be
set to ‘1’, and an interrupt will be generated to the host.
When this happens, the interrupt must be serviced before another command may be written to the Command
Register.
An Invalid command is defined as a command written to
the Am79C974 that is either not supported, not allowed
in the specified mode, or a command that has an unsupported command mode.
The following conditions will also cause an Invalid Command interrupt to occur:
An Initiator Information Transfer, Transfer Pad, or
Command Complete is issued when ACK is still
asserted.
Idle State Commands
Select without ATN Steps
41
C1
Select with ATN Steps
42
C2
Select with ATN and Stop Steps
43
C3
Enable Selection/Reselection*
44
C4
Disable Selection/Reselection
45
–
Select with ATN3 Steps
46
C6
No Operation*
00
80
Clear FIFO*
01
–
Reset Device*
02
–
Reset SCSI Bus**
03
–
A Selection command is issued with the DMA bit
enabled, if the Selection command was previously
issued with the DMA enabled.
Command Window
The window at the point where the Disable Selection/
Reselection command (45h/C5h) has been loaded into
the Command Register ((B)+0Ch), and before bus-initiated Selection begins, has been eliminated. This prevents a false Successful Operation Interrupt from being
generated when the Selection sequence continues to
completion after the Disable command has been
loaded.
General Commands
Notes:
* These commands do not generate interrupt.
Initiator Commands
** An interrupt is generated when SCSI bus reset interrupt
reporting is not disabled (see Control Register1/DISR
bit6).
Command Stacking
Initiator commands are executed by the device when it
is in the Initiator mode. If the device is not in the Initiator
mode and an Initiator command is received the device
will ignore the command, generate an Invalid Command
interrupt and clear the Command Register.
The microprocessor may stack commands in the Command Register ((B)+0Ch) since it functions as a twobyte deep FIFO. Non-DMA commands may not be
stacked, and commands which transfer data in opposing directions should not be stacked together; otherwise, the results are unpredictable.
Should the Target disconnect from the SCSI bus by
deasserting the BSY signal line while the Am79C974
(Initiator) is waiting for the Target to assert REQ, a Disconnected Interrupt will be issued 1.5 to 3.5 clock cycles
following BSY going false.
If DMA commands are queued together, the Start
Transfer Count must be written before the associated
command is loaded into the Command Register. Since
Upon receipt of the last byte during Message In phase,
ACK will remain asserted to prevent the Target from issuing any additional bytes, while the Initiator decides to
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is cleared and the DMA interface is disabled to
prevent any transfer of data (phase) bytes.
accept/reject the message. If non-DMA commands are
used, the last byte signals the SCSI FIFO is empty. If
DMA commands are used, the Current Transfer Count
signals the last byte.
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in,
it is not reported since the Status Register will report the status of the command just completed.
The parity error flag and the ATN signal will be
asserted when the next Information Transfer command begins execution.
A Reset SCSI Bus command (03h/83h) will force the
Am79C974 to abort the current operation and disconnect from the bus. If the DISR bit is reset (Bit 6, Control
Register One (B)+20h)), the host processor will be interrupted with a SCSI Reset Interrupt before the
Am79C974 proceeds to Disconnect.
Message Out/Command Phase – When a phase
change to Synchronous Data-In or Synchronous
Data-Out is detected by the device, the Command
Register is cleared and the DMA interface is disabled to prevent any transfer of data (phase)
bytes.
If parity checking is enabled in the Initiator mode during
the Data-in phase and an error is detected, ATN will be
asserted for the erroneous byte before deasserting
ACK.
Information Transfer Command
(Command Code 10h/90h)
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in,
it is not reported since the Status Register will report the status of the command just completed.
The parity error flag and the ATN signal will be asserted when the next Information Transfer command begins execution.
The Information Transfer command is used to transfer
information bytes over the SCSI bus. This command
may be issued during any SCSI Information Transfer
phase. Synchronous data transmission requires use of
the DMA mode.
The Target changes the SCSI bus phase before
the expected number of bytes are transferred. The
Am79C974 clears the Command Register
(CMDREG), and generates a Service Request
interrupt when the Target asserts REQ.
The SCSI FIFO Register will be latched and will
remain in that condition until the next command
begins execution. The value in the SCSI FIFO
Register indicates the number of non-data bytes in
the SCSI FIFO when the phase changed to Synchronous Data-In. These bytes are cleared from
the FIFO, and only incoming data bytes are retained.
Transfer has successfully completed. If the phase
is Message Out, the Am79C974 deasserts ATN
before asserting ACK for the last byte of the message. When the Target asserts REQ, a Service
Request interrupt is generated.
In the Synchronous Data-Out phase, the threshold
counter is incremented as REQ pulses are received. The transfer is completed when the FIFO is
empty and the Current Transfer Count Register is
‘0’. The threshold counter will not be ‘0’.
In the Message In phase when the device receives
the last byte. The Am79C974 keeps the ACK signal asserted and generates a Successful Operation interrupt.
In the Synchronous Data-In phase, the Current
Transfer Count Register is decremented as bytes
are read from the SCSI FIFO rather than when the
bytes are being written to the SCSI FIFO. The
transfer is completed when Current Transfer Count
Register is ‘0’. However, the SCSI FIFO may not
be empty.
The device will continue to transfer information until it is
terminated by any one of the following conditions:
During Synchronous Data transfers the Target may
send up to the maximum synchronous offset number of
REQ pulses to the Initiator. If it is the Synchronous DataIn phase then the Target sends the data and the REQ
pulses. These bytes are stored by the Initiator in the
FIFO as they are received.
The Information Transfer Command, when issued during the following SCSI phases and terminated in Synchronous Data phases, is handled as described below:
Message In/Status Phase – When a phase change
to Synchronous Data-In or Synchronous Data-Out
is detected by the device, the Command Register
84
Initiator Command Complete Steps
(Command Code 11h/91h)
The Initiator Command Complete Steps command is
normally issued when the SCSI bus is in the Status In
phase. One Status byte followed by one Message byte
is transferred if this command completes normally. After
receiving the message byte the device will keep the
ACK signal asserted to allow the Initiator to examine the
message and assert the ATN signal if it is unacceptable.
The command terminates early if the Target does not
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switch to the Message In phase or if the Target disconnects from the SCSI bus. This command does not utilize
the Internal State Register ((B)+18h).
Message Accepted Command
(Command Code 12h)
The Message Accepted Command is used to release
the ACK signal. This command is normally used to complete a Message In handshake. Upon execution of this
command the device generates a Service Request interrupt after REQ is asserted by the Target.
After the device has received the last byte of message, it
keeps the ACK signal asserted. This allows the device
to either accept or reject the message. To accept the
message, Message Accepted Command is issued. To
reject the message the ATN signal must be asserted
(with the help of the Set ATN Command) before issuing
the Message Accepted Command. In either case, the
Message Accepted Command has to be issued to release the ACK signal.
Transfer Pad Bytes Command
(Command Code 18h/98h)
The Transfer Pad Bytes Command is used to recover
from an error condition. This command is similar to the
Information Transfer Command, only the information
bytes consists of null data. It is used when the Target expects more data bytes than the Initiator has to send. It is
also used when the Initiator receives more information
than expected from the Target.
When sending data to the SCSI bus, the SCSI FIFO is
loaded with null bytes which are sent out to the SCSI
bus. Although an actual DMA request is not made, DMA
interface must be enabled when pad bytes are transmitted since the Am79C974 uses the Current Transfer
Count Register to terminate transmission.
This command terminates under the same conditions as
the Information Transfer Command, but the device does
not keep the ACK signal asserted during the last byte of
the Message In phase. Should this command terminate
prematurely due to a Disconnect or a phase change before the Current Transfer Count Register decrements to
zero, the SCSI FIFO may contain residual Pad bytes.
Set ATN Command
(Command Code 1Ah)
The Set ATN Command is used to drive the ATN signal
active on the SCSI bus. An interrupt is not generated at
the end of this command. The ATN signal is deasserted
before asserting the ACK signal during the last byte of
the Message Out phase.
Note: The ATN signal is asserted by the device without
this command in the following cases:
If any select with ATN command is issued and the
arbitration is won.
An Initiator needs the Target’s attention to send a
AMD
message. The ATN signal is asserted before
deasserting the ACK signal.
Reset ATN Command
(Command Code 1Bh)
The Reset ATN Command is used to deassert the ATN
signal on the SCSI bus. An interrupt is not generated at
the end of this command. This command is used only
when interfacing with devices that do not support the
Common Command Set (CCS). These older devices do
not deassert their ATN signal automatically on the last
byte of the Message Out phase. This device does deassert its ATN signal automatically on the last byte of the
Message Out phase.
Idle State Commands
The Idle State Commands can be issued to the device
only when the device is disconnected from the SCSI
bus. If these commands are issued to the device when it
is logically connected to the SCSI bus, the commands
are ignored, an Invalid Command interrupt is generated,
and the Command Register (CMDREG) is cleared.
Select Without ATN Steps Command
(Command Code 41h/C1h)
The Select without ATN Steps Command is used by the
Initiator to select a Target. When this command is issued, the device arbitrates for the control of the SCSI
bus. When the device wins arbitration, it selects the Target device and transfers the Command Descriptor Block
(CDB). Before issuing this command the SCSI Timeout
Register (STIMREG), Control Register One
(CNTLREG1), and the SCSI Destination ID Register
(SDIDREG) must be set to the proper values. If DMA is
enabled, the Start Transfer Count Register (STCREG)
must be set to the total length of the command. If DMA is
not enabled, the data must be loaded into the FIFO before issuing this command. This command will be terminated early if the SCSI Timeout Register times out, if the
Target does not go to the Command Phase following the
Selection Phase, or if the Target exits the Command
Phase prematurely. A Successful Operation interrupt
will be generated following normal command execution.
Select With ATN Steps Command
(Command Code 42h/C2h)
The Select with ATN Steps Command is used by the Initiator to select a Target. When this command is issued,
the device arbitrates for the control of the SCSI bus.
When the device wins arbitration, it selects the Target
device with the ATN signal asserted and transfers the
Command Descriptor Block (CDB) and a one byte message. Before issuing this command the SCSI Timeout
Register (STIMREG), Control Register One
(CNTLREG1) and the SCSI Destination ID Register
(SDIDREG) must be set to the proper values. If DMA is
enabled, the Start Transfer Count Register (STCREG)
must be set to the total length of the command and message. If DMA is not enabled, the data must be loaded
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AMD
PRELIMINARY
into the FIFO before issuing this command. This command will be terminated early in the following situations:
The SCSI Timeout Register times out
The Target does not go to the Message Out Phase
following the Selection Phase
The Target exits the Message Phase early
The Target does not go to the Command Phase
following the Message Out Phase
The Target exits the Command Phase early
A Successful Operation/Service Request interrupt is
generated when this command is completed
successfully.
Select With ATN and Stop Steps Command
(Command Code 43h/C3h)
The Select with ATN and Stop Steps Command is used
by the Initiator to send messages with lengths other than
1 or 3 bytes. When this command is issued, the device
executes the Selection process, transfers the first message byte, then STOPS the sequence. ATN is not deasserted at this time, allowing the Initiator to send
additional message bytes after the ID message. To
send these additional bytes, the Initiator must write the
transfer counter with the number of bytes which will follow, then issue a Transfer Information Command.
(Note: the Target is still in the Message Out phase when
this command is issued). ATN will remain asserted until
the Current Transfer Count Register decrements
to zero.
Reselection. When this command is issued before a
bus-initiated Selection or Reselection is in progress, it
resets the internal state bits previously set by the Enable
Selection/Reselection Command. The device also generates a Successful Operation interrupt to the processor. If however, this command is issued after a
bus-initiated Selection/Reselection has begun, this
command and all incoming commands are ignored
since the Command Register (CMDREG) is held reset.
The Am79C974 also generates a Selected or
Reselected interrupt when the sequence is complete.
Select With ATN3 Steps Command
(Command Code 46h/C6h)
The Select with ATN3 Steps Command is used by the
Initiator to select a Target. This command is similar to
the Select with ATN Steps Command, except that it
sends exactly three message bytes. When this command is issued the Am79C974 arbitrates for control of
the SCSI bus. When the device wins arbitration, it selects the Target device with the ATN signal asserted and
transfers the Command Descriptor Block (CDB) and
three message bytes. Before issuing this command the
SCSI Timeout Register (STIMREG), Control Register
One (CNTLREG1), and the SCSI Destination ID Register (SDIDREG) must be set to the proper values. If DMA
is enabled, the Start Transfer Count Register
(STCREG) must be set to the total length of the command. If DMA is not enabled, the data must be loaded
into the FIFO before issuing this command. This command will be terminated early in the following situations:
The SCSI Timeout Register (STIMREG), Control Register One (CNTLREG1), and the SCSI Destination ID
Register (SDIDREG) must be set to the proper values
before the Initiator issues this command. This command
will be terminated early if the STIMREG times out or if
the Target does not go to the Message Out Phase following the Selection Phase.
Enable Selection/Reselection Command
(Command Code 44H/C4H)
The Target does not go to the Message Out Phase
following the Selection Phase
The Target removes Command Phase early
The Target does not go to the Command Phase
following the Message Out Phase
The Target exits the Command Out Phase early
The Enable Selection/Reselection Command is used to
respond to a bus-initiated Selection or Reselection.
Upon disconnecting from the bus the Selection/
Reselection circuit is automatically disabled by the device. This circuit must be enabled for the Am79C974 to
respond to subsequent reselection attempts and the Enable Selection/Reselection Command is issued to do
that. This command is normally issued within 250 ms
(select/reselect timeout) after the device disconnects
from the bus. If DMA is enabled, the device loads the
received data to the buffer memory. If the DMA is disabled, the received data stays in the FIFO.
Disable Selection/Reselection Command
(Command Code 45H)
The Disable Selection/Reselection Command is used
by the Target to disable response to a bus-initiated
86
The SCSI Timeout Register times out
A Successful Operation/Service Request interrupt is
generated when this command is executed
successfully.
General Commands
No Operation Command
(Command Code 00h/80h)
The No Operation Command administers no operation,
therefore an interrupt is not generated upon completion.
This command is issued following the Reset Device
Command to clear the Command Register (CMDREG).
A No Operation Command in the DMA mode may be
used to verify the contents of the Start Transfer Count
Register (STCREG). After the STCREG is loaded with
the transfer count and a DMA No Operation Command
is issued, reading the Current Transfer Count Register
(CTCREG) returns the transfer count value.
Am79C974
PRELIMINARY
Clear FIFO Command
(Command Code 01h)
The Clear FIFO Command is used to initialize the SCSI
FIFO to the empty condition. The Current FIFO Register
(CFISREG) reflects the empty FIFO status and the bottom of the FIFO is set to zero. No interrupt is generated
at the end of this command.
Reset Device Command
(Command Code 02h)
The Reset Device Command immediately stops any device operation and resets all the functions of the device.
Additionally, it returns the device to the disconnected
state and it generates a hard reset. The Reset Device
Command remains on the top of the Command Register
FIFO holding the device in the reset state until the No
Operation Command is loaded. Once loaded, the No
Operation command serves to re-enable the Command
Register.
Reset SCSI Bus Command
(Command Code 03h)
The Reset SCSI Bus Command forces the SCSI^RST
signal active for a period of 25 ms, and drives the chip to
the Disconnected state. An interrupt is not generated
upon command completion, however, if bit 6 is set to ‘0’
in Control Register One (CNTLREG1), a SCSI Reset interrupt will be issued.
SCSI Power Management Features
As a leader in low-voltage technology, AMD has incorporated power-saving features into the Am79C974.
Through hardware and software, the Am79C974 can be
powered down to reduce consumption during chip
inactivity.
AMD
ered down by turning off the input buffers on the SCSI
Bus lines (set bit 5 in Control Register Four (B)+34h).
For further power reduction, the internal registers may
be programmed to a predetermined state, and the input
clock disconnected via external logic.
Power Down Pin (PWDN Pin)
When PWDN is driven active, it sets the PWDN bit in the
Status Register (Bit 0, DMA Status Register (B)+54h),
signaling the Am79C974 that the host would like to
power down the SCSI interface. An interrupt is generated when this bit is first set.
Software Disk Spin-Down
Incorporated into the SCSI ROM BIOS and certain device driver’s of AMD’s software solution is a module
which physically spins down SCSI fixed disks when the
host system elects to enact power management on the
SCSI system. The software module is activated upon
the ROM BIOS and/or other device driver’s receipt of an
interrupt caused by the PWDN pin being driven active.
Upon receipt of this interrupt, the current software process is suspended and software control is given to the
power management module.
When the power management module is activated, it
checks the status of all SCSI fixed disks on the system
under its control. The SCSI fixed disks that are idle are
issued a command to spin down their media. All fixed
disks that are active at the time will be scheduled for spin
down upon completion of their pending commands.
Once the BIOS and/or drivers have detected the completion of each fixed disk’s final pending commands,
they are issued the command to spin down as well.
Reduced Power Mode
To spin down the disk drives, the power management
module issues a SCSI command (1B– Start/Stop unit).
When the command is received by the drive, it spins
down and waits in an idle state. For multiple drives on
the SCSI bus, the power management driver spins
down each drive individually. The drives remain in the
idle state until the BIOS and/or driver receives a command for the particular fixed disk. Once this occurs, the
drive is issued the command to spin up. When the drive
has completely spun up and is ready, the pending command is issued to the drive. Only the particular fixed disk
issued the command is instructed to spin up. All other
drives will remain in the spun down state until a command is issued to them.
When there is no activity on the SCSI Bus, and there are
no pending commands, the Am79C974 may be pow-
Note: This sequence does not turn off the input buffers
as described in the previous section.
SCSI Activity Pin
The SCSI Bus activity is reflected by the BUSY output
line. This signal, when active, indicates that the SCSI
Bus is in use, therefore the Am79C974 should not be
powered down. This signal is the logical equivalent to
the SCSI bus signal BSY, however, it is not physically
connected to the BSY signal on the bus. To correctly
identify the Bus Free State on the SCSI bus, this BUSY
output line must be inactive for at least 250 ms (Selection Timeout period).
Am79C974
87
AMD
PRELIMINARY
NAND Tree Testing
The Am79C974 controller provides a NAND tree test
mode to allow checking connectivity to the device on a
printed circuit board. The NAND tree is built on all PCI
bus signals (see Figure 27 and Table 8).
The NAND tree testing is enabled by asserting RST. All
PCI bus signals will become inputs when RST is asserted. The result of the NAND tree test can be observed on the BUSY pin.
+5 V
RST
(pin 120)
INTA
(pin 117)
INTB
(pin 118)
CLK
(pin 121)
PCnet-SCSI
Core
AD2
(pin 54)
AD1
(pin 56)
AD0
(pin 57)
BUSY
PWDN
(pin 58)
MUX
B
O
A S
BUSY
(pin 62)
18681A-35
Figure 27. Am79C974 NAND Tree Test Structure
88
Am79C974
AMD
PRELIMINARY
As shown in Figure 27, Pin 120 (RST) is the first input to
the NAND tree. Pin 117 (INTA) is the second input to the
NAND tree, followed by pin 118 (INTB). All other PCI
bus signals follow, counterclockwise, with pin 58
(PWDN) being the last. Ethernet and SCSI specific pins
and all power supply pins are not part of the NAND tree.
Table 8 shows the complete list of pins connected to the
NAND tree.
Table 8. NAND Tree Configuration
NAND
Tree
Input #
Pin #
Name
NAND
Tree
Input #
Pin #
Name
NAND
Tree
Input #
Pin #
Name
1
120
RST
20
12
AD23
39
36
AD15
2
117
INTA
21
13
AD22
40
38
AD14
3
118
INTB
22
15
AD21
41
39
AD13
4
121
CLK
23
16
AD20
42
40
AD12
5
123
GNTB
24
18
AD19
43
41
AD11
6
124
GNTA
25
19
AD18
44
42
AD10
AD9
7
126
REQB
26
21
AD17
45
44
8
127
REQA
27
22
AD16
46
45
AD8
9
128
AD31
28
23
C/BE2
47
47
C/BE0
10
129
AD30
29
24
FRAME
48
48
AD7
11
131
AD29
30
25
IRDY
49
49
AD6
12
132
AD28
31
26
TRDY
50
51
AD5
13
2
AD27
32
27
DEVSEL
51
52
AD4
14
3
AD26
33
28
STOP
52
53
AD3
15
5
AD25
34
29
LOCK
53
54
AD2
16
6
AD24
35
31
PERR
54
56
AD1
17
7
C/BE3
36
32
SERR
55
57
AD0
18
9
IDSELA
37
34
PAR
56
58
PWDN
19
10
IDSELB
38
35
C/BE1
Am79C974
89
AMD
PRELIMINARY
RST must be asserted low to start a NAND tree test sequence. Initially, all NAND tree inputs except RST
should be driven high. This will result in a high output at
the BUSY pin. If the NAND tree inputs are driven low in
the same order as they are connected to build the NAND
tree, BUSY will toggle every time an additional input is
driven low. BUSY will change to a ZERO, when INTA is
driven low and all other NAND tree inputs stay high.
BUSY will toggle back to high, when CLK is additionally
driven low. BUSY will continue toggling as long as the
NAND tree inputs are toggling in the sequence shown in
Figure 28. BUSY will be high, when all NAND tree inputs
are driven low.
When testing is complete, deassert RST to exit this test
mode.
Note that some of the pins connected to the NAND tree
are outputs in normal mode of operation. They must not
be driven from an external source until the PCnet-SCSI
controller is configured for NAND tree testing.
RST
INTA
INTB
CLK
GNTB
GNTA
REQB
REQA
AD[31:0]
C/BE[3:0]
0000FFFF
FFFFFFFF
F
3
7
1
IDSELA
IDSELB
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
PERR
SERR
PAR
PWDN
BUSY
18681A-36
Figure 28. NAND Tree Waveform
90
Am79C974
AMD
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltages
(AVDD, VDD, VDDB, VDDBS, DVDD) . . . . . . . . . +5 V ± 5%
All Inputs within the Range:
AVSS – 0.5 V ≤ VIN ≤ AVDD + 0.5 V,
or VSS – 0.5 V ≤ VIN ≤ VDD + 0.5 V,
or VSSB – 0.5 V ≤ VIN ≤ VDDB + 0.5 V
or VSSBS – 0.5 V ≤ VIN ≤ VDDBS + 0.5 V
or DVSS – 0.5 V ≤ VIN ≤ DVDD + 0.5 V
Ambient Temperature
Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage to AVSS or VSSB or VSSBS or DVSS
(AVDD, VDD, VDDB, VDDBS, DVDD) . . . –0.3 V to +6.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified
PCI and Board Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
0.8
V
Digital Input Voltage
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
2.0
V
Digital Output Voltage
VOL
Output LOW Voltage
IOL1 = 3 mA
0.55
V
0.4
V
IOL2 = 6 mA
IOL3 = 12 mA
(Note 1)
VOH
Output HIGH Voltage (Note 2)
IOH = –2 mA (Note 5)
2.4
V
Digital Input Leakage Current
IIL
Input Low Leakage Current (Note 3)
VIN = 0
–10
10
µA
IIH
Input High Leakage Current (Note 3)
VIN = VDD, VDDB
–10
+10
µA
Digital Output Leakage Current
IOZL
Output Low Leakage Current (Note 4)
VOUT = 0.4 V
–10
+10
µA
IOZH
Output High Leakage Current (Note 4)
VOUT = VDD, VDDB
–10
+10
µA
–0.5
0.8
V
Crystal Input Current
VILX
XTAL1 Input LOW Voltage Threshold
VIN = External Clock
VIHX
XTAL1 Input HIGH Voltage Threshold
VIN = External Clock
IILX
XTAL1 Input LOW Current
VIN = External Clock
IIHX
XTAL1 Input HIGH Current
VDD – 0.8 VDD + 0.5
V
Active
–120
0
µA
VIN = VSS
Sleep
–10
+10
µA
VIN = External Clock
Active
0
120
µA
VIN = VDD
Sleep
400
µA
Am79C974
91
AMD
PRELIMINARY
DC CHARACTERISTICS (continued)
Attachment Unit Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
–1 V < VIN < AVDD+0.5V
–500
+500
µA
Attachment Unit Interface (AUI)
IIAXD
Input Current at DI+ and DI–
IIAXC
Input Current at CI+ and CI–
–1 V < VIN < AVDD+0.5V
–500
+500
µA
VAOD
Differential Output Voltage |(DO+)–(DO–)|
RL = 78 Ω
630
1200
mV
VAODOFF
Transmit Differential Output Idle Voltage
RL = 78 Ω (Note 9)
–40
40
mV
IAODOFF
Transmit Differential Output Idle Current
RL = 78 Ω (Note 8)
–1
1
mA
VCMT
Transmit Output Common Mode Voltage
RL = 78 Ω
2.5
AVDD
V
VODI
DO± Transmit Differential Output
Voltage Imbalance
RL = 78 Ω (Note 7)
25
mV
VATH
Receive Data Differential Input Threshold
–35
35
mV
VASQ
DI± and CI± Differential Input Threshold
(Squelch)
–275
–160
mV
DI± and CI± Differential Mode Input
Voltage Range
–1.5
1.5
V
VIRDVD
VICM
DI± and CI± Input Bias Voltage
IIN = 0 mA
VOPD
DO± Undershoot Voltage at ZERO
Differential on Transmit Return to
ZERO (ETD)
(Note 9)
AVDD–3.0 AVDD–1.0
–100
V
mV
Twisted Pair Interface (10BASE-T)
Input Current at RXD±
RXD± Differential Input Resistance
VTIVB
RXD±, RXD– Open Circuit Input
Voltage (Bias)
IIN = 0 mA
VTIDV
Differential Mode Input Voltage
Range (RXD±)
AVDD = 5.0 V
–3.1
3.1
V
VTSQ+
RXD Positive Squelch Threshold (peak)
Sinusoid, 5 MHz ≤ f ≤ 10 MHz
300
520
mV
VTSQ-
RXD Negative Squelch Threshold (peak)
Sinusoid, 5 MHz ≤ f ≤ 10 MHz
–520
–300
mV
VTHS+
RXD Post-Squelch Positive Threshold
(peak)
Sinusoid, 5 MHz ≤ f ≤ 10 MHz
150
293
mV
VTHS-
RXD Post-Squelch Negative Threshold
(peak)
Sinusoid, 5 MHz ≤ f ≤ 10 MHz
–293
–150
mV
VLTSQ+
RXD Positive Squelch Threshold (peak)
LRT = LOW
180
312
mV
VLTSQ-
RXD Negative Squelch Threshold (peak)
LRT = LOW
–312
–180
mV
VLTHS+
RXD Post-Squelch Positive Threshold
(peak)
LRT = LOW
90
176
mV
VLTHS-
RXD Post-Squelch Negative Threshold
(peak)
LRT = LOW
–176
–90
mV
VRXDTH
–500
500
10
KΩ
AVDD–3.0 AVDD–1.5
V
RXD Switching Threshold
(Note 4)
–35
35
mV
VTXH
TXD± and TXP± Output HIGH Voltage
VSS = 0 V
VDD–0.6
VDD
V
VTXL
TXD± and TXP± Output LOW Voltage
VDD = 5 V
VTXI
TXD± and TXP± Differential Output
Voltage Imbalance
VTXOFF
RTX
92
AVDD < VIN < AVDD
µA
IIRXD
RRXD
VSS
VSS+0.6
V
–40
40
mV
40
mV
40
80
Ω
TXD± and TXP± Idle Output Voltage
TXD± , TXP± Differential Driver Output
Impedance
(Note 4)
Am79C974
AMD
PRELIMINARY
DC CHARACTERISTICS (continued)
SCSI Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
SCSI and PWDN
VIH
Input High Voltage
All SCSI Inputs, PWDN
2.0
VDD +
0.5
V
VIL
Input Low Voltage
All SCSI Inputs, PWDN
VSS –
0.5
0.8
V
VIHST
Input Hysteresis (Note 6)
All SCSI Inputs
4.75 V < VDD < 5.25 V
300
mV
VOH
Output High Voltage (Note 2)
IOH = –2 mA (Note 5)
2.4
VDD
V
VOL
SCSI Output Low Voltage
ATN, BSY, SEL,
SCSI^RST, ACK, SD [7:0], SDP
IOL = 48 mA
VSS
0.5
V
IIL
Input Low Leakage
All SCSI Inputs, PWDN
0.0 V < VIN < 2.7 V
–10
+10
µA
IIH
Input High Leakage
All SCSI Inputs, PWDN
2.7 V < VIN < VDD
–10
+10
µA
IOZ
High Impedance Leakage
All I/O Pins
0.4 V < VOUT < VDD
–10
+10
µA
Power Supply Current
IDD
IDDCOMA
IDDSNOOZE
Active Power Supply Current
XTAL1 = 20 MHz, CLK = 33 MHz
150
mA
Sleep Mode Power Supply Current
SLEEP Active
TBD
µA
Auto Wake Mode Power Supply Current
Awake Bit Set Active
TBD
µA
Notes:
1. IOL1 applies to AD[31:00], C/BE[3:0], PAR, and REQ
IOL2 applies to FRAME, IRDY, TRDY, DEVSEL, STOP, SERR, PERR, and LOCK
IOL3 applies to EESK/LED1, EEDO/LED3, and EEDI/LNKST
2. VOH does not apply to open-drain output pins.
3. IIL and IIH apply to all input pins except XTAL1.
4. IOZL and IOZH apply to all three-state output pins and bi-directional pins.
5. Outputs are CMOS and will be driven to rail if the load is not resistive.
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
7. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
8. Correlated to other tested parameters – not tested directly.
9. Test not implemented to data sheet specification.
Am79C974
93
AMD
PRELIMINARY
DC CHARACTERISTICS (continued)
Capacitance, ESD, and Latch Up
Parameter
Symbol
Parameter Description
Pin Names
Test Conditions
Min
Max
Unit
Pin Capacitance (Note 1) (VCC = 5.0 V, TA = 25∞ C, f = 1.0 MHz)
CIN
Input Pins
All SCSI Inputs
All Ethernet Inputs
PWDN
All PCI Inputs except
IDSEL
VIN = 0 V
10
pF
IDSEL
VIN = 0 V
8
pF
CI/O
I/O or Output Pins
All SCSI, Ethernet,
PCI Output and I/O
Pins, BUSY
VI/O = 0 V
12
pF
CCLK
Clock Pins
CLK (PCI)
SCSI CLK
VIN = 0 V
12
pF
Input Static Discharge
Pin-to-Pin
Human Body Model:
100 pF at 1.5 KΩ
All I/O
VLU ≤ 10 V
ESD (Note 1)
2K
V
Latchup (Note 1)
ILU
Latchup Current
–100
+100
mA
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
94
Am79C974
AMD
PRELIMINARY
AC SWITCHING CHARACTERISTICS over operating range unless otherwise specified
PCI Bus Interface and Board Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
0
33
MHz
∞
ns
Clock Timing
CLK Frequency
tCYC
CLK Period
@ 1.5 V
30
tHIGH
CLK High Time
@ 2.0 V
12
ns
tLOW
CLK Low Time
@ 0.8 V
12
ns
tFALL
CLK Fall Time
over 2 V p-p
1
4
V/ns
tRISE
CLK Rise Time
over 2 V p-p
1
4
V/ns
AD[31:00], C/BE[3:0], PAR,
FRAME, IRDY, TRDY, STOP,
LOCK, DEVSEL, PERR, SERR
Valid Delay
2
11
ns
tVAL (REQ)
REQ Valid Delay
1
12
ns
fEESK
EESK Frequency
(See note below)
EEDI Valid Output Delay from EESK
(See note below)
Output and Float Delay Timing
tVAL
tVAL (EEDI)
tVAL (EESK) EECS Valid Output Delay from EESK
tON
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, LOCK, DEVSEL
Active Delay
tOFF
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, LOCK, DEVSEL
Float Delay
(See note below)
650
KHz
100
400
ns
0
400
ns
2
11
ns
28
ns
Setup and Hold Timing
tSU
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, LOCK, DEVSEL,
IDSEL
Setup Time
7
ns
tH
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, LOCK, DEVSEL,
IDSEL
Hold Time
0
ns
tSU (GNT)
GNT Setup Time
10
ns
tH (GNT)
GNT Hold Time
0
ns
tSU (EEDO) EEDO Setup Time to EESK
(See note below)
50
ns
tH (EEDO)
(See note below)
0
ns
EEDO Hold Time from EESK
Note:
Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the EEPROM,
software is responsible for meeting EEPROM timing requirements.
Am79C974
95
AMD
PRELIMINARY
AC SWITCHING CHARACTERISTICS
10BASE-T Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
250
350
ns
Transmit Timing
tTETD
Transmit Start of Idle
tTR
Transmitter rise time
(10% to 90%)
5.5
ns
tTF
Transmitter fall time
(90% to 10%)
5.5
ns
tTM
Transmitter rise and fall time mismatch
(tTM = | tTR – tTF|)
1
ns
8
24
ms
(See note below)
75
120
ns
(See note below)
45
55
ns
Transmit jabber activation time
20
150
ms
Transmit jabber reset time
250
750
ms
Transmit jabber recovery time
(minimum time gap between
transmitted frames to prevent
jabber activation)
1.0
µs
136
ns
tPERLP
Idle Signal Period
tPWLP
Idle Link Pulse Width
tPWPLP
Predistortion Idle Link Pulse Width
tJA
tJR
tJREC
Receiving Timing
tPWNRD
RXD pulse width not to turn off
internal carrier sense
VIN > VTHS (min)
tPWROFF
RXD pulse width to turn off
VIN > VTHS (min)
tRETD
Receive Start of Idle
Note:
Not tested; parameter guaranteed by characterization.
96
200
200
Am79C974
ns
ns
AMD
PRELIMINARY
AC SWITCHING CHARACTERISTICS
Attachment Unit Interface
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
5.0
ns
AUI Port
tDOTR
DO+, DO– Rise Time (10% to 90%)
2.5
2.5
tDOTF
DO+, DO– Fall Time (10% to 90%)
tDORM
DO+, DO– Rise and Fall Time Mismatch
5.0
ns
1.0
ns
tDOETD
DO± End of Transmission
tPWODI
DI Pulse Width Accept/Reject Threshold
|VIN| > |VASQ| (Note 1)
200
375
ns
15
45
ns
tPWKDI
DI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ| (Note 2)
136
200
ns
tPWOCI
CI Pulse Width Accepth/Reject Threshold
|VIN| > |VASQ| (Note 3)
10
26
ns
tPWKCI
CI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ| (Note 4)
90
160
ns
50.001
ns
Internal MENDEC Clock Timing
tx1
XTAL1 Period
VIN = External Clock
49.995
tx1H
XTAL1 HIGH Pulse Width
VIN = External Clock
20
20
ns
tx1L
XTAL1 LOW Pulse Width
VIN = External Clock
tx1R
XTAL1 Rise Time
VIN = External Clock
5
ns
ns
tx1F
XTAL1 Fall Time
VIN = External Clock
5
ns
Notes:
1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn internal
DI carrier sense off.
3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn internal
CI carrier sense off.
Am79C974
97
AMD
PRELIMINARY
AC SWITCHING CHARACTERISTICS
SCSI Interface
FastClk Disabled (Control Register Three (0CH) bit 3=0), See Figure 29
No.
Parameter
Symbol
Parameter Description
1
tPWL1
Clock Pulse Width Low
2
tCP
Clock Period (1 ÷ Clock Frequency)
3
tL
Synchronization Latency
14.58
1
4
tPWH
Clock Pulse Width High
5
tRISE*
Clock Rise Time
Test Conditions
6
tFALL*
Clock Fall Time
Notes:
1. For Synchronous data transmissions, the following conditions must be true:
2tCP + tPWL ≥ 97.92 ns
2tCP + tPWH ≥ 97.92 ns
Min
Max
Unit
14.58
0.65 • tCP
ns
40
100
ns
54.58
tPWL + tCP
ns
0.65 • tCP
ns
over 2 V p-p
1
4
V/ns
over 2 V p-p
1
4
V/ns
Clock Frequency Range for Fast Clk disabled.
= 10 MHz to 25 MHz for Asynchronous Transmission
= 12 MHz to 25 MHz for Synchronous Transmission
*
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design
is modified where these parameters may be affected.
FastClk Enabled (Control Register Three (0CH) bit 3=1), See Figure 29
No.
Parameter
Symbol
Parameter Description
Test Conditions
Max
Unit
0.4 • tCP
0.6 • tCP
ns
25
50
ns
54.58
2 • tCP
ns
1
tPWL
Clock Pulse Width Low
2
tCP
Clock Period (1 ÷ Clock Frequency)
3A
tL
Synchronization Latency
4
tPWH
Clock Pulse Width High
0.4 • tCP
0.6 • tCP
ns
5
tRISE*
Clock Rise Time
over 2 V p-p
1
4
V/ns
6
tFALL*
Clock Fall Time
over 2 V p-p
1
4
V/ns
Notes:
Clock Frequency Range for Fast Clk enabled.
= 20 MHz to 40 MHz for Asynchronous Transmission
= 20 MHz to 40 MHz for Synchronous Transmission
98
Min
*
These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design
is modified where these parameters may be affected.
Am79C974
AMD
PRELIMINARY
AC SWITCHING CHARACTERISTICS (continued)
SCSI Interface
No.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Single Ended: Asynchronous Initiator Transmit, See Figure 30
7
tS
Data to ACK
8
tPD
REQ
to Data Delay
9
tPD
REQ
to ACK
10
tPD
REQ
to ACK
Set Up Time
60
ns
5
Delay
Delay
ns
50
ns
50
ns
Single Ended: Asynchronous Initiator Receive, See Figure 31
11
tPD
REQ
to ACK
Delay
50
ns
12
tPD
REQ
to ACK
Delay
50
ns
13
tS
Data to REQ
14
tH
REQ
Set Up Time
to Data Hold Time
10
ns
18
ns
55*
ns
Normal SCSI: (Single Ended) Synchronous Initiator Transmit, See Figure 32
15
tS
Data to REQ or ACK
Set Up Time
16
tPWL
REQ or ACK Pulse Width Low
90*
ns
17
tPWH
REQ or ACK Pulse Width High
90*
ns
18
tH
ACK or REQ
100*
ns
Data to REQ or ACK
Set Up Time
25*
ns
REQ or ACK Pulse Width Low
30*
ns
REQ or ACK Pulse Width High
30*
ns
ACK or REQ
35*
ns
to Data Hold Time
Fast SCSI: (Single Ended) Synchronous Initiator Transmit, See Figure 32
15
tS
16
tPWL
17
tPWH
18
tH
to Data Hold Time
Synchronous Initiator Receive, See Figure 33
19
tPWL
REQ Pulse Width Low
27
ns
19
tPWL
ACK Pulse Width Low
20
ns
20
tPWH
REQ Pulse Width High
20
ns
20
tPWH
ACK Pulse Width High
20
ns
21
tS
Data to REQ or ACK
Set Up Time
10
ns
22
tH
REQ or ACK
15
ns
to Data Hold Time
SCSI Bus Lines
tRISE**
Rise Time, 10% to 90%
SCSI Termination
+ 20 pF
8
20
ns
tFALL**
Fall Time, 10% to 90%
SCSI Termination
+ 20 pF
5
12
ns
dVH/dt**
Slew Rate, Low to High
SCSI Termination
+ 20 pF
0.15
0.50
V/ns
dVL/dt**
Slew Rate, High to Low
SCSI Termination
+ 20 pF
0.25
0.80
V/ns
* The minimum values have a wide range since they depend on the Synchronization latency. The synchronization latency, in
turn, depends on the operating frequency of the device.
**These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where these parameters may be affected.
Am79C974
99
AMD
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
AC SWITCHING TEST CIRCUITS
IOL
Sense Point
VTHRESHOLD
CL
IOH
18681A-37
Normal and Three-State Outputs
100
Am79C974
AMD
PRELIMINARY
AC SWITCHING TEST CIRCUITS
AVDD
52.3 Ω
DO+
DO–
Test Point
154 Ω
100 pF
AVSS
18681A-38
AUI DO Switching Test Circuit
DVDD
294 Ω
TXD+
TXD–
Test Point
294 Ω
100 pF
Includes test
jig capacitance
DVSS
18681A-39
TXD Switching Test Circuit
DVDD
715 Ω
TXP+
TXP–
Test Point
100 pF
Includes test
jig capacitance
715 Ω
DVSS
18681A-40
TXP Outputs Test Circuit
Am79C974
101
AMD
PRELIMINARY
AC SWITCHING WAVEFORMS
System Bus Interface
tHIGH
2.4V
2.0 V
1.5 V
0.8 V
CLK
tLOW
0.4 V
2.0 V
1.5 V
0.8 V
tFALL
tRISE
tCYC
18681A-41
CLK Waveform
Tx
Tx
CLK
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, LOCK,
DEVSEL, IDSEL
tSU
tH
tSU(GNT)
tH(GNT)
GNT
18681A-42
Input Setup and Hold Timing
102
Am79C974
AMD
PRELIMINARY
AC SWITCHING WAVEFORMS
System Bus Interface
Tx
Tx
Tx
CLK
tVAL
AD[31:00] C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, LOCK,
DEVSEL, PERR, SERR
MIN
MAX
Valid n+1
Valid n
tVAL(REQ)
MIN
Valid n
REQ
MAX
Valid n+1
18681A-43
Output Valid Delay Timing
Tx
Tx
Tx
CLK
tON
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, LOCK,
DEVSEL
Valid n
tOFF
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, LOCK,
DEVSEL
Valid n
18681A-44
Output Tri-State Delay Timing
Am79C974
103
AMD
PRELIMINARY
AC SWITCHING WAVEFORMS
10BASE-T Interface
tTR
tTF
TXD+
tTETD
TXP+
TXD–
TXP–
tXMTON
tXMTOFF
XMT
(Note 1)
18681A-45
Note:
1. Internal signal and is shown for clarification only.
Transmit Timing
tPWPLP
TXD+
TXP+
TXD–
TXP–
tPWLP
tPERLP
18681A-46
Idle Link Test Pulse
104
Am79C974
AMD
PRELIMINARY
SWITCHING WAVEFORMS
10BASE-T Interface
VTSQ+
VTHS+
RXD±
VTHS–
VTSQ–
tmau_RCV_LRT_HI
18681A-47
Receive Thresholds (LRT=0)
VLTSQ+
VLTHS+
RXD±
VLTHS–
VLTSQ–
tmau_RCV_LRT_HI
18681A-48
Receive Thresholds (LRT=1)
Am79C974
105
AMD
PRELIMINARY
AC SWITCHING WAVEFORMS
Attachment Unit Interface
tX1H
XTAL1
tX1L
tX1F
tX1R
tXI
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
ITXDAT+
(Note 1)
1
1
0
0
tDOTR
tDOTF
DO+
DO–
1
DO±
18681A-49
Note:
1. Internal signal and is shown for clarification only.
Transmit Timing – Start of Frame
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
ITXDAT+
(Note 1)
0
0
DO+
DO–
DO±
1
0
0
Bit (n–2)
Bit (n–1)
Note:
1. Internal signal and is shown for clarification only.
tDOETD
Typical > 200 ns
Bit (n)
Transmit Timing – End of Frame (Last Bit = 0)
106
Am79C974
18681A-50
AMD
PRELIMINARY
SWITCHING WAVEFORMS
Attachment Unit Interface
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
1
ITXDAT+
(Note 1)
0
DO+
DO–
tDOETD
Typical > 250 ns
DO±
1
0
Bit (n–2)
Bit (n–1) Bit (n)
Note:
1. Internal signal and is shown for clarification only.
18681A-51
Transmit Timing – End of Frame (Last Bit = 1)
tPWKDI
DI+/–
VASQ
tPWKDI
tPWODI
18681A-52
Receive Timing
Am79C974
107
AMD
PRELIMINARY
AC SWITCHING WAVEFORMS
Attachment Unit Interface
tPWKCI
CI+/–
VASQ
tPWOCI
18681A-53
tPWKCI
Collision Timing
tDOETD
DO+/–
40 mV
0V
100 mV max.
80 Bit Times
Port DO ETD Waveform
108
Am79C974
18681A-54
AMD
PRELIMINARY
AC SWITCHING TEST WAVEFORMS
SCSI Interface
3.0 V
All Inputs
1.5 V
0.0 V
2.3 V
0.8 V
VOH
2.0 V
VOL
True Data Outputs SD [7:0], SDP
VOH – 0.3 V
2.0 V
VOL + 0.3 V
Hi-Z Outputs SD [7:0], SDP
2.0 V
0.8 V
All Open Drain Outputs
VOL
18681A-55
5
6
SCSI CLK
1
4
2
3
3A
18681A-56
Figure 29. Clock Input
SD [7:0]
SDP
7
8
ACK
9
10
REQ
18681A-57
Figure 30. Asynchronous Initiator Transmit
Am79C974
109
AMD
PRELIMINARY
AC SWITCHING TEST WAVEFORMS
SCSI Interface
SD [7:0]
SDP
14
ACK
11
13
12
REQ
18681A-58
Figure 31. Asynchronous Initiator Receive
SD [7:0]
SDP
18
17
15
16
REQ
ACK
18681A-59
Figure 32. Synchronous Initiator Transmit
SD [7:0]
SDP
22
20
21
19
REQ
ACK
18681A-60
Figure 33. Synchronous Initiator Receive
110
Am79C974
AMD
PRELIMINARY
PHYSICAL DIMENSIONS*
PQB132
Plastic Quad Flat Pack Trimmed and Formed (measured in inches)
Pin 66
0.947
0.953
1.097
1.103
1.075
1.085
Pin 33
0.008
0.012
0.947
0.953
1.075
1.085
1.097
1.103
0.008
Pin 1 ID
0.016
Pin 2
Pin 99
Pin 132
Top View
0.130
0.025 Basic
0.150
0.160
0.180
0.80
REF
0.020
0.040
Side View
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Trademarks
Copyright  1994 Advanced Micro Devices, Inc. All rights reserved.
20010A
CL85
08/27/93 MH
AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79C974
111
APPENDIX A
Register Summary
Ethernet PCI Configuration Registers
Note: RO = read only, RW = read/write, U = undefined value
Offset
Width in Bit
Access Mode
Default Value
00h
Name
Vendor ID
16
RO
1022h
02h
Device ID
16
RO
2000h
04h
Command
16
RW
0uuu
06h
Status
16
RW
uu00
08h
Revision ID
8
RO
00h
09h
Programming IF
8
RO
00h
0Ah
Sub-Class
8
RO
00h
0Bh
Base-Class
8
RO
02h
0Dh
Latency Timer
8
RO
00h
0Eh
Header Type
8
RO
00h
10h
Base Address
32
RW
uuuu uuuu
3Ch
Interrupt Line
8
RW
uu
3Dh
Interrupt Pin
8
RO
02h
SCSI PCI Configuration Registers
Note: RO = read only, RW = read/write, U = undefined value
Offset
112
Width in Bit
Access Mode
Default Value
00h
Name
Vendor ID
16
RO
1022h
02h
Device ID
16
RO
2020h
04h
Command
16
RW
0080h
06h
Status
16
RW
uuuu
08h
Revision ID
8
RO
00h
09h
Programming IF
8
RO
00h
0Ah
Sub-Class
8
RO
00h
0Bh
Base-Class
8
RO
01h
0Dh
Latency Timer
8
RO
00h
0Eh
Header Type
8
RO
00h
10h
Base Address
32
RW
uuuu uuuu
3Ch
Interrupt Line
8
RW
uu
3Dh
Interrupt Pin
8
RO
01h
40h
Reserved for Software
32
RW
uuuu
44h
Reserved for Software
32
RW
uuuu
48h
Reserved for Software
32
RW
uuuu
4Ch
Reserved for Software
32
RW
uuuu
Am79C974
AMD
PRELIMINARY
Ethernet Controller
Control and Status Registers
Note: u = undefined value, R = Running register, S = Setup register, T = Test register
RAP Addr
Symbol
Default Value
After
H_RESET
00
CSR0
uuuu 0004
PCnet-SCSI Status Register
R
01
CSR1
uuuu uuuu
IADR[15:0]: Base Address of INIT Block Lower
S
02
CSR2
uuuu uuuu
IADR[31:16]: Base Address of INIT Block Upper
S
03
CSR3
uuuu 0000
Interrupt Masks and Deferral Control
S
04
CSR4
uuuu 0115
Test and Features Control
R
05
CSR5
uuuu 0000
Reserved
T
06
CSR6
uuuu uuuu
RXTX: RX/TX Descriptor Table Lengths
T
07
CSR7
uuuu 0000
Reserved
T
08
CSR8
uuuu uuuu
LADR0: Logical Address Filter — LADRF[15:0]
T
09
CSR9
uuuu uuuu
LADR1: Logical Address Filter — LADRF[31:16]
T
10
CSR10
uuuu uuuu
LADR2: Logical Address Filter — LADRF[47:32]
T
11
CSR11
uuuu uuuu
LADR3: Logical Address Filter — LADRF[63:48]
T
12
CSR12
uuuu uuuu
PADR0: Physical Address Register — PADR[15:0]
T
13
CSR13
uuuu uuuu
PADR1: Physical Address Register — PADR[31:16]
T
14
CSR14
uuuu uuuu
PADR2: Physical Address Register — PADR[47:32]
T
15
CSR15
see reg. desc.
MODE: Mode Register
S
16
CSR16
uuuu uuuu
IADR[15:0]: Alias of CSR1
T
17
CSR17
uuuu uuuu
IADR[31:16]: Alias of CSR2
T
18
CSR18
uuuu uuuu
CRBAL: Current RCV Buffer Address Lower
T
19
CSR22
uuuu uuuu
CRBAU: Current RCV Buffer Address Upper
T
20
CSR20
uuuu uuuu
CXBAL: Current XMT Buffer Address Lower
T
21
CSR21
uuuu uuuu
CXBAU: Current XMT Buffer Address Upper
T
Comments
Am79C974
Use
113
AMD
PRELIMINARY
Control and Status Registers (continued)
RAP Addr
Symbol
Default Value
After
H_RESET
22
CSR22
uuuu uuuu
NRBAL: Next RCV Buffer Address Lower
T
23
CSR23
uuuu uuuu
NRBAU: Next RCV Buffer Address Upper
T
24
CSR24
uuuu uuuu
BADRL: Base Address of RCV Ring Lower
S
25
CSR25
uuuu uuuu
BADRU: Base Address of RCV Ring Upper
S
26
CSR26
uuuu uuuu
NRDAL: Next RCV Descriptor Address Lower
T
27
CSR27
uuuu uuuu
NRDAU: Next RCV Descriptor Address Upper
T
28
CSR28
uuuu uuuu
CRDAL: Current RCV Descriptor Address Lower
T
29
CSR29
uuuu uuuu
CRDAU: Current RCV Descriptor Address Upper
T
30
CSR30
uuuu uuuu
BADXL: Base Address of XMT Ring Lower
S
31
CSR31
uuuu uuuu
BADXU: Base Address of XMT Ring Upper
S
32
CSR32
uuuu uuuu
NXDAL: Next XMT Descriptor Address Lower
T
33
CSR33
uuuu uuuu
NXDAU: Next XMT Descriptor Address Upper
T
34
CSR34
uuuu uuuu
CXDAL: Current XMT Descriptor Address Lower
T
35
CSR35
uuuu uuuu
CXDAU: Current XMT Descriptor Address Upper
T
36
CSR36
uuuu uuuu
NNRDAL: Next Next Receive Descriptor Address Lower
T
37
CSR37
uuuu uuuu
NNRDAU: Next Next Receive Descriptor Address Upper
T
38
CSR38
uuuu uuuu
NNXDAL: Next Next Transmit Descriptor Address Lower
T
39
CSR39
uuuu uuuu
NNXDAU: Next Next Transmit Descriptor Address Upper
T
40
CSR40
uuuu uuuu
CRBC: Current RCV Byte Count
T
41
CSR41
uuuu uuuu
CRST: Current RCV Status
T
42
CSR42
uuuu uuuu
CXBC: Current XMT Byte Count
T
43
CSR43
uuuu uuuu
CXST: Current XMT Status
T
44
CSR44
uuuu uuuu
NRBC: Next RCV Byte Count
T
45
CSR45
uuuu uuuu
NRST: Next RCV Status
T
46
CSR46
uuuu uuuu
POLL: Poll Time Counter
T
47
CSR47
uuuu uuuu
POLLINT: Polling Interval
S
48
CSR48
uuuu uuuu
Reserved
T
49
CSR49
uuuu uuuu
Reserved
T
50
CSR50
uuuu uuuu
Reserved
T
51
CSR51
uuuu uuuu
Reserved
T
52
CSR52
uuuu uuuu
Reserved
T
53
CSR53
uuuu uuuu
Reserved
T
54
CSR54
uuuu uuuu
Reserved
T
55
CSR55
uuuu uuuu
Reserved
T
56
CSR56
uuuu uuuu
Reserved
T
57
CSR57
uuuu uuuu
Reserved
T
58
CSR58
see reg. desc.
SWS: Software Style
S
59
CSR59
uuuu 0105
IR: IR Register
T
60
CSR60
uuuu uuuu
PXDAL: Previous XMT Descriptor Address Lower
T
61
CSR61
uuuu uuuu
PXDAU: Previous XMT Descriptor Address Upper
T
62
CSR62
uuuu uuuu
PXBC: Previous XMT Byte Count
T
63
CSR63
uuuu uuuu
PXST: Previous XMT Status
T
64
CSR64
uuuu uuuu
NXBA: Next XMT Buffer Address Lower
T
114
Comments
Am79C974
Use
AMD
PRELIMINARY
Control and Status Registers (continued)
RAP Addr
Symbol
Default Value
After
H_RESET
65
CSR65
uuuu uuuu
NXBAU: Next XMT Buffer Address Upper
T
66
CSR66
uuuu uuuu
NXBC: Next XMT Byte Count
T
67
CSR67
uuuu uuuu
NXST: Next XMT Status
T
68
CSR68
uuuu uuuu
Reserved
T
69
CSR69
uuuu uuuu
Reserved
T
70
CSR70
uuuu uuuu
Reserved
T
71
CSR71
uuuu uuuu
Reserved
T
72
CSR72
uuuu uuuu
RCVRC: RCV Ring Counter
T
73
CSR73
uuuu uuuu
Reserved
T
74
CSR74
uuuu uuuu
XMTRC: XMT Ring Counter
T
75
CSR75
uuuu uuuu
Reserved
T
76
CSR76
uuuu uuuu
RCVRL: RCV Ring Length
S
77
CSR77
uuuu uuuu
Reserved
T
78
CSR78
uuuu uuuu
XMTRL: XMT Ring Length
S
79
CSR79
uuuu uuuu
Reserved
T
80
CSR80
uuuu E810
DMATCFW: DMA Transfer Counter and FIFO Threshold
S
81
CSR81
uuuu uuuu
Reserved
T
82
CSR82
uuuu 0000
DMABAT: Bus Activity Timer
S
83
CSR83
uuuu uuuu
Reserved
T
84
CSR84
uuuu uuuu
DMABAL: DMA Address Register Lower
T
85
CSR85
uuuu uuuu
DMABAU: DMA Address Register Upper
T
86
CSR86
uuuu uuuu
DMABC: Buffer Byte Counter
T
87
CSR87
uuuu uuuu
Reserved
T
88
CSR88
0242 0003
Chip ID Register Lower
T
89
CSR89
uuuu 0242
Chip ID Register Upper
T
90
CSR90
uuuu uuuu
RAEO Register
S
91
CSR91
uuuu uuuu
Reserved
T
92
CSR92
uuuu uuuu
RCON: Ring Length Conversion
T
93
CSR93
uuuu uuuu
Reserved
T
94
CSR94
uuuu 0000
XMTTDR: Transmit Time Domain Reflectometry Count
T
95
CSR95
uuuu uuuu
Reserved
T
96
CSR96
uuuu uuuu
Reserved
T
97
CSR97
uuuu uuuu
Reserved
T
98
CSR98
uuuu uuuu
Reserved
T
Comments
Use
99
CSR99
uuuu uuuu
Reserved
T
100
CSR100
uuuu 0200
MERRTO: Bus Time-Out
S
101
CSR101
uuuu uuuu
Reserved
T
102
CSR102
uuuu uuuu
Reserved
T
103
CSR103
uuuu 0105
Reserved
T
104
CSR104
uuuu uuuu
Reserved
T
105
CSR105
uuuu uuuu
Reserved
T
106
CSR106
uuuu uuuu
Reserved
T
107
CSR107
uuuu uuuu
Reserved
T
Am79C974
115
AMD
PRELIMINARY
Control and Status Registers (continued)
RAP Addr
Symbol
Default Value
After
H_RESET
108
CSR108
uuuu uuuu
Reserved
T
109
CSR109
uuuu uuuu
Reserved
T
110
CSR110
uuuu uuuu
Reserved
T
111
CSR111
uuuu uuuu
Reserved
T
112
CSR112
uuuu 0000
MFC: Missed Frame Count
R
113
CSR113
uuuu uuuu
Reserved
T
114
CSR114
uuuu 0000
RCC: Receive Collision Count
R
115
CSR115
uuuu uuuu
Reserved
T
116
CSR116
uuuu uuuu
Reserved
T
117
CSR117
uuuu uuuu
Reserved
T
118
CSR118
uuuu uuuu
Reserved
T
119
CSR119
uuuu uuuu
Reserved
T
120
CSR120
uuuu uuuu
Reserved
T
121
CSR121
uuuu uuuu
Reserved
T
122
CSR122
see reg. desc.
Receive Frame Alignment Control
S
123
CSR123
uuuu uuuu
Reserved
T
124
CSR124
see reg. desc.
Test Register 1
T
125
CSR125
uuuu uuuu
Reserved
T
126
CSR126
uuuu uuuu
Reserved
T
127
CSR127
uuuu uuuu
Reserved
T
Comments
Use
BCR—Bus Configuration Registers
Writes to those registers marked as “Reserved” will have no effect. Reads from these locations will produce undefined
values.
Programmability
BCR
MNEMONIC
Default
Description
User
EEPROM
0
MSRDA
0005h
Reserved
No
No
1
MSWRA
0005h
Reserved
No
No
2
MC
N/A*
Miscellaneous Configuration
Yes
Yes
3
Reserved
N/A
Reserved
No
No
4
LNKST
00C0h
Link Status (Default)
Yes
No
5
LED1
0084h
Receive Status (Default)
Yes
No
6
LED2
0088h
Reserved
Yes
No
7
LED3
0090h
Transmit Status (Default)
Yes
No
8–15
Reserved
N/A
Reserved
No
No
16
IOBASEL
N/A*
Reserved
Yes
Yes
17
IOBASEU
N/A*
Reserved
Yes
Yes
18
BSBC
2101h
Burst Size and Bus Control
Yes
Yes
19
EECAS
0002h
EEPROM Control and Status
Yes
No
20
SWS
0000h
Software Style
Yes
No
21
INTCON
N/A*
Reserved
Yes
Yes
* Registers marked with an “*” have no default value, since they are not observable without first being programmed through the
EEPROM read operation. Therefore, the only observable values for these registers are those that have been programmed and
a default value is not applicable.
116
Am79C974
PRELIMINARY
AMD
SCSI Controller
SCSI Register Map
Register
Acronym
CTCREG
STCREG
CTCREG
STCREG
FFREG
CMDREG
STATREG
SDIDREG
INSTREG
STIMREG
ISREG
STPREG
CFISREG
SOFREG1
CNTLREG1
CLKFREG
RES
CNTLREG2
CNTLREG3
CNTLREG4
CTCREG
STCREG
RES
Address (Hex.)
(B)+00
(B)+00
(B)+04
(B)+04
(B)+08
(B)+0C
(B)+10
(B)+10
(B)+14
(B)+14
(B)+18
(B)+18
(B)+1C
(B)+1C
(B)+20
(B)+24
(B)+28
(B)+2C
(B)+30
(B)+34
(B)+38
(B)+38
(B)+3C
Register Description
Current Transfer Count Register Low
Start Transfer Count Register Low
Current Transfer Count Register Middle
Start Transfer Count Register Middle
SCSI FIFO Register
SCSI Command Register
SCSI Status Register
SCSI Destination ID Register
Interrupt Status Register
SCSI Timeout Register
Internal State Register
Synchronous Transfer Period Register
Current FIFO/Internal State Register
Synchronous Offset Register
Control Register One
Clock Factor Register
Reserved
Control Register Two
Control Register Three
Control Register Four
Current Transfer Count Register High/Part-Unique ID Code
Start Current Transfer Count Register High
Reserved
Type
Read
Write
Read
Write
Read/Write
Read/Write
Read
Write
Read
Write
Read
Write
Read
Write
Read/Write
Write
Write
Read/Write
Read/Write
Read/Write
Read
Write
Write
DMA Register Map
Register
Acronym
CMD
STC
SPA
WBC
WAC
STATUS
SMDLA
WMAC
Address (Hex.)
(B)+40
(B)+44
(B)+48
(B)+4C
(B)+50
(B)+54
(B)+58
(B)+5C
Register Description
Command
Starting Transfer Count
Starting Physical Address
Working Byte Counter
Working Address Counter
Status Register
Starting Memory Descriptor List (MDL) Address
Working MDL Counter
Am79C974
Type
R/W
R/W
R/W
R
R
R
R/W
R
117
APPENDIX B
PCnet-SCSI Compatible Media Interface Modules
PCnet-SCSI COMPATIBLE 10BASE-T
Filters and Transformers
Manufacturer
Bel Fuse
Part #
Package
A556-2006-DE
16 pin 0.3” DIL
Description
Transmit and receive filters and transformers.
Bel Fuse
0556-2006-00
14-pin SIP
Transmit and receive filters and transformers.
Bel Fuse
0556-2006-01
14-pin SIP
Transmit and receive filters, transformers and common mode
chokes.
Bel Fuse
0556-6392-00
16-pin 0.5” DIL
Transmit and receive filters, transformers and common mode
chokes.
Halo Electronics
FD02-101G
16-pin 0.3” DIL
Transmit and receive filters and transformers.
Halo Electronics
FD12-101G
16-pin 0.3” DIL
Transmit and receive filters and transformers, transmit common
mode choke.
Halo Electronics
FD22-101G
16-pin 0.3” DIL
Transmit and receive filters, transformers and common mode
chokes.
PCA Electronics
EPA1990A
16-Pin 0.3” DIL
Transmit and receive filters and transformers.
PCA Electronics
EPA2013D
16-Pin 0.3” DIL
Transmit and receive filters and transformers, transmit common
mode choke.
Pulse Engineering
PE-65434
10-pin SIP
Transmit and receive filters, transformers, and common
mode choke.
Pulse Engineering
PE-65445
16-pin 0.3” DIL
Transmit and receive filters and transformers
(for SMT use PE-65446)
Pulse Engineering
PE65467
16-Pin 0.3” DIL
Transmit and receive filters, transformers, common mode
chokes, and AMD specified resistors.
Pulse Engineering
PE-65424
16-Pin 0.3” DIL
Transmit and receive filters, transformers, and common
mode chokes.
TDK
TLA 470
14-pin SIP
Transmit and receive filters and transformers.
TDK
HIM3000
24-pin 0.6” DIL
Transmit and receive filters, transformers and common mode
chokes.
Valor Electronics
PT3877
16-pin 0.3” DIL
Transmit and receive filters and transformers.
Valor Electronics
PT3983
8-pin 0.3” DIL
Transmit and receive common mode chokes.
Valor Electronics
FL1012
16-pin 0.3” DIL
Transmit and receive filters and transformers, transmit common
mode choke.
118
Am79C974
AMD
PRELIMINARY
PCnet-SCSI COMPATIBLE AUI
Isolation Transformers
Manufacturer
Part #
Package
Description
Bel Fuse
A553-0506-AB
16-Pin 0.3” DIL
50 µH
Halo Electronics
TD01-0756K
16-Pin 0.3” DIL
75 µH
Halo Electronics
TG01-0756W
16-Pin 0.3” SMD
75 µH
PCA Electronics
EP9531-4
16-Pin 0.3” DIL
50 µH
Pulse Engineering
PE64106
16-Pin 0.3” DIL
50 µH
TDK
TLA 100-3E
16-Pin 0.3” DIL
100 µH
Valor Electronics
LT6031
16-Pin 0.3” DIL
50 µH
MANUFACTURER CONTACT INFORMATION
Contact the following companies for further
information on their products:
Bel Fuse
Phone: (317) 831-4226
FAX: (317) 831-4547
Halo Electronics
Phone: (415) 989-7313
FAX: (415) 367-7158
PCA Electronics
Phone: (408) 954-0400
FAX: (408) 954-1440
Pulse Engineering
Phone: (619) 674-8218
FAX: (619) 675-8262
TDK
Phone: (213) 530-9397
FAX: (213) 530-8127
Valor Electronics
Phone: (619) 458-1471
FAX: (619) 458-0875
Am79C974
119
APPENDIX C
Recommendation for Power and Ground
Decoupling
The PCnet-SCSI controller is an integrated, combination Ethernet and Fast SCSI controller, which contains
both digital and analog circuitry. The analog circuitry
contains a high speed Phase-Locked Loop (PLL) and
Voltage Controlled Oscillator (VCO). Because of the
mixed signal characteristics of this chip, some extra precautions must be taken into account when designing
with this device.
Digital Decoupling
The PCnet-SCSI controller separates the digital power
supply pins into two groups. The VSSB and VDDB pins supply power to the I/O buffers that connect to the PCI bus.
The VSS and VDD pins supply power to all internal circuitry. AMD recommends that at least one low frequency bulk decoupling capacitor be used for each
group of digital power pins. 22 µF capacitors have
worked well for this. In addition, a total of four or five
0.1 µF capacitors have proven sufficient around VSSB
and VDDB pins that supply the drives of the PCI bus output pins. An additional two to the three 0.1 µF capacitors
shoud be used around the VSS and VDD pins.
The CMOS technology used in fabricating the PCnetSCSI controller employs an n-type substrate. In this
technology, all VDD and VDDB pins are electrically connected to each other internally. Hence, in a multi-layer
board, when decoupling between VDD/VDDB and critical
VSS/VSSB pins, the specific VDD/VDDB pin that you connect
to is not critical. In fact, the VDD/VDDB connection of the
decoupling capacitor can be made directly to the power
plane, near the closest VDD/VDDB pin to the VSS/VSSB pin
of interest. However, we recommend that the VSS/VSSB
connection of the decoupling capacitor be made directly
to the VSS/VSSB pin of interest as shown.
AMD recommends that at least one low-frequency bulk
decoupling capacitor be used in the area of the PCnetSCSI controller. 22 µF capacitors have worked well for
this. In addition, a total of four or five 0.1 µF capacitors
have proven sufficient around the VSSB and VDDB pins
that supply the drivers of the PCI bus output pins.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are located in one corner of the device. Specific requirements
of the analog supply pins are listed below.
AVSS1 (Pin 100) and AVDD3 (Pin 96)
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1 µF capacitor between these pins
is recommended.
AVSS2 (Pin 98) and AVDD2 (Pin 108)
These pins are the most critical pins on the PCnet-SCSI
controller because they provide the power and ground
for the PLL portion of the chip. The VCO portion of the
PLL is sensitive to noise in the 60 kHz –200 kHz. range.
To prevent noise in this frequency range from disrupting
the VCO, AMD strongly recommends that the low-pass
filter shown below be implemented on these pins. Tests
using this filter have shown significantly increased noise
immunity and reduced Bit Error Rate (BER) statistics in
designs using the PCnet-SCSI controller.
via to VDD plane
VDD Plane
33 µF to 6.8 µF
AVDD
Pin 108
AVSS
Pin 98
R1
2.7 Ω to 20 Ω
VDD/VDDB Pin
PCnet-SCSI
18681A-62
VSS/VSSB Pin
via to VSS plane
PCnet-SCSI
18681A-61
120
Am79C974
PRELIMINARY
To determine the value for the resistor and capacitor,
the formula is:
R * C ≥ 88
AMD
AVDD1 (Pin 103) and AVDD4 (Pin 91)
These pins provide power for the AUI and twisted-pair
receive circuitry. No specific decoupling has been necessary on these pins.
Where R is in ohms and C is in microfarads. Some possible combinations are given below. To minimize the
voltage drop across the resistor, the R value should not
be more than 20 Ω.
R
C
2.7 Ω
33 µF
4.3 Ω
22 µF
6.8 Ω
15 µF
10 Ω
10 µF
20 Ω
6.8 µF
Am79C974
121
APPENDIX D
Alternative Method for Initialization
of Ethernet Controller
The Ethernet portion of the PCnet-SCSI controller may
be initialized by performing I/O writes only. That is, data
can be written directly to the appropriate control and
status registers (CSR) instead of reading from the
initialization Block in memory. The registers that must
be written are shown in the table below. These register
writes are followed by writing the START bit in CSR0.
Control and Status Register
Comment
CSR8
LADRF[15:0]
CSR9
LADRF[31:16]
CSR10
LADRF[47:32]
CSR11
LADRF[63:48]
CSR12
PADR[15:0]
CSR13
PADR[31:16]
CSR14
PADR[47:32]
CSR15
Mode
CSR24-25
BADR
CSR30-31
BADX
CSR47
POLLINT
CSR76
RCVRL
CSR78
XMTRL
Note:
The INIT bit must not be set or the initialization block will be accessed instead.
122
Appendix D
APPENDIX E
SCSI System Considerations
INTRODUCTION
This appendix covers motherboard design considerations which use the Am79C974. It discusses SCSI component placement, signal routing, PCI interface
recommendations, noise considerations and termination schemes.
SIGNAL ROUTING AND SCSI
PLACEMENT
The main components for board design include the
Am79C974 (whose maximum trace length from the PCI
speedway is 1.5′′), SCSI connectors (either one or two
depending internal/external support), a 40 MHz crystal
oscillator and regulated terminators (on-board) which
can be up to .1 m (3.937 in) away from the Am79C974.
There are many ways to route SCSI bus traces on a host
adapter board or motherboard. Ideally, traces from the
internal SCSI bus connector, from the Am79C974 and
from the external SCSI bus connector should all connect
in series. Care should be taken not to have any stubs in
the SCSI bus. (Stubs are any extensions off of the main
bus. The maximum SCSI bus stub length allowed is .1
m). This routing scheme helps maintain signal integrity
by reducing the possibility of signal reflections and other
undesirable effects. Auto-routing programs used for
board layout may not follow this scheme, and may create “non-ideal” environments by routing internal and external on-board connectors first instead of routing both
sets of traces to the Am79C974. When peripherals are
added either internally or externally, a “three-pronged”
SCSI bus will be created instead of a linear one. If this or
any other stub problem occurs, changes should be
made manually to follow the ideal scheme. Refer to Figures E-1 and E-2.
Termination
connector for
internal peripheral
High-density
SCSI-2
Connectors
linear busno stubs
External
Peripheral
External
SCSI-2
bus cable
High-Density
SCSI-2
Termination
25
Am79C974
to PCI Bus
18681A-63
Figure E-1. Ideal Routing Scheme
Am79C974
123
AMD
PRELIMINARY
Termination
Connector for
Internal Peripheral
Bracketed card joining
ribbon cable with highdensity SCSI-2 cable
3-Pronged Bus
(not recommended)
High-Density
SCSI-2
Connectors
External
Peripheral
External SCSI-2
Bus Cable
25
High-Density
SCSI-2
Termination
stub
Am79C974
to PCI Bus
18681A-64
Figure E-2. A Poor Routing Scheme
The Motherboard
The following two layouts may be used as a guideline
for the design of motherboards which incorporate the
Am79C974. For both layouts, the SCSI connectors
should be placed as far away from the PCI Speedway as
possible. Each layout refers to termination considerations which are described in further detail in the Termination Considerations section.
linear routing scheme. The following lists the requirements for implementation, while Figure E-3 illustrates
this approach.
Layout #1
This approach avoids the cost of placing an external
connector on the motherboard. In this configuration, the
Am79C974 is always at one end of the SCSI bus, therefore, the regulated terminators remain active. This eliminates the problem of switching the regulated
terminators on or off to accommodate peripheral configurations. This approach also preserves the ideal
124
Am79C974
One connector on the motherboard connected to
one end of the internal bus ribbon cable and its
components.
The other end of the internal bus ribbon cable connected to one end of the external bus high density
cable and its peripherals via a bracketed add-on
card. The internal bus may also be crimped to a
SCSI connector mounted on a bracket.
On board regulated terminators a maximum of
0.1 m (3.937 in) from the Am79C974.
External terminators connected to the end of the
external bus.
AMD
PRELIMINARY
External SCSI-2 Bus Cable
Connector for
Internal Peripheral
High-Density
SCSI-2
Connector
Bracketed card
joining ribbon cable
with high-density
SCSI-2 cable
Internal SCSI bus cable
Keyboard
Connector
External
Peripheral
To DC Power
Ferrite Bead
To SCSI CLK1
and CLK2
Am79C974
Termination
High-Density
SCSI-2
Termination
25
CPU
to PCI Bus
MEMORY
always on
18681A-65
Figure E-3. Motherboard Layout — Approach #1
Layout #2
This approach uses a “pizza-box” type of motherboard,
which has been incorporated into PC systems and workstations. This design reduces the system’s height so
that its casing resembles a pizza box. This is partly the
result of a riser card that enables cards to rest on their
side instead of upright. This approach requires the following and is illustrated in Figure E-4:
bus consists of motherboard routings (not just ribbon cable).
An internal connector on the motherboard to accommodate internal drives.
On-board regulated terminators for SCSI drives
not mounted within the system. However, should
the user decide to connect a drive internally, terminators are not needed.
If on-board regulated terminators are used, they
should be placed within .1 m (3.937 in) from the
Am79C974.
An external connector mounted on the motherboard with routings that connect to the
Am79C974.
The Am79C974 must be as close as possible to
this external connector since this part of the SCSI
Am79C974
125
AMD
PRELIMINARY
Riser Card
High-Density
SCSI-2
Connectors
To DC Power
To SCSI CLK1 Ferrite Bead
and CLK2
Am79C974
External SCSI
Bus Cable
to PCI Bus
High-Density
SCSI-2
Termination
CPU
Termination
25
External
Peripheral
Internal
Drive
(Terminated)
Termination
Keyboard
Connector
Mounted
High-Density
SCSI-2
Connector
This is optional. Use
accordingly to terminate both
ends of the SCSI Bus.
Memory
18681A-66
Figure E-4. Motherboard Layout — Approach #2
Motherboard designs which place an internal and external connector on either side of the Am79C974 are discouraged since:
Electromagnetic Interference (EMI)
There are several ways to reduce the amount of noise
present in these areas:
Two SCSI connectors are required on the motherboard—one more than what the other two approaches call for.
When the number of internal and external bus
components increase, the on-board terminators
would have to be turned off either through software
or hardware, which may be undesirable to a board
designer.
The possibility for creating stubs exists if the connectors and Am79C974 are not routed correctly.
See Figure E-1 for the ideal routing scheme.
NOISE CONSIDERATIONS
Some areas of a PCI motherboard or host adapter design (which include the Am79C974) are more susceptible to noise. They are:
the 40 MHz crystal oscillator
the SCSI cables
the DC power planes
pins on the ICs, specifically the Am79C974.
126
Am79C974
A 40 MHz crystal oscillator must be used in order
to have a 10 MB/s SCSI data rate. Use of this
40 MHz crystal oscillator, which drives the
SCSI CLK pin on the Am79C974, introduces the
possibility of unwanted high frequency components, including harmonics, coupling with
Am79C974 signals. To help prevent this, a resistor
should be placed in series with the oscillator to
form a low pass filter with the input capacitance
(10 pF) of the SCSI CLK pin. This filter reduces the
edge rate of the clock waveform, increasing both
rise and fall times by 2 ns. This removes higher
frequencies, specifically harmonics from the crystal
oscillator waveform and thus reduces the amount
of noise introduced into the Am79C974.
A ferrite bead, which is essentially an inductor,
may be used with the oscillator to prevent coupling
of higher frequencies with DC power supply signals. The ferrite bead blocks high frequency noise
while acting like a short to the DC components.
PRELIMINARY
From an EMI standpoint, SCSI-2 high-density cables should be used instead of a SCSI-1 cables.
Unlike the SCSI-1 flat ribbon cable, the SCSI-2
cable is electrically more substantial. It is shielded
and signal wires are strategically placed for better
signal travel.
Decoupling Methods
As stated in Appendix C, decoupling capacitors should
be used across the VDD and VSS pins on the motherboard
There are pairs of VDD and VSS pins on the Am79C974
that should each have their own decoupling capacitor.
The following decoupling method should be used for the
VDD/VSS pairs:
Am79C974
AMD
Connect the capacitor directly between a VDD/VSS
pair of the Am79C974 so that it sits on the component side of the board. This configuration will allow
the capacitor to filter undesired high frequency
components directly at the Am79C974 and not
only at the power planes. This not only minimizes
the noise on the power planes that the chip sees,
but it also filters any noise generated by the chip
before it reaches the power planes. The leads to
each end of the capacitor should be wide and may
contain several feed-throughs to the VDD and VSS
planes to reduce the inductance present. Refer to
Figure E-5.
127
AMD
PRELIMINARY
Decoupling methods which are NOT recommended
include:
connecting a capacitor only between the VDD and
VSS planes so that it sits on the component side of
the board. This doesn’t allow the capacitor to reduce noise directly at the chip, but it does allow for
a reduction of power plane noise and of board
components. (capacitors).
connecting a capacitor only between the VDD and
VSS planes so that it sits on the solder side of the
board. This configuration also doesn’t allow direct
decoupling at the chip. It does save board space,
but it requires an extra manufacturing step.
TERMINATION CONSIDERATIONS
The use of active or regulated termination for terminators on the motherboard is recommended (see Figure
E-6), while external SCSI terminators can be used to
terminate other parts of the SCSI bus. Terminators must
match the impedance seen by a signal at the end of the
SCSI bus to the characteristic impedance of the SCSI
bus. This impedance is typically 84 +/– 12 Ω, but can
vary greatly with PC board characteristics and cabling.
R3-11
TERMPWR
DB (0-7,P)
R12
R3-20 are
110 Ω 1%
VIN
Low
Dropout
Voltage
Regulator
VOUT
2.85 V
BSY
R14
ACK
C3
.1 µf
Ceramic
25 V
R1
121 Ω
1%
1/4W
R15
RST
R16
MSG
R17
V adj
C1
10 µf
Alum. or
4.7 µf Tant.
15 V
ATN
R13
SEL
R2
154 Ω
1%
1/4W
C2
150 µf
Alum. or
22 µf Tant.
10 V
R18
C/D
R19
REQ
R20
I/O
18681A-68
Figure E-6. Regulated Termination
Am79C974
129
AMD
PRELIMINARY
Termination
Scheme #3
There are three general termination schemes that apply
to motherboard or host adapter setups when using regulated terminators. Each scheme recognizes that the
SCSI bus must be terminated on both ends. Therefore,
as more components and peripherals are added to the
bus, terminators must be relocated accordingly. Each
scheme is also based on an ideal routing situation, that
is one where the internal peripherals, external peripherals and the Am79C974 chip are connected by a linear
SCSI bus. See Figure E-1.
In this case, both internal and external SCSI peripherals
are used. The regulated terminators should be deactivated (since the Am79C974 will sit in the middle of the
SCSI bus). This may be accomplished through hardware or software. The hardware approach involves developing a mechanism to detect peripherals connected
to the SCSI bus. This mechanism must then activate a
signal to turn the regulated terminators on or off accordingly. The software approach involves having the user
tell the system interactively that the regulated terminators should be turned on or off. Care should be taken to
ensure that each end of the Bus is terminated.
Scheme #1
In this case, the system uses only SCSI internal peripherals. The regulated terminators on board should be activated. Peripherals can be added to the bus by
connecting them to a 50-pin ribbon cable. A SCSI terminator should be attached to the last peripheral to terminate the other end of the bus.
Scheme #2
In this case, the system uses only external SCSI peripherals. As in Scheme #1, the on-board regulated terminators should be activated. In this scheme, a 50-pin high
density SCSI-2 cable should connect the external port
on the motherboard or host adapter to the first external
peripheral. Peripherals may be added with more cables
and the last peripheral should be terminated.
130
OTHER CONSIDERATIONS
The following are motherboard considerations for routing and layout. They should be taken into account along
with SCSI considerations.
Motherboards
1. High speed signals should be referenced only to
the ground plane or exclusively to one of the power
planes. If not, the power planes should be
decoupled.
2. For a PCI CLK of 33 MHz, the maximum round trip
time of any shared mother board signal should be
10 ns.
Am79C974
APPENDIX F
Designing a Single Motherboard for AMD
PCI Family
Three devices in the AMD PCI family, the Am53C974,
the Am79C970, and the Am79C794, were designed
with very similar pin assignments so that a single motherboard design could be used for three different products: one with a built-in SCSI controller, one with a
built-in Ethernet controller, and one with both a SCSI
controller and an Ethernet controller. This discussion
describes some implementation details.
Pin Out Differences
bonded to the die inside the device package. These pins
can be driven by any signal without affecting the operation of the device. Those pins that are shown in the PCI
family data sheets as RESERVED are connected to test
logic on the die. These pins are active only during standalone chip testing, and therefore they may also be connected to signals on the board without affecting the
operation of the device. On the other hand, pin 116
which is shown as RESERVED-DNC (for Do Not Connect) must not be connected to anything on the board.
The table below shows the pins that are not the same on
the three devices. All pins that are shown as NC are not
Pin Numbers
Am79C970 (Ethernet)
Function
Am53C974 (SCSI)
Function
Am79C974 (Combination)
Function
9
RESERVED
IDSEL
IDSELA
10
IDSEL
NC
IDSELB
58
RESERVED
PWDN
PWDN
60
NC
SCSICLK1
SCSICLK
68, 69, 70, 71, 73,
74, 75, 77, 78
NC
SCSI data & parity bus
SCSI data & parity bus
64, 65, 66, 80, 81,
83, 85, 86, 87
NC
SCSI control lines
SCSI control lines
89, 90, 92, 93, 94, 95
10Base-T lines
NC
10Base-T lines
97
XTAL1
SCSICLK2
SCSICLK
99
XTAL2
NC
XTAL2
101, 102, 104, 105, 106, 107
AUI lines
NC
AUI lines
110, 111, 112, 114
EEPROM interface &
LED pins
NC
EEPROM interface &
LED pins
115
SLEEP
NC
SLEEP
116
RESERVED_DNC
RESERVED_DNC
RESERVED_DNC
117
INTA
INTA
INTA
118
NC
NC
INTB
126
REQ
NC
REQB
127
RESERVED
REQ
REQA
123
GNT
NC
GNTB
124
NC
GNT
GNTA
INTx (Pins 117 and 118)
The Am79C970 and Am53C974 devices have only one
interrupt output, which is connected to pin 117. The
Am79C974, on the other hand, has two interrupt outputs: INTA, which is used for SCSI interrupts, is
connected to pin 117; while INTB, which is used for
Ethernet interrupts, is connected to pin 118. The
motherboard can connect these pins directly to dedicated inputs to its interrupt controller, or it can connect
Am79C974
131
AMD
PRELIMINARY
them to multiplex logic that can map these outputs to interrupt controller inputs by means of software.
REQ and GNT (pins 123, 124, 126,
and 127)
The Am53C974 uses pins 127 and 124 (REQ and GNT)
for bus master arbitration, while the Am79C790 uses
pins 126 and 123. The Am79C974 uses pins 127 and
124 (REQA and GNTA) for bus arbitration from the SCSI
controller, and it uses pins 126 and 123 (REQB and
GNTB) for arbitration for the Ethernet controller. The
motherboard can connect both pairs of signals to its bus
arbitration logic through jumpers or zero Ohm series resistors. One pair of resistors or jumpers would be omitted for a SCSI only product, and the other pair would be
omitted for an Ethernet only product. Both pairs would
be inserted for a product with both SCSI and Ethernet.
If the motherboard uses a PCI controller that allows a
limited number of bus masters, you may have to omit
one PCI slot or define one slot to be slave only for a product with both SCSI and Ethernet on the motherboard.
IDSEL (Pins 9 and 10)
The Am53C974 uses pin 9 for IDSEL, which is a chip select for the PCI configuration space, while the
Am79C790 uses pin 10 for IDSEL. The Am79C974,
which has two separate configuration spaces, uses pin
9 (IDSELA) to access the configuration space for the
SCSI controller and pin 10 (IDSELB) for the Ethernet
controller. IDSEL is used only during configuration cycles, which are defined by the command on the C/BE
lines during the address phase.
each of the IDSEL pins of the various PCI devices and
expansion slots. Since a typical PCI motherboard will
not have more than 10 PCI devices and slots, two of the
high order address lines can be connected directly to
pins 9 and 10 of the AMD device. The Am79C970 will
respond only to configuration cycles when pin 10 is active and will ignore configuration cycles when pin 9 is active. The Am53C794 will respond only to configuration
cycles when pin 9 is active.
Clocks (Pins 60, 97, and 99)
The Am53C974 requires two clock inputs: SCSICLK1
(pin 60) and SCSICLK2 (pin 97). These clock inputs can
be driven by the same clock source. The Am79C790 requires either a crystal connected to the XTAL1 and
XTAL2 pins (97 and 99) or an external oscillator connected to XTAL1. The Am79C974 requires both a clock
input for SCSICLK (pin 60) and either a crystal connected to the XTAL1 and XTAL2 pins (97 and 99) or an
external oscillator connected to XTAL1.
To satisfy all of these requirements, the motherboard
can connect pin 60 to pin 97 through a jumper or zero
Ohm resistor. For the SCSI only product, the oscillator
or crystal should be omitted and the jumper inserted.
For the Ethernet-only product the oscillator or crystal
should be inserted and the jumper omitted. It does not
matter whether or not the SCSI oscillator is included.
For the combination SCSI plus Ethernet product, the
crystal and the SCSI oscillator should be included, and
the jumper must be omitted.
Figure F-1 illustrates these connections.
A typical way to generate the IDSEL signals on a
motherboard is to connect a separate address line to
132
Am79C974
AMD
PRELIMINARY
99 XTAL2
Crystal
97 XTAL1/SCSICLK2
SCSI
OSC.
60 SCSICLK1
127 REQA
124 GNTA
BUS
Arbiter
Am79C970,
Am53C974,
or
Am79C974
126 REQB
123 GNTB
ADx
9 IDSELA
ADy
10 IDSELB
IRQ1
IRQ2
117 INTA
.
.
.
MUX
118 INTB
IRQ15
MUX
Control
18681A-69
Figure F-1. PCI Family Connections
Am79C974
133
AMD
PRELIMINARY
For information on additional SCSI software products contact:
Sequoia Advanced Technologies, Inc.
(415) 459-7978
(415) 459-7988 FAX
71322, 1020 CompuServe ID
Trademarks
Copyright  1994 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and Am386 are registered trademarks of Advanced Micro Devices, Inc.
GLITCH EATER, PCnet, PCSCSI, HIMIB, MACE, ILACC, IMR+, and Am486 are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
134
Am79C974
AMENDMENT
Am79C974
PCnetTM-SCSI Combination Ethernet and SCSI Controller
for PCI Systems
Advanced
Micro
Devices
This amendment corrects a few minor inaccuracies and adds or clarifies a few sections. Minor corrections should be
made on the existing data sheets. However, for ease of use, pages with more than a word or two of corrections are
printed with this amendment.
Details:
Page 12
(Reprinted as page 5 of this amendment)
CONNECTION DIAGRAM
Change the names of the following power pins:
—
—
—
—
Change from VDD3B to VDDB.
Change from VSS3B to VSSB.
Change from VDDB to VDDBS.
Change from VSSB to VSSBS.
Pages 14–15
(Reprinted as pages 6, 7 of this amendment)
PIN DESIGNATIONS, Listed by Pin Number and Pin Name
Change the names of the following power pins:
—
—
—
—
Change from VDD3B to VDDB.
Change from VSS3B to VSSB.
Change from VDDB to VDDBS.
Change from VSSB to VSSBS.
Page 17
(Reprinted as page 8 of this amendment)
PIN DESIGNATIONS, Quick Reference Pin Description
The number of each type of power pin is incorrect. The numbers should be:
—
—
—
—
Change from VDD to VDD/DVDD, Digital Power, 5 pins
Change from VDDB/VDD3B to VDDB/VDDBS, I/O Buffer Power, 5 pins
Change from VSS to VSS/DVSS, Digital Ground, 9 pins
Change from VSSB/VSS3B to VSSB/VSSBS, I/O Buffer Ground, 11 pins
PIN DESIGNATIONS, Listed By Driver Type
Change the IOH value for both TS3 and TS6 from –0.4 mA to –2.0 mA.
Publication# 18681 Rev. A
Issue Date: April 1994
Amendment /1
AMD
AMENDMENT
Page 19
(Reprinted as page 9 of this amendment)
PIN DESCRIPTION, GNTA
Add after the second paragraph:
The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active
REQA from the Am79C974 controller, the Am79C794 will actively drive the AD[31:00], C/BE[3:0], and PAR lines.
Page 20
Note that INTA and INTB are both open drain pins.
Page 24
Note that ATN is open drain.
Page 25
The number of each type of power pin is incorrect. The numbers should be:
—
—
—
—
VDD/DVDD, Digital Power, 5 pins
VDDB/VDDBS, I/O Buffer Power, 5 pins
VSS/DVSS Digital Ground, 9 pins
VSSB/VSSBS, I/O Buffer Ground, 11 pins
Page 30
The second sentence should read, “It is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer which is initiated by the
host CPU.” (The original omitted “8-bit”).
Page 32
(Reprinted as page 10 of this amendment)
In Figure 6, data on the AD lines should be driven during clock 6 and the second instance of PAR should be driven
during clock 7. In each case this is one cycle earlier than what is shown in the figure.
Page 35
Line 2, change “type 15” to “type 14”.
Page 39
(Reprinted as page 11 of this amendment)
Replace the last two sentences with the following:
“For SCSI, when target aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at offset
54h) is set. For either Ethernet or SCSI a target abort causes RTABORT (bit 12) of the status register in the appropriate
PCI configuration space to be set.” (The original stated that INTA will be asserted.)
Page 42
(Reprinted as page 12 of this amendment)
Replace the last sentence with the following:
“For SCSI, when the master aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at
offset 54h) is set. For either Ethernet or SCSI a master abort causes RMABORT (bit 13) of the status register in the
appropriate PCI configuration space to be set.” (The original stated that INTA will be asserted.)
2
Am79C974
AMENDMENT
AMD
Page 44
Change SPRINTEN to LAPPEN in lines 12 and 13.
Page 54
Line 17, change 100% to 10%.
Page 59
Line 12 should read, “When the Am79C974 controller samples its IDSELA or IDSELB input ...” (The original ommitted
“IDSELA”).
Page 62
Column 2, line 30, change “lower two bytes” to “upper two bytes”.
Page 71
Line 15, change “DRCBC” to “DRCVPA”.
Page 76
(Reprinted as pages 13 and 14 of the amendment)
“DMA BLAST command” section has been extensively revised.
Page 77
(Reprinted as page 15 of this amendment)
The description of the CMD1–0 bits at the end of column 2 should read, “These two bits are encoded to represent four
commands: IDLE, BLAST, START, and ABORT.” (The BLAST command was omitted in the original.)
In the table at the bottom, the description of the IDLE command should read, “Resets the DMA block to the IDLE state.
Stops any current transfer. Does not affect status bits or cause an interrupt.”
Pages 78–80
(Reprinted as pages 16–18 of this amendment)
“DMA Scatter-Gather Operation (4K aligned elements)” section has been extensively revised.
Page 81
Delete lines 19 and 20, which read, “The DMA transfer request was aborted (ABORT command, or the Master or
Target Abort).”
Page 92
ABSOLUTE MAXIMUM RATINGS
Line 4: Add “or VSSBS or DVSS” to read “Supply Voltage to AVSS or VSSB or VSSBS or DVSS”
Line 5: Add “VDDBS, DVDD” to read “(AVDD, VDD, VDDB, VDDBS, DVDD)”
Page 92
OPERATING RANGES
Line 3: Add “VDDBS, DVDD” to read “(AVDD, VDD, VDDB, VDDBS, DVDD)”
After Line 7: Add “or VSSBS –0.5 V ≤ VIN ≤ VDDBS +0.5 V” and “or DVSS –0.5 V ≤ VIN ≤ DVDD +0.5 V”
In the DC Characteristics table, VOL (max) for those pins to which IOL1 or IOL2 applies is 0.55 V (to comply with the PCI
specification) rather than 0.45 V. Also, VOL (max) for those pins to which IOL3 applies is 0.4 V rather than 0.45 V.
Am79C974
3
AMD
AMENDMENT
Page 94
In the DC Characteristics table, delete row 5, VSOL1. Change the parameter symbol for row 6 from VSOL2 to VOL. Add
SD[7:0] and SDP to the parameter description for row 6.
Page 95
In the DC Characteristics table, move “PWDN” from the list of pin names in row 1 as a separate item from PCI input
exceptions. The entry in row 1, column 3 should read, “All SCSI inputs. All Ethernet Inputs. PWDN. All PCI inputs
except IDSEL.”
Page 113
In the Ethernet PCI Configuration Registers table, the default value for the Interrupt pin (row 13, column 5) should be
02h, not 01h.
Page 129
(Reprinted as page 19 of this amendment)
Figure E-5 Decoupling Capacitor Placement
Change the names of the following power pins:
—
—
—
—
4
Change from VDD3B to VDDB.
Change from VSS3B to VSSB.
Change from VDDB to VDDBS.
Change from VSSB to VSSBS.
Am79C974
AMD
AMENDMENT
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
AD28
AD29
VSSB
AD30
AD31
REQA
REQB
VSS
GNTA
GNTB
VDD
CLK
RST
VSS
INTB
INTA
RESERVE
SLEEP
EECS
DVSS
EESK/LED1
EEDI/LNKST
EEDO/LED3
DVDD
AVDD2
CI+
CIDI+
DIAVDD1
DO+
DOAVSS1
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Am79C974
PCnet-SCSI
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXDTXPAVDD4
RXD+
RXDDVSS
I/O
C/D
MSG
VDD
ACK
VSSBS
REQ
SEL
DVSS
SDP
SD7
VDDBS
SD6
SD5
SD4
VSSBS
SD3
SD2
SD1
SD0
VSSBS
PAR
C/BE1
AD15
VSSB
AD14
AD13
AD12
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
VSSB
AD5
AD4
AD3
AD2
VSSB
AD1
AD0
PWDN
VDD
SCSICLK
VSS
BUSY
VSS
BSY
ATN
SCSI^RST
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
IDSELA
IDSELB
VSS
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
18681A/1-3
Pin 1 is marked for orientation.
RESERVE = Don’t Connect.
Am79C974
5
AMENDMENT
AMD
PIN DESIGNATIONS
Listed by Pin Number
6
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
VDDB
34
PAR
67
VSSBS
100
AVSS1
2
AD27
35
C/BE1
68
SD0
101
DO–
3
AD26
36
AD15
69
SD1
102
DO+
4
VSSB
37
VSSB
70
SD2
103
AVDD1
5
AD25
38
AD14
71
SD3
104
DI–
6
AD24
39
AD13
72
VSSBS
105
DI+
7
C/BE3
40
AD12
73
SD4
106
CI–
8
VDD
41
AD11
74
SD5
107
CI+
9
IDSELA
42
AD10
75
SD6
108
AVDD2
10
IDSELB
43
VSSB
76
VDDBS
109
DVDD
11
VSS
44
AD9
77
SD7
110
EEDO/LED3
12
AD23
45
AD8
78
SDP
111
EEDI/LNKST
13
AD22
46
VDDB
79
DVSS
112
EESK/LED1
14
VSSB
47
C/BE0
80
SEL
113
DVSS
15
AD21
48
AD7
81
REQ
114
EECS
16
AD20
49
AD6
82
VSSBS
115
SLEEP
17
VDDB
50
VSSB
83
ACK
116
RESERVE
18
AD19
51
AD5
84
DVDD
117
INTA
19
AD18
52
AD4
85
MSG
118
INTB
20
VSSB
53
AD3
86
C/D
119
VSS
21
AD17
54
AD2
87
I/O
120
RST
22
AD16
55
VSSB
88
DVSS
121
CLK
23
C/BE2
56
AD1
89
RXD–
122
VDD
24
FRAME
57
AD0
90
RXD+
123
GNTB
25
IRDY
58
PWDN
91
AVDD4
124
GNTA
26
TRDY
59
VDD
92
TXP–
125
VSS
27
DEVSEL
60
SCSICLK
93
TXD–
126
REQB
28
STOP
61
VSS
94
TXP+
127
REQA
29
LOCK
62
BUSY
95
TXD+
128
AD31
30
VSS
63
VSS
96
AVDD3
129
AD30
31
PERR
64
BSY
97
XTAL1
130
VSSB
32
SERR
65
ATN
98
AVSS2
131
AD29
33
VDDB
66
SCSI^RST
99
XTAL2
132
AD28
Am79C974
AMD
AMENDMENT
PIN DESIGNATIONS
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
ACK
83
ATN
65
GNTB
123
STOP
28
AD0
57
AVDD1
103
IDSELA
9
TRDY
26
AD1
56
AVDD2
108
IDSEL
10
XTAL1
97
AD2
54
AVDD3
96
INTA
117
XTAL2
99
AD3
53
AVDD4
91
INTB
118
TXD–
93
AD4
52
AVSS1
100
I/O
87
TXD+
95
AD5
51
AVSS2
98
IRDY
25
TXP–
92
AD6
49
BSY
64
LOCK
29
TXP+
94
AD7
48
BUSY
62
MSG
85
VDD
8
AD8
45
C/BE0
47
PAR
34
VDD
59
AD9
44
C/BE1
35
PERR
31
VDD
122
AD10
42
C/BE2
23
PWDN
58
VDDB
1
AD11
41
C/BE3
7
REQ
81
VDDB
17
AD12
40
C/D
86
REQA
127
VDDB
33
AD13
39
CLK
121
REQB
126
VDDB
46
AD14
38
CI–
106
RESERVE
116
VDDBS
76
AD15
36
CI+
107
RST
120
VSS
11
AD16
22
DEVSEL
27
RXD–
89
VSS
30
AD17
21
DI–
104
RXD+
90
VSS
61
AD18
19
DI+
105
SCSICLK
60
VSS
63
AD19
18
DO–
101
SCSI^RST
66
VSS
119
AD20
16
DO+
102
SD0
68
VSS
125
AD21
15
DVDD
84
SD1
69
VSSB
4
AD22
13
DVDD
109
SD2
70
VSSB
14
AD23
12
DVSS
79
SD3
71
VSSB
20
AD24
6
DVSS
88
SD4
73
VSSB
37
AD25
5
DVSS
113
SD5
74
VSSB
43
AD26
3
EECS
114
SD6
75
VSSB
50
AD27
2
EEDI/LNKST
111
SD7
77
VSSB
55
AD28
132
EEDO/LED3
110
SDP
78
VSSB
130
AD29
131
EESK/LED1
112
SEL
80
VSSBS
67
AD30
129
FRAME
24
SERR
32
VSSBS
72
AD31
128
GNTA
124
SLEEP
115
VSSBS
82
Am79C974
7
AMENDMENT
AMD
PIN DESIGNATIONS (continued)
Quick Reference Pin Description
Pin Name
Description
Type
Driver
# Pins
SCSI SPECIFIC
SCSI Interface
SD [7:0]
SCSI Data
IO
OD48
8
SDP
SCSI Data Parity
IO
OD48
1
MSG
Message
C/D
Command/Data
I
1
I/O
Input/Output
I
1
ATN
Attention
O
OD48
1
BSY
Busy
IO
OD48
1
SEL
Select
IO
OD48
1
SCSI^RST
SCSI Bus Reset
IO
OD48
1
REQ
Request
I
ACK
Acknowledge
O
SCSI CLK
SCSI Core Clock
I
1
RESERVE
Reserved, DO NOT CONNECT
I
1
Power Down Indicator
I
1
NAND Tree Test Output
O
O3
1
AVDD
Analog Power
P
NA
4
AVSS
Analog Ground
P
NA
2
VDD, DVDD
Digital Power
P
NA
5
VSS, DVSS
Digital Ground
P
NA
9
VDDB, VDDBS
I/O Buffer Power
P
NA
5
VSSB, VSSBS
I/O Buffer Ground
P
NA
11
I
1
1
OD48
1
Miscellaneous
Power Management
PWDN
Test Interface
BUSY
Power Supplies
Listed by Driver Type
The following table describes the various types of drivers that are implemented in the PCnet-SCSI controller. Current
is given as milliamperes:
Name
IOL (mA)
IOH (mA)
pF
Tri-State
3
–2.0
50
TS6
Tri-State
6
–2.0
50
O3
Totem Pole
3
–0.4
50
O6
Totem Pole
6
–0.4
50
TS3
TM
O8
Totem Pole
8
–0.4
50
OD6
Open Drain
6
NA
50
OD48
Open Drain
48
NA
—
LED
12
–0.4
50
LED
8
Type
Am79C974
AMENDMENT
PIN DESCRIPTION
PCI Bus Interface
AD[31:00]
AMD
CLK
Clock
Input
Address and Data
Input/Output, Active High
These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subsequent clocks AD[31:00] contain data. Byte ordering is little endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnetSCSI controller can be programmed for big endian byte
ordering. See CSR3, bit 2 (BSWP) for more details.
This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-SCSI controller. All bus signals are sampled on
the rising edge of CLK and all parameters are defined
with respect to this edge. The PCnet-SCSI controller operates over a range of 0 to 33 MHz.
When RST is active, CLK is an input for NAND tree
testing.
DEVSEL
Device Select
Input/Output, Active Low
During the address phase of the transaction, when the
PCnet-SCSI controller is a bus master, AD[31:2] will address the active DWORD (double-word). The PCnetSCSI controller always drives AD[1:0] to ‘00’ during the
address phase indicating linear burst order. When the
PCnet-SCSI controller is not a bus master, the
AD[31:00] lines are continuously monitored to determine if an address match exists for I/O slave transfers.
This signal when actively driven by the PCnet-SCSI
controller as a slave device signals to the master device
that the PCnet-SCSI controller has decoded its address
as the target of the current access. As an input it indicates whether any device on the bus has been selected.
During the data phase of the transaction, AD[31:00] are
driven by the PCnet-SCSI controller when performing
bus master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-SCSI controller when
performing bus master reads and slave write
operations.
FRAME
When RST is active, AD[31:0] are inputs for NAND tree
testing.
C/BE [3:0]
When RST is active, DEVSEL is an input for NAND tree
testing.
Cycle Frame
Input/Output, Active Low
This signal is driven by the PCnet-SCSI controller when
it is the bus master to indicate the beginning and duration of the access. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted when the
transaction is in the final data phase.
When RST is active, FRAME is an input for NAND tree
testing.
Bus Command and Byte Enables
Input/Output, Active Low
These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/BE[3:0]
define the bus command. During the data phase
C/BE[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/BE0 applies to byte 0 (AD[07:00]) and C/BE3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND tree
testing.
GNTA
Bus Grant
Input, Active Low
This signal indicates that the access to the bus has been
granted to the Am79C974’s SCSI controller.
The Am79C974 supports bus parking. When the PCI
bus is idle and the system arbiter asserts GNTA without
an active REQA from the Am79C974 controller, the
Am79C974 will actively drive the AD[31:00], C/BE[3:0],
and PAR lines.
When RST is active, GNTA is an input for NAND tree
testing.
Am79C974
9
AMENDMENT
AMD
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C974 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Cycles
All Am79C974 controller non-burst read accesses are of
the PCI command type Memory Read (type 6). Note that
during all non-burst read operations, the Am79C974
controller will always activate all byte enables, even
though some byte lanes may not contain valid data as
indicated by a buffer pointer value. In such instances,
the Am79C974 controller will internally discard unneeded bytes.
Figure 6 shows a typical non-burst read access. The
Am79C974 controller asserts IRDY at clock 5 immediately after the address phase and starts sampling
DEVSEL. The target extends the cycle by asserting
DEVSEL not until clock 6. Additionally, the target inserts
one wait state by asserting its ready (TRDY) at clock 8.
CLK
1
2
3
4
5
6
7
8
9
FRAME
AD
C/BE
PAR
ADDR
0110
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A/1-10
Figure 6. Non-Burst Read Cycles With Wait States
10
Am79C974
AMD
AMENDMENT
Target Abort
Since data integrity is not guaranteed, the Am79C974
controller cannot recover from a target abort event. For
Ethernet, the Am79C974 controller will reset all CSR
and BCR locations to their H_RESET values. Any
on-going network activity will be stopped immediately.
The PCI configuration registers will not be cleared. For
SCSI, when target aborts, INTA will not be asserted, but
the ABORT bit (bit 2 of the DMA status register at offset
54h), is set. For either Ethernet or SCSI a target abort
causes RTABORT (bit 12) of the status register in the
appropriate PCI configuration space to be set.
Figure 13 shows a target abort sequence. The target asserts DEVSEL for one clock. It then deasserts DEVSEL
and asserts STOP on clock 4. A target can use the target
abort sequence to indicate that it cannot service the data
transfer and that it does not want the transaction to be
retried. Additionally, the Am79C974 controller cannot
make any assumption about the success of the previous
data transfers in the current transaction. The
Am79C974 controller terminates the current transfer
with the deassertion of FRAME on clock 5 and one clock
cycle later with the deassertion of IRDY. It finally releases the bus on clock 6.
CLK
1
2
3
4
5
6
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A/1-17
Figure 13. Target Abort
Am79C974
11
AMENDMENT
AMD
Master Abort
The PCI configuration registers will not be cleared. For
SCSI, when the master aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at offset 54h), is set. For either Ethernet or SCSI a
master abort causes RMABORT (bit 13) of the status
register in the appropriate PCI configuration space to
be set.
The Am79C974 controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted within
4 clocks after FRAME is asserted. Master Abort is
treated as a fatal error by the Am79C974 controller. For
the Ethernet, the Am79C974 controller will reset all CSR
and BCR locations to their H_RESET values. Any
on-going network activity will be stopped immediately.
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
C/BE
PAR
ADDR
0111
DATA
0000
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled by the Am79C974 controller.
18681A/1-20
Figure 16. Master Abort
12
Am79C974
AMENDMENT
Since the PCI bus is 4 bytes wide and the SCSI bus is
only 1 byte wide, funneling logic is included in this engine to handle byte alignment and to ensure that data is
properly transferred between the SCSI bus and the
wider PCI bus. All boundary conditions are handled
through hardware by the DMA Engine.
The DMA engine is also designed for block type (4
KByte page) transfers to support scatter-gather operations. Implementation of this feature is described further
in the DMA Scatter-Gather Mechanism section.
DMA FIFO
Data transfers from the SCSI FIFO to the DMA FIFO
take place each time the threshold of two bytes is
reached on the SCSI side. The transfer is initiated by the
SCSI block when the internal DREQ is asserted, and
continues with the DACK handshaking which typically
takes place in DMA accesses. Data is accumulated in
the DMA FIFO until a threshold of 16 DWORD (64 bytes)
is reached. Data is then burst across the PCI bus to
memory. Residue data which is less than the threshold
in each FIFO is sent in non-contiguous bursts. For memory read operations, data is sent in burst mode to the
DMA FIFO and continues through to the SCSI FIFO and
onto the SCSI bus.
DMA BLAST Command
This command is used to retrieve the contents of the
DMA FIFO when the Target disconnects during a DMA
Write operation. This could happen for example if a
SCSI disk drive detected the end of a sector and decided to give up the bus while it was looking for the next
sector. The Target Disconnect can leave some bytes of
data in the DMA FIFO and some in the SCSI FIFO, while
some bytes have yet to be transferred from the peripheral device. When this happens, the controller will assert
INTA to interrupt the processor, the SCSI state machine
will continue to empty its contents into the DMA FIFO,
but the DMA FIFO will not necessarily dump its contents
into memory (unless the 64-byte DMA threshold happens to have been exceeded at this time).
The BLAST command causes the contents of the DMA
FIFO to be emptied into memory. There are some restrictions on when this command should be used.
First, the command should be used only to recover
from an interrupted DMA write operation—not a
read operation.
Second, the command must not be issued until the
SCSI FIFO has finished dumping its contents into
the DMA FIFO.
Third, the command should never be issued when
the DMA FIFO has already been emptied. This is
indicated by the state of the DONE bit in the DMA
STATUS register at ((B)+54h).
AMD
(This is a test for a special case that can occur when a
Target Disconnect leaves only 1 byte left to be transferred from the SCSI peripheral. In this case, if the original transfer count was even, an odd number of bytes will
be left in the SCSI FIFO. Since the SCSI engine transfers data to the DMA FIFO two bytes at a time, the last
transfer consists of one byte of valid data and one byte
of garbage. The DMA engine treats this final invalid byte
as valid data and writes it to memory. When it does this,
it decrements its Working Byte Counter to zero and sets
the DONE bit, even though 1 byte still needs to be retrieved from the peripheral device.)
The following procedure outlines the use of the BLAST
command after an interrupt has occurred. Note that the
order of steps 2–4 is not critical. The order can be
changed to tune the performance. Also note that each
register is read only once in this procedure even though
several tests may be made on data from one register.
1. Verify that INT (bit 7 of the SCSI status register at
((B)+10h) is set to indicate that a SCSI interrupt is
pending.
2. Read the SCSI current FIFO count (bits 4:0 of the
Current FIFO/Internal State register at ((B)+1Ch).
If this value is not zero, wait for the SCSI FIFO to
empty its contents into the DMA FIFO.
3. If bit 4 of the SCSI status register (CTZ) is set,
stop here. The transfer is complete, and it is not
necessary to execute the BLAST command.
4. Verify that DIR (bit 7 of DMA command register at
((B)+40h) is set to one to indicate that the direction
of transfer is from SCSI to memory.
5. Test the error bits in the DMA status register and
the SCSI status register (STATREG at ((B)+10h)
to verify that the contents of the DMA and SCSI
FIFOs are not invalid.
6. Test the DMA DONE bit in the DMA STATUS
register. If DONE is not set, write ‘01’ to the DMA
command register to issue the BLAST command.
This will move the remaining data from the DMA
FIFO into memory.
7. Wait until the BLAST complete (BCMPLT) in the
DMA STATUS register is set to indicate the completion of the BLAST operation.
8. Write ‘00’ to the DMA command register to issue
the IDLE command to the DMA engine. (Note
that the IDLE command does not generate an
interrupt.)
The above procedure insures that the data that has
been transferred from the SCSI peripheral does not get
lost in the DMA FIFO when a Target Disconnect occurs.
However, it does not complete the original transfer. The
software must now read the SCSI Current Transfer
Count register (CTCREG) to find out how many bytes
Am79C974
13
AMENDMENT
AMD
have yet to be transferred from the SCSI peripheral device and must start a new transfer operation to get the
rest of the data. (CTCREG consists of three bytes located at ((B)+00h, (B)+04h, and (B)+38h.)
Logic block via a 32-bit data bus, and the funnel logic
properly reduces this stream of data to a 16-bit stream to
properly interface with the SCSI FIFO.
Funneling Logic
Figure 26 shows the internal DMA logic interface with
the SCSI block. The DMA FIFO interfaces to the Funnel
18681A/1-30
Figure 26. DMA FIFO to SCSI FIFO Interface
SCSI DMA Programming Sequence
5. Issue the START command to the DMA engine
The following section outlines the procedure for executing SCSI DMA operations:
6. At the end of the DMA transaction, issue the IDLE
command to the DMA engine
1. Issue IDLE command to the DMA Engine
MDL Based DMA Programming
2. Configure the SCSI block registers (e.g. synchronous operation, offset values, etc.)
The following section outlines the procedure for executing MDL based DMA operation:
3. Program the DMA registers to set up address and
transfer count
1. Set up the MDL list
4. Issue a transfer command to the SCSI command
registers
14
2. Use the programming sequence defined earlier for
initiating a SCSI DMA transfer
Am79C974
AMENDMENT
DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
AMD
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Configuration Base Address (B) and its corresponding offset
value. The Base address for the Am79C974 is stored at
register address (10h) in the PCI configuration space.
Table 6. The DMA Registers
Register Acronym
Addr (Hex)
Register Description
Type
CMD
(B)+40
Command (bits 31:8 reserved, bits 7:0 used)
R/W
STC
(B)+44
Starting Transfer Count (bits 31:24 reserved, bits 23:0 used)
R/W
SPA
(B)+48
Starting Physical Address (bits 31:0 used)
R/W
WBC
(B)+4C
Working Byte Counter
R
WAC
(B)+50
Working Address Counter (bits 31:0 used)
R
STATUS
(B)+54
Status Register (bits 31:8 reserved, bits 7:0 used)
SMDLA
(B)+58
Starting Memory Descriptor List (MDL) Address
WMAC
(B)+5C
Working MDL Counter
R
Command Register (CMD)
INTE_P:
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Page transfer active interrupt bit.
Address (B)+40h, LSB
7
6
5
4
DIR
INTE_D
INTE_P
MDL
READ/WRITE
3
2
Reserved Reserved
1
CMD1
0
CMD0
R
R/W
MDL:
Memory Descriptor List (MDL) SPA enable bit.
RESERVED:
Reserved for future expansion. The zero value must be
written in these bits.
DIR:
CMD1-0:
Data transfer direction bit.
These two bits are encoded to represent four commands: IDLE, BLAST, START, and ABORT.
INTE_D:
DMA transfer active interrupt bit.
CMD1
CMD0
Command
0
0
IDLE
Description
0
1
BLAST
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
1
0
ABORT
Terminates the current DMA transfer. The DMA engine
should be restored to the ‘IDLE’ state following execution of
this command.
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Note: This is only valid after a ‘START’ command is issued.
1
1
START
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note: This command should be issued only after all other
control bits have been initialized.
Am79C974
15
AMENDMENT
AMD
DMA Scatter-Gather Mechanism
The Am79C974 contains a scatter-gather translation
mechanism which facilitates faster data transfers. This
feature uses a Memory Descriptor List (a list of contiguous physical memory addresses) which is stored in system memory. Use of the Memory Descriptor List allows
a single SCSI transfer to be read from (or written to) noncontiguous physical memory locations. This mechanism avoids copying the transfer data and MDL list,
which was previously required for conventional DMA
operations.
DMA Scatter-Gather Operation
(4k aligned elements)
The scatter-gather mechanism described below
assumes 4k page alignment and size for all MDL entries
except the first and last entry. This feature is enabled by
setting the MDL bit in the DMA Command register (Bit 4,
Address (B)+40h).
1. a) Prepare the Memory Descriptor List (MDL)
through software and store it in system
memory.
b) Load the address of the starting entry in the
Memory Descriptor List (MDL) into the Start
Memory Descriptor List Address (SMDLA)
register. This value is automatically copied into
the Working MDL Address Counter (WMAC).
Memory Descriptor List (MDL)
The MDL is a non-terminated (no End Of File marker)
list of 32-bit page frame addresses, which is always
aligned on a Double Word boundary. The format is
shown below:
31
12 11
Page Frame Address
c) Program the Starting Transfer Count (STC)
register with the total transfer length (i.e., # of
bytes). Also program the Starting Physical
Address (SPA) register (bits 11:0) with the
starting offset of the first entry.
0
Ignored
Note: The value in the SMDLA register must be double
word aligned. Therefore, read/write transactions will always begin on a double word boundary.
31
0
SMDLA
31
MDL
31
12
0
Page Frame Address #1
Ignored
Page Frame Address #2
Ignored
0
WMAC
Page Frame Address #3
Page Frame Address #4
Ignored
Ignored
Page Frame Address #n
Ignored
18681A/1-31
16
Am79C974
AMD
AMENDMENT
In this example, the contents of the WMAC register is
pointing to page frame address #1. When the first entry
in the MDL in read (page frame address #1), the WMAC
register is incremented to point to the next page entry
(page frame address #2).
MDL entry and combines it with the first page offset value in the Starting Physical Address (SPA)
register (bits 11:0). This 32-bit value is loaded into
the Working Address Counter (WAC) register and
becomes the physical address for page#1, as
shown below. The WMAC is then incremented to
point to the next entry in the MDL.
2. Issue the Start DMA Command. The Am79C974
reads the page frame address (bits 31:12) from the
Programmed by
the software
31
SPA
12
XXXX
0
Starting Offset
From the MDL
31
WAC
4K Page #1
12
Page Frame Address #1
0
Starting Offset
Data
18681A/1-32
3. When the WAC register (bits 11:0) reaches the
first 4K byte boundary, the Am79C974 reads the
second MDL entry and combines the page frame
address (bits 31:12) from this entry of the MDL
with bits 11:00 of the WAC register. This becomes
the physical address for page#2. Since the WAC
register (bits 11:0) has rolled over to ‘00h’, the
WAC now points to the beginning of the Page
Frame Address #2 as shown below. The WMAC
is then incremented to point to the next entry in
the MDL.
From the MDL
31
WAC
12
Page Frame Address #2
0
4K Page #2
0
Data
18681A/1-33
Am79C974
17
AMENDMENT
AMD
When WAC (bits 11:0) again reaches the next 4K byte
boundary, the next MDL entry is read into the WAC. The
operation continues in this way until WMAC register
reaches the last MDL entry (Page Frame Address #n in
this example).
4. The WAC register points to the beginning of the last
page#n and the DMA operation continues until the
byte count is exhausted in the Working Byte
Counter (WBC) register. When WBC=0, the chip
stops incrementing the WAC register. This is
shown below.
From the MDL
31
WAC
12
Page Frame Address #n
0
4K Page #n
0
Data
WBC = 0
18681A/1-34
DMA Scatter-Gather Operation
(Non-4k aligned elements MDL not set)
There is another way to implement a scatter-gather operation which does not force the data elements to be
aligned on 4k boundaries. It assumes a “traditional”
scatter-gather list of the following format:
Element 0
Physical Address Byte Count
Element 1
Physical Address Byte Count
...
Element n
Physical Address Byte Count
This second implementation is described as follows:
1. Set the SCSI Start Transfer Count Register
((B)+00h, (B)+04h, (B)+38h) to the Byte count of
the first Scatter-Gather element.
2. Program the DMA Starting Transfer Count Register ((B)+44h) to the Byte Count of the first ScatterGather element.
18
3. Program the DMA Starting Physical Address Register ((B)+48h) to the Physical Address of the first
Scatter-Gather element.
4. Start the SCSI operation by issuing a SCSI Information Transfer command.
5. Start the DMA Engine with DMA Transfer Interrupt
Enable (Bit 6, (B)+40h).
6. When the Scatter-Gather element’s Byte Count
is exhausted, the DMA engine will generate an
interrupt.
7. Reprogram the next Scatter-Gather element’s Byte
Count into the SCSI Start Transfer Count Register
and the DMA Starting Transfer Count Register.
8. Reprogram the DMA Starting Physical Address
Register ((B)+48h) to the Physical Address of the
next Scatter-Gather element.
9. Repeat steps 4–8 until the Scatter-Gather list is
completed.
Am79C974
AMENDMENT
AMD
18681A/1-67
where C1 – C9 are decoupling capacitors.
Figure E-5. Decoupling Capacitor Placement
Am79C974
19