Cypress CY7C1218F-133AC 1-mb (32k x36) pipelined sync sram Datasheet

CY7C1218F
1-Mb (32K x36) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 32K × 36 common I/O architecture
• 3.3V core power supply
• 3.3V I/O operation
• Fast clock-to-output times
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1218F operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP package
• “ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1218F SRAM integrates 32,768 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
Q0
LOGIC
ADSC
ADSP
BWD
DQD,DQD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQB,DQPB
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
OUTPUT
BUFFERS
E
DQA,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05422 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 26, 2004
CY7C1218F
Selection Guide
166 MHz
133 MHz
Unit
Maximum Access Time
3.5
4.0
ns
Maximum Operating Current
240
225
mA
Maximum CMOS Standby Current
40
40
mA
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1218F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Document #: 38-05422 Rev. **
A
A
A
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configuration
Page 2 of 16
CY7C1218F
Pin Definitions
Name
TQFP
I/O
Description
A0, A1, A
InputAddress Inputs used to select one of the 32K address locations. Sampled at the
37,36,
32,33,34,3 Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
5,44,45,46,
sampled active. A1, A0 feed the 2-bit counter.
47,48,81,8
2,99,
100
BWA, BWB
BWC, BWD
93,94,95,9
6
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
GW
88
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of
Synchronous CLK, a global Write is conducted (ALL bytes are written, regardless of the values on
BW[A:D] and BWE).
BWE
87
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
CLK
89
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
CE2
97
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
CE3
92
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA.
Where referenced, CE3 is assumed active throughout this document for BGA.
OE
86
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of a
Read cycle when emerging from a deselected state.
ADV
83
InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted, it automatically increments the address in a burst cycle.
84
InputAddress Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, A is captured in the address registers. A1, A0 are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
85
InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, A is captured in the address registers. A1, A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
64
InputZZ “Sleep” Input, active HIGH. This input, when High places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQA, DQB
DQC, DQD
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,
8,9,12,13,
18,19,22,
23,24,25
28,29,
1,30,51,80
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by “A” during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQP[A:D] are placed in a three-state condition.
CE1
ADSP
DQPA,
DQPB
Document #: 38-05422 Rev. **
Page 3 of 16
CY7C1218F
Pin Definitions (continued)
Name
TQFP
I/O
Description
VDD
15,41,65,
91
Power Supply Power supply inputs to the core of the device.
VSS
17,40,67,
90
Ground
Ground for the core of the device.
VDDQ
4,11,20,
27,54,61,
70,77
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
5,10,21,
26,55,60,
71,76
I/O Ground
Ground for the I/O circuitry.
MODE
31
NC
14,16,38,
39,42,43,
49,50,66
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1218F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
Document #: 38-05422 Rev. **
data is allowed to propagate through the output register and
onto the data bus within tCO if OE is active LOW. The only
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
three-stated during the first cycle of the access. After the first
cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW[A:D]) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW[A:D]
signals. The CY7C1218F provides Byte Write capability that is
described in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[A:D]) input, will selectively write to only the desired bytes.
Bytes not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1218F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE.
Page 4 of 16
CY7C1218F
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a Write to
the desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQs is written into the corresponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Because the CY7C1218F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQs are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1218F provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1, A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to snooze current
This parameter is sampled
tRZZI
ZZ Inactive to exit snooze current
This parameter is sampled
Document #: 38-05422 Rev. **
2tCYC
ns
2tCYC
0
ns
ns
Page 5 of 16
CY7C1218F
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle
Add. Used
ZZ
CE2
DQ
Write
Unselected
None
L
CE3
X
Unselected
None
L
H
Unselected
None
L
X
L
L
L
X
X
X
Three-State
X
Unselected
None
L
H
X
L
H
L
X
X
Three-State
X
Unselected
None
L
X
L
L
H
L
X
X
Three-State
X
Begin Read
External
L
L
H
L
L
X
X
X
Three-State
X
Begin Read
External
L
L
H
L
H
L
X
X
Three-State
Read
Continue Read
Next
L
X
X
X
H
H
L
H
Three-State
Read
Continue Read
Next
L
X
X
X
H
H
L
L
DQ
Read
Continue Read
Next
L
X
X
H
X
H
L
H
Three-State
Read
Continue Read
Next
L
X
X
H
X
H
L
L
DQ
Read
Suspend Read
Current
L
X
X
X
H
H
H
H
Three-State
Read
X
CE1
H
ADSP
X
ADSC
L
ADV
X
OE
X
Three-State
X
X
L
L
X
X
X
Three-State
X
Suspend Read
Current
L
X
X
X
H
H
H
L
DQ
Read
Suspend Read
Current
L
X
X
H
X
H
H
H
Three-State
Read
Suspend Read
Current
L
X
X
H
X
H
H
L
DQ
Read
Begin Write
Current
L
X
X
X
H
H
H
X
Three-State
Write
Begin Write
Current
L
X
X
H
X
H
H
X
Three-State
Write
Begin Write
External
L
L
H
L
H
H
X
X
Three-State
Write
Continue Write
Next
L
X
X
X
H
H
H
X
Three-State
Write
Continue Write
Next
L
X
X
H
X
H
H
X
Three-State
Write
Suspend Write
Current
L
X
X
X
H
H
H
X
Three-State
Write
Suspend Write
Current
L
X
X
H
X
H
H
X
Three-State
Write
ZZ “Sleep”
None
H
X
X
X
X
X
X
X
Three-State
X
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD),BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active(LOW).
Document #: 38-05422 Rev. **
Page 6 of 16
CY7C1218F
Truth Table for Read/Write[2, 3]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Document #: 38-05422 Rev. **
Page 7 of 16
CY7C1218F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Commercial
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to VDDQ + 0.5V
Ambient
Temperature
0°C to +70°C
VDD
3.3V
–5%/+10%
VDDQ
3.3V –5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
3.135
VDD
V
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VIH
Input HIGH Voltage[8]
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VIL
Input LOW
Voltage[8]
VDDQ = 3.3V
–0.3
0.8
V
IX
Input Load Current
except ZZ and MODE
–5
5
µA
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
2.4
5
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CS
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB1
µA
µA
–5
30
µA
5
µA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133 MHz
90
mA
All speeds
40
mA
Input = VDD
IOZ
µA
–30
Input = VDD
Input Current of ZZ
V
–5
ISB2
Automatic CS
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
VDD = Max, Device Deselected, or 6-ns cycle, 166 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 7.5-ns cycle, 133 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
85
mA
75
mA
Automatic CS
Power-down
Current—TTL Inputs
45
mA
ISB4
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05422 Rev. **
Page 8 of 16
CY7C1218F
Thermal Resistance[10]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP
Package
Unit
41.83
°C/W
9.99
°C/W
Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
Capacitance[10]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
Max. Unit
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
5
pF
5
pF
5
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
VL = 1.5V
(a)
ALL INPUT PULSES
VDD
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Note:
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05422 Rev. **
Page 9 of 16
CY7C1218F
Switching Characteristics Over the Operating Range[11, 12]
166 MHz
Parameter
tPOWER
Description
VDD(Typical) to the First Access[13]
Min.
Max
133 MHz
Min.
Max
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
6.0
7.5
ns
tCH
Clock HIGH
2.5
3.0
ns
tCL
Clock LOW
2.5
3.0
ns
Output Times
tCO
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
tCLZ
Clock to Low-Z[14, 15, 16]
tCHZ
High-Z[14, 15, 16]
tOEV
tOELZ
Clock to
OE LOW to Output Valid
OE LOW to Output Low-Z[14, 15, 16]
3.5
ns
2.0
2.0
ns
0
0
ns
3.5
4.0
ns
3.5
4.5
ns
0
[14, 15, 16]
tOEHZ
4.0
0
3.5
OE HIGH to Output High-Z
Set-up Times
ns
4.0
ns
tAS
Address Set-up before CLK Rise
1.5
1.5
ns
tADS
1.5
1.5
ns
1.5
1.5
ns
tWES
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW[A:D] Set-up before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-Up before CLK Rise
1.5
1.5
ns
tADVS
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
ns
0.5
ns
0.5
0.5
ns
tWEH
ADSP , ADSC Hold aAfter CLK Rise
ADV Hold after CLK Rise
GW,BWE, BW[A:D] Hold after CLK Rise
0.5
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
tADH
tADVH
Notes:
11. Timing reference level is 1.5V when VDDQ = 3.3V.
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05422 Rev. **
Page 10 of 16
CY7C1218F
Switching Waveforms
Read Cycle Timing[17]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BW[A:D]
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note:
17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05422 Rev. **
Page 11 of 16
CY7C1218F
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
t CYC
CLK
tCL
tCH
tADS
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A :D]
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A: D] LOW..
Document #: 38-05422 Rev. **
Page 12 of 16
CY7C1218F
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Note:
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
20. GW is HIGH.
Document #: 38-05422 Rev. **
Page 13 of 16
CY7C1218F
Switching Waveforms (continued)
ZZ Mode Timing[21, 22]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in High-Z when exiting ZZ sleep mode.
Ordering Information
Speed
(MHz)
133
Ordering Code
CY7C1218F-133AC
Package
Name
A101
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
Please contact your local Cypress sales representative for availability of the166-MHz speed grade option.
Document #: 38-05422 Rev. **
Page 14 of 16
CY7C1218F
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05422 Rev. **
Page 15 of 16
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1218F
Document History Page
Document Title: CY7C1218F 1-Mb (32K x36) Pipelined Sync SRAM
Document Number: 38-05422
REV.
ECN NO.
Issue Date
Orig. of
Change
**
200661
12/19/03
NJY
Document #: 38-05422 Rev. **
Description of Change
New Data Sheet
Page 16 of 16