ASAHI KASEI [AK4665A] - AK4665A 20-Bit Stereo CODEC with MIC/HP-AMP GENERAL DESCRIPTION The AK4665A is a 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AK4665A includes a microphone/line input selector and an ALC circuit for input, and a stereo line output buffer, analog volume controls and capless stereo headphone amplifier for output. The AK4665A also features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features “pop-free” power-on/off, a mute control and delivers 31mW of power into 16Ω load. The AK4665A is housed in a 32pin QFN package, making it suitable for portable applications. FEATURE 2ch 20bit ADC - Mono MIC-Amp: +30dB/+6dB/0dB/−6dB - Single-ended Input - Input Selector - Digital ALC: +41.25dB ∼ −54dB, 0.375dB Step, Mute - Digital HPF for DC-offset cancellation - I/F format: 20bit MSB justified, I2S - S/N: 93dB 2ch 20bit DAC - Digital ATT: 0dB ∼ −127dB, Mute, 0.5dB step (soft transition) - Soft Mute - Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz - Bass Boost - I/F Format: I2S, 20bit MSB justified, 20bit/16bit LSB justified Sampling Rate: 8kHz ∼ 48kHz System clock: 256fs/512fs Analog Mixing Circuit Stereo Lineout - ALC: +19.5dB ∼ −12dB, 0.5dB step - Analog Volume: 0dB ∼ −30dB, Mute, 2dB step Capless Stereo Headphone Amplifier - Output Power: 31mW x 2ch @16Ω - Line output mode: 1Vrms @10kΩ - Charge pump circuit for negative power supply - S/N: 88dB µP Interface: 3-wire Power Management Power Supply: - AVDD, DVDD, HVDD: 2.6V ∼ 3.6V - TVDD (Digital I/O): 1.6V ∼ 3.6V Power Supply Current: 20mA Ta: −30 ∼ 85°C Small Package: 32pin QFN (5mm x 5mm, 0.5mm pitch) MS0440-E-01 2006/05 -1- ASAHI KASEI [AK4665A] AVDD AVSS VREF VCOM VREF VCOM DVDD DVSS TVDD PMMP MPWR MIC Power PMVCM PMADC MICIN MIC-Amp AINL1 MCLK ADC HPF ALC1 AINR1 BICK PMHPL PMDAC Audio I/F Controller HPL LRCK SDTO HP-Amp DATT DEM SMUTE Boost DAC PMHPR SDTI HPR Control LOUT ATT Register ALC2 CSN CCLK CDTI ROUT PMLO PDN LIN LPF RIN LPF MIN LPF PMHPL or PMHPR or PMLO PMCP HVDD HVSS Charge Pump CP CN NVSS Figure 1. Block Diagram MS0440-E-01 2006/05 -2- ASAHI KASEI [AK4665A] Ordering Guide 32pin QFN (0.5mm pitch) −30 ∼ +85°C Evaluation board for AK4665A AK4665AEN AKD4665A MICIN MPWR AINL1 AINR1 LIN RIN MIN LOUT 24 23 22 21 20 19 18 17 Pin Layout NVSS PDN 29 Top View 12 HVSS CSN 30 11 HVDD CCLK 31 10 CN CDTI 32 9 CP 8 13 DVDD AK4665AEN 7 28 DVSS VREF 6 HPL TVDD 14 5 27 SDTO VCOM 4 HPR SDTI 15 3 26 BICK AVDD 2 ROUT MCLK 16 1 25 LRCK AVSS Comparison Table between AK4569 and AK4665A Function AK4569 HP-Amp Power Supply Single Power Supply HP-Amp Output MIC-Amp MIC-Power ALC for Playback Loopback SDTO Disable Lineout MCLK 8.7mW@16Ω No No Analog MIC: +32 ∼ −19dB, 0.5dB step LINE: +20 ∼ −31dB, 0.5dB step No No No Mono CMOS or AC coupling input Power Supply 2.5 ∼ 3.6V Package 28QFN (5.2mm x 5.2mm, 0.5mm pitch) ALC for Recording MS0440-E-01 AK4665A Dual Power Supply (Single Power Supply as external case) 31mW@16Ω Yes Yes Digital +41.25 ∼ −54dB, 0.375dB step Yes Yes Yes Stereo CMOS input AVDD, DVDD, HVDD: 2.6 ∼ 3.6V TVDD: 1.6 ∼ 3.6V 32QFN (5mm x 5mm, 0.5mm pitch) 2006/05 -3- ASAHI KASEI [AK4665A] PIN/FUNCTION No. Pin Name I/O Function L/R Clock Pin This clock determines which audio channel is currently being output on SDTO pin and input on SDTI pin. Master Clock Input Pin 2 MCLK I Serial Bit Clock Pin 3 BICK I This clock is used to latch audio data. Audio Data Input Pin 4 SDTI I Audio Data Output Pin 5 SDTO O SDTO pin goes to DVSS when PDN pin is “L” or PMADC bit is “0”. 6 TVDD Digital I/O Power Supply Pin 7 DVSS Digital Ground Pin 8 DVDD Digital Power Supply Pin Positive Charge Pump Capacitor Terminal Pin 9 CP O Negative Charge Pump Capacitor Terminal Pin 10 CN I Power Supply Pin for Headphone Amplifier and Charge Pump Circuit 11 HVDD Ground Pin for Headphone Amplifier and Charge Pump Circuit 12 HVSS 13 NVSS O Negative Voltage Output Pin for Headphone Amplifier and Charge Pump Circuit Lch Headphone Amplifier Output Pin 14 HPL O HPL pin goes to AVSS when PMHPL bit is “0”. Rch Headphone Amplifier Output Pin 15 HPR O HPR pin goes to AVSS when PMHPR bit is “0”. Rch Analog Output Pin 16 ROUT O Lch Analog Output Pin 17 LOUT O Mono Analog Input Pin 18 MIN I Rch Analog Input Pin 19 RIN I Lch Analog Input Pin 20 LIN I 21 AINR1 I Rch Analog Input 1 Pin for ADC (LINE Input) 22 AINL1 I Lch Analog Input 1 Pin for ADC (LINE Input) 23 MPWR O MIC Power Supply Pin 24 MICIN I MIC Input Pin 25 AVSS Analog Ground Pin 26 AVDD Analog Power Supply Pin Common Voltage Output Pin, 1.2V (typ, respect to AVSS) 27 VCOM O Normally connected to AVSS pin with a 0.1µF ceramic capacitor in parallel with a 2.2µF electrolytic capacitor. VCOM pin goes to AVSS when PMVCM bit = ”0”. Reference Voltage Output Pin, 2.1V (typ, respect to AVSS) Reference Voltage Output Pin, 2.1V (typ, respect to AVSS) 28 VREF O Normally connected to AVSS pin with a 0.1µF ceramic capacitor in parallel with a 4.7µF electrolytic capacitor. VREF pin goes to AVSS when PMVCM bit = ”0”. Power-down Pin 29 PDN I When “L”, the AK4665A is in power-down mode and is held in reset. The AK4665A should always be reset upon power-up. 30 CSN I Control Data Chip Select Pin 31 CCLK I Control Clock Input Pin 32 CDTI I Control Data Input Pin Note 1. Do not allow digital input pins except analog input pins (MICIN, AINL1, AINR1, LIN, RIN and MIN pins) to float. 1 LRCK I MS0440-E-01 2006/05 -4- ASAHI KASEI [AK4665A] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name HPR, HPL, LOUT, ROUT, MICIN, Analog AINR1, AINL1, MPWR SDTO Digital SDTI Setting These pins should be open. This pin should be open. This pin should be connected to DVSS. ABSOLUTE MAXIMUM RATING (AVSS, DVSS, HVSS=0V; Note 2) Parameter Symbol min max Power Supplies Analog 4.0 AVDD −0.3 4.0 Digital DVDD −0.3 Digital I/O TVDD 4.0 −0.3 HP-AMP HVDD 4.0 −0.3 |AVSS – HVSS| (Note 3) 0.3 ∆GND1 |AVSS – DVSS| (Note 3) 0.3 ∆GND2 Input Current (any pins except for supplies) IIN ±10 Analog Input Voltage (Note 4) VINA (AVDD+0.3) or 4.0 −0.3 Digital Input Voltage (Note 5) VIND (TVDD+0.3) or 4.0 −0.3 85 Ambient Temperature Ta −30 Storage Temperature Tstg 150 −65 Note 2. All voltages with respect to ground Note 3. AVSS, DVSS and HVSS must be connected to the same analog ground plane. Note 4. MIN, RIN, LIN, MICIN, AINR1, AINL1 pins Max is smaller value between (AVDD+0.3)V and 4.0V. Note 5. PDN, CSN, CCLK, CDTI, LRCK, MCLK, BICK, SDTI pins Max is smaller value between (TVDD+0.3)V and 4.0V. Units V V V V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies Analog AVDD 2.6 3.0 3.6 V Digital DVDD 2.6 3.0 3.6 V HP-AMP HVDD 2.6 3.0 3.6 V Digital I/O TVDD 1.6 3.0 DVDD V Difference 0 +0.3 V AVDD−DVDD −0.3 Note 2. All voltages with respect to ground Note 6. If each power supply is gradually switched on or off, some supply current may occur at the other power supply that is still switched on during the supply voltage transition time. Note: AKM assumes no responsibility for usage beyond the conditions in this datasheet. MS0440-E-01 2006/05 -5- ASAHI KASEI [AK4665A] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=HVDD=TVDD=3.0V, AVSS=DVSS=HVSS=0V; fs=44.1kHz; ALC1=DEM =BOOST=ALC2=OFF; ATTL=ATTR=ATTS=0dB; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; unless otherwise specified) Parameter min Typ max Units 20 bit ADC Resolution MIC Amplifier: MICIN pin MGAIN1-0 bits = “00” or “01” 40 60 80 kΩ Input Resistance MGAIN1-0 bits = “10” or “11” 20 30 40 kΩ MGAIN1-0 bits = “00” 1.5 Vpp MGAIN1-0 bits = “01” 3.0 Vpp Input Voltage MGAIN1-0 bits = “10” 0.75 Vpp MGAIN1-0 bits = “11” 0.047 Vpp MGAIN1-0 bits = “00” 0 dB MGAIN1-0 bits = “01” dB −6 Gain MGAIN1-0 bits = “10” +6 dB MGAIN1-0 bits = “11” +30 dB MIC Power Supply: MPWR pin Output Voltage 1.8 2.0 2.2 V Load Resistance 2 kΩ Load Capacitance 30 pF AINL1/AINR1 pins ADC IVOL, IVOL=0dB, ALC1=OFF ADC Analog Input Characteristics: → → 78 90 dB S/(N+D) (−1dBFS) 84 94 dB D-Range (−60dBFS, A-weighted) S/N (A-weighted) 84 94 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 200 ppm/°C Input Voltage 1.35 1.5 1.65 Vpp Input Resistance 40 60 80 kΩ Power Supply Rejection (Note 7) 50 dB 20 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 8) RL =16Ω, HPG bit = “0” S/(N+D) 0dBFS Output, HPG bit = “0”, Po=17mW@16Ω 40 60 dB −3dBFS Output, HPG bit = “1”, Po=31mW@16Ω 20 dB 0dBFS Output, HPG bit = “1”, RL=10kΩ 80 dB 80 88 dB D-Range (−60dBFS Output, A-weighted) S/N (A-weighted) 80 88 dB Interchannel Isolation 60 80 dB Interchannel Gain Mismatch 0.2 1.0 dB Gain Drift 200 ppm/°C Output Voltage 0dBFS Output, HPG bit = “0”, RL=16Ω 1.35 1.5 1.65 Vpp 2.0 Vpp −3dBFS Output, HPG bit = “1”, RL=16Ω 2.83 Vpp 0dBFS Output, HPG bit = “1”, RL=10kΩ Load Resistance 16 Ω Load Capacitance 300 pF Power Supply Rejection (Note 7) 50 dB Note 7. PSR is applied to AVDD, DVDD and HVDD with 1kHz, 50mVpp. Note 8. DACHL=DACHR bits = “1”, MINHL=MINHR=LINHL=RINHR bits = “0”, ATTL7-0=ATTR7-0 bits=0dB. MS0440-E-01 2006/05 -6- ASAHI KASEI [AK4665A] Parameter min Typ max Units Stereo Line Output: (LOUT/ROUT pins) (Note 9) S/(N+D) (0dBFS Output) 72 84 dB S/N (A-weighted) 80 88 dB Interchannel Isolation 70 90 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 200 ppm/°C Output Voltage 1.35 1.5 1.65 Vpp Load Resistance (Note 10) 10 kΩ Load Capacitance 30 pF Power Supply Rejection (Note 7) 50 dB Output Volume (OPGA): (LOUT/ROUT pins) Step Size 1 2 3 dB Gain Control Range 0 dB −30 Analog Input: (LIN/RIN/MIN pins) Input Resistance 100 200 300 kΩ Gain 0 +1 dB LIN→HPL, RIN→HPR, HPG bit = “0”, LING bit = “0” −1 dB LIN→HPL, RIN→HPR, HPG bit = “0”, LING bit = “1” −12 +5.5 dB LIN→HPL, RIN→HPR, HPG bit = “1”, LING bit = “0” dB LIN→HPL, RIN→HPR, HPG bit = “1”, LING bit = “1” −6.5 0 +1 dB MIN→HPL/HPR, HPG bit = “0” −1 +5.5 dB MIN→HPL/HPR, HPG bit = “1” 0 +1 dB LIN/MIN→LOUT, RIN/MIN→ROUT, ATTS=0dB −1 Power Supplies Power Supply Current: AVDD+DVDD+TVDD+HVDD Normal Operation (PDN pin = “H”) (Note 11) 20 30 mA Power-Down Mode (PDN pin = “L”) (Note 12) 1 100 µA Note 9. DACL=DACR bits = “1”, LINL=RINR=MINL=MINR bits = “0”, ATTL7-0=ATTR7-0=ATTS3-0 bits=0dB. Note 10. AC Load Note 11. All blocks are powered-up (MVCM=PMADC=PMDAC=PMHPL=PMHPR=PMLO=PMCP=PMMP bits = “1”), and HP-AMP output is off. Output current of MPWR pin is 0mA. AVDD=12mA(typ), DVDD+TVDD=2mA(typ), HVDD=6mA(typ). 14mA(typ) at playback only (PMVCM=PMDAC=PMHPL=PMHPR=PMLO=PMCP bits = “1”, PMADC bit = “0”), AVDD=6.5mA(typ), DVDD+TVDD=1.5mA(typ), HVDD=6mA(typ). Note 12. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at DVDD or DVSS. PDN pin is held at DVSS. MS0440-E-01 2006/05 -7- ASAHI KASEI [AK4665A] FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD=2.6 ∼ 3.6V; TVDD=1.6∼ 3.6V; fs=44.1kHz; DEM=OFF; BOOST=OFF) Parameter Symbol min typ max Units ADC Digital Filter (LPF): kHz Passband (Note 13) PB 0 17.3 ±0.16dB kHz 19.4 −0.66dB kHz 19.9 −1.1dB kHz 22.1 −6.9dB Stopband (Note 13) SB 26.1 kHz dB Passband Ripple PR ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 14) GD 17 1/fs Group Delay Distortion 0 ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 13) FR 3.4 Hz −3dB 10 Hz −0.5dB 22 Hz −0.1dB DAC Digital Filter: (Note 15) Passband (Note 13) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband (Note 13) SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 14) GD 17.5 1/fs 0 Group Delay Distortion µs ∆GD DAC Digital Filter + Analog Filter: (Note 15) dB FR Frequency Response: 0 ∼ 20.0kHz ±1.0 Analog Filter: (Note 16) FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 BOOST Filter: (Note 17) Frequency Response 20Hz FR dB 5.76 100Hz dB MIN 2.92 1kHz dB 0.02 20Hz FR dB 10.80 100Hz dB MID 6.84 1kHz dB 0.13 20Hz FR dB 16.06 dB MAX 100Hz 10.54 1kHz dB 0.37 Note 13. The passband and stopband frequencies scale with fs. For example (DAC), PB=0.44*fs(@±0.1dB), SB=0.57*fs(@−59dB). Note 14. This is the calculated delay time caused by digital filtering. This time is measured from the input of analog signal to setting the 20 bit data of both channels on input register to the output register of ADC. For DAC, this time is from setting the 20 bit data of both channels on input register to the output of analog signal. Note 15. BOOST OFF (BST1-0 bits = “00”) Note 16. LIN→HPL, RIN→HPR, MIN→HPL/HPR. Note 17. These frequency responses scale with fs. If high-level signal is input, the AK4665A clips at low frequency. MS0440-E-01 2006/05 -8- ASAHI KASEI [AK4665A] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD = 2.6 ∼ 3.6V; TVDD=1.6∼ 3.6V) Parameter Symbol min High-Level Input Voltage 2.2V≤TVDD≤3.6V VIH 70%TVDD 1.6V≤TVDD<2.2V VIH 80%TVDD Low-Level Input Voltage 2.2V≤TVDD≤3.6V VIL 1.6V≤TVDD<2.2V VIL High-Level Output Voltage (Iout= −100µA) VOH TVDD−0.4 Low-Level Output Voltage (Iout= 100µA) VOL Input Leakage Current Iin - MS0440-E-01 typ - max 30%TVDD 20%TVDD 0.4 ±10 Units V V V V V V µA 2006/05 -9- ASAHI KASEI [AK4665A] SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD = 2.6 ∼ 3.6V; TVDD=1.6∼ 3.6V; CL = 20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 2.048 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Timing Frequency fs 8 Duty Cycle Duty 45 Serial Interface Timing (Note 18) BICK Period tBCK 325.5 BICK Pulse Width Low tBCKL 130 Pulse Width High tBCKH 130 tLRB 50 LRCK Edge to BICK “↑” (Note 19) tBLR 50 BICK “↑” to LRCK Edge (Note 19) LRCK to SDTO(MSB) tLRS tBSD BICK “↓” to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” Power-down & Reset Timing PDN Pulse Width (Note 20) tPD 150 tPDV PMADC “↑” to SDTO valid (Note 21) Note 18. Refer to “Serial Data Interface”. Note 19. BICK rising edge must not occur at the same time as LRCK edge. Note 20. The AK4665A can be reset by bringing PDN= “L” to “H” only upon power up. Note 21. This is the count of LRCK “↑” from PMADC bit=”1”. MS0440-E-01 typ max Units - 24.576 - MHz ns ns 44.1 48 55 kHz % - 80 80 - ns ns ns ns ns ns ns ns ns - - ns ns ns ns ns ns ns ns 2081 - ns 1/fs 2006/05 - 10 - ASAHI KASEI [AK4665A] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 2. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 3. Serial Interface Timing MS0440-E-01 2006/05 - 11 - ASAHI KASEI [AK4665A] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL Figure 4. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Figure 5. WRITE Data Input Timing PMADC bit tPDV SDTO 50%TVDD Figure 6. Power Down & Reset Timing 1 tPD PDN VIL Figure 7. Power Down & Reset Timing 2 MS0440-E-01 2006/05 - 12 - ASAHI KASEI [AK4665A] OPERATION OVERVIEW System Clock The external clocks required to operate the AK4665A are MCLK (256fs/512fs), LRCK (fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The sampling frequency is selected by FS3-0 bits (refer to Table 1). The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 2 shows system clock example. FS3 FS2 FS1 FS0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 LRCK fs 8kHz 11.025kHz 12kHz 16kHz 22.05kHz 24kHz 32kHz 44.1kHz 48kHz fs 44.1kHz 32kHz 48kHz 22.05kHz 16kHz 24kHz 11.025kHz 8kHz 12kHz Others N/A Table 1. Sampling Frequency MCLK (MHz) 256fs 512fs 2.048 4.096 2.8224 5.6448 3.072 6.144 4.096 8.192 5.6448 11.2896 6.144 12.288 8.192 16.384 11.2896 22.5792 12.288 24.576 Table 2. Systems Clock Example Default BICK (MHz) 64fs 0.512 0.7056 0.768 1.024 1.4112 1.536 2.048 2.8224 3.072 External clocks (MCLK, BICK and LRCK) are needed to operate ADC, DAC, ALC2 or HP-Amp. External clocks are also needed for each path setting of HP-Amp (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits) and Lineout (DACL, LINL, MINL, DACR, RINR and MINR bits) when MOFF8 bit = “0” or MOFF9 bit = “0”. All external clocks (MCLK, BICK and LRCK) should always be present whenever ADC, DAC, ALC2 or HP-Amp is in normal operation mode (PMADC bit = “1”, PMDAC bit = “1”, PMLO=ALC2 bits = “1” or PMCP=PMHPL=PMHPR bits = “1”). If these clocks are not provided, the AK4665A may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4665A should be placed in power-down mode (PDN pin = “L” or PMADC=PMDAC=ALC2=PMCP=PMHPL=PMHPR bits = “0”). MS0440-E-01 2006/05 - 13 - ASAHI KASEI [AK4665A] For low sampling rates, outband noise causes S/N to degrade. S/N is improved by setting DFS bit to “1”. Table 3 shows S/N of DAC output for both HP-Amp and Stereo-Lineout. When DFS bit is “1”, MCLK needs 512fs. S/N (fs=8kHz, BW=20kHz, A-weighted) HP-amp Lineout 256fs/512fs 84dB 84dB Default 8kHz∼48kHz 512fs 90dB 88dB 8kHz∼24kHz Table 3. Relationship among fs, MCLK frequency and S/N of HP-amp and Lineout DFS fs 0 1 MCLK Serial Data Interface The AK4665A interfaces with external systems via the BICK, LRCK, SDTO and SDTI pins. Four data formats are available and are selected by setting DIF1-0 bits (Table 4). Mode 0 of SDTI is compatible with existing 16bit DAC and digital filters. Mode 1 of SDTI is a 20bit version of Mode 0. Mode 2 of SDTI is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In SDTI Modes 2 and 3, the following formats are also valid: 16-bit data followed by four zeros and 18-bit data followed by two zeros. In all modes, the serial data is MSB first and 2’s complement format. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO SDTI 20bit, MSB justified 16bit, LSB justified 20bit, MSB justified 20bit, LSB justified 20bit, MSB justified 20bit, MSB justified IIS (I2S) IIS (I2S) Table 4. Audio Data Format BICK ≥ 32fs ≥ 40fs ≥ 40fs ≥ 40fs LRCK H/L H/L H/L L/H Default LRCK 0 1 2 16 17 18 19 20 21 31 0 1 2 16 17 18 19 20 21 31 0 1 BICK(64fs) SDTO(o) 19 18 SDTI(i) 4 3 Don’t Care 0 1 2 1 0 15 14 13 12 8 2 9 10 11 19 18 11 12 1 13 14 Don’t Care 0 15 3 4 0 1 2 1 0 15 14 13 2 8 9 10 19 12 11 11 12 1 13 14 0 15 0 1 BICK(32fs) SDTO(o) 19 18 12 11 SDTI(i) 15 14 8 7 10 9 8 7 6 5 4 19 18 6 5 4 3 2 1 0 15 14 Lch Data 12 11 8 7 10 9 8 7 6 5 4 19 6 5 4 3 2 1 0 15 Rch Data Figure 8. Mode 0 Timing MS0440-E-01 2006/05 - 14 - ASAHI KASEI [AK4665A] LRCK 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1 BICK(64fs) SDTO(o) 19 18 SDTI(i) 8 7 Don’t Care 6 0 19 18 12 19 18 11 1 8 7 Don’t Care 0 6 0 19 18 12 Lch Data 19 11 1 0 Rch Data Figure 9. Mode 1 Timing LRCK 0 1 2 15 16 17 18 19 20 30 31 0 1 2 15 16 17 18 19 20 30 31 0 1 BICK(64fs) SDTO(o) 19 18 4 SDTI(i) 16bit 15 14 0 SDTI(i) 18bit 17 16 2 1 0 SDTI(i) 20bit 19 18 4 3 2 3 2 1 0 1 0 19 18 4 3 Don’t Care 15 14 0 Don’t Care 17 16 2 1 0 Don’t Care 19 18 4 3 2 Lch Data 2 1 0 1 19 0 Don’t Care 15 Don’t Care 17 Don’t Care 19 Rch Data Figure 10. Mode 2 Timing LRCK 0 1 2 3 16 17 18 19 20 21 30 31 0 1 2 3 16 17 18 19 20 21 30 31 0 1 BICK(64fs) SDTO(o) 19 18 4 SDTI(i) 16bit 15 14 0 SDTI(i) 18bit 17 16 2 1 0 SDTI(i) 20bit 19 18 4 3 2 3 2 1 1 0 0 19 18 4 Don’t Care 15 14 0 Don’t Care 17 16 2 1 0 Don’t Care 19 18 4 3 2 Lch Data 3 2 1 0 Don’t Care Don’t Care 1 0 Don’t Care Rch Data Figure 11. Mode 3 Timing MS0440-E-01 2006/05 - 15 - ASAHI KASEI [AK4665A] Digital High Pass Filter The AK4665A has a Digital High Pass Filter (HPF) to cancel DC-offsets in ADC. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This filter scales with the sampling frequency (fs). Mono-MIC Gain Amplifier (MICIN pin) The AK4665A has a gain amplifier for mono-mic input. The gain of Mic-Amp is selected by MGAIN1-0 bits (see Table 5). The input impedance is 60kΩ(typ) at MGAIN1-0 bits = “00”, “01” and 30kΩ(typ) at MGAIN1-0 bits = “10”, “11”. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain Input Resistance 0dB 0 60kΩ (typ) 1 60kΩ (typ) −6dB +6dB 0 30kΩ (typ) +30dB 1 30kΩ (typ) Table 5. MIC Input Gain Default MIC Power (MPWR pin) When PMMP bit is “1”, MPWR pin supplies power for the microphone. This output voltage is 2.0V(typ), and the load resistance is minimum 2kΩ. Capacitor must not be connected directly to MPWR pin (see Figure 12). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 6. MIC Power Default MIC Power MPWR ≥ 2kΩ Microphone MICIN MIC-Amp Figure 12. MIC Block Circuit MS0440-E-01 2006/05 - 16 - ASAHI KASEI [AK4665A] Input Selector The AK4665A has 2-input selector for ADC. ADC input is selected by INL1, INR1 and INL2 bits. INL1 bit 1 0 INR1 bit 1 0 INL2 bit Lch 0 AINL1 1 MICIN Table 7. Input Selector Rch AINR1 MICIN Default The input impedance of stereo line input (AINL1 and AINR1 pins) are 60kΩ(typ). Mono-Record Mode When ADM bit is “1”, ADC Lch data is output on both Lch and Rch of SDTO. ADM bit 0 1 Lch Rch L R L L Table 8. Mono-Record Mode MS0440-E-01 Default 2006/05 - 17 - ASAHI KASEI [AK4665A] ALC1 Operation (MIC-ALC) The ALC1 (Automatic Level Control) is done by ALC1 block when ALC1 bit is “1”. 1. ALC1 Limiter Operation During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level (LMTH1-0 bits: Table 9), the IVOL value (same value for Lch and Rch) is attenuated automatically by the ALC1 limiter ATT step (LMAT1-0 bits: Table 10). When ZELMN bit is “0” (zero crossing detection is enabled), the IVOL value is changed by the ALC1 limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both the ALC1 limiter and recovery operation (Table 11). When ZELMN bit is “1” (zero crossing detection is disabled), the IVOL value is immediately (period: 1/fs) changed by the ALC1 limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits. After completing the attenuation operation, unless ALC1 bit is changed to “0”, the operation repeats when the input signal level exceeds ALC1 limiter detection level. LMTH1 0 0 1 1 LMTH0 ALC1 Limier Detection Level ALC1 Recovery Waiting Counter Reset Level 0 ALC1 Output ≥ −4.1dBFS −4.1dBFS > ALC1 Output ≥ −6.0dBFS 1 ALC1 Output ≥ −6.0dBFS −6.0dBFS > ALC1 Output ≥ −8.5dBFS 0 ALC1 Output ≥ −8.5dBFS −8.5dBFS > ALC1 Output ≥ −12dBFS 1 ALC1 Output ≥ −10.1dBFS −10.1dBFS > ALC1 Output ≥ −14.5dBFS Table 9. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level ZELMN 0 1 FS3 0 0 0 1 1 1 1 1 1 FS2 FS1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 Others FS0 0 1 0 0 1 0 0 1 0 LMAT1 LMAT0 ALC1 Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1 step 0.375dB Table 10. ALC1 Limiter ATT Step (x: Don’t care) ZTM=00 (Default) 384/fs (8.7ms) 256/fs (8.0ms) 384/fs (8.0ms) 192/fs (8.7ms) 128/fs (8.0ms) 192/fs (8.0ms) 96/fs (8.7ms) 64/fs (8.0ms) 96/fs (8.0ms) ALC1 Zero Cross Timeout ZTM=01 ZTM=10 768/fs (17.4ms) 512/fs (16.0ms) 768/fs (16.0ms) 384/fs (17.4ms) 256/fs (16.0ms) 384/fs (16.0ms) 192/fs (17.4ms) 128/fs (16.0ms) 192/fs (16.0ms) 1536/fs (34.8ms) 1024/fs (32.0ms) 1536/fs (32.0ms) 768/fs (34.8ms) 512/fs (32.0ms) 768/fs (32.0ms) 384/fs (34.8ms) 256/fs (32.0ms) 384/fs (32.0ms) N/A Table 11. ALC1 Zero Crossing Timeout Period MS0440-E-01 Default Default ZTM=11 3072/fs (69.7ms) 2048/fs (64.0ms) 3072/fs (64.0ms) 1536/fs (69.7ms) 1024/fs (64.0ms) 1536/fs (64.0ms) 768/fs (69.7ms) 512/fs (64.0ms) 768/fs (64.0ms) Default 2006/05 - 18 - ASAHI KASEI 2. [AK4665A] ALC1 Recovery Operation The ALC1 recovery operation waits for WTM1-0 bits (Table 12) to be set after completing the ALC1 limiter operation. If the input signal does not exceed “ALC1 recovery waiting counter reset level” (Table 9) during the wait time, the ALC1 recovery operation is done. The IVOL value (same value for Lch and Rch) is automatically incremented by RGAIN1-0 bits (Table 13) up to the set reference level (Table 14) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 11). The ALC1 recovery operation is done at a period set by WTM1-0 bits. When zero cross is detected at both channels during the wait period set by WTM1-0 bits, the ALC1 recovery operation waits until WTM1-0 period and the next recovery operation is done. The setting period of WTM1-0 bits should be the same as ZTM1-0 bits or longer time. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, the IVOL is changed to 32H by the ALC1 limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When “ALC1 recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC1 recovery operation, the waiting timer of ALC1 recovery operation is reset. When “ALC1 recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. FS3 0 0 0 1 1 1 1 1 1 FS2 FS1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 Others FS0 0 1 0 0 1 0 0 1 0 WTM=00 (Default) 384/fs (8.7ms) 256/fs (8.0ms) 384/fs (8.0ms) 192/fs (8.7ms) 128/fs (8.0ms) 192/fs (8.0ms) 96/fs (8.7ms) 64/fs (8.0ms) 96/fs (8.0ms) ALC1 Recovery Time WTM=01 WTM=10 1536/fs (34.8ms) 1024/fs (32.0ms) 1536/fs (32.0ms) 768/fs (34.8ms) 512/fs (32.0ms) 768/fs (32.0ms) 384/fs (34.8ms) 256/fs (32.0ms) 384/fs (32.0ms) N/A Table 12. ALC1 Recovery Operation Period RGAIN1 0 0 1 1 768/fs (17.4ms) 512/fs (16.0ms) 768/fs (16.0ms) 384/fs (17.4ms) 256/fs (16.0ms) 384/fs (16.0ms) 192/fs (17.4ms) 128/fs (16.0ms) 192/fs (16.0ms) RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 13. ALC1 Recovery GAIN Step MS0440-E-01 WTM=11 3072/fs (69.7ms) 2048/fs (64.0ms) 3072/fs (64.0ms) 1536/fs (69.7ms) 1024/fs (64.0ms) 1536/fs (64.0ms) 768/fs (69.7ms) 512/fs (64.0ms) 768/fs (64.0ms) Default Default 2006/05 - 19 - ASAHI KASEI [AK4665A] REF7-0 GAIN(dB) Step FFH +41.25 FEH +40.875 FDH +40.5 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 14. Reference Level at ALC1 Recovery Operation MS0440-E-01 2006/05 - 20 - ASAHI KASEI 3. [AK4665A] Example for ALC1 Operation Table 15 shows the examples of the ALC1 setting. Register Name Comment LMTH ZELMN ZTM1-0 Limiter detection Level 00 Limiter zero crossing detection 0 Zero crossing timeout period 00 Recovery waiting period *WTM1-0 bits should be the same data 00 8ms as ZTM1-0 bits Maximum gain at recovery operation E1H +30dB Gain of IVOL 91H 0dB Limiter ATT step 00 0.375dB Recovery GAIN step 00 0.375dB ALC1 enable 1 Enable Table 15. Example for the ALC1 setting WTM1-0 REF7-0 IVOL7-0 LMAT1-0 RGAIN1-0 ALC1 Data 8kHz 16kHz 32kHz −4.1dBFS Enable 8ms fs 11.025kHz 22.05kHz 44.1kHz −4.1dBFS Enable 8.7ms 12kHz 24kHz 48kHz −4.1dBFS Enable 8ms 8.7ms 8ms +30dB 0dB 0.375dB 0.375dB Enable +30dB 0dB 0.375dB 0.375dB Enable The following registers should not be changed during the ALC1 operation. These bits should be changed after the ALC1 operation is finished by ALC1 bit = “0” or PMADC bit = “0”. - LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN Example: Limiter = Zero crossing Enable Recovery Cycle = 8ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS Manual Mode WR (IVOL7-0) ALC1 bit = “1” * The value of IVOL should be (1) Addr=05H, Data=91H the same or smaller than REF’s WR (ZTM1-0, WTM1-0) (2) Addr=02H, Data=00H WR (REF7-0) (3) Addr=04H, Data=E1H WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC1= “1”) (4) Addr=03H, Data=20H ALC1 Operation Note : WR : Write Figure 13. Registers set-up sequence at ALC1 operation MS0440-E-01 2006/05 - 21 - ASAHI KASEI [AK4665A] Input Digital Volume (IVOL: Manual Mode) The input digital volume becomes a manual mode when ALC1 bit is “0”. This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVOL7-0 bits set the gain of the volume control (Table 16). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVOL7-0 bits are written during PMADC bit = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADC bit is changed to “1”. IVOL7-0 FFH FEH FDH : 92H 91H 90H : 03H 02H 01H 00H GAIN (dB) Step +41.25 +40.875 +40.5 : +0.375 0.375dB 0.0 −0.375 : −53.25 −53.625 −54 MUTE Table 16. Input Digital Volume MS0440-E-01 Default 2006/05 - 22 - ASAHI KASEI [AK4665A] When writing to IVOL7-0 bits continuously, the control register should be written by an interval more than zero crossing timeout. If not, the IVOL is not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVOL, the write operation is ignored and zero crossing counter is not reset. Therefore, IVOL can be written by an interval less than zero crossing timeout. ALC1 bit ALC1 Status Disable Enable E1H(+ 30dB ) IVOL7-0 bits Internal IVOL Disable E1H(+ 30dB ) E1(+30dB) --> F1(+36dB ) (1) E1(+30dB) (2) Figure 14. IVOL value during ALC1 operation (1) ALC1 operation starts from the IVOL value when ALC1 bit is changed to “1”. The wait time from ALC1 bit = “1” to ALC1 operation start by IVOL7-0 bits is at most recovery time (WTM1-0 bits) plus zero cross timeout period (ZTM1-0 bits). (2) Writing to IVOL register (05H) is ignored during ALC1 operation. After ALC1 is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC1 is enabled again, ALC1 bit should be set to “1” by an interval more than zero crossing timeout period after ALC1 bit = “0”. ADC Output ON/OFF (SDTO pin) SDTO pin becomes “L” when SDOD bit is “1”. SDOD bit SDTO pin 0 Output Default 1 “L” Table 17. ADC Output ON/OFF Digital Loopback ADC output data is internally passed to DAC when LOOP bit is “1”. The external input data to SDTI pin is ignored. This operation is independent of SDOD bit. LOOP bit DAC Input 0 SDTI pin Default 1 ADC Output Table 18. Digital Loopback MS0440-E-01 2006/05 - 23 - ASAHI KASEI [AK4665A] Digital Output Volume (DATT) The AK4665A has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (DATT). At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the Lch level and ATTR7-0 bits control the Rch level. ATTL/R7-0 Attenuation FFH 0dB FEH −0.5dB FDH −1.0dB FCH −1.5dB : : : : 02H −126.5dB 01H −127.0dB 00H Default MUTE (−∞) Table 19. Digital Volume Code Table The ATS bit sets the transition time between set values of ATTL/R7-0 bits as either 1061/fs or 256/fs (Table 20). When ATS bit is “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from “FFH” (0dB) to “00H” (MUTE). When PDN pin is “L”, ATTL/R bits are initialized to “00H”. The ATTL/R bits are “00H” when PMDAC bit is “0”. When PMDAC bit returns to “1”, the ATTL/R bits fade to their current value. ATS bit 0 1 Transition time between ATTL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 20. Transition Time Setting of Digital Output Volume MS0440-E-01 Default 2006/05 - 24 - ASAHI KASEI [AK4665A] Soft Mute (SMUTE) Soft mute operation is performed in the digital domain. When SMUTE bit goes to “1”, the output signal is attenuated by −∞ (“0”) via the cycle set by ATS bit (Table 20). When SMUTE bit returns to “0”, the mute is cancelled and the output attenuation gradually changes to 0dB via the cycle set by ATS bit. If the soft mute is cancelled within the cycle set by ATS bit after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATS bit ATS bit ATTL/R7-0 bits (1) (3) Attenuation -∞ GD (2) GD Analog Output Figure 15. Soft Mute Function Notes: (1) The output signal is attenuated until −∞ (“0”) by the cycle set by ATS bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by ATS bit, the attenuation is discontinued and returned to the setting value by the same cycle. MS0440-E-01 2006/05 - 25 - ASAHI KASEI [AK4665A] De-emphasis Filter (DEM) The AK4665A includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 21). DEM1 0 0 1 1 DEM0 De-emphasis 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 21. De-emphasis Control Bass Boost Function (BOOST) By controlling BST1-0 bits, the bass boost signal can be output from DAC. The setting value is common in Lch and Rch (Table 22). The frequency of bass boost filter scales sampling frequency. BST1 0 0 1 1 BST0 BOOST 0 OFF 1 MIN 0 MID 1 MAX Table 22. Bass Boost Default Boost Filter (fs=44.1kHz) 20 MAX Level [dB] 15 MID 10 MIN 5 0 -5 10 100 1000 10000 Frequency [Hz] Figure 16. Bass Boost Frequency (fs=44.1kHz) MS0440-E-01 2006/05 - 26 - ASAHI KASEI [AK4665A] External Analog Input (LIN, RIN, MIN pins) The input signals from LIN/RIN/MIN pins can be output from headphone and lineout. LIN/RIN/MIN input buffers are 2nd order LPF (fc=50kHz(typ)) in order to attenuate the high frequency noise of external analog input signals. DC component of input signal should be cut by external capacitor. The cut-off frequency (fc) of HPF depends on the internal input resistance (Ri) and the external capacitor value (C): fc=1/(2πRiC). The input resistance is 200kΩ±50%, The gain is 0dB(typ) for both Lineout and HP-Amp (HPG=LING bits = “0”). When HPG bit = “1” and LING bit = “0”, the gain of HP-Amp is −5.5dB(typ). When HPG bit = “0” and LING bit = “1”, the gain of LIN/RIN → HPL/HPR paths are −12dB(typ). LIN/RIN/MIN input buffers powered-up when either bits of PMHPL, PMHPR and PMLO bits become “1”. AK4665A Lineout LIN/RIN/MIN pin − C Ri HP-Amp + Figure 17. External Analog input circuit MS0440-E-01 2006/05 - 27 - ASAHI KASEI [AK4665A] ALC2 Operation (LOUT, ROUT pins) The ALC2 (Automatic Level Control) of stereo line out is done by ALC2 block when ALC2 bit is “1”. The gain of ALC2 block is fixed to 0dB when ALC2 bit is “0”. (1) ALC2 Limiter Operation During the ALC2 limiter operation, when the ALC2 output level exceeds the ALC2 limiter detection level (LMTHP bit: Table 23), the volume value of ALC2 is attenuated automatically by the amount defined by the ALC2 limiter ATT step (LMATP1-0 bits: Table 24). The volume value is changed without zero crossing detection. LTMP1-0 bits (Table 25) set the ALC2 limiter operation period. LMTHP ALC2 Limiter Detection Level ALC2 Recovery Waiting Counter Reset Level 0 ALC2 Output ≥ −7.5dBV −7.5dBV > ALC2 Output ≥ −9.5dBV 1 ALC2 Output ≥ −11.5dBV −11.5dBV > ALC2 Output ≥ −13.5dBV Table 23. ALC2 Limiter Detection Level / Recovery Waiting Counter Reset Level LMATP1 0 0 1 1 FS3 0 0 0 1 1 1 1 1 1 FS2 FS1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 Others FS0 0 1 0 0 1 0 0 1 0 LMATP0 ATT STEP 0 1 step 0.5dB 1 2 step 1.0dB 0 3 step 1.5dB 1 4 step 2.0dB Table 24. ALC2 Limiter ATT step LTMP=00 (Default) 6/fs (136µs) 4/fs (125µs) 6/fs (125µs) 3/fs (136µs) 2/fs (125µs) 3/fs (125µs) 1.5/fs (136µs) 1/fs (125µs) 1.5/fs (125µs) Default ALC2 Limiter Time LTMP=01 LTMP=10 12/fs (272µs) 8/fs (250µs) 12/fs (250µs) 6/fs (272µs) 4/fs (250µs) 6/fs (250µs) 3/fs (272µs) 2/fs (250µs) 3/fs (250µs) Default 24/fs (544µs) 16/fs (500µs) 24/fs (500µs) 12/fs (544µs) 8/fs (500µs) 12/fs (500µs) 6/fs (544µs) 4/fs (500µs) 6/fs (500µs) LTMP=11 48/fs (1088µs) 32/fs (1000µs) 48/fs (1000µs) 24/fs (1088µs) 16/fs (1000µs) 24/fs (1000µs) 12/fs (1088µs) 8/fs (1000µs) 12/fs (1000µs) Default N/A Table 25. ALC2 Limiter Operation Period (2) ALC2 Recovery Operation The ALC2 recovery operation waits for WTMP1-0 bits (Table 26) to be set after completing the ALC2 limiter operation. If the input signal does not exceed “ALC2 recovery waiting counter reset level” (LMTHP bit) during the wait time, the ALC2 recovery operation is done. The ALC2 value is automatically incremented by RGAINP bit (Table 27) up to the set reference level (REFP5-0 bits: Table 28). The ALC2 recovery operation is done at a period set by WTMP1-0 bits. When zero cross is detected at both channels during the wait period set by WTM1-0 bits, the ALC recovery operation waits until WTM1-0 period and the next recovery operation is done. The setting period of WTM1-0 bits should be the same as ZTM1-0 bits or longer time. When MOFF9 bit is “0”, the volume value is incremented with soft transition. The soft transition time is set by PTS1-0 bits (Table 39). The WTMP1-0 bits should be set to the same period as PTS1-0 bits or longer. When MOFF9 bit is “1”, the volume increase immediately. During the ALC2 recovery operation, the ALC2 limiter operation starts immediately as soon as the ALC2 output level exceeds the ALC2 limiter detection level (LMTHP bit). MS0440-E-01 2006/05 - 28 - ASAHI KASEI [AK4665A] When “ALC2 recovery waiting counter reset level ≤ ALC2 Output Signal Level < ALC2 limiter detection level” during the ALC2 recovery operation, the waiting timer of ALC2 recovery operation is reset. When “ALC2 recovery waiting counter reset level > ALC2 Output Signal Level”, the waiting timer of ALC1 recovery operation starts. FS3 0 0 0 1 1 1 1 1 1 FS2 FS1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 Others FS0 0 1 0 0 1 0 0 1 0 WTMP=00 (Default) 768/fs (17.4ms) 512/fs (16.0ms) 768/fs (16.0ms) 384/fs (17.4ms) 256/fs (16.0ms) 384/fs (16.0ms) 192/fs (17.4ms) 128/fs (16.0ms) 192/fs (16.0ms) ALC2 Recovery Time WTMP=01 WTMP=10 1536/fs (34.8ms) 3072/fs (69.7ms) 1024/fs (32.0ms) 2048/fs (64.0ms) 1536/fs (32.0ms) 3072/fs (64.0ms) 768/fs (34.8ms) 1536/fs (69.7ms) 512/fs (32.0ms) 1024/fs (64.0ms) 768/fs (32.0ms) 1536/fs (64.0ms) 384/fs (34.8ms) 768/fs (69.7ms) 256/fs (32.0ms) 512/fs (64.0ms) 384/fs (32.0ms) 768/fs (64.0ms) N/A Table 26. ALC2 Recovery Operation Period WTMP=11 24576/fs (557ms) 16384/fs (512ms) 24576/fs (512ms) 12288/fs (557ms) 8192/fs (512ms) 12288/fs (512ms) 6144/fs (557ms) 4096/fs (512ms) 6144/fs (512ms) Default RGAINP GAIN STEP 0 1 step 0.5dB Default 1 2 step 1.0dB Table 27. ALC2 Recovery Gain Step REFP5-0 GAIN(dB) Step 3FH +19.5 3EH +19.0 3DH +18.5 3CH +18.0 Default : : 19H +0.5 0.5dB 18H 0.0 17H −0.5 : : 02H −11.0 01H −11.5 00H −12.0 Table 28. Reference Level at ALC2 Recovery Operation MS0440-E-01 2006/05 - 29 - ASAHI KASEI [AK4665A] (3) Example for ALC2 Operation Table 29 shows the examples of the ALC2 setting. The ALC2 operation starts from 0dB. Register Name LMTHP LTMP1-0 WTMP1-0 REFP7-0 LMATP1-0 RGAINP PTS1-0 ALC2 8kHz Comment Data 16kHz 32kHz Limiter detection Level 1 −11.5dBV Maximum gain at recovery operation 10 500µs Recovery waiting period 11 512ms Maximum gain at recovery operation 30H +12dB Limiter ATT Step 00 0.5dB Recovery GAIN Step 0 0.5dB ALC2 recovery transition time 11 128ms ALC2 Enable bit 1 Enable Table 29. Example for the ALC2 setting fs 11.025kHz 22.05kHz 44.1kHz −11.5dBV 544µs 557ms +12dB 0.5dB 0.5dB 139ms Enable 12kHz 24kHz 48kHz −11.5dBV 500µs 512ms +12dB 0.5dB 0.5dB 128ms Enable The following registers should not be changed during the ALC2 operation. These bits should be changed after the ALC2 operation is finished by ALC2 bit is “0” or PMLO bit is “0”. - LMTHP, LTMP1-0, LMATP1-0, WTMP1-0, RGAINP, REFP5-0, PTS1-0 Example: Limiter Cycle = 544µs @ fs=44.1kHz Recovery Cycle = 557ms @ fs= 44.1kHz Limiter and Recovery Step = 1 Maximum Gain = +12dB Limiter Detection Level = −11.5dBV Recovery Transition Time = 139ms @ fs=44.1kHz ALC2=OFF ALC2 bit = “1” WR (LMATP1-0, RGAINP, WT MP1-0) (1) Addr=12H, Data=18H WR (LMTHP, LTMP1-0) (2) Addr=13H, Data=18H WR (REFP5-0) (3) Addr=11H, Data=30H WR (PTS1-0) (4) Addr =14H, Data=C0H WR (ALC2= “1”) (5) Addr=12H, Data=38H ALC2 Operation Note : WR : Write Figure 18. Registers set-up sequence at ALC2 operation MS0440-E-01 2006/05 - 30 - ASAHI KASEI [AK4665A] Output Analog Volume (LOUT, ROUT pins) When the LMUTE bit is “0”, ATTS3-0 bits (0dB ∼ −30dB, 2dB step, Table 30) control the LOUT/ROUT output level. Some pop noise occurs at the changing of output volume of LOUT/ROUT. LMUTE ATTS3-0 Attenuation FH 0dB EH −2dB DH −4dB CH −6dB 0 : : : : 1H −28dB 0H −30dB 1 x MUTE Default Table 30. LOUT/ROUT Volume ATT (x: Don’t care) Stereo Line Output (LOUT, ROUT pins) The common voltage is VCOM, and the load resistance is min. 10kΩ. Stereo Lineout is powered-up when PMLO bit is “1”. The ON/OFF of each path is set by DACL, LINL, MINL, DACR, RINR and MINR bits. When ALC2 bit is “0” and ATTS3-0 bits is “FH”(0dB), the summation gain of each path is 0dB (typ). LIN/RIN pin LINL/RINR bit ALC2 OPGA LOUT/ ROUT pin MIN pin MINL/MINR bit DACL/DACR DACL/DACR bit Figure 19. LOUT/ROUT Summation Circuit (L+R)/2 signal of DAC is output from LOUT and ROUT pins when LOM bit is “1”. DACL 0 1 LOM bit LOUT pin x Path OFF 0 L 1 (L+R)/2 Table 31. Line Output Mode (Lch) DACR 0 1 LOM bit ROUT pin x Path OFF 0 R 1 (L+R)/2 Table 32. Line Output Mode (Rch) MS0440-E-01 Default Default 2006/05 - 31 - ASAHI KASEI [AK4665A] Headphone Output (HPL/HPR pins) Power supply voltage for headphone amplifiers is applied from HVDD pin for the positive supply and the negative supply generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and centered on 0V (AVSS). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 16Ω. HPG bit set the output voltage (Table 33). HPG bit 0 1 Output Voltage Output Power 1.5Vpp@0dBFS 17mW@16Ω 2.0Vpp@−3dBFS 31mW@16Ω Table 33. Headphone Output Voltage / Power Default The headphone output is enabled when HPMTN bit is “1” and muted when HPMTN bit is “0”. The mute ON/OFF time are set by PTS1-0 bits (Table 39) when MOFF8 bit is “0”. When MOFF8 bit is “1”, the ON/OFF is done immediately. When PMHPL and PMHPR bits are “0”, the headphone amplifiers are powered-down completely. At that time, the HPL and HPR pins are AVSS voltage. The power-up/down time are set by PUT1-0 bits (Table 38) when MOFF0 bit is “0”. When MOFF0 bit is “1”, the power up/down is done immediately. PMHPL/R bits 0 1 HPMTN bit HP-Amp x Power-down 0 Power-up & Mute 1 Power-up & Output Table 34. Headphone output states Default The ON/OFF of each path is set by DACHL, LINHL, MINHL, DACHR, RINHR and MINHR bits. The summation gain of each path is 0dB (typ) at HPG bit = “0” and +5.5dB (typ) at HPG bit = “1”. LIN/RIN pin LINHL/RINHR bit HPL/HP R pin MIN pin MINHL/MINHR bit DACL/DACR DACHL/DACHR bit Figure 20. The Summation Circuit of Headphone Output (L+R)/2 signal of DAC is output from HPL and HPR pins when HPM bit is “1”. DACHL 0 1 HPM bit HPL pin x Path OFF 0 L 1 (L+R)/2 Table 35. Headphone Output Mode (Lch) DACHR 0 1 HPM bit HPR pin x Path OFF 0 R 1 (L+R)/2 Table 36. Headphone Output Mode (Rch) MS0440-E-01 Default Default 2006/05 - 32 - ASAHI KASEI [AK4665A] Transition Time The power-up/down time of HP-Amp at the change of PMHPL/R bits is set by PUT1-0 bits (Table 38). The mute ON/OFF timing of HP-Amp, the ON/OFF timing of output path for HPL/HPR and LOUT/ROUT, and the gain changing at ALC2 recovery operation are changed by the soft transition respectively. The transition time is set by PTS1-0 bits (Table 39). The register value of same address must be changed by an interval more than transition time. The Enable/Disable for the soft transition is set by MOFF0, MOFF8 and MOFF9 bits (Table 37). The soft transition is disabled while these bits are “1”, and ON/OFF is done immediately. As shown in Table 37, if the soft transition is enabled, the register value of same address must be changed by an interval more than transition time. The write operation is ignored if the same values are written as the previous write operation. PUT1-0 bits Address 00H 08H PTS1-0 bits 09H FS3 0 0 0 1 1 1 1 1 1 FS3 0 0 0 1 1 1 1 1 1 FS2 FS1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 Others FS2 FS1 FS0 0 1 0 0 1 0 0 1 0 FS0 Register Name PMHPL, PMHPR bits DACHL, LINHL, MINHL, DACHR, RINHR, MINHR, HPMTN bits DACL, LINL, RINR, MINL, DACR, MINR bits Table 37. Registers with Transition Time PUT=00 (Default) 770/fs (17.5ms) 514/fs (16.1ms) 770/fs (16.1ms) 386/fs (17.5ms) 258/fs (16.1ms) 386/fs (16.1ms) 194/fs (17.6ms) 130/fs (16.3ms) 194/fs (16.2ms) Power-up/down Time PUT=01 PUT=10 1538/fs (34.9ms) 3074/fs (69.7ms) 1026/fs (32.1ms) 2050/fs (64.1ms) 1538/fs (32.1ms) 3074/fs (64.1ms) 770/fs (34.9ms) 1538/fs (69.8ms) 514/fs (32.1ms) 1026/fs (64.1ms) 770/fs (32.1ms) 1538/fs (64.1ms) 386/fs (35.0ms) 770/fs (69.8ms) 258/fs (32.3ms) 514/fs (64.3ms) 386/fs (32.2ms) 770/fs (64.2ms) N/A Table 38. HP-Amp Power-up/down Time PTS=00 (Default) 768/fs (17.4ms) 512/fs (16.0ms) 768/fs (16.0ms) 384/fs (17.4ms) 256/fs (16.0ms) 384/fs (16.0ms) 192/fs (17.4ms) 128/fs (16.0ms) 192/fs (16.0ms) Transition Time PTS=01 PTS=10 Enable/Disable MOFF0 bit MOFF8 bit MOFF9 bit PUT=11 6146/fs (139ms) 4098/fs (128ms) 6146/fs (128ms) 3074/fs (139ms) 2050/fs (128ms) 3074/fs (128ms) 1538/fs (140ms) 1026/fs (128ms) 1538/fs (128ms) PTS=11 0 0 0 1536/fs (34.8ms) 3072/fs (69.7ms) 6144/fs (139ms) 0 0 1 1024/fs (32.0ms) 2048/fs (64.0ms) 4096/fs (128ms) 0 1 0 1536/fs (32.0ms) 3072/fs (64.0ms) 6144/fs (128ms) 0 0 0 768/fs (34.8ms) 1536/fs (69.7ms) 3072/fs (139ms) 0 0 1 512/fs (32.0ms) 1024/fs (64.0ms) 2048/fs (128ms) 0 1 0 768/fs (32.0ms) 1536/fs (64.0ms) 3072/fs (128ms) 1 0 0 384/fs (34.8ms) 768/fs (69.7ms) 1536/fs (139ms) 1 0 1 256/fs (32.0ms) 512/fs (64.0ms) 1024/fs (128ms) 1 1 0 384/fs (32.0ms) 768/fs (64.0ms) 1536/fs (128ms) Others N/A Table 39. HP-Amp Mute ON/OFF, Path ON/OFF & ALC2 Recovery Transition Time MS0440-E-01 Default Default 2006/05 - 33 - ASAHI KASEI [AK4665A] Charge Pump Circuit The internal charge pump circuit generates negative voltage from HVDD voltage. The generated voltage is used to headphone amplifier. When PMCP bit is set to “1”, the charge pump circuit is powered-up. All clocks (MCLK, BICK and LRCK) should be supplied at this time. The power-up time of charge pump circuit depends on FS3-0 bits (Table 40). Power up time of Charge Pump Circuit 0 0 512/fs = 11.6ms 44.1kHz 0 1 256/fs = 8.0ms 32kHz 1 0 512/fs = 10.7ms 48kHz 0 0 256/fs = 11.6ms 22.05kHz 0 1 128/fs = 8.0ms 16kHz 1 0 256/fs = 10.7ms 24kHz 0 0 128/fs = 11.6ms 11.025kHz 0 1 64/fs = 8.0ms 8kHz 1 0 128/fs = 10.7ms 12kHz Others N/A N/A Table 40. Power up time of Charge Pump Circuit FS3 FS2 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 FS1 FS0 fs Default System Reset The AK4665A should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, all blocks (VCOM, ADC, DAC, HPL, HPR, Lineout and charge pump circuit) switch to the power-down state. The contents of the control register are maintained until the reset is done. ADC exits reset and power down state after PMADC bit is changed to “1”, and then ADC is powered-up and the internal timing starts clocking by LRCK edge. ADC is in power-down mode until MCLK and LRCK are input. DAC also exits reset and power down state when MCLK and LRCK are input after PMDAC bit is changed to “1”. MS0440-E-01 2006/05 - 34 - ASAHI KASEI [AK4665A] Power-Up/Down Sequence 1) ADC (MICIN) Power Supply (1) >150ns PDN pin (2) >0 FS3-0, DFS bits 0H, 0 XH, X 0H, 0 (3) >0 PMVCM bit (5) Clock Input PMADC bit ADC Internal State Don’t care Don’t care (4) >0 (7) 2081/fs PD(Power-down)Init Cycle Normal Operation PD (Hi-Z) (6) MICIN pin (Hi-Z) (8) GD (8) GD SDTO pin Figure 21. Power-up/down Sequence of ADC (1) (2) (3) (4) (5) (6) PDN pin should be set to “H” at least 150ns after the power is supplied. FS3-0 and DFS bits should be set after PDN pin goes to “H”. PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set. PMADC bit should be changed to “1” after PMVCM bit is changed to “1”. External clocks (MCLK, BICK and LRCK) are needed to operate ADC. When PMADC bit is changed to “1”, MICIN pin is biased to VCOM voltage. Rising time constant is determined by input capacitor for AC coupling and input resistance. In case of 0.22µF input capacitor, time constant is τ = 0.22µF x 30kΩ = 6.6ms (typ) at MGAIN1 bit = “1” τ = 0.22µF x 60kΩ = 13.2ms (typ) at MGAIN1 bit = “0” (7) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state. SDTO is “L” at that time. (8) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µs@fs=44.1kHz). MS0440-E-01 2006/05 - 35 - ASAHI KASEI [AK4665A] 2) ADC (Line In: in case of common jack with headphone) Power Supply (1) >150ns PDN pin (2) >0 FS3-0, DFS bits 0H, 0 XH, X 0H, 0 (3) >0 PMVCM bit (4) >0 (10) PMCP bit (5) Don’t care Clock Input Don’t care 0V 0V −HVDD NVSS pin PMADC bit (6) >0 ADC Internal State (8) 2081/fs PD(Power-down) Init Cycle Normal Operation PD (Hi-Z) (7) (Hi-Z) AINL1/R1 pins (9) GD (9) GD SDTO pin PMHPL/R bits (11) Figure 22. Power-up/down Sequence of ADC (1) (2) (3) (4) PDN pin should be set to “H” at least 150ns after the power is supplied. FS3-0 and DFS bits should be set after PDN pin goes to “H”. PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set. PMCP bit should be changed to “1” after PMVCM bit is changed to “1”. The charge pump circuit is powered-up and NVSS pin goes to –HVDD voltage according to the setting of FS3-0 and DFS bits. (5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit and ADC. (6) PMADC bit should be changed to “1” after NVSS pin goes to –HVDD voltage. (7) When PMADC bit is changed to “1”, AINL1/R1 pins are biased to VCOM voltage. Rising time constant is determined by input capacitor for AC coupling and input resistance. In case of 1µF input capacitor, time constant is τ = 1µF x 60kΩ = 60ms (typ) (8) The analog part of ADC is initialized during 2081/fs (=47ms@fs=44.1kHz) after exiting the power-down state. SDTO is “L” at that time. (9) Digital output corresponding to analog input has the group delay (GD) of 17/fs (=385µs@fs=44.1kHz). (10) When PMCP bit is changed to “0”, the charge pump circuit is powered-down and NVSS pin becomes 0V. Falling time constant is determined by capacitor and internal resistance (typ 17.5kΩ). In case of 2.2µF capacitor, time constant is τ = 2.2µF x 17.5kΩ = 38.5ms (typ) (11) When PMHPL/R bits = “0”, HPL/R pins are connected to AVSS with internal pull-down resistance (typ 100kΩ). MS0440-E-01 2006/05 - 36 - ASAHI KASEI [AK4665A] 3) DAC → HP-Amp Power Supply (1) >150ns PDN pin (2) >0 FS3-0, DFS bits 0H, 0 PUT1-0 bits PTS1-0 bits 00, 00 XH, X 0H, 0 XX, XX 00, 00 (3) >0 PMVCM bit (4) >0 DACHL bit DACHR bit (5) Clock Input Don’t care Don’t care (14) (6) >0 PMCP bit 0V 0V −HVDD NVSS pin PMDAC bit DAC Internal State Normal Operation PD PD SDTI pin PMHPL/R bits (11) HPMTN bit HP-Amp State ATTL/R7-0 bits MT PD Normal Operation FFH(0dB) 00H(MUTE) (7) (8) (9) GD (10) 1061/fs (9) (10) MT PD 00H(MUTE) (12) (13) HPL/R pins Figure 23. Power-up/down Sequence of DAC and HP-Amp (1) (2) (3) (4) PDN pin should be set to “H” at least 150ns after the power is supplied. FS3-0, DFS, PUT1-0 and PTS1-0 bits should be set after PDN pin goes to “H”. PMVCM bit should be changed to “1” after FS3-0, DFS, PUT1-0 and PTS1-0 bits are set. DACHL and DACHR bits should be changed to “1” after PMVCM bit is changed to “1”. Each path is switched-on during the transition time set by FS3-0 and PTS1-0 bits. (5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit, HP-Amp or DAC. External clocks are also needed for each path (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits) setting. (6) PMCP, PMDAC, PMHPL and PMHPR bits should be changed to “1” after DACHL and DACHR bits are changed to “1”. When PMCP bit is changed to “1”, the charge pump circuit is powered-up and NVSS pin goes to −HVDD voltage according to the setting of FS3-0 and DFS bits (7) After power-up of the charge pump circuit, HP-Amp is powered-up. Rising time of HP-Amp is determined by FS3-0, DFS and PUT1-0 bits. (8) HPMTN bit should be changed to “1” to release the mute after HP-Amp is powered-up. The transition time of mute release is determined by FS3-0,DFS and PTS1-0 bits. (9) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397µs@fs=44.1kHz). (10) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz). (11) HPMTN bit should be changed to “0” to mute HP-Amp. (12) After the transition time for mute, PMDAC, PMHPL and PMHPR bits should be changed to “0” to power-down of DAC and HP-Amp. (13) After power-down of the HP-Amp, PMCP bit should be changed to “0” to power-down the charge pump circuit. Falling time constant is determined by external capacitor connected with NVSS pin and internal resistance (typ 17.5kΩ). In case of 2.2µF capacitor, time constant is τ = 2.2µF x 17.5kΩ = 38.5ms (typ) (14) Clocks should be stopped after PMCP bit is changed to “0”. MS0440-E-01 2006/05 - 37 - ASAHI KASEI [AK4665A] 4) DAC → Line Out Power Supply (1) >150ns PDN pin (2) >0 DACL, DACR bits PMVCM bit (4) Clock Input Don’t care Don’t care PMDAC bit (3) >0 DAC Internal State PD Normal Operation PD(Power-down) SDTI pin PMLO bit ATTL/R7-0 bit LMUTE, ATTS3-0 bits FFH(0dB) 00H(MUTE) (6) GD (Hi-Z) 10H 0FH(0dB) 10H(MUTE) LOUT/ROUT pins 00H(MUTE) (5) (7) 1061/fs (6) (7) (5) (Hi-Z) Figure 24. Power-up/down Sequence of DAC and Line Out (1) PDN pin should be set to “H” at least 150ns after the power is supplied. (2) DACL and DACR bits should be changed to “1” after PDN pin goes to “H”. Each path is switched-on during the transition time set by FS3-0 and PTS1-0 bits. (3) PMDAC and PMLO bits should be changed to “1” after DACL and DACR pins are changed to “1”. (4) External clocks (MCLK, BICK and LRCK) are needed to operate DAC. External clocks are also needed for each path (DACL, LINL, MINL, DACR, RINR and MINR bits) setting. (5) When PMLO bit is changed to “1”, pop noise is output from LOUT/ROUT pins. (6) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397µs@fs=44.1kHz). (7) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz). MS0440-E-01 2006/05 - 38 - ASAHI KASEI [AK4665A] 5) LIN/RIN/MIN → HP-Amp Power Supply (1) >150ns PDN pin (2) >0 FS3-0, DFS bits 0H, 0 PUT1-0 bits PTS1-0 bits 00, 00 XH, X 0H, 0 XX, XX 00, 00 (3) >0 PMVCM bit (4) >0 LINHL, MINHL, RINHR, MINHR bits (5) Clock Input Don’t care Don’t care (13) (6) >0 PMCP bit 0V 0V −HVDD NVSS pin (Hi-Z) (7) LIN/RIN/MIN pins (Hi-Z) PMHPL/R bits (10) HPMTN bit HP-Amp State PD MT Normal Operation (8) (9) MT PD (11) (12) HPL/R pins Figure 25. Power-up/down Sequence of LIN/RIN/MIN and HP-Amp (1) (2) (3) (4) PDN pin should be set to “H” at least 150ns after the power is supplied. FS3-0, DFS, PUT1-0 and PTS1-0 bits should be set after PDN pin goes to “H”. PMVCM bit should be changed to “1” after FS3-0, DFS, PUT1-0 and PTS1-0 bits are set. LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. Each path is switched-on during the transition time set by FS3-0 and PTS1-0 bits. (5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit and HP-Amp. External clocks are also needed for each path (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits) setting. (6) PMCP, PMHPL and PMHPR bits should be changed to “1” after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. When PMCP bit is changed to “1”, the charge pump circuit is powered-up and NVSS pin goes to −HVDD voltage according to the setting of FS3-0 and DFS bits. (7) When PMHPL, PMHPR or PMLO bit is changed to “1”, LIN, RIN and MIN pins are biased to VCOM voltage. Rising time constant is determined by capacitor for AC coupling and input resistance 200kΩ (typ). In case of 0.047µF input capacitor, time constant is τ = 0.047µF x 200kΩ = 9.4ms (typ) (8) After power-up the charge pump circuit, HP-Amp is powered-up. Rising time of HP-Amp is determined by FS3-0,DFS and PUT1-0 bits. (9) HPMTN bit should be changed to “1” to release the mute after HP-Amp is powered-up. The transition time of mute release is determined by FS3-0,DFS and PTS1-0 bits. (10) HPMTN bit should be changed to “0” to mute HP-Amp. (11) After the transition time for mute, PMHPL and PMHPR bits should be changed to “0” to power-down of HP-Amp. (12) After power-down of the HP-Amp, PMCP bit should be changed to “0” to power-down of the charge pump circuit. Falling time constant is determined by external capacitor connected with NVSS pin and internal resistance (typ 17.5kΩ). In case of 2.2µF capacitor, time constant is τ = 2.2µF x 17.5kΩ = 38.5ms (typ) (13) Clocks should be stopped after PMCP bit is changed to “0”. MS0440-E-01 2006/05 - 39 - ASAHI KASEI [AK4665A] Serial Control Interface Internal registers may be written via the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of Chip address (2bits, Fixed to “10”), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Data is clocked in on the rising edge of CCLK. For write operations, data is latched on the rising edge of 16th clock of CCLK. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN= “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “10”) Read/Write (Fixed to “1”: Write only) Register Address Control Data Figure 26. Control Interface MS0440-E-01 2006/05 - 40 - ASAHI KASEI [AK4665A] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H Register Name Power Management Input Select Timer Select ALC1 Mode Control 1 ALC1 Mode Control 2 IVOL Control Mode Control 1 DAC Control HP Output Select Line Output Select DAC Lch ATT DAC Rch ATT Lineout ATT Test 1 Test 2 Test 3 Test 4 ALC2 Mode Control 1 ALC2 Mode Control 2 Mode Control 2 Mode Control 3 D7 MOFF0 D6 0 0 MGAIN1 MGAIN0 RGAIN1 LMTH1 REF7 IVOL7 0 0 MOFF8 MOFF9 ATTL7 ATTR7 0 TEST7 TEST7 TEST7 TEST7 0 HPG 0 PTS1 REF6 IVOL6 0 0 PMCP D5 PMLO PMMP ZTM1 ALC1 REF5 IVOL5 0 D4 D3 D2 D1 D0 PMHPR PMHPL PMDAC PMADC PMVCM ADM ZTM0 0 WTM1 INR1 WTM0 INL2 0 INL1 0 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 REF4 IVOL4 ATS REF3 IVOL3 HPM BST1 REF2 IVOL2 DIF1 BST0 REF1 IVOL1 DIF0 DEM1 REF0 IVOL0 DFS DEM0 HPMTN SMUTE MINHR DATTC RINHR DACHR MINHL LINHL DACHL LOM ATTL6 ATTR6 0 TEST6 TEST6 TEST6 TEST6 0 LING 0 PTS0 MINR ATTL5 ATTR5 0 TEST5 TEST5 TEST5 TEST5 REFP5 ALC2 0 PUT1 DACR ATTL4 ATTR4 MINL ATTL3 ATTR3 RINR ATTL2 ATTR2 LINL ATTL1 ATTR1 DACL ATTL0 ATTR0 LMUTE ATTS3 ATTS2 ATTS1 ATTS0 TEST4 TEST4 TEST4 TEST4 REFP4 TEST3 TEST3 TEST3 TEST3 REFP3 TEST2 TEST2 TEST2 TEST2 REFP2 TEST1 TEST1 TEST1 TEST1 REFP1 TEST0 TEST0 TEST0 TEST0 REFP0 WTMP1 WTMP0 LMATP1 LMATP0 RGAINP LMTHP LTMP1 FS3 LTMP0 FS2 SDOD FS1 LOOP FS0 PUT0 All registers inhibit writing at PDN pin = “L”. Note: Unused bits must contain a “0” value. Note: For addresses from 0DH to 10H and from 15H to 1FH, “0”data must be written. MS0440-E-01 2006/05 - 41 - ASAHI KASEI [AK4665A] Register Definitions Addr 00H Register Name Power Management Default D7 PMCP 0 D6 0 0 D5 PMLO 0 D4 D3 D2 D1 D0 PMHPR PMHPL PMDAC PMADC PMVCM 0 0 0 0 0 PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMADC: Power Management for MIC-Amp and ADC Blocks 0: Power OFF (Default) 1: Power ON MCLK should be present when PMADC bit is “1”. PMDAC: Power Management for DAC Block 0: Power OFF (Default) 1: Power ON When PMDAC bit is changed from “0” to “1”, DAC is powered-up to the current register values (ATT value, sampling rate, etc). PMHPL: Power Management for Lch of Headphone Amp 0: Power OFF (Default). HPL pin becomes AVSS (0V). 1: Power ON PMHPR: Power Management for Rch of Headphone Amp 0: Power OFF (Default). HPR pin becomes AVSS (0V). 1: Power ON PMLO: Power Management for Stereo Lineout 0: Power OFF (Default). LOUT and ROUT pins become Hi-Z. 1: Power ON PMCP: Power Management for Charge Pump Circuit 0: Power OFF (Default) 1: Power ON All blocks can be powered-down by setting PDN pin to “L” regardless of register values setting. In this case, all control register values are initialized. When PMVCM, PMADC, PMDAC, PMHPL, PMHPR, PMLO and PMCP bits are “0”, all blocks are powered-down. The register values remain unchanged. Power supply current is 100µA(typ) in this case. For fully shut down (typ. 1µA), PDN pin should be “L”. MS0440-E-01 2006/05 - 42 - ASAHI KASEI Addr 01H Register Name Input Select Default [AK4665A] D7 MOFF0 0 D6 0 0 D5 PMMP 0 D4 ADM 0 D3 0 0 D2 INR1 1 D1 INL2 0 D0 INL1 1 D1 0 0 D0 0 0 INL1: Select ON/OFF of Lch Line input 0: OFF 1: ON (Default) INL2: Select ON/OFF of Mono Mic input 0: OFF (Default) 1: ON INR1: Select ON/OFF of Rch Line input 0: OFF 1: ON (Default) ADM: Mono Recording Mode (Table 8) 0: Stereo (Default) 1: MONO When ADM bit is “1”, ADC Lch data is output on both Lch and Rch of SDTO. PMMP: Power Management for MPWR pin 0: Power down: Hi-Z (Default) 1: Power up MOFF0: Soft transition for changing PMHPL, PMHPR bits 0: Enable (Default) 1: Disable Addr 02H Register Name Timer Select Default D7 D6 MGAIN1 MGAIN0 0 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 WTM1-0: ALC1 Recovery Waiting Period (Table 12) ZTM1-0: ALC1 Zero Crossing Timeout Period (Table 11) MGAIN1-0: MIC-Amp Gain (Table 5) MS0440-E-01 2006/05 - 43 - ASAHI KASEI Addr 03H Register Name ALC1 Mode Control 1 Default [AK4665A] D7 D6 RGAIN1 LMTH1 0 0 D5 ALC1 0 D4 D3 D2 D1 D0 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 0 0 0 0 0 LMTH1-0: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9) RGAIN1-0: ALC1 Recovery Gain Step (Table 13) LMAT1-0: ALC1 Limiter ATT Step (Table 10) ZELMN: Zero Crossing Detection Enable at ALC1 Limiter Operation 0: Enable (Default) 1: Disable ALC1: ALC1 Enable 0: ALC1 Disable (Default) 1: ALC1 Enable ALC1 is enabled at ALC1 bit is “1”. Addr 04H Register Name ALC1 Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 REF7-0: Reference Value at ALC1 Recovery Operation (Table 14) Addr 05H Register Name IVOL Control Default D7 IVOL7 1 D6 IVOL6 0 D5 IVOL5 0 D4 IVOL4 1 D3 IVOL3 0 D2 IVOL2 0 D1 IVOL1 0 D0 IVOL0 1 D5 0 0 D4 ATS 0 D3 HPM 0 D2 DIF1 1 D1 DIF0 0 D0 DFS 0 IVOL7-0: Input Digital Volume (Table 16) Addr 06H Register Name Mode Control Default D7 0 0 D6 0 0 DFS: Sampling Speed Mode (Table 1) DIF1-0: Audio Interface Format (Table 4) Default: “10” (Mode 2) HPM: Mono Output Select of Headphone (Table 35,Table 36) ATS: Digital attenuator transition time setting (Table 20) MS0440-E-01 2006/05 - 44 - ASAHI KASEI Addr 07H Register Name DAC Control Default [AK4665A] D7 0 0 D6 0 0 D5 D4 SMUTE DATTC 0 0 D3 BST1 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DEM1-0: De-emphasis Filter Frequency Select (Table 21) BST1-0: Bass Boost Function Select (Table 22) DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent When DATTC bit is “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of ATTL7-0 bits are not written to ATTR7-0 bits. When DATTC bit is “0”, ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted Addr 08H Register Name Output Select 0 Default D7 MOFF8 0 D6 D5 D4 D3 D2 D1 D0 HPMTN MINHR RINHR DACHR MINHL LINHL DACHL 0 0 0 0 0 0 0 DACHL: DAC Lch output signal is added to Lch of headphone amp. 0: OFF (Default) 1: ON LINHL: Input signal to LIN pin is added to Lch of headphone amp. 0: OFF (Default) 1: ON MINHL: Input signal to MIN pin is added to Lch of headphone amp. 0: OFF (Default) 1: ON DACHR: DAC Rch output signal is added to Rch of headphone amp. 0: OFF (Default) 1: ON RINHR: Input signal to RIN pin is added to Rch of headphone amp. 0: OFF (Default) 1: ON MINHR: Input signal to MIN pin is added to Rch of headphone amp. 0: OFF (Default) 1: ON HPMTN: Mute of headphone amp. 0: Mute (Default) 1: Normal operation. MOFF8: Soft transition for changing of DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits 0: Enable (Default) 1: Disable MS0440-E-01 2006/05 - 45 - ASAHI KASEI Addr 09H Register Name Output Select 1 Default [AK4665A] D7 MOFF9 0 D6 LOM 0 D5 MINR 0 D4 DACR 0 D3 MINL 0 D2 RINR 0 D1 LINL 0 D0 DACL 0 D1 ATTL1 ATTR1 0 D0 ATTL0 ATTR0 0 DACL: DAC Lch output signal is added to buffer amp of LOUT. 0: OFF (Default) 1: ON LINL: Input signal to LIN pin is added to buffer amp of LOUT. 0: OFF (Default) 1: ON RINR: Input signal to RIN pin is added to buffer amp of ROUT. 0: OFF (Default) 1: ON MINL: Input signal to MIN pin is added to buffer amp of LOUT. 0: OFF (Default) 1: ON DACR: DAC Rch output signal is added to buffer amp of ROUT. 0: OFF (Default) 1: ON MINR: Input signal to MIN pin is added to buffer amp of ROUT. 0: OFF (Default) 1: ON LOM: Lineout MONO output (Table 31,Table 32) MOFF9: Soft transition for changing of DACL, LINL, RINR, MINL, DACR and MINR bits 0: Enable (Default) 1: Disable Addr 0AH 0BH Register Name DAC Lch ATT DAC Rch ATT Default D7 ATTL7 ATTR7 0 D6 ATTL6 ATTR6 0 D5 ATTL5 ATTR5 0 D4 ATTL4 ATTR4 0 D3 ATTL3 ATTR3 0 D2 ATTL2 ATTR2 0 ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 19) ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 19) Addr 0CH Register Name Lineout ATT Default D7 0 0 D6 0 0 D5 0 0 D4 D3 D2 D1 D0 LMUTE ATTS3 ATTS2 ATTS1 ATTS0 1 0 0 0 0 ATTS3-0: Analog volume control for LOUT/ROUT (Table 30) LMUTE: Mute control for LOUT/ROUT 0: Normal operation. ATTS3-0 bits control attenuation value. 1: Mute. ATTS3-0 bits are ignored. (Default) MS0440-E-01 2006/05 - 46 - ASAHI KASEI Addr 0DH 0EH 0FH 10H Register Name Test 1 Test 2 Test 3 Test 4 Default [AK4665A] D7 TEST7 TEST7 TEST7 TEST7 0 D6 TEST6 TEST6 TEST6 TEST6 0 D5 TEST5 TEST5 TEST5 TEST5 0 D4 TEST4 TEST4 TEST4 TEST4 0 D3 TEST3 TEST3 TEST3 TEST3 0 D2 TEST2 TEST2 TEST2 TEST2 0 D1 TEST1 TEST1 TEST1 TEST1 0 D0 TEST0 TEST0 TEST0 TEST0 0 D5 REFP5 1 D4 REFP4 1 D3 REFP3 1 D2 REFP2 1 D1 REFP1 0 D0 REFP0 0 TEST7-0: Test bits, “0”data must be written. Addr 11H Register Name ALC2 Mode Control 1 Default D7 0 0 D6 0 0 REFP7-0: Reference Value at ALC2 Recovery Operation (Table 28) Addr 12H Register Name ALC2 Mode Control 2 Default D7 HPG 0 D6 LING 0 D5 ALC2 0 D4 D3 D2 D1 D0 WTMP1 WTMP0 LMATP1 LMATP0 RGAINP 0 0 0 0 0 RGAINP: ALC2 Recovery Gain Step (Table 27) LMATP1-0: ALC2 Limiter ATT Step (Table 24) WTMP1-0: ALC2 Recovery Operation period (Table 26) ALC2: ALC2 Enable 0: ALC2 Disable (Default) 1: ALC2 Enable LING: LIN/RIN → HPL/HPR Path Gain 0: 0dB (Default) 1: −12dB HPG: HP-Amp Output Gain 0: 0dB (Default) 1: +5.5dB MS0440-E-01 2006/05 - 47 - ASAHI KASEI Addr 13H Register Name Mode Control 2 Default [AK4665A] D7 0 0 D6 0 0 D5 0 0 LMTHP D4 0 D3 LTMP1 0 D2 LTMP0 0 D1 SDOD 0 D0 LOOP 0 D5 PUT1 0 D4 PUT0 0 D3 FS3 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 LOOP: Internal Loopback (Table 18) 0: OFF (Default) 1: ON SDOD: SDTO Output Disable (Table 17) 0: Enable (Default) 1: Disable LTMP1-0: ALC2 Limiter Operation Period (Table 25) LMTHP: ALC2 Limiter Detection Level (Table 23) Addr 14H Register Name Mode Control 3 Default D7 PTS1 0 D6 PTS0 0 FS3-0: Sampling Frequency Setting (Table 1) PUT1-0: HP-Amp Power-up/down Time (Table 38) PTS1-0: HP-Amp Mute ON/OFF, Path ON/OFF and ALC2 Recovery Transition Time (Table 39) MS0440-E-01 2006/05 - 48 - ASAHI KASEI [AK4665A] SYSTEM DESIGN Figure 27 shows the system connection diagram. An evaluation board [AKD4665A] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Mono Mic In External Analog In Stereo Line Out Analog Ground 24 23 22 21 20 19 18 17 AINL1 AINR1 LIN RIN MIN LOUT 16 26 AVDD HPR 15 27 VCOM HPL 14 0.1u Headphone 0.1u 2.2u (+):Note 10 CP 9 DVDD CN 32 CDTI 8 31 CCLK DVSS 11 7 HVDD SDTO 30 CSN TVDD 12 6 HVSS 5 Top View SDTI 29 PDN 4 13 BICK NVSS 3 AK4665AEN MCLK 28 VREF LRCK µP + ROUT 2 4.7u 25 AVSS 1 2.2u + MPWR 0.1u MICIN 2.2k Digital Ground Stereo Line In 0.1u 0.1u + 10u 2 Power Supply 2.6 ∼ 3.6V 2.2u (+):Note 10 + DSP Power Supply 1.6 ∼ 3.6V Figure 27. Typical Connection Diagram Note: - - A 2Ω resistor must be added in series between HVDD pin and power supply line in order to limit the current. These capacitors at CP/CN pins and HVSS/NVSS pins require low ESR (Equivalent Series Resistance) over all temperature range. When these capacitors are not bipolar, the positive side should be connected to CP pin and HVSS respectively. AVSS, DVSS and HVSS of the AK4665A should be distributed separately from the ground of external controllers. All digital input should not be left floating. MS0440-E-01 2006/05 - 49 - ASAHI KASEI [AK4665A] 1. Grounding and Power Supply Decoupling The AK4665A requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the analog power supply in the system and DVDD&TVDD is supplied from AVDD via a 10Ω resistor. Alternatively if AVDD, DVDD, TVDD and HVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and HVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4665A as possible, with the small value ceramic capacitors being the nearest. 2. Internal Voltage Reference Internal voltage reference is output on the VREF pin (typ. 2.1V). An electrolytic capacitor 4.7µF in parallel with a 0.1µF ceramic capacitor is attached between VREF and AVSS to eliminate the effects of high frequency noise. VCOM is 1.2V(typ) and is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor should be connected between VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor should be connected to VCOM pin and located as close as possible to the AK4665A. No load current may be drawn from VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to avoid unwanted coupling into the AK4665A. 3. Analog Inputs The analog inputs are single-ended and the input resistance 60kΩ (typ) for AINL1/AINR1 pins and 60kΩ (typ)@0dB/−6dB or 30kΩ (typ)@+6dB/+30dB for MICIN pin. The input signal range is 1.5Vpp (typ) centered on VCOM voltage. Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2πRC). The AK4665A can accept input voltages from AVSS to AVDD. The ADC output data format is 2’s complement. The ADC’s DC offset is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz). 4. Analog Outputs The analog outputs are single-ended outputs. The output signal range of lineout is 1.5Vpp(typ) centered on the VCOM voltage. The output signal range of headphone is 1.5Vpp(typ)@HPG bit = “0” or 2.83Vpp(typ)@HPG bit = “1” centered on AVSS voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for 7FFFFH(@20bit) and negative full scale for 80000H(@20bit). The ideal output is VCOM voltage (lineout) or AVSS voltage (headphone) for 00000H(@20bit). DC offsets on the lineout outputs is eliminated by AC coupling since the lineout outputs have a DC offset equal to VCOM plus a few mV. MS0440-E-01 2006/05 - 50 - ASAHI KASEI [AK4665A] PACKAGE 32pin QFN (Unit: mm) 5.00 ± 0.10 0.40 ± 0.10 4.75 ± 0.10 24 17 16 4.75 ± 0.10 B 3.5 5.00 ± 0.10 25 32 1 1 3.5 0.50 +0.07 -0.05 32 C0.42 8 A 0.23 Exposed Pad 9 0.85 ± 0.05 0.10 M AB 0.08 C 0.04 0.01+- 0.01 0.20 C Note: The exposed pad on the bottom surface of package must be open or connected to ground. Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS0440-E-01 2006/05 - 51 - ASAHI KASEI [AK4665A] MARKING 4665A XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Date (YY/MM/DD) 05/11/22 06/05/11 Revision 00 01 Reason First Edition Spec change Page Contents 1,13,14 49 MCLK=256fs/384fs/512fs Æ 256fs/512fs System Design 2Ω series resistor was added at HVDD pin. IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0440-E-01 2006/05 - 52 -