2-Channel 500 MSPS DDS with 10-Bit DACs AD9958 FEATURES APPLICATIONS 2 synchronized DDS channels @ 500 MSPS Independent frequency/phase/amplitude control between channels Matched latencies for frequency/phase/amplitude changes Excellent channel-to-channel isolation (>72 dB) Linear frequency/phase/amplitude sweeping capability Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable) 2 integrated 10-bit D/A converters (DACs) Individually programmable DAC full-scale currents 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O Port (SPI) with 800Mbps data throughput Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) Multiple device synchronization Selectable 4× to 20× REF_CLK multiplier (PLL) Selectable REF_CLK crystal oscillator 56-Lead LFCSP Agile local oscillator Phased array radar/sonar Instrumentation Synchronized clocking RF source for AOTF Single-side band suppressed carrier Quadrature communications FUNCTIONAL BLOCK DIAGRAM AD9958 DDS CORE 32 Σ 32 Σ 32 Σ 32 Σ Σ 15 COS(X) IOUT 10 10 DAC 10 10 DAC IOUT DDS CORE FTW ∆FTW 32 SYNC_IN SYNC_OUT I/O_UPDATE COS(X) 14 IOUT AMP/ ∆AMP 10 SCALABLE DAC REF CURRENT TIMING AND CONTROL LOGIC SYSTEM CLK ÷4 REF_CLK REF_CLK PHASE/ ∆PHASE 15 BUFFER/ XTAL OSCILLATOR CLK_MODE_SEL REF CLOCK MULTIPLIER 4× TO 20× CHANNEL REGISTERS MASTER_RESET I/O PORT BUFFER PROFILE REGISTERS 1.8V 1.8V AVDD DVDD DAC_RSET PWR_DWN_CTL CONTROL REGISTERS MUX IOUT PS0 PS1 PS2 PS3 SCLK CS SDIO_0 SDIO_1 SDIO_2 SDIO_3 05252-001 SYNC_CLK Σ DVDD_I/O Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9958 TABLE OF CONTENTS Features .............................................................................................. 1 Sweep and Phase Accumulator Clearing Functions .............. 25 Applications....................................................................................... 1 Output Amplitude Control Mode............................................ 26 Functional Block Diagram .............................................................. 1 Synchronizing Multiple AD9958 Devices ................................... 27 General Description ......................................................................... 3 Automatic Mode Synchronization ........................................... 27 Specifications..................................................................................... 4 Manual Software Mode Synchronization................................ 27 Absolute Maximum Ratings............................................................ 8 Manual Hardware Mode Synchronization.............................. 27 ESD Caution.................................................................................. 8 I/O_Update, SYNC_CLK, and System Clock Relationships 28 Equivalent Input and Output Circuits....................................... 8 Serial I/O Port ................................................................................. 29 Pin Configuration and Function Descriptions............................. 9 Overview ..................................................................................... 29 Typical Performance Characteristics ........................................... 11 Instruction Byte Description .................................................... 30 Application Circuits ....................................................................... 14 Serial I/O Port Pin Description ................................................ 30 Theory of Operation ...................................................................... 17 Serial I/O Port Function Description ...................................... 30 DDS Core..................................................................................... 17 MSB/LSB Transfer Description ................................................ 30 D/A Converter ............................................................................ 17 Serial I/O Modes of Operation................................................. 31 Modes of Operation ....................................................................... 18 Register Maps.................................................................................. 34 Channel Constraint Guidelines ................................................ 18 Control Register Map ................................................................ 34 Power Supplies ............................................................................ 18 Channel Register Map ............................................................... 35 Single-Tone Mode ...................................................................... 18 Profile Register Map................................................................... 35 Reference Clock Modes ............................................................. 19 Control Register Descriptions ...................................................... 36 Scalable DAC Reference Current Control Mode ................... 20 Channel Select Register (CSR) ................................................. 36 Power-Down Functions............................................................. 20 Channel Function Register (CFR) Description...................... 37 Modulation Mode....................................................................... 20 Outline Dimensions ....................................................................... 39 Modulation Using SDIO Pins for RU/RD............................... 22 Ordering Guide .......................................................................... 39 Linear Sweep (Shaped) Modulation Mode ............................. 22 Linear Sweep—No-Dwell Mode............................................... 24 REVISION HISTORY 9/05—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD9958 GENERAL DESCRIPTION The AD9958 consists of two DDS cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout related mismatches. Since both channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation. The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices DDS products. Flexibility is provided by four data pins (SDIO_0:3) that allow four programmable modes of serial I/O operation. The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input source is common to both channels and can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REF_CLK multiplier. The AD9958 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires the pin labeled DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9958 operates over the industrial temperature range of −40°C to +85°C. The AD9958 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates two integrated, high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. Rev. 0 | Page 3 of 40 AD9958 SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK multiplier bypassed), unless otherwise noted. Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier Bypassed REF_CLK Multiplier Enabled Internal VCO Output Frequency Range VCO Gain Bit Set High1 Internal VCO Output Frequency Range VCO Gain Bit Set Low1 Crystal REF_CLK Source Range Input Power Sensitivity Min Typ Channel-to-Channel Output Amplitude Matching Error Output Current Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Voltage Compliance Range Channel-to-Channel Isolation Unit Test Conditions/Comments See Figure 33 and Figure 34 1 10 255 500 125 500 MHz MHz MHz 100 160 MHz 20 −5 30 3 MHz dBm Input Voltage Bias Level Input Capacitance Input Impedance Duty Cycle w/REF_CLK Multiplier Bypassed Duty Cycle w/REF_CLK Multiplier Enabled CLK Mode Select (Pin 24) Logic 1 Voltage CLK Mode Select (Pin 24) Logic 0 Voltage DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Max 1.15 2 1500 45 35 1.25 1.25 −10 –2.5 1 ±0.5 ±1.0 3 AVDD – 0.50 72 Ω 55 65 1.8 0.5 % % V V 10 10 10 Bits mA %FS 2.5 25 % µA LSB LSB pF V dB AVDD + 0.50 WIDEBAND SFDR 1 to 20 MHz Analog Out −65 dBc 20 to 60 MHz Analog Out −62 dBc 60 to 100 MHz Analog Out −59 dBc 100 to 150 MHz Analog Out −56 dBc 150 to 200 MHz Analog Out −53 dBc NARROWBAND SFDR 1.1 MHz Analog Out (±10 kHz) −90 dBc 1.1 MHz Analog Out (±50 kHz) −88 dBc 1.1 MHz Analog Out (±250 kHz) −86 dBc 1.1 MHz Analog Out (±1 MHz) −85 dBc 15.1 MHz Analog Out (±10 kHz) −90 dBc 15.1 MHz Analog Out (±50 kHz) −87 dBc 15.1 MHz Analog Out (±250 kHz) −85 dBc 15.1 MHz Analog Out (±1 MHz) −83 dBc 40.1 MHz Analog Out (±10 kHz) −90 dBc 40.1 MHz Analog Out (±50 kHz) −87 dBc 40.1 MHz Analog Out (±250 kHz) −84 dBc 40.1 MHz Analog Out (±1 MHz) −82 dBc 75.1 MHz Analog Out (±10 kHz) −87 dBc Rev. 0 | Page 4 of 40 Measured at the pin (single-ended) V pF 1.8V digital input logic 1.8 V digital input logic Must be referenced to AVDD DAC supplies tied together (see Figure 21) The frequency range for wideband SFDR is defined as dc to Nyquist AD9958 Parameter 75.1 MHz Analog Out (±50 kHz) Typ −85 75.1 MHz Analog Out (±250 kHz) −83 75.1 MHz Analog Out (±1 MHz) −82 dBc 100.3 MHz Analog Out (±10 kHz) −87 dBc 100.3 MHz Analog Out (±50 kHz) −85 dBc 100.3 MHz Analog Out (±250 kHz) −83 dBc 100.3 MHz Analog Out (±1 MHz) −81 dBc 200.3 MHz Analog Out (±10 kHz) −87 dBc 200.3 MHz Analog Out (±50 kHz) −85 dBc 200.3 MHz Analog Out (±250 kHz) −83 dBc −81 dBc –150 –159 –165 –165 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –142 –151 –160 –162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –135 –146 –154 –157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –134 –144 –152 –154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –139 –149 –153 –148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –130 –140 –145 –139 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –123 –134 –138 –132 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –120 –130 –135 –129 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 200.3 MHz Analog Out (±1 MHz) PHASE NOISE CHARACTERISTICS Residual Phase Noise @15.1 MHz (fOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @40.1 MHz (fOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 75.1 MHz (fOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 100.3 MHz (fOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 15.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 5× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 40.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 5× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 75.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 5× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 100.3 MHz (fOUT) w/REF_CLK Multiplier Enabled 5× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Min Rev. 0 | Page 5 of 40 Max Unit dBc dBc Test Conditions/Comments AD9958 Parameter Residual Phase Noise @ 15.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 40.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 75.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 100.3 MHz (fOUT) w/REF_CLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset SERIAL PORT TIMING CHARACTERISTICS Maximum Frequency Serial Clock (SCLK) Minimum SCLK Pulse Width Low (tPWL) Minimum SCLK Pulse Width High (tPWH) Minimum Data Set-Up Time (tDS) Minimum Data Hold Time Minimum CSB Set-Up Time (tPRE) Minimum Data Valid Time for Read Operation MISCELLANEOUS TIMING CHARACTERISTICS Master_Reset Minimum Pulse Width I/O_Update Minimum Pulse Width Minimum Set-Up Time (I/O_Update to SYNC_CLK) Minimum Hold Time (I/O_Update to SYNC_CLK) Minimum Set-Up Time (Profile Inputs to SYNC_CLK) Minimum Hold Time (Profile Inputs to SYNC_CLK) Minimum Set-Up Time (SDIO Inputs to SYNC_CLK) Minimum Hold Time (SDIO Inputs to SYNC_CLK) Propagation Time Between REF_CLK and SYNC_CLK CMOS LOGIC INPUTS VIH VIL Logic 1 Current Logic 0 Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) VOH VOL POWER SUPPLY Total Power Dissipation—Both Channels On, SingleTone Mode Total Power Dissipation—Both Channels On, with Sweep Accumulator Total Power Dissipation—Full Power Down IAVDD—Both Channels On, Single Tone Mode Min Typ Max –127 –136 –139 –138 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –117 –128 –132 –130 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –110 –121 –125 –123 dBc/Hz dBc/Hz dBc/Hz dBc/Hz –107 –119 –121 –119 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 200 1.6 2.2 2.2 0 1.0 12 1 1 4.8 0 5.4 0 2.5 0 2.25 Unit 3.5 5.5 2.0 3 −12 2 0.8 12 Test Conditions/Comments MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Min pulse width = 1 sync clock period Min pulse width = 1 sync clock period Rising edge to rising edge Rising edge to rising edge V V µA µA pF 2.7 0.4 V V 315 380 mW Dominated by supply variation 350 420 mW Dominated by supply variation 105 mA 13 90 Rev. 0 | Page 6 of 40 mW AD9958 Parameter Min IAVDD—Both Channels On, Sweep Accumulator, REF_CLK Multiplier and 10-Bit Output Scalar Enabled IDVDD—Both Channels On, Single Tone Mode IDVDD—Both Channels On, Sweep Accumulator, REF_CLK Multiplier and 10-Bit Output Scalar Enabled IDVDD_I/O IDVDD_I/O IAVDD Power-Down Mode IDVDD Power-Down Mode DATA LATENCY (PIPELINE DELAY) SINGLE TONE MODE2, 3 Frequency, Phase, and Amplitude Words to DAC Output w/Matched Latency Enabled Frequency Word to DAC Output w/Matched Latency Disabled Phase Offset Word to DAC Output w/Matched Latency Disabled Amplitude Word to DAC Output w/Matched Latency Disabled DATA LATENCY (PIPELINE DELAY) MODULATION MODE3, 4 Frequency Word to DAC Output Phase Offset Word to DAC Output Amplitude Word to DAC Output DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE3, 4 Frequency Rising/Falling Delta Tuning Word to DAC Output Phase Offset Rising/Falling Delta Tuning Word to DAC Output Amplitude Rising/Falling Delta Tuning Word to DAC Output Typ 95 Max 110 Unit mA 60 70 mA 70 80 mA 22 30 2.5 2.5 mA mA mA mA 29 Sys Clk 29 Sys Clk 25 Sys Clk 17 Sys Clk 34 29 21 Sys Clk Sys Clk Sys Clk 41 Sys Clk 37 Sys Clk 29 Sys Clk 1 For the VCO frequency range of 160 MHz to 255 MHz there is no guarantee of operation. Data latency is reference to the I/O_UPDATE> Data latency is fixed. 4 Data latency is referenced to a profile change. 2 3 Rev. 0 | Page 7 of 40 Test Conditions/Comments IDVDD = read IDVDD = write AD9958 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) θJA θJC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating 150°C 4V 2V −0.7 V to +4 V 5 mA –65°C to +150°C –40°C to +85°C 300°C 21°C/W 2°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. EQUIVALENT INPUT AND OUTPUT CIRCUITS REF_CLK INPUTS CMOS DIGITAL INPUTS AVDD DAC OUTPUTS DVDD_I/O = 3.3V 1.5kΩ Z Z REF_CLK 1.5kΩ REF_CLK AVDD OUTPUT IOUT IOUT Figure 2. TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED OUTPUTS' VOLTAGE COMPLIANCE. 05252-003 05252-002 AMP AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS. Figure 3. Rev. 0 | Page 8 of 40 REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DCCOUPLED. Figure 4. OSC 05252-004 INPUT AVDD AD9958 56 55 54 53 52 51 50 49 48 47 46 45 44 43 DGND DVDD SYNC_CLK SDIO_3 SDIO_2 SDIO_1 SDIO_0 DVDD_I/O SCLK CS I/O_UPDATE DVDD DGND P3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD9958 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2 P1 P0 AVDD NC AVDD AVDD AVDD NC AVDD NC AVDD AVDD AVDD AVDD AGND DAC_RSET AGND AVDD AGND AVDD REF_CLK REF_CLK CLK_MODE_SEL AGND AVDD LOOP_FILTER NC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SYNC_IN SYNC_OUT MASTER_RESET PWR_DWN_CTL AVDD AGND AVDD CH0_IOUT CH0_IOUT AGND AVDD AGND CH1_IOUT CH1_IOUT NOTES 1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND. 2. PIN 49 IS DVDD_IO AND IS TIED TO 3.3V. 05252-005 NC = NO CONNECT Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic SYNC_IN I/O I 2 SYNC_OUT O 3 MASTER_RESET I 4 5, 7, 11, 15, 19, 21, 26, 29, 30, 31, 33, 35, 36, 37, 39 6, 10, 12, 16, 18, 20, 25 45, 55 44, 56 8 9 13 14 17 PWR_DWN_CTL AVDD I I Description Used to Synchronize Multiple AD9958s. Connects to the SYNC_OUT pin of the master AD9958 device. Used to Synchronize Multiple AD9958s. Connects to the SYNC_IN pin of the slave AD9958 devices. Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9958’s internal registers to their default state, as described in the Register Map. External Power-Down Control. Analog Power Supply Pins (1.8 V). AGND I Analog Ground Pins. DVDD DGND CH0_IOUT CH0_IOUT CH1_IOUT CH1_IOUT DAC_RSET I I O O O O I 22 REF_CLK I 23 REF_CLK I Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. True DAC Output. Terminates into AVDD. Complementary DAC Output. Terminates into AVDD. True DAC Output. Terminates into AVDD. Complementary DAC Output. Terminates into AVDD. Establishes the Reference Current for all DACs. A 1.91 kΩ resistor (nominal) is connected from Pin 17 to AGND. Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this pin should be decoupled to AVDD or AGND with a 0.1 µF capacitor. Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See Modes of Operation section for the reference clock configuration. Rev. 0 | Page 9 of 40 AD9958 Pin No. 24 Mnemonic CLK_MODE_SEL I/O I 27 LOOP_FILTER I 28, 32, 34, 38 40, 41,42,43 NC P0, P1, P2, P3 I 46 I/O_UPDATE I 47 48 CS SCLK I I 49 50 51 52, 53 DVDD_I/O SDIO_0, SDIO_1 SDIO_2, SDIO_3 SYNC_CLK I I/O I/O 54 O Description Control Pin for the Oscillator Section. CAUTION: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed. Connects to the external zero compensation network of the PLL loop filter. Typically the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD. No Connection. Data pins used for modulation (FSK, PSK, ASK), start/stop for the sweep accumulators or are used to ramp up/down the output amplitude. Note the SYNC_CLK must be enabled in these modes. Any toggle of these data inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the set-up and hold time requirements to the SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of uncertainty exists. The functionality of these pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>. A rising edge transfers data from the serial I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the set-up and hold time requirements to the. SYNC_CLK to guarantee a fixed pipeline delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty exists. The minimum pulse width is one SYNC_CLK period. Active low chip select allowing multiple devices to share a common I/O bus (SPI). Serial Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 3.3 V Digital Power Supply for SPI Port and Digital I/O. Data Pin SDIO_0 is dedicated to the Serial Port I/O only. Data Pins SDIO_1:3 can be used for the serial port I/O port or used to initiate a ramp up/down (RU/RD) of the DAC output amplitude. The SYNC_CLK runs at one fourth the system clock rate. It can be disabled. I/O_UPDATE or data (Pins 40 to 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pins 40 to 43) must meet the set-up and hold time requirements to the rising edge of SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists. Rev. 0 | Page 10 of 40 AD9958 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 (T1) –71.73dB 4.50901804MHz REF LVL 0dBm RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB 0 0 A 1 –30 –30 –40 –40 –50 20dB UNIT dB A 1 1AP –50 –70 1 1 05252-006 –90 –100 START 0Hz 25MHz/DIV –90 –100 START 0Hz STOP 250MHz DELTA 1 (T1) –62.84dB 40.08016032MHz RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB REF Lv] 0dBm 0 A 1 25MHz/DIV STOP 250MHz Figure 9. fOUT = 15.1 MHz, fCLK = 500 MSPS, Wideband SFDR Figure 6. fOUT = 1.1 MHz, fCLK = 500 MSPS, Wideband SFDR REF LVL 0dBm 05252-009 –80 –80 –10 DELTA 1 (T1) –60.13dB 75.15030060MHz RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB A 1 –10 –20 –20 1AP –30 –30 –40 –40 (dB) –50 –60 –50 –60 1 –80 –80 05252-007 –70 –90 –100 25MHz/DIV –90 –100 STOP 250Hz START 0Hz Figure 7. fOUT = 40.1 MHz, fCLK = 500 MSPS, Wideband SFDR REF LVL 0dBm DELTA 1 (T1) –59.04dB 100.70140281MHz RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB 0 25MHz/DIV REF LVL 0dBm RBW DELTA 1 (T1) VBW –53.84dB –101.20240481MHz SWT 20dB UNIT dB A –20 1AP –30 –40 –40 (dB) –30 –60 RF ATT 1 –10 –50 20kHz 20kHz 1.6s 0 –10 –20 STOP 250MHz Figure 10. fOUT = 75.1 MHz, fCLK = 500 MSPS, Wideband SFDR A 1 05252-010 1 –70 START 0Hz 1AP 1AP –50 –60 1 1 –70 –80 –80 05252-008 –70 –90 –100 START 0Hz 25MHz/DIV 05252-011 (dB) RF ATT –60 –60 (dB) 20kHz 20kHz 1.6s –20 1AP (dB) (dB) –20 0 RBW VBW SWT –10 –10 –70 DELTA 1 (T1) –69.47dB 30.06012024MHz REF LVL 0dBm –90 –100 STOP 250MHz START 0Hz Figure 8. fOUT = 100.3 MHz, fCLK = 500 MSPS, Wideband SFDR 25MHz/DIV STOP 250MHz Figure 11. fOUT = 200.3 MHz, fCLK = 500 MSPS, Wideband SFDR Rev. 0 | Page 11 of 40 AD9958 REF LVL 0dBm DELTA 1 (T1) –84.73dB 254.50901604kHz 0 RBW VBW SWT 500Hz 500Hz 20s RF ATT 20dB UNIT dB 1 REF LVL 0dBm 20dB UNIT dB A 1 –20 1AP –30 –30 –40 –40 (dB) –50 –50 –60 –60 –70 –70 –80 1AP –80 1 –100 CENTER 1.1MHz 100kHz/DIV –90 –100 SPAN 1MHz CENTER 15.1MHz Figure 12. fOUT = 1.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz REF LVL 0dBm RBW DELTA 1 (T1) VBW –84.10dB 120.24048096kHz SWT 0 500Hz 500Hz 20s RF ATT 20dB UNIT dB 100kHz/DIV SPAN 1MHz Figure 15. fOUT = 15.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz REF LVL 0dBm RBW VBW SWT DELTA 1 (T1) –86.03dB 262.56513026kHz 500Hz 500Hz 20s RF ATT 20dB UNIT dB 0 A 1 05252-015 1 05252-012 –90 A 1 –10 –10 –20 –20 1AP –30 –40 –40 (dB) –30 –50 –50 –60 –60 –70 –70 –80 1AP –80 –90 –100 CENTER 40.1MHz 100kHz/DIV –100 SPAN 1MHz CENTER 75.1MHz Figure 13. fOUT = 40.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz REF LVL 0dBm DELTA 1 (T1) –82.63dB 400.80160321kHz RBW VBW SWT 500Hz 500Hz 20s RF ATT 20dB UNIT dB 0 100kHz/DIV SPAN 1MHz Figure 16. fOUT = 75.1 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz REF LVL 0dBm RBW VBW SWT DELTA 1 (T1) –83.72dB –400.80160321kHz 500Hz 500Hz 20s RF ATT 20dB UNIT dB 0 A 1 1 –90 05252-016 05252-013 1 A 1 –10 –10 –20 –20 1AP –30 –40 –40 (dB) –30 –50 1AP –50 –60 –60 –70 –70 –80 1 –90 –100 CENTER 100.3MHz 100kHz/DIV 05252-014 –80 –90 05252-017 (dB) RF ATT –10 –20 (dB) 500Hz 500Hz 20s 0 A –10 (dB) RBW VBW SWT DELTA 1 (T1) –84.86dB –200.40080160kHz 1 –100 CENTER 200.3MHz SPAN 1MHz 100kHz/DIV SPAN 1MHz Figure 17. fOUT = 200. 3MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz Figure 14. fOUT = 100.3 MHz, fCLK = 500 MSPS, NBSFDR, ±1 MHz Rev. 0 | Page 12 of 40 AD9958 –60 –100 75.1MHz CHANNEL ISOLATION (dBc) –120 –130 100.3MHz –140 –150 40.1MHz 05252-018 15.1MHz –170 100 –70 SINGLE DAC POWER PLANE –75 –80 –160 10 –65 1k 10k 100k 1M 05252-021 PHASE NOISE (dBc/Hz) –110 SEPARATED DAC POWER PLANES –85 50.3 25.3 10M 75.3 100.3 125.3 150.3 175.3 200.3 FREQUENCY OF COUPLING SPUR (MHz) FREQUENCY OFFSET (Hz) Figure 18. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz, 75.1 MHz, 100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier Bypassed Figure 21. Channel Isolation at 500 MSPS Operation. Conditions are Channel of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept. 600 –70 PHASE NOISE (dBc/Hz) –90 –100 100.3MHz –110 75.1MHz –120 –130 –140 40.1MHz –150 05252-019 15.1MHz –160 –170 10 100 1k 10k 100k 1M 500 400 2 CHANNELS ON 300 1 CHANNEL ON 200 100 05252-022 TOTAL POWER DISSIPATION (mW) –80 0 500 10M 450 400 350 300 250 200 150 100 50 REFERENCE CLOCK FREQUENCY (MHz) FREQUENCY OFFSET (Hz) Figure 19. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1MHz, 75.1 MHz, 100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier = 5x Figure 22. Reference Clock Frequency vs. Power Dissipation vs. Channel(s) Power On/Off –45 –70 –80 –50 –100 SFDR AVERAGED 100.3MHz –110 –55 SFDR (dBc) 75.1MHz –120 –130 40.1MHz –140 –65 15.1MHz –150 05252-020 –70 –160 –170 10 –60 100 1k 10k 100k 1M 05252-023 PHASE NOISE (dBc/Hz) –90 –75 1.1 10M 15.1 40.1 75.1 100.3 FOUT (MHz) FREQUENCY OFFSET (Hz) Figure 20. Residual Phase Noise(SSB) with fOUT = 15.1 MHz, 40.1MHz, 75.1 MHz,100.3 MHz, fCLK = 500 MHz with REF_CLK Multiplier = 20× Rev. 0 | Page 13 of 40 Figure 23. Averaged Channel SFDR vs. fOUT 200.3 AD9958 APPLICATION CIRCUITS PULSE ANTENNA RADIATING ELEMENTS AD9958 CH 0 FILTER FILTER CH 1 FILTER FILTER 05252-024 LO REF CLK Figure 24. Phase Array Radar Using Precision Frequency/Phase Control from DDS in FMCW or Pulsed Radar Applications. DDS Provides Either Continuous Wave or Frequency Sweep. AD8348 AD8347 AD8346 ADL5390 I BASEBAND AD8349 CH 0 LO AD9958 PHASE SPLITTER RF OUTPUT CH 1 05252-025 REF CLK Q BASEBAND Figure 25. Single-Sideband-Suppressed Carrier-Up Conversion AD9510, AD9511, ADF4106 ÷ REFERENCE PHASE COMPARATOR CHARGE PUMP LOOP FILTER VCO ÷ LPF REF CLK 05252-026 AD9958 Figure 26. DDS in PLL Locking to Reference Offering Distribution with Fine Frequency and Delay Adjust Tuning Rev. 0 | Page 14 of 40 AD9958 AD9510 CLOCK DISTRIBUTOR WITH DELAY EQUALIZATION CLOCK SOURCE REF_CLK AD9510 SYNCHRONIZATION DELAY EQUALIZATION SYNC_OUT C1 S1 SYNC_IN DATA AD9958 FPGA A1 (MASTER) SYNC_CLK C2 S2 DATA AD9958 FPGA CENTRAL CONTROL A2 (SLAVE 1) SYNC_CLK C3 S3 DATA AD9958 FPGA A3 (SLAVE 2) SYNC_CLK AD9958 A4 (SLAVE 3) SYNC_CLK A_END 05252-027 C4 S4 DATA FPGA Figure 27. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC Clock OPTICAL FIBER CHANNEL W/MULITIPLE DISCRETE WAVELENGTHS SPLITTER WDM SOURCE WDM SIGNAL INPUTS CH 0 AD9958 CH 0 AMP CH 1 ACOUSTIC OPTICAL TUNABLE FILTER CH 1 OUTPUTS CH 0 CH 1 SELECTABLE WAVELENGTH FROM EACH CHANNEL VIA DDS TUNING AOTF Figure 28. DDS Providing Stimulus for Acoustic Optical Tunable Filter Rev. 0 | Page 15 of 40 05252-028 REF CLK AMP AD9958 CH 0 – ADCMP563 AD9958 CH 1 + 05252-029 REF CLK Figure 29. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to Comparator PROGRAMMABLE 1 TO 32 DIVIDER AND DELAY ADJUST CLOCK OUTPUT SELECTION(S) AD9515 AD9514 AD9513 AD9512 CH 0 n LVPECL LVDS CMOS n LVPECL LVDS CMOS CH 1 IMAGE AD9515 AD9514 AD9513 AD9512 n = DEPENDENT ON PRODUCT SELECTION Figure 30. Clock Generation Circuit Using the AD951x Series of Clock Distribution Chips Rev. 0 | Page 16 of 40 05252-030 AD9958 REF CLK AD9958 THEORY OF OPERATION DDS CORE D/A CONVERTER The AD9958 has two DDS cores each consisting of a 32-bit phase accumulator and phase-to-amplitude converter. Together these digital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word) is greater than 0. The phase-toamplitude converter simultaneously translates phase information to amplitude information by a COS (θ) operation. The AD9958 incorporates two 10-bit current output DACs. The DAC converts a digital code (amplitude) into a discrete analog quantity. The DAC’s current outputs can be modeled as a current source with high output impedance (typically 100 kΩ). Unlike many DACs, these current outputs require termination into AVDD via a resistor or a center-tapped transformer for expected current flow. The output frequency (fO) of each DDS channel is a function of the rollover rate of each phase accumulator. The exact relationship is given in the following equation: Each DAC has complementary outputs that provide a combined full-scale output current (IOUT + IOUTB). The outputs always sink current and their sum equals the full-scale current at any point in time. The full-scale current is controlled by means of an external resistor (RSET) and the scalable DAC current control bits discussed in the Modes of Operation section. The resistor RSET is connected between the DAC_RSET pin and analog ground (AGND). The full-scale current is inversely proportional to the resistor value as follows: fO = (FTW )( f S ) with 0 ≤ FTW ≤ 231 232 where: fS = the system clock rate. FTW = the frequency tuning word. 232 represents the phase accumulator’s capacity. R SET = Since both channels share a common system clock, they are inherently synchronized. The DDS core architecture also supports the capability to phase offset the output signal. This is performed by the channel phase offset word (CPOW). The CPOW is a 14-bit register that stores a phase offset value. This value is added to the output of the phase accumulator to offset the current phase of the output signal. Each channel has its own phase offset word register. This feature can be used for placing both channels in a known phase relationship relative to one another. The exact value of phase offset is given by the following equation: 18.91 I OUT The maximum full-scale output current of the combined DAC outputs is 15 mA, but limiting the output to 10 mA provides optimal spurious-free dynamic range (SFDR) performance. The DAC output voltage compliance range is AVDD + 0.5 V to AVDD − 0.5 V. Voltages developed beyond this range can cause excessive harmonic distortion. Proper attention should be paid to the load termination to keep the output voltage within its compliance range. Exceeding this range could potentially damage the DAC output circuitry. LPF IOUT POW Φ = ⎛⎜ 14 ⎞⎟ × 360° ⎝ 2 ⎠ DAC AVDD 1:1 50Ω 05252-031 IOUT Figure 31. Typical DAC Output Termination Configuration Rev. 0 | Page 17 of 40 AD9958 MODES OF OPERATION There are many combinations of modes (for example, singletone, modulation, linear sweep) that the AD9958 can perform simultaneously. However, some modes require multiple data pins, which can impose limitations. The following guidelines can help determine if a specific combination of modes can be performed simultaneously by the AD9958. Note the SYNC_CLK must be enabled in all modes except single-tone mode. CHANNEL CONSTRAINT GUIDELINES 1. Single tone generation, 2-level modulation, and linear sweep modes can be enabled on either channel and in any combination simultaneously. 2. Both channels can perform 4-level modulation simultaneously. 3. Either channel can perform 8-level or 16-level modulation. The other channel can only be in single-tone mode. 4. The RU/RD function can be used on both channels in single-tone generation mode. See the Output Amplitude Control Mode section for the RU/RD function. 5. When Profile Pins P2 and P3 are used for RU/RD, either channel can perform 2-level modulation with RU/RD or both channels can perform linear frequency or phase sweep with RU/RD. 6. When Profile Pin P3 is used for RU/RD, either channel can be used in 8-level modulation with RU/RD. The other channel can only be in single-tone generation mode. 7. When SDIO_1:3 pins are used for RU/RD, either or both channels can perform 2-level modulation with RU/RD. If one channel is not in 2-level modulation it can only be in single-tone generation mode. 8. When the SDIO_1:3 pins are used for RU/RD, either or both channels can perform 4-level modulation with RU/RD. If one channel is not in 4-level modulation it can only be in single-tone generation mode. 9. When the SDIO_1:3 pins are used for RU/RD, either channel can perform 8-level modulation with RU/RD. The other channel can only be in single-tone generation mode. 10. When the SDIO_1:3 pins are used for RU/RD, either channel can perform 16-level modulation with RU/RD. The other channel can only be in single-tone generation mode. 11. Amplitude modulation, linear amplitude sweep modes, and the RU/RD function cannot operate simultaneously, but frequency and phase modulation can operate simultaneously with the RU/RD function. POWER SUPPLIES The AVDD and DVDD supply pins provide power to the DDS core and supporting analog circuitry. These pins connect to a 1.8 V nominal power supply. The DVDD_I/O pin connects to a 3.3 V nominal power supply. All digital inputs are 3.3 V logic except for the CLK_MODE_SEL input. The CLK_MODE_SEL (Pin 24) is an analog input and should be operated by 1.8 V logic. SINGLE-TONE MODE Single-tone mode is the default mode of operation after a master reset signal. In this mode, both DDS channels share a common address location for the frequency tuning word (Register 0x04) and phase offset word address location (Register 0x05). Channel enable bits are provided in combination with these shared addresses. As a result, the frequency tuning word and/or phase offset word can be independently programmed between channels (see the following Step 1 through Step 5). The channel enable bits do not require an I/O update to enable or disable a channel. See the Register Map section for a description of the channel enable bits in the channel select register or CSR (Register 0x00). The channel enable bits are enabled or disabled immediately after the CSR’s data byte is written. Address sharing enables channels to be written simultaneously, if desired. The default state enables all channel enable bits. Therefore, the frequency tuning word and/or phase offset word is common to both channels, but written only once through the serial I/O port. The following steps present a basic protocol to program a different frequency tuning word and/or phase offset word for each channel using the channel enable bits. 1. Power up DUT and issue a master reset. A master reset places the part in single-tone mode and single-bit mode for serial programming operations (refer to the Serial I/O Modes of Operation section). Frequency tuning words and phase offset words default to 0 at this point. 2. Enable only one channel enable bit (Register 0x00), disable the other channel enable bit. 3. Using the serial I/O port, program the desired frequency tuning word (Register 0x04) and/or the phase offset word (Register 0x05) for the enabled channel. 4. Repeat Step 2 and Step 3 for each channel. 5. Send an I/O update signal. After an I/O update, both channels should output their programmed frequency and/or phase offset value. Rev. 0 | Page 18 of 40 AD9958 Single-Tone Mode—Matched Pipeline Delay In single-tone mode, the AD9958 offers matched pipeline delay to the DAC input for all frequency, phase, and amplitude changes. This avoids having to deal with different pipeline delays between the three input ports for such applications. The feature is enabled by asserting the match pipeline delay bit found in the channel function register (CSR) (Register 0x03). This feature is available in single-tone mode only. REFERENCE CLOCK MODES Enabling the on-chip oscillator for crystal operation is performed by driving the CLK_MODE_SEL (Pin 24) to logic high (1.8 V logic). With the on-chip oscillator enabled, connection of an external crystal to the REF_CLK and REF_CLKB inputs is made producing a low frequency reference clock. The crystal’s frequency must be in the range of 20 MHz to 30 MHz. Table 4 summarizes the clock modes of operation. See the Specifications section for more details. Table 4. When FR1 <22:18> is programmed with values ranging from 4 to 20 (decimal) the clock multiplier is enabled. The integer value in the register represents the multiplication factor. The system clock rate with the clock multiplier enabled is equal to the reference clock rate times the multiplication factor. If FR1 <22:18> is programmed with a value less than 4 or greater than 20 the clock multiplier is disabled and the multiplication factor is effectively 1. Whenever the PLL clock multiplier is enabled or the multiplication value is changed, time should be allowed to lock the PLL (typically 1 ms). High = 1.8 V logic High = 1.8 V logic Low Low M < 4 or M > 20 4 ≤ M ≤ 20 M < 4 or M > 20 Yes No No System Min/Max Freq. Range Clock (MHz) (fSYS CLK) 100 < fSYSCLK fSYS CLK = fOSC × M < 500 20 < fSYSCLK fSYS CLK = FOSC < 30 fSYS CLK = 100 < fSYSCLK FREF CLK × < 500 M 0 < fSYS CLK < fSYS CLK = FREF CLK 500 Reference Clock Input Circuitry The reference clock input circuitry has two modes of operation controlled by the logic state of Pin 24 (clock mode select). The first mode (logic low) configures as an input buffer. In this mode, the reference clock must be ac-coupled to the input due to internal dc biasing. This mode supports either differential or single-ended configurations. If single-ended mode is chosen, the complementary reference clock input (Pin 23) should be decoupled to AVDD or AGND via a 0.1 µF capacitor. Figure 32 and Figure 34 exemplify typical reference clock configurations for the AD9958. 1:1 BALUN REFERENCE CLOCK SOURCE 0.1µF REF_CLK PIN 23 50Ω 0.1µF REF_CLK PIN 22 Figure 32. The reference clock inputs can also support an LVPECL or PECL driver as the reference clock source. Note that the output frequency of the PLL is restricted to a frequency range of 100 MHz to 500 MHz. However, there is a VCO gain bit that must be used appropriately. The VCO gain bit defines two ranges (low/high) of frequency output. The VCO gain bit defaults to low (see Specifications for details). The charge pump current in the PLL defaults to 75 µA. This setting typically produces the best phase noise characteristics. Increasing charge pump current may degrade phase noise, but decreases the lock time and changes the loop bandwidth. 4 ≤ M ≤ 20 Oscillator Enabled Yes 05252-032 Enabling the PLL allows multiplication of the reference clock frequency from 4× to 20×, in integer steps. The PLL multiplication value is represented by a 5-bit multiplier value. These bits are located in the Function Register 1 (FR1), bits <22:18>. Refer to the Register Map. CLK_MODE_SEL FR1<22:18> PLL, Bits = M Pin (24) 0.1µF LVPECL/ PECL DRIVER REF_CLK PIN 23 TERMINATION 0.1µF REF_CLK PIN 22 05252-033 The AD9958 supports multiple reference clock configurations to generate the internal system clock. As an alterative to clocking the part directly with a high frequency clock source, the system clock may be generated using the internal, PLLbased reference clock multiplier. An on-chip oscillator circuit is also available for providing a low frequency reference signal by connecting a crystal to the clock input pins. Enabling these features allows the part to operate with a low frequency clock source and still provide a high update rate for the DDS and DAC. However, using the clock multiplier changes the output phase noise characteristics. For best phase noise performance, a clean, stable clock with a high slew is required. Refer to Figure 19 and Figure 20. Figure 33. The second mode of operation (Pin 24 = logic high = 1.8 V) provides an internal oscillator for crystal operation. In this mode, both clock inputs are dc-coupled via the crystal leads and bypassed. The range of crystal frequencies supported is from 20 MHz to 30 MHz. Figure 34 shows the configuration for using a crystal. Rev. 0 | Page 19 of 40 AD9958 22pF When the PWR_DWN_CTL input pin is high, the individual power down bits (CFR <7:6>) and FR1 <7>) are invalid (don’t care) and are unused. When the PWR_DWN_CTL input pin is low, the individual power-down bits control the power-down modes of operation. REF_CLK PIN 23 25MHz XTAL REF_CLK PIN 22 05252-034 22pF Figure 34. SCALABLE DAC REFERENCE CURRENT CONTROL MODE The RSET is common to both DACs. As a result, the full-scale currents are equal as a default. The scalable DAC reference can be used to set each DAC’s full-scale current independently from one another. This is accomplished by using the CFR register bits <9:8>. Table 5 shows how each DAC can be individually scaled for independent channel control. This provides for binary attenuation. Table 5. 1 0 1 0 CFR <9:8> 1 1 0 0 LSB Current State Full scale Half scale Quarter scale Eighth scale POWER-DOWN FUNCTIONS The AD9958 supports an externally controlled power-down feature and the more common software programmable powerdown bits found in previous Analog Devices DDS products. The software control power down allows the input clock circuitry, DAC, and the digital logic (for each separate channel) to be individually powered down via unique control bits (CFR <7:6>). These bits are not active when the externally controlled power-down pin (PWR_DWN_CTL) is high. When the PWR_DWN_CTL input pin is high, the AD9958 enters a power-down mode based on the FR1 <6> bit. When the PWR_DWN_CTL input pin is low, the external power-down control is inactive. Note that the power-down signals are all designed such that a Logic 1 indicates the low power mode and Logic 0 indicates the powered-up mode. MODULATION MODE The AD9958 can perform 2-/4-/8- or 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is achieved by applying data to the profile pins. Each channel can be programmed separately, but the ability to modulate both channels simultaneously is constrained by the limited number of profile pins. For instance, 16-level modulation uses all four profile pins, which inhibits modulation for the remaining channel. In addition, the AD9958 has the ability to ramp up or ramp down the output amplitude before, during, or after a modulation (FSK, PSK only) sequence. This is performed by using the 10-bit output scalar. If the RU/RD feature is desired, unused profile pins or unused SDIO_1:3 pins can be configured to initiate the operation. See the Output Amplitude Control Mode section for more details of the RU/RD feature. In modulation mode, each channel has its own set of control bits to determine the type (frequency, phase, or amplitude) of modulation. Each channel has 16 profile registers for flexibility. Register Addresses 0x0A through 0x18 are profile registers for modulation of frequency, phase, or amplitude. Registers 0x04, 0x05, and 0x06 are dedicated registers for frequency, phase, and amplitude, respectively. These registers contain the first frequency, phase offset, and amplitude word. Frequency modulation has a 32-bit resolution, phase modulation is 14 bits, and amplitude is 10 bits. When modulating phase or amplitude, the word value must be MSB-aligned in the profile registers and the unused bits are don’t care bits. When the FR1 <6> bit is zero, and the PWR_DWN_CTL input pin is high, the AD9958 is put into a fast recovery power-down mode. In this mode, the digital logic and the DACs digital logic are powered down. The DACs bias circuitry, oscillator, and clock input circuitry is not powered down. In modulation mode, AFP bits (CFR <23:22>) and level bits (FR1 <9:8>) are programmed to configure the modulation type and level. See Table 6 and Table 7 settings. Note that the linear sweep enable bit must be set to Logic 0 in direct modulation mode. When the FR1 <6> bit is high and the PWR_DWN_CTL pin is high, the AD9958 is put into the full power-down mode. In this mode, all functions are powered down. This includes the DACs and PLL, which take a significant amount of time to power up. When the PLL is bypassed, the PLL is shut down to conserve power. Table 6. AFP CFR <23:22> Linear Sweep Enable CFR <14> Description 0 0 1 1 X 0 0 0 Modulation disabled Amplitude modulation Frequency modulation Phase modulation Rev. 0 | Page 20 of 40 0 1 0 1 AD9958 Table 7. Table 10. Modulation Level Bits FR1 <9:8> Description 0 0 1 1 2-level modulation 4-level modulation 8-level modulation 16-level modulation 0 1 0 1 When modulating, the RU/RD function can be limited based on pins available for controlling the feature. SDIO pins are for RU/RD only, not modulation. Table 8. RU/RD Bits FR1 <11:10> 0 0 0 1 1 0 1 1 Description RU/RD disabled. Only profile Pin 2 and Pin 3 available for RU/RD operation. Only profile Pin 3 available for RU/RD operation. Only SDIO Pins 1, 2, and 3 available for RU/RD operation. Forces the serial I/O to only be used in 1-bit mode. If profile pins are used for RU/RD, Logic 0 is for ramp-up and Logic 1 is for ramp-down. Because of the two channels and limited data pins, it is necessary to assign the profile pins and/or SDIO_1:3 pins to a dedicated channel. This is controlled by the profile pin configuration or PPC bits (FR1 <14:12>). Each modulation description to follow incorporates data pin assignments. 2-Level Modulation—No RU/RD Modulation level bits are set to 00 (2-level). AFP bits are set to the desired modulation type. RU/RD bits and the linear sweep bit are disabled. Table 9 displays how the profile pins and channels are assigned. Table 9. Profile Pin Configuration(PPC) Bits FR1<14:12> P0 P1 P2 P3 Description x N/A N/A CH0 CH1 2-level mode both channels, no RU/RD x x As shown in Table 9, only Profile Pin P2 can be used to modulate Channel 0. If the P2 pin is Logic 0, Register 0 (Register 0x04) is chosen; if the P2 pin is Logic 1, Register 1 (Register 0x0A) is chosen. Profile Pin Config. (PPC) Bits FR1 <14:12> 1 0 1 P1 CH0 P2 CH1 P3 CH1 Description 4-level modulation on CH0 and CH1, no RU/RD For this condition, the profile register chosen is based on the two bit value presented to profile pins <P0:P1> or <P2:P3>. For example, if PPC = 101, <P0:P1>= 11, and <P2:P3>= 01, then the contents of Profile Register 3 of Channel 0 are presented to Channel 0’s output and the contents of Profile Register 1 of Channel 1 are presented to Channel 1’s output. 8-Level Modulation—No RU/RD Modulation level bits are set to 10 (8-level). AFP bits are set to a nonzero value. RU/RD bits and the linear sweep bit are disabled. Note that the AFP bits of the three channels not being used must be set to 00. Table 11 shows the assignment of profile pins and channels. Table 11. Profile Pin Config. Bits FR1 <14:12> x 1 0 P0 CH0 P1 CH0 P2 CH0 P3 x x CH1 CH1 CH1 x 1 1 Description 8-level modulation on CH0, no RU/RD 8-level modulation on CH1, no RU/RD For this condition, the profile register (1 of 16) chosen is based on the 3-bit value presented to the profile <P0-P2> pins. For example, if PPC = X10 and <P0-P2> = 111, the contents of Profile Register 7 of Channel 0 are presented to Channel 0. 16-Level Modulation—No RU/RD Modulation level bits are set to 11 (16-level). AFP bits are set to the desired modulation type. RU/RD bits and the linear sweep bit are disabled. The AFP bits of the three channels not being used must be set to 00. Table 12 displays how the profile pins and channels are assigned. Table 12. Profile Pin Config. (PPC) Bits FR1 <14:12> x 1 0 P0 CH0 P1 CH0 P2 CH0 P3 CH0 x CH1 CH1 CH1 CH1 4-Level Modulation—No RU/RD Modulation level bits are set to 01 (4-level). AFP bits are set to the desired modulation type. RU/RD bits and the linear sweep bit are disabled. Table 10 displays how the profile pins and channels are assigned to each other. P0 CH0 1 1 Description 16-level modulation on CH0, no RU/RD 16-level modulation on CH1, no RU/RD For these conditions, the profile register chosen is based on the 4-bit value presented to profile <P0-P3> pins. For example if PPC = X11 and <P0-P3> = 1110, the contents of Profile Register 14 of Channel 1 is presented to Channel 1. Rev. 0 | Page 21 of 40 AD9958 2-Level Modulation Using Profile Pins for RU/RD Table 17. When the RU/RD bit = 01, Profile Pins P2 and P3 are available for RU/RD. Note that only a modulation level of two is available in this mode. See Table 13 for available pin assignments. Profile Pin Config. Bits FR1 <14:12> 1 0 1 Table 13. Profile Pin Config. Bits FR1 <14:12> 1 0 1 P0 CH0 P1 CH1 P2 CH0 P3 CH1 RU/RD RU/RD Description 2-level modulation With RU/RD, CH0, CH1 8-Level Modulation Using a Profile Pin for RU/RD When the RU/RD bit = 10, Profile Pin P3 is available for RU/RD. Note that only a modulation level of eight is available. See Table 14 for available pin assignments. Table 14. Profile Pin Config. Bits FR1 <14:12> x 1 0 x 1 1 For RU/RD bits = 11, SDIO Pins 1, 2, and 3 are available for RU/RD. In this mode, modulation levels of 2/4/16 are available. Note that the serial I/O port can only be used in 1-bit serial mode. For the configuration shown in Table 17, the profile register is chosen based on the two bit value presented to <P1:P2> or <P3:P4>. For example, if PPC = 101, <P0:P1> = 11, and <P2:P3> = 01, then the contents of Profile Register 3 of Channel 0 are presented to Channel 0’s output and the contents of Profile Register 1 of Channel 1 are presented to Channel 1’s output. SDIO Pins 1 and 2 provide the RU/RD function. 16-Level Modulation Using SDIO Pins for RU/RD RU/RD = 11 (SDIO Pin 1 available for RU/RD) and the level is set to 16. See the pin assignment shown in the Table 18. Table 15. x P0 N/A P1 N/A Profile Pin Configuration FR1<14:12> x 1 0 P0 CH0 P1 CH0 P2 CH0 P3 CH0 x CH1 CH1 CH1 CH1 1 1 SDIO 1 CH0 RU/RD CH1 RU/RD SDIO 2 NA SDIO 3 NA NA NA For the configuration shown in Table 18, the profile register is chosen based on the 4-bit value presented to <P0:P3>. For example, if PPC = X11 and <P0-P3> = 1101, then the contents of Profile Register 13 of Channel 1 is presented to Channel 1. The SDIO_1 pin provides the RU/RD function. LINEAR SWEEP (SHAPED) MODULATION MODE 2-Level Modulation Using SDIO Pins for RU/RD P2 CH0 P3 CH1 For this configuration, each profile pin is dedicated to a specific channel. In this case, the SDIO pins can be used for the RU/RD function, as described in Table 16. Table 16. SDIO Pins 1 2 3 1 0 0 1 0 1 1 1 0 1 1 1 P2 P3 SDIO 1 SDIO 2 SDIO 3 CH1 CH1 CH0 CH1 N/A RU/RD RU/RD Table 18. P0 P1 P2 P3 Description CH0 CH0 CH0 CH0 8-level modulation RU/RD with RU/RD, CH0 CH1 CH1 CH1 CH1 8-level modulation RU/RD with RU/RD, CH1 MODULATION USING SDIO PINS FOR RU/RD Profile Pin Config. Bits FR1 <14:12> x x P0 P1 CH0 CH0 Description Triggers the ramp-up function for CH0 Triggers the ramp-down function for CH0 Triggers the ramp-up function for CH1 Triggers the ramp-down function for CH1 4-Level Modulation Using SDIO Pins for RU/RD For RU/RD = 11 (SDIO Pins 1 and 2 are available for RU/RD), the modulation level is set to four. See Table 17 for pin assignments, including SDIO pin assignments. Linear sweep enables the user to sweep frequency, phase, or amplitude from a starting point (S0) to an endpoint (E0). The purpose of linear sweep modes is to provide better bandwidth containment compared to direct modulation by replacing greater instantaneous changes with more gradual, user-defined changes between S0 and E0. In linear sweep mode, S0 is loaded into Profile Register 0 (Profile 0 is represented by one of the three Registers 0x04, 0x05, or 0x06 depending on the type of sweep) and E0 is always loaded into Profile Register 1 (Register 0x0A). If E0 is configured for frequency sweep, the resolution is 32 bits, phase sweep is 14 bits, and amplitude sweep is 10 bits. When sweeping phase or amplitude, the word value must be MSB-aligned in Profile 1 register. The unused bits are don’t care bits. The profile pins are used to trigger and control the direction of the linear sweep for frequency, phase, and amplitude. Both channels can be programmed separately for a linear sweep. In linear sweep mode, Profile Pin 2 is dedicated to Channel 0. Profile Pin 3 is dedicated to Channel 1, and so on. Rev. 0 | Page 22 of 40 To enable linear sweep mode for a particular channel, AFP bits (CFR <23:22>), modulation level bits (FR1 <9:8>), and the linear sweep enable bit (CFR <14>) are programmed. The AFP bits determine the type of linear sweep to be performed. The modulation level bits must be set to 00 (2-level) for that specific channel (see Table 19 and Table 20). EO RDW FDW ∆f,p,a ∆f,p,a RSRR ∆t ∆t SO PROFILE PIN TIME Figure 35. Table 19. AFP CFR <23:22> 0 0 0 1 1 0 1 1 FSRR 05252-035 The AD9958 has the ability to ramp up or ramp down (RU/RD) the output amplitude (using the 10-bit output scalar) before and after a linear sweep. If the RU/RD feature is desired, unused profile pins or unused SDIO_1:3 pins can be configured for the RU/RD operation. (FREQUENCY/PHASE/AMPLITUDE) LINEAR SWEEP AD9958 Linear Sweep Enable CFR <14> 1 1 1 1 Description N/A Amplitude sweep Frequency sweep Phase sweep For a piecemeal or a nonlinear transition between S0 and E0, the delta-tuning words and ramp rate words can be reprogrammed during the transition to produce the desired response. The formulae for calculating the step size of RDW or FDW for delta frequency, delta phase, or delta amplitude are as follows: RDW ∆f = ⎛⎜ 32 ⎞⎟ × SYNC _ CLK (Hz) ⎝ 2 ⎠ Table 20. Modulation Level Bits FR1 <9:8> 0 0 0 1 1 0 1 1 Description 2-level modulation 4-level modulation 8-level modulation 16-level modulation RDW ΔΦ = ⎛⎜ 14 ⎞⎟ × 360° ⎝ 2 ⎠ RDW ∆a = ⎛⎜ 10 ⎞⎟ × 1024 (DAC full-scale current) ⎝ 2 ⎠ Setting the Slope of the Linear Sweep The slope of the linear sweep is set by the intermediate step size (delta-tuning word) between S0 and E0 and the time spent (sweep ramp rate word) at each step. The resolution of the delta-tuning word is 32 bits for frequency, 14 bits for phase, and 10 bits for amplitude. The resolution for the delta ramp rate word is 8 bits. In linear sweep, each channel is assigned a rising delta word (RDW, Register 0x08) and a rising sweep ramp rate word (RSRR, Register 0x07). These settings apply when sweeping up towards E0. The falling delta word (FDW, Register 0x09) and falling sweep ramp rate (FSRR, Register 0x07) apply when sweeping down towards S0. Note the sweep accumulator overflows if the rising or falling delta word is too large. To prevent this from happening, the magnitude of the rising or falling delta word should not be greater than the difference between full scale and the E0 value (full scale − E0). For a frequency sweep, full scale is 231−1. For a phase sweep, full scale is 214 −1. For an amplitude sweep, full scale is 210−1. The following graph displays a linear sweep up and then down using a profile pin. Note that the no-dwell bit is disabled; otherwise, the sweep accumulator returns to 0 upon reaching EO. The formula for calculating delta time from RSRR or FSRR is RSRR t = ⎛⎜ 8 ⎞⎟ × 1/ SYNC _ CLK ⎝ 2 ⎠ At 500 MSPS operation (SYNC_CLK =125 MHz), the maximum time interval between steps is 1/125 MHz × 256 = 2.048 µs. The minimum time interval is (1/125 MHz) × 1 = 8.0 ns. The sweep ramp rate block (timer) consists of a loadable 8-bit down counter that continuously counts down from the loaded value to 1. When the ramp rate timer equals 1, the proper ramp rate value is loaded and the counter begins counting down to 1 again. This load and count down operation continues for as long as the timer is enabled. However the count can be reloaded before reaching 1 by either of the following two methods. Method one is by changing the profile pin. When the profile pin changes from Logic 0 to Logic 1, the rising sweep ramp rate register (RSRR) value is loaded into the ramp rate timer, which then proceeds to count down as normal. When the profile pin changes from Logic 1 to Logic 0, the falling sweep ramp rate register (FSRR) value is loaded into the ramp rate timer, which then proceeds to count down as normal. Rev. 0 | Page 23 of 40 AD9958 Method two is by setting the CFR <14> bit and issuing an I/O update. If sweep is enabled and CFR <14> is set, the ramp rate timer loads the value determined by the profile pin: If the profile pin is high the ramp rate timer loads the RSRR, if the profile pin is low the ramp rate timer loads the FSRR. The sweep is then complete and the output is held constant in frequency. See Figure 36 for the linear sweep block diagram. Figure 38 depicts a frequency sweep with no-dwell mode disabled. In this mode, the output follows the state of the profile pin. A phase or amplitude sweep works in the same manner. Frequency Linear Sweep Example: AFP Bits = 10 Modulation level bits = 00, sweep enable = 1, no-dwell bit = 0. LINEAR SWEEP—NO-DWELL MODE In linear sweep mode, when the profile pin transitions from low to high, the RDW is applied to the input of the sweep accumulator and the RSRR register is loaded into the sweep rate timer. If the linear sweep no-dwell bit is set (CFR <15>), the rising sweep is started in an identical manner to the dwell linear sweep mode. That is, upon detecting Logic 1 on the profile input pin, the rising sweep action is initiated. The word continues to sweep up at the rate set by the rising sweep ramp rate at the resolution set by the rising delta tuning word until it reaches the terminal value. Upon reaching the terminal value, the output immediately reverts back to the starting point and remains until Logic 1 is detected on the profile pin. Figure 37 shows an example of the no-dwell mode. The points labeled “A” indicate where a rising edge is detected on the profile pin and the points labeled “B” indicate where the AD9958 has determined that the output has reached E0 and reverts to S0. The RDW accumulates at the rate given by the ramp rate (RSRR) until the output is equal to the CTW1 register value. The sweep is then complete and the output is held constant in frequency. When the profile pin transitions from high to low, the FDW is applied to the input of the sweep accumulator and the FSRR register is loaded into the sweep rate timer. The FDW accumulates at the rate given by the ramp rate (FSRR) until the output is equal to the CTW0 register value. The falling ramp rate register and the falling delta word are unused in this mode. SWEEP ACCUMULATOR 0 FDW 0 32 Z–1 32 32 0 32 1 MUX RDW 32 MUX 0 SWEEP ADDER 0 1 MUX 0 1 MUX 1 32 PROFILE PIN CTW0 RAMP RATE TIMER: 8-BIT LOADABLE DOWN COUNTER ACCUMULATOR RESET LOGIC 8 LIMIT LOGIC TO KEEP SWEEP BETWEEN S0 AND E0 PROFILE PIN RATE TIME LOAD CONTROL LOGIC MUX FSRR CTW1 1 05252-036 0 32 RSRR Figure 36. Linear Sweep Block Diagram Rev. 0 | Page 24 of 40 AD9958 FOUT B B B FTW1 A FTW0 A A TIME SINGLE–TONE MODE PS<2> = 1 PS<2> = 0 PS<2> = 1 PS<2> = 0 PS<2> = 1 05252-037 PS<2> = 0 LINEAR SWEEP MODE ENABLE, NO-DWELL BIT SET Figure 37. FOUT B FTW1 A FTW0 TIME PS<2> = 0 LINEAR SWEEP MODE PS<2> = 1 PS<2> = 0 AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW. AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW. 05252-038 SINGLE–TONE MODE Figure 38. Linear Sweep with the No-Dwell Feature Disabled Continuous Clear Bits SWEEP AND PHASE ACCUMULATOR CLEARING FUNCTIONS The AD9958 allows two different clearing functions. The first is a continuous zeroing of the sweep logic and phase accumulator (clear and hold). The second is a clear and release or automatic zeroing function. CFR <4> is the automatic clear sweep accumulator bit and CFR <2> is the automatic clear phase accumulator bit. The continuous clear bits are located in CFR, where CFR <3> clears the sweep accumulator and CFR <1> clears the phase accumulator. The continuous clear bits are static control signals that, when active high, hold the respective accumulator at 0 while the bit is active. When the bit goes low, the respective accumulator is allowed to operate. Clear and Release Bits The auto clear sweep accumulator bit, when set, clears and releases the sweep accumulator upon an I/O update or a change in the profile input pins. The auto clear phase accumulator, when set, clears and releases the phase accumulator upon an I/O update or a change in the profile pins. The automatic clearing function is repeated for every subsequent I/O update or change in profile pins until the clear and release bits are reset via the serial port. Rev. 0 | Page 25 of 40 AD9958 OUTPUT AMPLITUDE CONTROL MODE The 10-bit scale factor (multiplier) controls the ramp-up and ramp-down (RU/RD) time of an on/off emission from the DAC. In burst transmissions of digital data, it reduces the adverse spectral impact of abrupt bursts of data. It can be bypassed by clearing the multiplier enable bit (ACR <12> = 0). Automatic and manual RU/RD modes are supported. The automatic mode generates a zero-scale up to a full-scale (10 bits) linear ramp at a rate determined by the amplitude ramp rate control register. The start and direction of the ramp can be controlled by either the profile pins or the SDIO1:3 pins. Manual mode allows the user to directly control the output amplitude by manually writing to the amplitude scale factor value in the amplitude control register (Register 0x06). Manual mode is enabled by setting the ACR <12> = 1 and ACR <11> = 0 bits. 1. In the first method the profile pin(s) or SDIO_1:3 pins are changed. When the control signal changes state, the ACR value is loaded into the ramp rate timer, which then proceeds to count down as normal. 2. In the second method, the load ARR timer bit (ACR <10>) is set and an I/O update is issued. 3. The last method is by changing from inactive auto RU/RD mode to active auto RU/RD mode. RU/RD Pin-to-Channel Assignment Automatic RU/RD Mode Operation The automatic RU/RD mode is active when both the ACR <12> and ACR <11> bits are set. When automatic RU/RD is enabled, the scale factor is internally generated and applied to the multiplier input port for scaling the output. The scale factor is the output of a 10-bit counter that increments/decrements at a rate set by the 8-bit output ramp rate register. The scale factor increments if the external pin is high and decrements if the pin is low. The internally generated scale factor step size is controlled by the <15:14> bits in the ACR register. Table 21 describes the increment/decrement step size of the internally generated scale factor per the ACR <15:14> bits. Table 21. Autoscale Factor Step Size ASF <15:14> (Binary) 00 01 10 11 If the load ARR timer bit ACR <10> is set, the ramp rate timer is loaded at an I/O update, a change in profile input, or on reaching a value of 1. The ramp timer can be loaded before reaching a count of 1 by three methods. Increment/Decrement Size 1 2 4 8 A special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor register (ASFR). This allows the user to ramp to a value less than full scale. 1. When both channels are in single-tone mode, the profile pins are used for RU/RD operation. 2. When both linear sweep and RU/RD modes are activated, SDIO_1:3 are used for RU/RD operation. 3. In modulation mode, please refer to the modulation mode section for pin assignments. Table 22. Profile Pin P2 P3 RU/RD Operation Ch 0 Ch 1 Table 23. SDIO LS and RU/RD Modes Enable Simultaneously Enable for CH0 1 1 2 0 3 0 Enable for CH0 1 0 1 Enable for CH1 1 1 0 Enable for CH1 1 1 1 Ramp Rate Timer The ramp rate timer is a loadable down counter, which generates the clock signal to the 10-bit counter that generates the internal scale factor. The ramp rate timer is loaded with the value of the ASFR every time the counter reaches 1 (decimal). This load and count down operation continues for as long as the timer is enabled unless the timer is forced to load before reaching a count of 1. Rev. 0 | Page 26 of 40 Ramp-Up/RampDown Control Signal Assignment Ramp-up function for CH0 Ramp-down function for CH0 Ramp-up function for CH1 Ramp-down function for CH1 AD9958 SYNCHRONIZING MULTIPLE AD9958 DEVICES The AD9958 allows easy synchronization of multiple AD9958 devices. At power-up the phase of SYNC_CLK can be offset between multiple devices. To correct for the offset and align the SYNC_CLK edges, there are three methods (one automatic mode and two manual modes) of synchronizing SYNC_CLKs. These modes force the internal state machines of multiple devices to a known state, which aligns SYNC_CLKs. Any mismatch in REF_CLK phase between devices results in a corresponding phase mismatch on the SYNC_CLKs. AUTOMATIC MODE SYNCHRONIZATION In automatic mode, multiple part synchronization is achieved by connecting the SYNC_OUT pin on the master device to the SYNC_IN pin of the slave device(s). Devices are configured as master or slave through programming bits, accessible via the serial port. A configuration for synchronizing multiple AD9958/59 devices in automatic mode is shown in the Application Circuits section. In this configuration, the AD9510 provides coincident REF_CLKs and SYNC_OUTs to all devices. Operation The first step is to program the master and slave devices for their respective roles. Enabling the master device is performed by writing its master enable bit (FR2 <6>) true. This causes the SYNC_OUT of the master device to output a pulse that has a pulse width equal to one system clock period and a frequency equal to one fourth of the system clock frequency. Enabling device(s) as slaves is performed by writing the slave enable bit (FR2 <7>) true. In automatic synchronizing mode, the slave device(s) sample SYNC_OUT pulses from the master device and a comparison of all state machines is made by the autosynchronization circuitry. If the slave device(s) state machines are not identical to the master, the slave device(s) state machines are stalled for one system clock cycle. This procedure synchronizes the slave device(s) within three SYNC_CLK periods. Delay Time Between SYNC_OUT and SYNC_IN When the delay between SYNC_OUT and SYNC_IN exceeds one system clock period, phase offset bits (FR2 <1:0>) are used to compensate. The default state of these bits is 00, which implies that the SYNC_OUT of the master and the SYNC_IN of the slave have a propagation delay of less than one system clock period. If the propagation time is greater than one system clock period, the time should be measured and the appropriate offset programmed. Table 24 describes the delays required per system clock offset value. Table 24. System Clock Offset Value 00 01 10 11 SYNC_OUT/SYNC_IN Propagation Delay 0 ≤ delay ≤ 1 1 ≤ delay ≤ 2 2 ≤ delay ≤ 3 3 ≤ delay ≤ 4 Automatic Synchronization Status Bits If a slave device falls out of sync, the sync status bit is set high. This bit can be read through the serial port bit (FR2 <5>). It is automatically cleared when read. The synchronization routine continues to operate regardless of the state of the status bit. The status bit can be masked by writing Logic 1 to the synchronization status mask bit (FR2 <4>). If the status bit is masked, it is held low. MANUAL SOFTWARE MODE SYNCHRONIZATION The manual software mode is enabled by setting the manual synchronization bit (FR1 <0>) to Logic 1 in a device. In this mode, the I/O update that writes the Manual SW synchronization bit to Logic 0 stalls the state machine of the clock generator for one system clock cycle. Stalling the clock generation state machine by one cycle changes the phase relationship of SYNC_CLK between devices by one system clock period (90°). Note that the user may have to repeat this process until the devices have their SYNC_CLK signals in phase. The SYNC_IN input may be left floating since it has an internal pull-up. The SYNC_OUT is not used. The synchronization is complete when the master and slave(s) devices have their SYNC_CLK signals in phase. MANUAL HARDWARE MODE SYNCHRONIZATION Manual hardware mode is enabled by setting the manual SW synchronization bit (FR1 <1>) to Logic 1 in a device. In manual HW synchronization mode, the SYNC_CLK stalls by one system clock cycle each time a rising edge is detected on the SYNC_IN input. Stalling SYNC_CLK’s state machine by one cycle changes the phase relationship of SYNC_CLK between devices by one system clock period (90°). Note that the user may have to repeat the process until the devices have their SYNC_CLK signals in phase. The SYNC_IN input might be left floating since it has an internal pull-up. The SYNC_OUT is not used. The synchronization is complete when the master and slave(s) devices have their SYNC_CLK signals in phase. Rev. 0 | Page 27 of 40 AD9958 I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS I/O_UPDATE and SYNC_CLK are used together to transfer data from the serial I/O buffer to the active registers in the device. Data in the buffer is inactive. The I/O UPDATE is essentially over sampled by the SYNC_CLK. Therefore, I/O_UPDATE must have a minimum pulse width greater than one SYNC_CLK period. SYNC_CLK is a rising edge active signal. It is derived from the system clock and a divide-by-4 frequency divider. The SYNC_CLK is externally provided, which can be used to synchronize external hardware to the AD9958’s internal clocks. The timing diagram shown in Figure 39 depicts when data in the buffer is transferred to the active registers. I/O_UPDATE initiates the start of a buffer transfer. It can be sent synchronously or asynchronous relative to the SYNC_CLK. If the set-up time between these signals is met, then constant latency (pipeline) to the DAC output exists. For example, if repetitive changes to phase offset via the SPI port are desired, the latency of those changes to the DAC output is constant, otherwise a time uncertainty of 1 SYNC_CLK period is present. SYSCLK A B SYNC_CLK I/O UPDATE DATA IN I/O BUFFERS DATA 2 DATA 1 DATA 1 DATA 2 DATA 3 DATA 3 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 39. Rev. 0 | Page 28 of 40 05252-039 DATA IN REGISTERS AD9958 SERIAL I/O PORT OVERVIEW The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices DDS products. The flexibility is provided by four data (SDIO_0:3) pins that allow four programmable modes of serial I/O operation. Phase 2 of the I/O cycle consists of the actual data transfer (write/read) between the serial port controller and the serial port buffer. The number of bytes transferred during this phase of the communication cycle is a function of the register being accessed. The actual number of additional SCLK rising edges required for the data transfer and instruction byte depends on the number of byte(s) in the register and the serial I/O mode of operation. Three of the four data pins (SDIO_1:3) can be used for other functions than serial I/O port operation. These pins can also be used to initiate a ramp-up or ramp-down (RU/RD) of the 10-bit amplitude output scalar. In addition, one of these pins (SDIO_3) can also be used to provide the SYNC_I/O function that resynchronizes the serial I/O port controller if it is out of proper sequence. For example, when accessing Function Register 1, (FR1) which is three bytes wide, Phase 2 of the I/O cycle requires that three bytes be transferred. After transferring all data bytes per the instruction byte, the communication cycle is completed for that register. The maximum speed of the serial I/O port SCLK is 200 MHz, but the four data (SDIO_0:3) pins can be used to further increase data throughput. The maximum data throughput using all SDIO_0:3 pins is 800 Mbps. At the completion of a communication cycle, the AD9958 serial port controller expects the next set of rising SCLK edges to be the instruction byte for the next communication cycle. All data written to the AD9958 is registered on the rising edge of SCLK. Data is read on the falling edge of SCLK. See Figure 36 and Figure 37. Note that both channels share Registers 0x03 to 0x18, which are shown in the Register Map section. This address sharing enables both DDS channels to be written to simultaneously. For example, if a common frequency tuning word is desired for both channels, it can be written once through the serial I/O port to both channels. This is the default mode of operation (both channels enabled). To enable each channel to be independent, the two channel enable bits found in the channel select register (CSR) must be used. Each set of communication cycles does not require an I/O_UPDATE to be issued. The I/O_UPDATE transfers data from the I/O port buffer to active registers. The I/O_UPDATE can be sent for each communication cycle or can be sent when all serial operations are complete. However, data is not active until an I/O_UPDATE is sent, with the exception of the channel enable bits in the Channel Select Register (CSR). These bits do not require an I/O_UPDATE to be enabled. Serial operation of the AD9958 occurs at the register level, not the byte level. That is, the controller expects that all byte(s) contained in the register address are accessed. The SYNC_I/O function can be used to abort an I/O operation, thereby allowing fewer than all bytes to be accessed. This feature can be used to program only a part of the addressed register. Note that only completed bytes are affected. There are two phases to a serial communications cycle. Phase 1 is the instruction cycle, which writes the instruction byte into the AD9958. Each bit of the instruction byte is registered on each corresponding rising edge of SCLK. The instruction byte defines whether the upcoming data transfer is either a write or read operation and contains the serial address of the address register. Rev. 0 | Page 29 of 40 tPRE tSCLK CS tDSU tSCLKPWL SCLK tSCLKPWH tDHLD SDIO SYMBOL tPRE tSCK tDSU tSCLKPWH tSCLKPWL tDHLD DEFINITION CS SETUP TIME PERIOD OF SERIAL DATACLOCK SERIAL DATA SETUP TIME SERIAL DATA CLOCK PULSE WIDTH HIGH SERIAL DATA CLOCK PULSE WIDTH LOW SERIAL DATA HOLD TIME MIN 1.0ns 5.0ns 2.2ns 2.2ns 1.6ns 0ns Figure 40. Setup and Hold Timing for the Serial I/O Port 05252-040 There are effectively two sets or copies of addresses (0x03 to 0x18) that channel enable bits can access to provide channel independence. See the Control Register Descriptions section for further discussion of programming channels that are common or independent from each other. AD9958 SERIAL I/O PORT FUNCTION DESCRIPTION CS Serial Data Out (SDO). The SDO function is available in singlebit (3-wire) mode only. In SDO mode, data is read from the SDIO_2 pin for protocols that use separate lines for transmitting and receiving data (see Table 26 for pin configuration options). Bits <2:1> in the CSR register (Register 0x00) control the configuration of this pin. The SDO function is not available in 2-bit or 4-bit serial I/O modes. SCLK SDIO SDO (SDIO_2) SYMBOL DEFINITION MIN tDV DATA VALID TIME 12ns 05252-041 tDV Figure 41. Timing Diagram for Data Read for Serial I/O Port INSTRUCTION BYTE DESCRIPTION The instruction byte contains the following information. Table 25. MSB D6 D5 D4 D3 D2 D1 LSB R/Wb x1 x1 A4 A3 A2 A1 A0 1 x = don’t care bit. Bit 7 of the instruction byte (R/Wb) determines whether a read or write data transfer occurs after the instruction byte write. A logic high indicates a read operation. Logic 0 indicates a write operation. Bits 4 to 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. The internal byte addresses are generated by the AD9958. SERIAL I/O PORT PIN DESCRIPTION Serial Data Clock (SCLK). The serial clock pin is used to synchronize data to and from the internal state machines of the AD9958. The maximum SCLK toggle frequency is 200 MHz. Chip Select (CS). The chip select pin allows more than one AD9958 device to be on the same set of serial communications lines. The chip select is an active low enable pin. Defined SDIO inputs go to a high impedance state when CS is high. If CS is driven high during any communications cycle, that cycle is suspended until CS is reactivated low. The CS pin can be tied low in systems that maintain control of SCLK. Serial Data I/O (SDIO_0:3). Of the four SDIO pins, only the SDIO_0 pin is a dedicated SDIO pin. SDIO_1:3 can also be used to RU/RD the output amplitude. Bits <2:1> in the channel select register (CSR Register 0x00) control the configuration of these pins. See the Serial I/O Modes of Operation section for more information. SYNC_I/O. The SYNC_I/O function is available in 1-bit and 2-bit modes. SDIO_3 serves as the SYNC_I/O pin when this function is active. Bits <2:1> in the CSR register (Register 0x00) control the configuration of this pin. Otherwise the SYNC_I/O function is used to synchronize the I/O port state machines without affecting the addressable register contents. An active high input on the SYNC_I/O (SDIO_3) pin causes the current communication cycle to abort. After SDIO_3 returns low (Logic 0), another communication cycle can begin, starting with the instruction byte write. The SYNC_I/O function is not available in 4-bit serial I/O mode. MSB/LSB TRANSFER DESCRIPTION The AD9958 serial port can support both MSB-first or LSB-first data formats. This functionality is controlled by CSR <0> in the channel select register (CSR). MSB-first is the default mode. When CSR <0> is set high, the serial port is in LSB-first format. The instruction byte must be written in the format indicated by CSR <0>. That is, if the AD9958 is in LSB-first mode, the instruction byte must be written from LSB to MSB. If the AD9958 is in MSB-first mode (default), the instruction byte must be written from MSB to LSB. Example Operation To write the Function Register 1 (FR1) in MSB-first format, apply an instruction byte of MSB > 00000001 < LSB, starting with the MSB. From this instruction, the internal controller recognizes a write transfer of three bytes starting with the MSB, Bit <23>, in the FR1 address (Register 0x01). Bytes are written on each consecutive rising SCLK edge until Bit<0> is transferred. Once the last data bit is written, the I/O communication cycle is complete and the next byte is considered an instruction byte. To write the Function Register 1 (FR1) in LSB-first format, apply an instruction byte of MSB > 00000001 < LSB, starting with the LSB. From this instruction, the internal controller recognizes a write transfer of three bytes, starting with the LSB <0> in the FR1 address (0x01). Bytes are written on each consecutive rising SCLK edge until Bit <23> is transferred. Once the last data bit is written, the I/O communication cycle is complete and the next byte is considered an instruction byte. Rev. 0 | Page 30 of 40 AD9958 SERIAL I/O MODES OF OPERATION 1. Single bit serial 2-wire mode (default mode). 2. Single bit serial 3-wire mode. 3. 2-bit serial mode. In single-bit serial mode, 2-wire interface operation, the SDIO_0 pin is the single serial data I/O pin. In single-bit serial mode 3-wire interface operation, the SDIO_0 pin is the serial data input pin and the SDIO_2 pin is the output data pin. Regardless of the number of wires used in the interface, the SDIO_3 pin is configured as an input and operates as the SYNC_I/O pin in the single-bit serial mode and 2-bit serial mode. The SDIO_1 pin is unused in this mode. See Table 26. 4. 4-bit serial mode (SYNC_I/O not available). 2-Bit Serial Mode The following are the four programmable modes of the serial I/O port operation: Table 6 displays the function of all six serial I/O interface pins, depending on the mode of serial I/O operation programmed. Table 26. Serial I/O Port Pin Function vs. Serial I/O Mode Single Bit Serial 2-Wire Mode Serial Clock Chip Select Single Bit Serial 3-Wire Mode Serial Clock Chip Select SDIO_0 Serial Data I/O Serial Data In SDIO_1 Not used for SDIO1 Not used for SDIO1 Serial Data I/O SDIO_2 Not used for SDIO1 Serial Data Out (SDO) Not used for SDIO1 SDIO_3 SYNC_I/O SYNC_I/O SYNC_I/O Pin Name SCLK CSB 2-Bit Serial Mode Serial Clock Chip Select Serial Data I/O 4-Bit Serial Mode Serial Clock Chip Select Serial Data I/O Serial Data I/O Serial Data I/O Serial Data I/O In serial mode, these pins can be used for RU/RD operation. 1 The two bits CSR <2:1> in the channel select register set the serial I/O mode of operation are defined as follows: CSR <2:1> = 00. Single bit serial mode (2-wire mode). The SPI port operation in 2-bit serial mode is identical to the SPI port operation in single bit serial mode, except that two bits of data are registered on each rising edge of SCLK. Therefore, it only takes four clock cycles to transfer eight bits of information. The SDIO_0 pin contains the even numbered data bits using the notation D <7:0> and the SDIO_1 pin contains the odd numbered data bits. This even and odd numbered pin/data alignment is valid in both MSB- and LSB-first formats (see Figure 39). 4-Bit Serial Mode The SPI port in 4-bit serial mode is identical to the SPI port in single bit serial mode, except that four bits of data are registered on each rising edge of SCLK. Therefore, it only takes two clock cycles to transfer eight bits of information. The SDIO_0 and SDIO_2 pins contain even numbered data bits using the notation D <7:0> and the SDIO_0 pin contains the LSB of the nibble. The SDIO_1 and SDIO_3 pins contain the odd numbered data bits and the SDIO_1 pin contains the LSB of the nibble to be accessed. Note that when programming the device for 4-bit serial mode, it is important to keep the SDIO_3 pin at Logic 0 until the device is programmed out of the single bit serial mode. Failure to do so can result in the serial I/O port controller being out of sequence. Figure 42 through Figure 44 represent write timing diagrams for each serial I/O modes available. Both MSB and LSB-first modes are shown. LSB-first bits are shown in parenthesis. The clock stall low/high feature shown is not required. It is used to show that data (SDIO) must have the proper setup time relative to the rising edge of SCLK. CSR <2:1> = 01. Single bit serial mode (3-wire mode). CSR <2:1> = 10. 2-bit serial mode. CSR <2:1> = 11. 4-bit serial mode. Single Bit Serial (2- and 3-Wire) Modes The single bit serial mode interface allows read/write access to all registers that configure the AD9958. MSB-first or LSB-first transfer formats are supported. In addition, the single bit serial mode interface port can be configured as either a single pin I/O, which allows a two-wire interface or two unidirectional pins for in/out, which enable a 3-wire interface. Single bit mode allows the use of the SYNC_I/O function. Rev. 0 | Page 31 of 40 AD9958 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO_0 I7 (I0) I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) 05252-042 SCLK Figure 42. Single-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO_1 I7 (I1) I5 (I3) I3 (I5) I1 (I7) D7 (D1) D5 (D3) D3 (D5) D1 (D7) SDIO_0 I6 (I0) I4 (I2) I2 (I4) I0 (I6) D6 (D0) D4 (D2) D2 (D4) D0 (D6) 05252-043 SCLK Figure 43. 2-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO_3 I7 (I3) I3 (I7) D7 (D3) D3 (D7) SDIO_2 I6 (I2) I2 (I6) D6 (D2) D2 (D6) SDIO_1 I5 (I1) I1 (I5) D5 (D1) D1 (D5) SDIO_0 I4 (I0) I0 (I4) D4 (D0) D0 (D4) 05252-044 SCLK Figure 44. 4-Bit Serial Mode Write Timing—Clock Stall Low Figure 45 through Figure 48 represent read timing diagrams for each serial I/O modes available. Both MSB and LSB-first modes are shown. LSB-first bits are shown in parenthesis. The clock stall low/high feature shown is not required. It is used to show that data (SDIO) must have the proper set-up time relative to the rising edge of SCLK for the instruction byte and the read data that follows the falling edge of SCLK. Rev. 0 | Page 32 of 40 AD9958 DATA TRANSFER CYCLE INSTRUCTION CYCLE CS I7 (I0) SDIO_0 I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) 05252-045 SCLK Figure 45. Single-Bit Serial Mode (2-Wire) Read Timing—Clock Stall High DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) DON'T CARE SDO D7 (D0) (SDIO_2 PIN) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) Figure 46. Single-Bit Serial Mode (3-Wire) Read Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO_1 I7 (I1) I5 (I3) I3 (I5) I1 (I7) D7 (D1) D5 (D3) D3 (D5) D1 (D7) SDIO_0 I6 (I0) I4 (I2) I2 (I4) I0 (I6) D6 (D0) D4 (D2) D2 (D4) D0 (D6) 05252-047 SCLK Figure 47. 2-Bit Serial Mode Read Timing—Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO_3 I7 (I3) I3 (I7) D7 (D3) D3 (D7) SDIO_2 I6 (I2) I2 (I6) D6 (D2) D2 (I6) SDIO_1 I5 (I1) I1 (I5) D5 (D1) D1 (D5) SDIO_0 I4 (I0) I0 (I4) D4 (D0) D0 (D4) Figure 48. 4-Bit Serial Mode Read Timing—Clock Stall High Rev. 0 | Page 33 of 40 D1 (D6) D0 (D7) 05252-046 I7 (I0) 05252-048 SDIO_0 AD9958 REGISTER MAPS CONTROL REGISTER MAP Table 27. Register Name (Address) Channel Select Register (CSR) (0x00) Function Register 1 (FR1) (0x01) Function Register Two (FR2) (0x02) Bit Range <7:0> Bit 7 (MSB) Channel 1 enable1 Bit 6 Channel 0 enable1 Bit 5 Open Bit 4 Open Bit 3 Must be 0 Bit 2 Bit 1 Serial I/0 mode select <2:1> Bit 0 (LSB) LSB first <7:0> Reference clock input power down External power down mode Sync clock disable DAC reference power down Open Open Manual software synchronization <15:8> Open <23:16> VCO gain control Multi-device synchronization slave enable <7:0> <15:8> 1 Both channels auto clear sweep accumulator Profile pin configuration <14:12> Ramp up/ramp down <11:10> PLL divider ratio <22:18> Manual hardware synchronization Default Value 0xF0 0x00 Modulation Level <9:8> 0x00 Charge pump control <17:16> 0x00 Multi-device synchronization master enable Multi-device synchronization status Multi-device synchronization mask Open <3:2> System clock offset <1:0> 0x00 Both channels clear sweep accumulator Both channels auto clear phase accumulator Both channels clear phase accumulator Open <11:10> Open <9:8> 0x00 Channel enable bits do not require an I/O update to be activated. These bits are active immediately after the byte containing the bits is written. All other bits need an I/O update to become active. The two channel enable bits shown in the register map are used to enable/disable any combination of the four channels. Both channels’ default are enabled. In the CSR register, if the user wants different frequencies for both DDS channels, the following protocol suffices. 1. Enable (Logic 1) the CH0 bit, which is located in the channel select register and disable the CH1 enable bit (Logic 0). 2. Write the desired frequency tuning word for CH0, as described in Step 1. 3. Disable CH0 enable bit (Logic 0) and enable the CH1 bit in the channel select register. 4. Write the desired frequency tuning word for CH1. Rev. 0 | Page 34 of 40 AD9958 CHANNEL REGISTER MAP Table 28. Register Name (Address) Channel Function1 (CFR) (0x03) Bit Range <7:0> <15:8> <23:16> Channel Frequency Tuning Word 01 (CTW0) (0x04) Channel Phase1 Offset Word 0 (CPW0) (0x05) Amplitude Control (ACR) (0x06) Linear Sweep Ramp Rate1 (LSR) (0x07) LSR Rising Delta1 (RDW) (0x08) LSR Falling Delta1 (FDW) (0x09) Bit 7 (MSB) Digital powerdown Linear sweep no-dwell Linear sweep enable Amplitude freq. phase select <23:22> <7:0> <15:8> <23:16> <31:24> <7:0> <15:8> <7:0> <15:8> Bit 6 DAC power down Bit 5 Matched pipe delays active Bit 4 Auto clear sweep accumulator Bit 3 Clear sweep accumulator Bit 2 Auto clear phase accumulator Load SRR at I/O Update Open Open Must be 0 (LSB) Bit 0 Sine wave output enable DAC full-scale current control <9:8> Bit 1 Clear phase accumulator2 Open <21:16> Increment/decrement step size <15:14> <23:16> <7:0> <15:8> <7:0> Open Amplitude scale factor Amplitude Ramp-up/ Load ARR at I/O multiplier ramp-down update enable enable Amplitude ramp rate <23:16> Linear sweep rising ramp rate (RSRR) <7:0> Linear sweep falling ramp rate (FSRR) <15:8> 0x03 0x00 Frequency Tuning Word 0 <7:0> Frequency Tuning Word 0 <15:8> Frequency Tuning Word 0 <23:16> Frequency Tuning Word 0 <31:24> Phase Offset Word 0 Phase Offset Word 0 <13:8> Open <15:14> Defaul t Value 0x02 0x00 0x00 0x00 Amplitude scale factor <9:8> 0x00 0x00 – – – Rising delta word <7:0> – <15:8> <23:16> <31:24> <7:0> Rising delta word <15:8> Rising delta word <23:16> Rising delta word <31:24> Falling delta word <7:0> – – – – <15:8> <23:16> <31:24> Falling delta word <15:8> Falling delta word <23:16> Falling delta word <31:24> – – – 1 There are two sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel’s channel registers and/or profile registers are written to or not. 2 The clear accumulator bit is set to Logic 1 after a master reset. It self clears or is set to Logic 0 when an I/O update is asserted. PROFILE REGISTER MAP Table 29. Register Name (address) Channel Word 1 (CTW1) (0x0A) Channel Word 2 (CTW2) (0x0B) Channel Word 3 (CTW3) (0x0C) Channel Word 3 (CTW4) (0x0D) Channel Word 5 (CTW5) (0x0E) Channel Word 6 (CTW6) (0x0F) Channel Word 7 (CTW7) (0x10) Channel Word 8 (CTW8) (0x11) Channel Word 9 (CTW9) (0x12) Channel Word 10 (CTW10) (0x13) Channel Word 11 (CTW11) (0x14) Channel Word 12 (CTW12) (0x15) Channel Word 13 (CTW13) (0x16) Channel Word 14 (CTW14) (0917) Channel Word 15 (CTW15) (0x18) Bit Range <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> <31:0> (MSB) Bit 7 (LSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. Tuning Word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. Tuning Word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22> Rev. 0 | Page 35 of 40 Default Value – – – – – – – – – – – – – – – AD9958 CONTROL REGISTER DESCRIPTIONS CHANNEL SELECT REGISTER (CSR) The CSR register determines if channels are enabled or disabled by the status of the two channel enable bits. Both channels are enabled by default. The CSR register also determines which serial mode of operation is selected. In addition, the CSR register offers a choice of MSB-first or LSB-first format. The functionality of each bit is detailed as follows: FR1 <0> = 0 (default), the software manual synchronization feature of multiple devices is inactive. FR1 <0> = 1. The manual software synchronization feature of multiple devices is active. See the Synchronizing Multiple AD9958 Devices section for details. FR1 <1> manual hardware synchronization bit. FR1<1> = 0 (default), the manual hardware synchronization feature of multiple devices is inactive.FR1 <1> = 1, the manual hardware synchronization feature of multiple devices is active. The CSR is comprised of one byte located in Register 0x00. CSR <0> LSB-first. CSR <0> = 0 (default), the serial interface accepts serial data in MSB-first format. CSR <0> = 1, the serial interface accepts serial data in LSB-first format. FR1 <2:3>. See the Synchronizing Multiple AD9958 Devices section for details. CSR <2:1> Serial I/O mode select. FR1 <4> = 0 (default). DACs reference is enabled. FR1 <4> = 1. DAC reference is powered down. CSR <2:1> 00 = Single bit serial (2-wire mode). 01 = Single bit serial (3-wire mode). 10 = 2-bit serial mode. 11 = 4-bit serial mode. FR1 <4> DACs reference power-down. FR1 <5> SYNC_CLK disable. See the Serial I/O Modes of Operation section for more details. CSR <3> = must be set to 0. CSR <7:6> channel enable bits. FR1 <5> = 0 (default), the SYNC_CLK pin is active. FR1 <5> = 1. The SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is shut down. However, the synchronization circuitry remains active internally to maintain normal device operation. FR1 <6> external power-down mode. CSR <7:4> bits are active immediately after being written. They do not require an I/O update to take effect. There are two sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register map. The addresses of both channel registers and profile registers are the same for each channel. Therefore, the channel enable bits distinguish each channel’s channel registers and profile registers values. For example, CSR <7:6> = 10, only Channel 1 receives commands from the channel registers and profile registers. CSR <7:6> = 01, only Channel 0 receives commands from the channel registers and profile registers. CSR <7:6> = 11, both Channel 0 and Channel 1 receive commands from the channel registers and profile registers. FR1 <6> = 0 (default). The external power-down mode is in the fast recovery power-down mode. In this mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DACs digital logic are powered down. The DACs bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. FR1 <6> = 1. The external power down mode is in the full power-down mode. In this mode, when the PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DACs and PLL, which take a significant amount of time to power up. FR1 <7> clock input power-down. FR1 <7> = 0 (default). The clock input circuitry is enabled for operation. FR1 <7> = 1. The clock input circuitry is disabled and is in a low power dissipation state. FR1 <9:8> modulation level bits. Function Register 1 (FR1) Description FR1 is comprised of three bytes located in Register 0x01. The FR1 is used to control the mode of operation of the chip. The functionality of each bit is detailed as follows: The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be performed for a channel. See the Modulation Mode section for more details. FR1<10:11> RU/RD bit. FR1 <0> manual software synchronization bit. Rev. 0 | Page 36 of 40 AD9958 FR2 <12> = 0 (default), the phase accumulator functions as normal. FR2 <12> = 1, the phase accumulator memory elements for both channels are asynchronously cleared. The RU/RD bits control the amplitude RU/RD time of a channel (see the Output Amplitude Control Mode section). FR1 <12:14> profile pin configuration bits. The profile pin configuration bits control the configuration of the data and SDIO pins for the different modulation modes. See the Modulation Mode section for details. FR1 <15> open. FR1 <17:16> charge pump current control. FR1 <17:16> = 00 (default), the charge pump current is 75 µA. = 01 charge pump current is 100 µA. = 10 charge pump current is 125 µA. = 11 charge pump current is 150 µA. FR1 <22:18> PLL divider values. FR1 <22:18>, if the value is > 3 and < 21, the PLL is enabled and the value sets the multiplication factor. If the value is < 4 or >20 the PLL is disabled. FR1 <23> PLL VCO gain. FR1 <23> = 0 (default), the low range (system clock below 160 MHz). FR1 <23> = 1, the high range (system clock above 255 MHz). FR2 <13> both channels auto clear phase accumulator. FR2 <13> = 0 (default). A new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into the accumulator. FR2 <13> = 1. This bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the I/O update sequence indicator on both channels. FR2 <14> both channels clear sweep accumulator. FR2 <14> = 0 (default), the sweep accumulator functions as normal.FR2 <14> = 1, the sweep accumulator memory elements for both channels are asynchronously cleared. FR2 <15> both channels auto clear sweep accumulator. FR2 <15> = 0 (default). A new delta word is applied to the input, as in normal operation, but not loaded into the accumulator. FR2 <15> = 1. This bit automatically synchronously clears (loads 0s) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator on both channels. CHANNEL FUNCTION REGISTER (CFR) DESCRIPTION Function Register 2 (FR2) Description The FR2 is comprised of two bytes located in Address 0x02. CFR <0> enable sine output. The FR2 is used to control the various functions, features, and modes of the AD9958. The functionality of each bit is detailed as follows: CFR <0> = 0 (default). The angle-to-amplitude conversion logic employs a cosine function. CFR <0> = 1. The angle-toamplitude conversion logic employs a sine function. FR2<1:0> system clock offset. CFR <1> clear phase accumulator. See the Synchronizing Multiple AD9958 Devices section for more details. FR2 <3:2> open. CFR <1> = 0 (default). The phase accumulator functions as normal. CFR <1> = 1. The phase accumulator memory elements are asynchronously cleared. FR2 <4> multi-device synchronization mask bit. CFR <2> clear phase accumulator. FR2 <5> multi-device synchronization status bit. CFR <2> = 0 (default). A new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into the accumulator. CFR <2> = 1. This bit automatically synchronously clears (loads 0s) the phase accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator. FR2 <6> multi-device synchronization master enable bit. FR2<7> multi-device synchronization slave enable bit. FR2 <4:7>. see the Synchronizing Multiple AD9958 Devices section for more details. FR2 <11:8> open. FR2 <12> both channels clear phase accumulator. CFR <3> clear frequency accumulator. CFR <3> = 0 (default). The sweep accumulator functions as normal .CFR <3> = 1. The sweep accumulator memory elements are asynchronously cleared. CFR <4> auto clear sweep accumulator. Rev. 0 | Page 37 of 40 AD9958 CFR <4> = 0 (default). A new delta word is applied to the input, as in normal operation, but not loaded into the accumulator. CFR <4> = 1. This bit automatically synchronously clears (loads 0s) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator. CFR <23:22> amplitude frequency phase select controls what type of modulation is to be performed for that channel. See the Modulation Mode section for details. Channel Frequency Tuning Word (CFTWO) Description CFTW0 <32:0> Frequency Tuning Word 0 for each channel. CFR <5> match pipe delays active. Channel Phase Offset Word (CPOW) Description CFR <5> = 0 (default), match pipe delay mode is inactive. CFR <5> = 1, match pipe delay mode is active. See the SingleTone Mode—Matched Pipeline Delay section for details. CPO0 <13:0> Phase Offset Word 0 for each channel. CFR <6> DAC power-down. Amplitude Control Register (ACR) Description CFR <6> = 0 (default). The DAC is enabled for operation. CFR <6> = 1. The DAC is disabled and is in its lowest power dissipation state. CFR <7>. digital power-down. CFR <7> = 0 (default). The digital core is enabled for operation. ACR <9:0> amplitude scale factor for each channel. ACR <10> amplitude ramp rate load control bit. ACR <10> = 0 (default). The amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded due to a I/O_UPDATE input signal (or change in the profile bits). ACR <10> = 1. The amplitude ramp rate timer is loaded upon timeout (timer =1) or at the time of an I/O_UPDATE input signal (or change in PS bits). CFR <7> = 1. The digital core is disabled and is in its lowest power dissipation state. CFR <8:9>. DAC LSB control. CFR <8:9> = 00 (default). The DAC is at the largest LSB value. CFR <10> must be set to 0. CFR <13>.linear sweep ramp rate load at I/O_UPDATE. CFR <13> = 0 (default). The linear sweep ramp rate timer is loaded only upon timeout (timer =1) and is not loaded because of an I/O_UPDATE input signal. CFR <13> = 1. The linear sweep ramp rate timer is loaded upon timeout (timer =1) or at the time of an I/O_UPDATE input signal. CFR <14> linear sweep enable. CFR <14> = 0 (default). The linear sweep capability of the AD9958 is inactive. CFR <14> = 1. The linear sweep capability of the AD9958 is enabled. When enabled, the delta frequency tuning word is applied to the frequency accumulator at the programmed ramp rate. ACR <11> auto RU/RD enable (only valid when ACR <12> is active high). ACR <11> = 0 (default). When ACR <12> is active, Logic 0 on ACR <11> enables the manual RU/RD operation. ACR <11> = 1. If ACR <12> is active, a Logic 1 on ACR <11> enables the AUTO RU/RD operation. See the Output Amplitude Control Mode section of this document for details. ACR <12> amplitude multiplier enable. ACR <12> = 0 (default). Amplitude multiplier is disabled. The clocks to this scaling function (auto RU/RD) are stopped for power saving and the data from the DDS core is routed around the multipliers. ACR <12> = 1, amplitude multiplier is enabled. ACR <13> open. ACR <15:14> amplitude increment/decrement step size. ACR <23:16> amplitude ramp rate value. Channel Linear Sweep Register (LSR) Description CFR <15> linear sweep no-dwell. CFR <15> = 0 (default). The linear sweep no-dwell function is inactive. CFR <15> = 1. The linear sweep no-dwell function is active. If CFR <15> is active, the linear sweep no-dwell function is activated. See the Linear Sweep (Shaped) Modulation Mode section for details. If CFR <14> is clear, this bit is don’t care. CFR <18:16> open. CPO0 <15:14> open. LSR <15:0> linear sweep rising ramp rate. Channel Linear Sweep Rising Delta Word Register (RDW) Description RDW <31:0> 32-bit rising delta tuning word. Channel Linear Sweep Falling Delta Word Register (FDW) Description FDW <31:0> 32-bit falling delta tuning word. Rev. 0 | Page 38 of 40 AD9958 OUTLINE DIMENSIONS 8.00 BSC SQ 0.60 MAX 0.60 MAX 0.30 0.23 0.18 43 42 PIN 1 INDICATOR TOP VIEW PIN 1 INDICATOR 56 1 6.25 6.10 SQ 5.95 EXPOSED PAD (BOTTOM VIEW) 7.75 BSC SQ 0.50 0.40 0.30 29 28 15 14 0.25 MIN 1.00 0.85 0.80 6.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.50 BSC SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56) Dimensions shown in millimeters ORDERING GUIDE Model AD9958BCPZ1 AD9958BCPZ-REEL71 AD9958/PCB 1 Temperature Range –40°C to +85°C –40°C to +85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = Pb-free part. Rev. 0 | Page 39 of 40 Package Option CP-56 CP-56 AD9958 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05252–0–9/05(0) Rev. 0 | Page 40 of 40