Cypress CY7C1463AV33-133AXC 36-mbit (1 m x 36/2 m x 18/512 k x 72) flow-through sram with nobl architecture Datasheet

CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
36-Mbit (1 M × 36/2 M × 18/512 K × 72)
Flow-Through SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte write capability
■
3.3 V and 2.5 V IO power supply
■
Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■
Clock Enable (CEN) pin to enable clock and suspend operation
■
Synchronous self timed writes
■
Asynchronous Output Enable
■
CY7C1461AV33,
CY7C1463AV33
available
in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 165-ball FBGA package. CY7C1465AV33
available in Pb-free and non-Pb-free 209-ball FBGA package
■
Three chip enables for simple depth expansion
■
Automatic power down feature available using ZZ mode or CE
deselect
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability — linear or interleaved burst order
■
Low standby power
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are
3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-Through
Burst SRAMs designed specifically to support unlimited true
back-to-back read and write operations without the insertion of
wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is
equipped with the advanced NoBL logic required to enable
consecutive read and write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
310
290
mA
Maximum CMOS Standby Current
120
120
mA
Note
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05356 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2011
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Logic Block Diagram – CY7C1461AV33 (1 M × 36)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
BW C
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
INPUT
REGISTER
OE
CE1
CE2
CE3
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1463AV33 (2 M × 18)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document #: 38-05356 Rev. *I
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Logic Block Diagram – CY7C1465AV33 (512 K × 72)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW a
BW b
BW c
BW d
BW e
BW f
BW g
BW h
WE
OE
CE1
CE2
CE3
ZZ
Document #: 38-05356 Rev. *I
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP a
DQP b
DQP c
DQP d
DQP e
DQP f
DQP g
DQP h
E
READ LOGIC
SLEEP
CONTROL
Page 3 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 9
Functional Overview ...................................................... 10
Single Read Accesses .............................................. 10
Burst Read Accesses ................................................ 10
Single Write Accesses ............................................... 11
Burst Write Accesses ................................................ 11
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................. 11
Linear Burst Address Table (MODE = GND) ................ 11
Sleep Mode ............................................................... 11
ZZ Mode Electrical Characteristics ............................... 11
Truth Table ...................................................................... 12
Truth Table for Read/Write ............................................ 13
Truth Table for Read/Write ............................................ 13
Truth Table for Read/Write ............................................ 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
TAP Controller State Diagram ....................................... 14
Test Access Port (TAP) ............................................. 14
TAP Controller Block Diagram ...................................... 14
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 15
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
Document #: 38-05356 Rev. *I
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
165-ball FBGA Boundary Scan Order .......................... 20
209-ball FBGA Boundary Scan Order .......................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Electrical Characteristics ............................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Page 4 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Configurations
A
40
41
42
43
44
45
46
47
48
49
50
NC/72M
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document #: 38-05356 Rev. *I
81
A
82
A
83
A
84
ADV/LD
VSS
90
85
VDD
91
OE
CE3
92
86
BWA
93
CEN
BWB
94
WE
BWC
95
88
BWD
96
CLK
CE2
97
89
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1461AV33
A
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
100-pin TQFP Pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 5 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Configurations (continued)
A
42
43
44
45
46
47
48
49
50
A
A
A
A
A
A
A
A
41
NC/72M
40
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document #: 38-05356 Rev. *I
81
A
82
A
83
A
84
85
ADV/LD
OE
86
VSS
90
CEN
VDD
91
WE
CE3
92
88
BWA
93
CLK
BWB
94
89
NC
95
NC
CE2
97
96
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1463AV33
A
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
100-pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 6 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Configurations (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1461AV33 (1 M × 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
1
A
CE1
BWC
BWB
CE3
CEN
ADV/LD
A
A
NC
NC/1G
A
CE2
BWD
BWA
CLK
WE
OE
A
A
NC
DQPC
DQC
NC
DQC
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC/288M
R
MODE
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
A
CY7C1463AV33 (2 M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC/576M
A
CE1
BWB
NC
CE3
CEN
ADV/LD
A
A
A
NC/1G
A
CE2
NC
BWA
CLK
WE
OE
A
A
NC
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
A
A
A
NC/144M NC/72M
MODE
A
Document #: 38-05356 Rev. *I
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
TDI
NC
A1
TDO
A
A
A
NC/288M
TMS
A0
TCK
A
A
A
A
Page 7 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Configurations (continued)
209-ball FBGA (14 × 22 × 1.76 mm) Pinout
CY7C1465AV33 (512 K × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A
CE2
A
ADV/LD
A
CE3
A
DQb
DQb
B
DQg
DQg
BWSc
BWSg
NC
WE
A
BWSb
BWSf
DQb
DQb
C
DQg
DQg
BWSh
BWSd NC/576M
CE1
NC
BWSe
BWSa
DQb
DQb
D
DQg
DQg
VSS
NC
NC/1G
OE
NC
NC
VSS
DQb
DQb
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPf
DQPb
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
VDDQ
DQf
DQf
NC
NC
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
NC
VDD
VDDQ
VDDQ
DQa
DQa
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQd
VSS
NC
NC
MODE
NC
NC
A
A
A
A
R
DQPd
T
DQd
U
DQd
DQd
V
DQd
DQd
A
A
A
A1
A
W
DQd
DQd
TMS
TDI
A
A0
A
Document #: 38-05356 Rev. *I
NC/144M
A
NC/72M
TDO
VSS
DQPa
DQPe
DQe
DQe
NC/288M
DQe
DQe
A
DQe
DQe
TCK
DQe
DQe
Page 8 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Definitions
Pin Name
IO
Description
A0, A1, A
InputAddress Inputs. Used to select one of the address locations. Sampled at the rising edge of the
Synchronous CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
Synchronous the rising edge of CLK.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance or Load Input. Used to advance the on-chip address counter or load a new address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW
to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select or deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select or deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select or deselect the device.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block
Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ
InputZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs
IOBidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQPX
IOBidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VDDQ
VSS
IO Power
Supply
Ground
Power Supply for IO Circuitry.
Ground for the Device.
Document #: 38-05356 Rev. *I
Page 9 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Definitions (continued)
Pin Name
IO
Description
TDO
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, leave this pin unconnected. This pin is not available on TQFP packages.
Output
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
Input
used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not
Synchronous available on TQFP packages.
TMS
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
Input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP
Synchronous packages.
TCK
JTAG-Clock
NC
N/A
No Connects. Not internally connected to the die.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/576M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/1G
N/A
Not Connected to the Die. Can be tied to any voltage level.
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
Functional Overview
■
CE1, CE2, and CE3 are ALL asserted active
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a
synchronous flow through burst SRAM designed specifically to
eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133 MHz
device).
■
The write enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). BWX can be used to conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
Document #: 38-05356 Rev. *I
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW for the device to
drive out the requested data. On the subsequent clock, another
operation (Read/Write/Deselect) can be initiated. When the
SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an
on-chip burst counter that provides the ability to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enable inputs or WE. WE is latched
at the beginning of a burst cycle. Therefore, the type of access
(read or write) is maintained throughout the burst sequence.
Page 10 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals.
The
CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
provides byte write capability that is described in the truth table.
Asserting the (WE) with the selected byte write select input
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remains unaltered. A synchronous
self timed write mechanism is provided to simplify the write
operations. Byte write capability is included to greatly simplify
Read/Modify/Write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is
a common IO device, data must not be driven into the device
when the outputs are active. The OE can be deasserted HIGH
before presenting data to the DQs and DQPX inputs. This
tri-states the output drivers. As a safety precaution, DQs and
DQPX are automatically tri-stated during the data portion of a
write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an
on-chip burst counter that provides the ability to supply a single
address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in the Single Write
Accesses section. When ADV/LD is driven HIGH on the
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the burst
write, to write the correct bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD)
.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, and CE3,
must remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
100
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document #: 38-05356 Rev. *I
Page 11 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Truth Table
The truth table for CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 follows. [2, 3, 4, 5, 6, 7, 8]
Address
Used
CE1
CE2
CE3
ZZ
Deselect Cycle
None
H
X
X
L
L
Deselect Cycle
None
X
X
H
L
Deselect Cycle
None
X
L
X
Continue Deselect Cycle
None
X
X
Read Cycle (Begin Burst)
External
L
Next
Operation
BWX
OE
X
X
X
L
L->H
Tri-State
L
X
X
X
L
L->H
Tri-State
L
L
X
X
X
L
L->H
Tri-State
X
L
H
X
X
X
L
L->H
Tri-State
H
L
L
L
H
X
L
L
L->H Data Out
(Q)
X
X
X
L
H
X
X
L
L
L->H Data Out
(Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle (Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
ADV/LD WE
CEN CLK
DQ
Notes
2. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for read or write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05356 Rev. *I
Page 12 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Truth Table for Read/Write[9, 10]
Function (CY7C1461AV33)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write – No Bytes Written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Truth Table for Read/Write[9, 10]
Function (CY7C1463AV33)
WE
BWb
BWa
Read
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Truth Table for Read/Write[9, 10]
Function (CY7C1465AV33)
WE
BWx
Read
H
X
Write – No Bytes Written
L
H
Write Byte X(DQx and DQPx)
L
L
Write All Bytes
L
All BW = L
Notes
9. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active
Document #: 38-05356 Rev. *I
Page 13 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3 V and 2.5 V IO logic level.
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. On power up, the device is up in a
reset state which does not interfere with the operation of the
device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending on the current state of
the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram).
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
2 1 0
1
TEST-LOGIC
RESET
TDI
Selection
Circuitry
0
0
RUN-TEST/
IDLE
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
Identification Register
0
1
CAPTURE-DR
x . . . . . 2 1 0
CAPTURE-IR
Boundary Scan Register
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
TCK
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
TAP CONTROLLER
TMS
0
PAUSE-DR
0
0
0
1
0
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05356 Rev. *I
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
On power up, the instruction register is loaded with the IDCODE
instruction. It is also loaded with the IDCODE instruction if the
controller is placed in a reset state as described in the previous
section.
Page 14 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board level serial test data path.
The IDCODE instruction is loaded into the instruction register on
power up or whenever the TAP controller is supplied a test logic
reset state.
Bypass Register
SAMPLE Z
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is
supplied during the Update IR state.
Boundary Scan Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the boundary scan
register for the SRAM in different packages is listed in the Scan
Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TAP Instruction Set
Overview
SAMPLE/PRELOAD
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in the following section in detail.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
IDCODE
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
The IDCODE instruction causes a vendor specific, 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
Document #: 38-05356 Rev. *I
BYPASS
EXTEST
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
Page 15 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
during the Shift-DR state. During Update-DR, the value loaded
into that shift register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set HIGH to enable
the output when the device is powered-up, and also when the
TAP controller is in the Test-Logic-Reset state.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
package). When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a High Z condition.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command and then shifting the desired bit into that cell,
TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document #: 38-05356 Rev. *I
UNDEFINED
Page 16 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
TAP AC Switching Characteristics
Over the Operating Range[11, 12]
Parameter
Description
Min
Max
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
–
ns
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
11. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05356 Rev. *I
Page 17 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input pulse levels................................................ VSS to 2.5 V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Input timing reference levels........................................ 1.25 V
Output reference levels ................................................. 1.5 V
Output reference levels .............................................. .1.25 V
Test load termination supply voltage ............................. 1.5 V
Test load termination supply voltage ........................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)[13]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Test Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
IOH = –100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
Note
13. All voltages referenced to VSS (GND).
Document #: 38-05356 Rev. *I
Page 18 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Identification Register Definitions
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
(1 M × 36)
(2 M × 18)
(512 K × 72)
Instruction Field
Revision Number (31:29)
Description
000
000
000
01011
01011
01011
Reserved for internal use
Architecture and Memory Type
(23:18)
001001
001001
001001
Defines memory type and
architecture
Bus Width and Density(17:12)
100111
010111
110111
Defines width and density
00000110100
00000110100
00000110100
1
1
1
Device Depth (28:24)
[14]
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number
Allows unique identification of
SRAM vendor
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Instruction
Bit Size (× 36)
Bit Size (× 18)
Bit Size (× 72)
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order (165-ball FBGA Package)
89
89
–
Boundary Scan Order (209-ball FBGA Package)
–
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document #: 38-05356 Rev. *I
Page 19 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
165-ball FBGA Boundary Scan Order [15]
CY7C1461AV33 (1 M × 36), CY7C1463AV33 (2 M × 18)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
27
D11
52
A2
77
N2
3
N10
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
A5
72
J2
23
H10
48
A4
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Note
15. Bit# 89 is preset HIGH.
Document #: 38-05356 Rev. *I
Page 20 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
209-ball FBGA Boundary Scan Order [16]
CY7C1465AV33 (512 K × 72)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
W6
36
F6
71
H6
106
K3
2
V6
37
K8
72
C6
107
K4
3
U6
38
K9
73
B6
108
K6
4
W7
39
K10
74
A6
109
K2
5
V7
40
J11
75
A5
110
L2
6
U7
41
J10
76
B5
111
L1
7
T7
42
H11
77
C5
112
M2
8
V8
43
H10
78
D5
113
M1
9
U8
44
G11
79
D4
114
N2
10
T8
45
G10
80
C4
115
N1
11
V9
46
F11
81
A4
116
P2
12
U9
47
F10
82
B4
117
P1
13
P6
48
E10
83
C3
118
R2
14
W11
49
E11
84
B3
119
R1
15
W10
50
D11
85
A3
120
T2
16
V11
51
D10
86
A2
121
T1
17
V10
52
C11
87
A1
122
U2
18
U11
53
C10
88
B2
123
U1
19
U10
54
B11
89
B1
124
V2
20
T11
55
B10
90
C2
125
V1
21
T10
56
A11
91
C1
126
W2
22
R11
57
A10
92
D2
127
W1
23
R10
58
C9
93
D1
128
T6
24
P11
59
B9
94
E1
129
U3
25
P10
60
A9
95
E2
130
V3
26
N11
61
D8
96
F2
131
T4
27
N10
62
C8
97
F1
132
T5
28
M11
63
B8
98
G1
133
U4
29
M10
64
A8
99
G2
134
V4
30
L11
65
D7
100
H2
135
W5
31
L10
66
C7
101
H1
136
V5
32
K11
67
B7
102
J2
137
U5
33
M6
68
A7
103
J1
138
Internal
34
L6
69
D6
104
K1
35
J6
70
G6
105
N6
Note
16. Bit# 138 is preset HIGH.
Document #: 38-05356 Rev. *I
Page 21 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Maximum Ratings
DC Input Voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND ......–0.5 V to +4.6 V
Range
Supply Voltage on VDDQ Relative to GND ..... –0.5 V to +VDD
DC Voltage Applied to Outputs
in Tri-State .........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
Electrical Characteristics
Over the Operating Range[17, 18]
Parameter
Description
Power Supply Voltage
VDD
IO Supply Voltage
VDDQ
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[17]
VIL
Input LOW Voltage[17]
IX
Input Leakage Current
except ZZ and MODE
Input Current of MODE
Input Current of ZZ
IOZ
IDD
Output Leakage Current
VDD Operating Supply
Current
ISB1
Automatic CE Power Down
Current—TTL Inputs
ISB2
Automatic CE Power Down
Current—CMOS Inputs
ISB3
Automatic CE Power Down
Current—CMOS Inputs
ISB4
Automatic CE Power Down
Current—TTL Inputs
Test Conditions
for 3.3 V IO
for 2.5 V IO
for 3.3 V IO, IOH = –4.0 mA
for 2.5 V IO, IOH = –1.0 mA
for 3.3 V IO, IOL = 8.0 mA
for 2.5 V IO, IOL = 1.0 mA
for 3.3 V IO
for 2.5 V IO
for 3.3 V IO
for 2.5 V IO
GND  VI  VDDQ
Input = VSS
Input = VDD
Input = VSS
Input = VDD
GND  VI  VDDQ, Output Disabled
VDD = Max, IOUT = 0 mA,
7.5 ns cycle, 133 MHz
f = fMAX = 1/tCYC
10 ns cycle, 100 MHz
7.5 ns cycle, 133 MHz
VDD = Max, Device Deselected,
VIN  VIH or VIN  VIL;
10 ns cycle, 100 MHz
f = fMAX, Inputs Switching
All speeds
VDD = Max, Device Deselected,
VIN 0.3 V or VIN > VDD – 0.3 V,
f = 0, Inputs Static
VDD = Max, Device Deselected, or 7.5 ns cycle, 133 MHz
VIN  0.3 V or VIN > VDDQ – 0.3 V 10 ns cycle, 100 MHz
f = fMAX, Inputs Switching
All Speeds
VDD = Max, Device Deselected,
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, Inputs Static
Min
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
Max
Unit
3.6
V
VDD
V
2.625
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3 V V
VDD + 0.3 V V
0.8
V
0.7
V
5
A
–30
–
–5
–
–5
–
–
–
–
–
5
–
30
5
310
290
180
180
A
A
A
A
A
mA
mA
mA
mA
–
120
mA
–
–
180
180
mA
mA
–
135
mA
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05356 Rev. *I
Page 22 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Capacitance
In the following table, the capacitance parameters are listed.[19]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CIO
Input/Output Capacitance
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Max
Max
Max
Test Conditions
TA = 25C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
6.5
7
5
pF
3
7
5
pF
5.5
6
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed[19]
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Package
Package
Package
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, according to
EIA/JESD51.
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
Figure 1. AC Test Loads and Waveforms
3.3V IO Test Load
3.3V
OUTPUT
R = 317
Z0 = 50
VT = 1.5V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5V IO Test Load
2.5V
OUTPUT
GND
R = 351
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1ns
 1ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538
(b)
10%
90%
10%
90%
 1ns
 1ns
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05356 Rev. *I
Page 23 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Switching Characteristics
Over the Operating Range[20, 21]
Parameter
Description
tPOWER[22]
133 MHz
100 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
10
–
ns
tCH
Clock HIGH
2.5
–
3.0
–
ns
tCL
Clock LOW
2.5
–
3.0
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
–
8.5
ns
tDOH
Data Output Hold After CLK Rise
2.5
–
2.5
–
ns
Clock to Low
Z[23, 24, 25]
2.5
–
2.5
–
ns
tCHZ
Clock to High
Z[23, 24, 25]
–
3.8
0
4.5
ns
tOEV
OE LOW to Output Valid
–
3.0
–
3.8
ns
0
–
0
–
ns
–
3.0
–
4.0
ns
tCLZ
tOELZ
tOEHZ
OE LOW to Output Low
Z[23, 24, 25]
OE HIGH to Output High
Z[23, 24, 25]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
1.5
–
ns
tALS
ADV/LD Setup Before CLK Rise
1.5
–
1.5
–
ns
tWES
WE, BWX Setup Before CLK Rise
1.5
–
1.5
–
ns
tCENS
CEN Setup Before CLK Rise
1.5
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.5
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
0.5
–
ns
tALH
ADV/LD Hold After CLK Rise
0.5
–
0.5
–
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
–
0.5
–
ns
tCENH
CEN Hold After CLK Rise
0.5
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
0.5
–
ns
Hold Times
Notes
20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 1 on page 23 unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 1 on page 23. Transition is measured ± 200 mV from steady-state voltage.
24. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document #: 38-05356 Rev. *I
Page 24 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Switching Waveforms
Figure 2. Read/Write Waveforms[26, 27, 28]
1
2
3
t CY C
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05356 Rev. *I
Page 25 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Switching Waveforms (continued)
Figure 3. NOP, STALL, and DESELECT Cycles[29, 30, 31]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05356 Rev. *I
Page 26 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Switching Waveforms (continued)
Figure 4. ZZ Mode Timing[32, 33]
CLK
t
ZZ
I
t ZZREC
ZZ
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or REA D Only
High-Z
DON’T CA RE
Notes
32. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
33. DQs are in High Z when exiting ZZ sleep mode.
Document #: 38-05356 Rev. *I
Page 27 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1461AV33-133AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
lndustrial
CY7C1463AV33-133AXC
CY7C1461AV33-133AXI
Ordering Code Definitions
CY 7C 146X
A V33 - 133 XX
X
Temperature range: X = C or I
C = Commercial; I = Industrial
Package Type:
AX = 100-pin TQFP (Pb-free)
Speed Grade: 133 MHz
V33 = 3.3 V
Process Technology  90 nm
146X = 1461 or 1463
1461 = FT, 1 Mb × 36 (36 Mb)
1463 = FT, 2 Mb × 18 (36 Mb)
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document #: 38-05356 Rev. *I
Page 28 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Package Diagrams
Figure 5. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050
51-85050 *D
Document #: 38-05356 Rev. *I
Page 29 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Package Diagrams (continued)
Figure 6. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165
51-85165 *B
Document #: 38-05356 Rev. *I
Page 30 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Package Diagrams (continued)
Figure 7. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167
51-85167 *A
Document #: 38-05356 Rev. *I
Page 31 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Document History Page
Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 38-05356
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
254911
See ECN
SYT
New data sheet
Part number changed from previous revision. New and old part number differ by the
letter “A”
*A
300131
See ECN
SYT
Removed 150- and 117-MHz Speed Bins
Changed JA and JC from TBD to 25.21 and 2.58 °C/W, respectively, for TQFP
package
Added Pb-free information for 100-pin TQFP, 165 FBGA and 209 FBGA packages
Added “Pb-free BG and BZ packages availability” below the Ordering Information
*B
320813
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA
Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical
Characteristics table
Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values
Replaced TBD’s for JA and JC to their respective values on the Thermal Resistance table for 165 FBGA and 209 FBGA Packages
Changed CIN, CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package
Removed “Pb-free BG packages availability” comment below the Ordering Information
*C
331551
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA
Packages according to JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced TBD to 100 mA for IDDZZ
Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by shading and unshading MPNs according to
availability
*D
417547
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 A to –30 & 5 A respectively and
also Changed IX current value in ZZ from –30 & 5 A to –5 & 30 A respectively on
page# 20
Modified test condition from VIH < VDD to VIH VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
Document #: 38-05356 Rev. *I
Page 32 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Document History Page (continued)
Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 38-05356
REV.
ECN NO. Issue Date
*E
473650
See ECN
Orig. of
Change
VKN
Description of Change
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*F
1274733
See ECN
VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform
*G
2499107
See ECN
VKN/PYRS Corrected typo in the CY7C1465AV33 ‘s Logic Block diagram
*H
2897278 03/22/2010
NJY
Removed obsolete part numbers from Ordering Information table and updated
package diagrams.
*I
3208774 03/29/2011
NJY
Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagrams.
Updated in new template.
Document #: 38-05356 Rev. *I
Page 33 of 34
[+] Feedback
CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05356 Rev. *I
Revised March 29, 2011
Page 34 of 34
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
[+] Feedback
Similar pages