TI CD74HC297 High-speed cmos logic digital phase-locked-loop Datasheet

[ /Title
(CD74
HC297
,
CD74
HCT29
7)
/Subject
(HighSpeed
CMOS
Logic
Digital
PhaseLocked
CD74HC297,
CD74HCT297
Data sheet acquired from Harris Semiconductor
SCHS177
High-Speed CMOS Logic
Digital Phase-Locked-Loop
November 1997
Features
Description
• Digital Design Avoids Analog Compensation Errors
The Harris CD74HC297 and CD74HCT297 are high-speed
silicon gate CMOS devices that are pin-compatible with low
power Schottky TTL (LSTTL).
• Easily Cascadable for Higher Order Loops
• Useful Frequency Range
- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)
These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the
exception of the divide-by-N counter, to build first-order
phase-locked-loops.
• Dynamically Variable Bandwidth
• Very Narrow Bandwidth Attainable
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
have a 50% duty factor to obtain the maximum lock-range.
• Power-On Reset
• Output Capability
- Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/DOUT
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the
designer to incorporate ripple cancellation (see Figure 2) or to
cascade to higher order phase-locked-loops.
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The length of the up/down K-counter is digitally programmable
according to the K-counter function table. With A, B, C and D
all LOW, the K-counter is disabled. With A HIGH and B, C and
D LOW, the K-counter is only three stages long, which widens
the bandwidth or capture range and shortens the lock time of
the loop. When A, B, C and D are all programmed HIGH, the
K-counter becomes seventeen stages long, which narrows
the bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A to
D inputs can maximize the overall performance of the digital
phase-locked-loop.
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• CD74HC297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V
- High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
• CD74HCT297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility
VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility II ≤ 1µA at VOL, VOH
The CD74HC297 and CD74HCT297 can perform the classic
first order phase-locked-loop function without using analog
components. The accuracy of the digital phase-locked-loop
(DPLL) is not affected by VCC and temperature variations but
depends solely on accuracies of the K-clock and loop propagation delays.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
PKG.
NO.
CD74HC297E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT297E
-55 to 125
16 Ld PDIP
E16.3
Pinout
CD74HC297, CD74HCT297 (PDIP)
TOP VIEW
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
B 1
16 VCC
A 2
15 C
ENCTR 3
14 D
KCP 4
I/DCP 5
D/U 6
I/DOUT 7
GND 8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
13 φA2
12 ECPDOUT
11 XORPDOUT
10 φB
9 φA 1
File Number
1852.1
CD74HC297, CD74HCT297
Functional Diagram
The phase detector generates an error signal waveform that,
at zero phase error, is a 50% duty factor square wave. At the
limits of linear operation, the phase detector output will be
either HIGH or LOW all of the time depending on the direction
of the phase error (φIN - φOUT). Within these limits the phase
detector output varies linearly with the input phase error
according to the gain Kd, which is expressed in terms of
phase detector output per cycle or phase error. The phase
detector output can be defined to vary between ±1 according
to the relation:
D
4
KCP
6
D/U
3
C
14 15
B
A
1
2
CARRY
MODULO-K
COUNTER
5
I/DCP
9
φA1
11
10
φB
The output of the phase detector will be Kdφe, where the
phase error φe = φIN - φOUT.
I/DOUT
I/D
CKT
ENCTR
%HIGH - %LOW
phase detector output = -------------------------------------------100
7
BORROW
J
13
φA2
K
F/F
12
Q
XORPDOUT
ECPDOUT
FUNCTION TABLE
EXCLUSIVE-OR PHASE DETECTOR
EXCLUSIVE-OR phase detectors (XORPD) and edge-controlled phase detectors (ECPD) are commonly used digital
types. The ECPD is more complex than the XORPD logic
function but can be described generally as a circuit that
changes states on one of the transitions of its inputs. The gain
(Kd) for an XORPD is 4 because its output remains HIGH
(XORPDOUT = 1) for a phase error of one quarter cycle.
Similarly, Kd for the ECPD is 2 since its output remains HIGH
for a phase error of one half cycle. The type of phase detector
will determine the zero-phase-error point, i.e., the phase separation of the phase detector inputs for a φe defined to be
zero. For the basic DPLL system of Figure 3, φe = 0 when the
phase detector output is a square wave.
φA1
φB
XORPD OUT
L
L
L
L
H
H
H
L
H
H
H
L
FUNCTION TABLE
EDGE-CONTROLLED PHASE DETECTOR
The XORPD inputs are one quarter cycle out-of-phase for
zero phase error. For the ECPD, φe = 0 when the inputs are
one half cycle out of phase.
The phase detector output controls the up/down input to the
K-counter. The counter is clocked by input frequency Mfc
which is a multiple M of the loop center frequency fc. When
the K-counter recycles up, it generates a carry pulse. Recycling while counting down generates a borrow pulse. If the
carry and the borrow outputs are conceptually combined into
one output that is positive for a carry and negative for a borrow, and if the K-counter is considered as a frequency divider
with the ratio Mfc/K, the output of the K-counter will equal the
input frequency multiplied by the division ratio. Thus the output from the K-counter is (KdφeMfc)/K.
φA2
φB
ECPD OUT
H or L
↓
H
↓
H or L
L
H or L
↑
No Change
↑
H or L
No Change
H = Steady-State High Level, L = Steady-State Low Level, ↑ = LOW
to HIGH φ Transition, ↓ = HIGH to LOW φ Transition
K-COUNTER FUNCTION TABLE
(DIGITAL CONTROL)
The carry and borrow pulses go to the increment/decrement
(I/D) circuit which, in the absence of any carry or borrow
pulses has an output that is one half of the input clock (I/DCP).
The input clock is just a multiple, 2N, of the loop center frequency. In response to a carry of borrow pulse, the I/D circuit
will either add or delete a pulse at I/DOUT. Thus the output of
the I/D circuit will be Nfc + (KdφeMfc)/2K.
The output of the N-counter (or the output of the phaselocked-loop) is thus: fo = fc + (KdφeMfc)/2KN.
If this result is compared to the equation for a first-order analog phase-locked-loop, the digital equivalent of the gain of the
VCO is just Mfc/2KN or fc/K for M = 2N.
Thus, the simple first-order phase-locked-loop with an adjustable K-counter is the equivalent of an analog phase-lockedloop with a programmable VCO gain.
2
A
MODULO
(K)
L
L
Inhibited
L
H
23
L
H
L
24
L
L
H
H
25
L
H
L
L
26
L
H
L
H
27
L
H
H
L
28
L
H
H
H
29
H
L
L
L
210
H
L
L
H
211
H
L
H
L
212
H
L
H
H
213
H
H
L
L
214
H
H
L
H
215
H
H
H
L
216
H
H
H
H
217
D
C
B
L
L
L
L
L
CD74HC297, CD74HCT297
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-6
(Note 4)
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
(Note 4)
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
(Note 4)
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
(Note 4)
6
-
-
0.26
-
0.33
-
0.4
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
VOL
VIH or
VIL
-
-
3
CD74HC297, CD74HCT297
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
II
VCC or
GND
-
ICC
VCC or
GND
High Level Input
Voltage
VIH
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
PARAMETER
Input Leakage
Current
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
±0.1
-
±1
-
±1
µA
0
6
-
-
8
-
80
-
160
µA
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VOH
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 3)
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
5. XORPD, ECPD
HCT Input Loading Table
INPUT
UNIT LOADS
ENCTR, D/U
0.3
A, B, C, D, KCP, φA2
0.6
I/DCP, φA1, φB
1.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
4
CD74HC297, CD74HCT297
Prerequisite For Switching Function
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Maximum Clock Frequency
KCP
fMAX
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
Maximum Clock Frequency
I/DCP
fMAX
2
4
-
3
-
2
-
MHz
4.5
20
-
16
-
13
-
MHz
6
24
-
19
-
15
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
125
-
155
-
190
-
ns
4.5
25
-
31
-
38
-
ns
6
21
-
26
-
32
-
ns
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
HC TYPES
Clock Pulse Width
KCP
tw
Clock Pulse Width
I/DCP
tW
Set-up Time
D/U, ENCTR to KCP
tSU
Hold Time
D/U, ENCTR to KCP
tH
HCT TYPES
Maximum Clock Frequency
KCP
fMAX
4.5
30
-
24
-
20
-
MHz
Maximum Clock Frequency
I/DCP
fMAX
4.5
20
-
16
-
13
-
MHz
Clock Pulse Width
KCP
tw
4.5
16
-
20
-
24
-
ns
Clock Pulse Width
I/DCP
tw
4.5
25
-
31
-
38
-
ns
Set-up Time
D/U, ENCTR to KCP
tSU
4.5
20
-
25
-
30
-
ns
Hold Time
D/U, ENCTR to KCP
tH
4.5
0
-
0
-
0
-
ns
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
34
43
ns
HC TYPES
Propagation Delay,
I/DCP to I/DOUT
5
CD74HC297, CD74HCT297
Switching Specifications
PARAMETER
Propagation Delay,
φA1, φB to XORPDOUT
Propagation Delay,
φB, φA2 to ECPDOUT
Output Transition Time
XORPDOUT
ECPDOUT
Output Transition Time
I/DOUT
Input Capacitance
Input tr, tf = 6ns (Continued)
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
tPHL, tPHL
tTLH
tTLH
CI
CL = 50pF
CL = 50pF
CL = 50pF
-
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
2
-
200
250
300
ns
4.5
-
40
50
60
ns
6
-
34
43
51
ns
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
2
-
60
75
90
ns
4.5
-
12
15
18
ns
6
-
10
13
15
ns
-
-
10
10
10
pF
HCT TYPES
Propagation Delay,
I/DCP to I/DOUT
tPLH, tPHL
CL = 50pF
4.5
-
35
44
53
ns
Propagation Delay,
φA1, φB to XORPDOUT
tPLH, tPHL
CL = 50pF
4.5
-
30
38
45
ns
Propagation Delay,
φB, φA2 to ECPDOUT
tPHL, tPHL
CL = 50pF
4.5
-
40
50
60
ns
Output Transition Time
XORPDOUT
tTLH
CL = 50pF
4.5
-
15
19
22
ns
Output Transition Time
ECPDOUT
tTLH
CL = 50pF
4.5
-
12
15
18
ns
-
-
10
10
10
pF
Input Capacitance
CI
-
6
CD74HC297, CD74HCT297
Logic Diagram
MODULO-K COUNTER
2
1
A
B
1
2
4
8
15
C
D
14
CONTROL CIRCUIT
14 13 12 11 10
0
9
8
7
6
5
4
3
2
1
TO MODE CONTROLS 12-2
(11 STAGES NOT SHOWN)
KCP
4
6
D/U
RD
D
CP FF
Q
T
RD
FF
Q
T
FF
R Q
T
FF
Q
R
D D
T FF14
R
D DQ
T FF13
Q
M
R
D DQ
T FF1
M
M
RD
T
Q
FF
T
Q
FF
3
ENCTR
D
M
T
CP FF
Q
D
FF
R Q
D
T
M
FF14
Q
T FF1
M
Q
T
FF13
DR
D
DR Q
D
DR
RD
D
POWER ON RESET
1=1 1
BORROW
CARRY
INCREMENT/DECREMENT CIRCUIT
5
I/DCP
7
I/DOUT
D
D
Q
CP FF
Q
Q
CP FF
Q
D
D
Q
CP FF
CP FF
Q
Q
CP FF
J
K
D
Q
CP FF
Q
φA1
D
Q
CP FF
Q
D
Q
D
Q
CP FF
CP FF
Q
9
EXCLUSIVE-OR PHASE DETECTOR
11
XORPDOUT
10
φB
EDGE-CONTROLLED PHASE DETECTOR
φA2
13
SD
Q
FF
Q
RD
12
SD
Q
FF
Q
RD
ECPDOUT
7
CD74HC297, CD74HCT297
CARRY
KCP
MfC
D/U
DIVIDE-BY-K
COUNTER
ENCTR
BORROW
XORPDOUT
φA1
φB
fOUT
φOUT
I/D CIRCUIT
ECPDOUT
φA2
fIN
φIN
J
I/DCP
2NfC
J
ECPD
K
FF
I/DOUT
DIVIDE-BY-N
COUNTER
FIGURE 1. DPLL USING BOTH PHASE DETECTORS IN A RIPPLE-CANCELLATION SCHEME
CARRY
KCP
MfC
D/U
DIVIDE-BY-K
COUNTER
BORROW
XORPDOUT
φA 1
φB
fOUT
φIN
I/D CIRCUIT
I/DCP
I/DOUT
fOUT
DIVIDE-BY-N
COUNTER
φOUT
FIGURE 2. DPLL USING EXCLUSIVE-OR PHASE DETECTION
CARRY PULSE
(INTERNAL SIGNAL)
BORROW PULSE
(INTERNAL SIGNAL)
I/DCP INPUT
I/DOUT OUTPUT
FIGURE 3. TIMING DIAGRAM: I/DOUT IN-LOCK CONDITION
8
2NfC
CD74HC297, CD74HCT297
øB INPUT
øA2 INPUT
ECPDOUT OUTPUT
FIGURE 4. TIMING DIAGRAM: EDGE CONTROLLED PHASE COMPARATOR WAVEFORMS
øB INPUT
øA1 INPUT
XORPDOUT OUTPUT
FIGURE 5. TIMING DIAGRAM: EXCLUSIVE OR PHASE DETECTOR WAVEFORMS
I/fMAX
tW
I/DCP
VS
tPHL
tPLH
VS
I/DOUT
tTLH
tTHL
FIGURE 6. WAVEFORMS SHOWING THE CLOCK (I/DCP) TO OUTPUT (I/DOUT) PROPAGATION DELAYS, CLOCK PULSE WIDTH,
OUTPUT TRANSITION TIMES AND MAXIMUM CLOCK PULSE FREQUENCY
VS
øB INPUT
VS
øA1 INPUT
tTLH
XORPDOUT
VS
OUTPUT
tPLH
tPLH
tPLH
tTHL
tPHL
FIGURE 7. WAVEFORMS SHOWING THE PHASE INPUT (øB, øA1) TO OUTPUT (XORPDOUT) PROPAGATION DELAYS AND
OUTPUT TRANSITION TIMES
9
CD74HC297, CD74HCT297
øB INPUT
VS
øA2 INPUT
VS
ECPDOUT
OUTPUT
tPHL
VS
tPLH
tTLH
tTHL
FIGURE 8. WAVEFORMS SHOWING THE PHASE INPUT (øB, øA2) TO OUTPUT (ECPDOUT) PROPAGATION DELAYS AND OUTPUT
TRANSITION TIMES
tH
D/U, ENCTR
INPUT
tH
VS
tSU
tSU
VS
KCP INPUT
tW
1/fMAX
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
FIGURE 9. WAVEFORMS SHOWING THE CLOCK (KCP) PULSE WIDTH AND MAXIMUM CLOCK PULSE FREQUENCY, AND THE
INPUT (D/U, ENCTR) TO CLOCK (KCP) SETUP AND HOLD TIMES
10
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