INTEGRATED CIRCUITS 74ALVCH16373 2.5V/3.3V 16-bit D-type transparent latch (3-State) Product specification Supersedes data of 1998 Jun 29 IC24 Data Handbook 1999 Sep 20 Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) FEATURES 74ALVCH16373 PIN CONFIGURATION • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C • Current drive ±24 mA at 3.0 V 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 DESCRIPTION 1Q7 12 37 1D7 The 74ALVCH16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE SW00066 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns PARAMETER SYMBOL tPHL/tPLH CI CONDITIONS TYPICAL Propagation g delay y Dn to Qn VCC = 2.5V, CL = 30pF 2.1 VCC = 3.3V, CL = 50pF 2.1 Propagation delay g y LE to Qn VCC = 2.5V, CL = 30pF 2.2 VCC = 3.3V, CL = 50pF 2.2 Input capacitance CPD 5.0 Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled 16 Outputs disabled 10 UNIT ns pF pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16373 DL ACH16373 DL SOT370-1 48-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16373 DGG ACH16373 DGG SOT362-1 1999 Sep 20 2 853-2086 22418 Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 PIN DESCRIPTION LOGIC SYMBOL PIN NUMBER SYMBOL 1 1OE Output enable input (active LOW) 2, 3, 5, 6, 8, 9, 11, 12 1Q0 to 1Q7 Data inputs/outputs 4, 10, 15, 21, 28, 34, 39, 45 GND 7, 18, 31, 42 VCC 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 24 2OE 25 2LE 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 1D0 to 1D7 48 1LE NAME AND FUNCTION Ground (0V) Positive supply voltage Data inputs/outputs Output enable input (active LOW) Latch enable input (active HIGH) Data inputs Data inputs Latch enable input (active HIGH) 1 24 1OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 36 2D0 2Q0 13 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 1LE 2LE 48 25 SW00067 LOGIC DIAGRAM 1D0 D Q 1Q0 D 2D0 LATCH 1 LE Q 2Q0 LATCH 9 LE LE 1LE 2LE 1OE 2OE TO 7 OTHER CHANNELS LE TO 7 OTHER CHANNELS SW00068 FUNCTION TABLE (per section of eight bits) INPUTS OUTPUTS nOE nLE nDn INTERNAL LATCHES Enable and read register (transparent mode) L L H H L H L H L H Latch and read register (hold mode) L L L L l h L H L H Latch register and disable outputs H H L L l h L H Z Z OPERATING MODES H h L l X Z = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = don’t care = high impedance OFF-state 1999 Sep 20 3 nQn Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 LOGIC SYMBOL (IEEE/IEC) 1OE 1 1EN 1LE 48 C3 2OE 24 2EN 2LE 25 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 47 BUS HOLD CIRCUIT VCC C4 2 1Q0 46 3 1Q1 44 5 1Q2 43 6 1Q3 41 8 1Q4 40 9 38 11 1Q6 37 12 1Q7 13 2Q0 35 14 2Q1 33 16 2Q2 32 17 2Q3 30 19 2Q4 29 20 2Q5 27 22 2Q6 26 23 36 1∇ 3D 2∇ 4D Data Input To internal circuit 1Q5 SW00044 2Q7 SW00524 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER MAX DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 For data input pins 0 VCC For control pins 0 5.5 0 VCC V –40 +85 °C 0 0 20 10 ns/V V DC Input voltage range VO DC output voltage range tr, tf 1999 Sep 20 UNIT MIN VI Tamb CONDITIONS Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V 4 V Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS DC supply voltage VI t0 IIK DC input diode current VI input DC in ut voltage IOK DC output diode current VO uVCC or VO t 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT RATING –0.5 to +4.6 V –50 mA For control pins2 –0.5 to +4.6 For data inputs2 –0.5 to VCC +0.5 V "50 DC VCC or GND current Storage temperature range Power dissipation per package –plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP) UNIT For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K mA –0.5 to VCC +0.5 V "50 mA "100 mA –65 to +150 °C 850 600 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage TYP1 VCC = 1.2V VCC VCC = 1.8V 0.7*VCC 0.9 VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 V VCC = 1.2V VIL VOH 1999 Sep 20 LOW level Input voltage HIGH level output voltage UNIT MAX GND VCC = 1.8V 0.9 0.2*VCC VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8 8 to 3 6V; VI = VIH or VIL; IO = –100µA 100µA VCC = 1 1.8 3.6V; 02 VCC*0.2 VCC VCC = 1.8V; VI = VIH or VIL; IO = –6mA VCC*0.4 VCC*0.10 VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC*0.3 VCC*0.08 VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC*0.17 VCC = 2.3V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC*0.26 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC*0.14 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC*0.28 5 V V Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). 8 to 3 6V; VI = VIH or VIL; IO = 100µA VCC = 1 1.8 3.6V; GND 0 20 0.20 VCC = 1.8V; VI = VIH or VIL; IO = 6mA 0.09 0.30 VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.20 VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.40 VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.23 0.60 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 Input leakage current per control pin VCC = 1.8 to 3.6V; VI = 5.5V or GND 0.1 5 Input leakage g current per data pin VCC = 1.8 to 3.6V; VI = VCC or GND 01 0.1 5 Input current for common I/O pins VCC = 1.8 to 2.7V; VI = VCC or GND 0.1 10 VCC = 3.6V; VI = VCC or GND 0.1 15 IOZ 3-State output OFF-state current VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 40 Quiescent supply current VCC = 1.8 to 2.7V; VI = VCC or GND; IO = 0 0.2 ICC VCC = 2.7 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 Additional quiescent supply current given per control pin VCC = 2.7V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 Additional quiescent supply current given per data I/O pin VCC = 2.7V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 VOL II IIHZ/IILZ ∆ICC LOW level output voltage µA µA µA µA µA IBHL2 Bus hold LOW sustaining g current VCC = 2.3V; VI = 0.7V 45 – VCC = 3.0V; VI = 0.8V 75 150 IBHH2 Bus hold HIGH sustaining g current VCC = 2.3V; VI = 1.7V –45 VCC = 3.0V; VI = 2.0V –75 2 IBHLO O Bus hold LOW overdrive current VCC = 2.7V 300 VCC = 3.6V 450 2 IBHHO O Bus hold HIGH overdrive current VCC = 2.7V –300 VCC = 3.6V –450 NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts. 1999 Sep 20 V 6 –175 µA µA µA µA Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE AND VCC < 2.3V GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.3 to 2.7V VCC = 1.8V VCC = 1.2V MIN TYP1, 2 MAX MIN TYP1 MAX TYP UNIT tPHL/tPLH Propagation delay nDn to nYn 1, 5 1.0 2.1 3.9 1.5 3.2 5.7 8.8 ns tPHL/tPLH Propagation delay nLE to nYn 2, 5 1.0 2.2 3.9 1.5 3.4 5.9 7.4 ns tPZH/tPZL 3-State output enable time nOE to nYn 4, 5 1.0 2.6 5.2 1.5 4.0 7.3 8.9 ns tPHZ/tPLZ 3-State output disable time nOE to nYn 4, 5 1.0 2.2 4.1 1.5 3.2 5.6 8.9 ns tW nLE pulse width HIGH 2 3.0 1.0 – 3.5 1.0 – – ns tSU Set-up time nDn to nLE 3 1.0 –0.1 – 1.0 –0.1 – – ns Hold time nDn to nLE 3 1.5 0.2 – 1.2 0.1 – – ns th NOTES: 1. All typical values are measured at Tamb = 25°C. 2. Typical value is measured at VCC = 2.5V. AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V VCC = 2.7V MIN TYP1, 2 MAX MIN TYP1 MAX WAVEFORM UNIT tPHL/tPLH Propagation delay nDn to nYn 1, 5 1.0 2.1 3.3 1.0 2.3 3.7 ns tPHL/tPLH Propagation delay nLE to nYn 2, 5 1.0 2.2 3.2 1.0 2.2 3.5 ns tPZH/tPZL 3-State output enable time nOE to nYn 4, 5 1.0 2.3 4.2 1.0 2.9 4.9 ns tPHZ/tPLZ 3-State output disable time nOE to nYn 4, 5 1.0 2.8 4.1 1.0 3.1 4.7 ns tW nLE pulse width HIGH 2 2.5 1.0 – 3.0 1.0 – ns tSU Set-up time nDn to nLE 3 1.0 0.0 – 1.0 –0.1 – ns Hold time nDn to nLE 3 1.2 0.2 – 1.5 0.4 – ns th NOTES: 1. All typical values are measured at Tamb = 25°C. 2. Typical value is measured at VCC = 3.3V. 1999 Sep 20 7 Philips Semiconductors Product specification 16-bit D-type transparent latch (3-State) 74ALVCH16373 AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE VI VM OE INPUT VM = 0.5 VCC VX = VOL + 0.15V VY = VOH –0.15V VOL and VOH are the typical output voltage drop that occur with the output load. V =V CC I VM GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE VM VX VOL VM = 1.5 V VX = VOL + 0.3V VY = VOH –0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I tPHZ tPZH VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND VI outputs enabled Dn INPUT outputs disabled outputs enabled VM VM SW00072 GND Waveform 4. 3-State enable and disable times tPHL tPLH TEST CIRCUIT VOH Qn OUTPUT VM S1 VCC VOL SW00070 Waveform 1. Input (Dn) to output (Qn) propagation delays RL = 500 Ω VO VI PULSE GENERATOR 2 * VCC Open GND D.U.T. RT RL = 500 Ω CL VI LE INPUT VM VM VM Test Circuit for switching times GND DEFINITIONS tw tPHL tPLH RL = Load resistor VOH CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM Qn OUTPUT SWITCH POSITION VOL TEST SW00071 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays tPLH/tPHL ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ tPLZ/tPZL tPHZ/tPZH S1 Open 2 VCC VCC VI < 2.7V VCC 2.7–3.6V 2.7V GND VI Dn INPUT SV00906 VM Waveform 5. Load circuitry for switching times GND th th tSU tSU VI LE INPUT VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SW00073 Waveform 3. Data set-up and hold times for the Dn input to the LE input 1999 Sep 20 8 Philips Semiconductors Product specification 2.5V/3.3V 16-bit D-type transparent latch (3-State) SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 1999 Sep 20 9 74ALVCH16373 SOT370-1 Philips Semiconductors Product specification 2.5V/3.3V 16-bit D-type transparent latch (3-State) TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1999 Sep 20 10 74ALVCH16373 SOT362-1 Philips Semiconductors Product specification 2.5V/3.3V 16-bit D-type transparent latch (3-State) NOTES 1999 Sep 20 11 74ALVCH16373 Philips Semiconductors Product specification 2.5V/3.3V 16-bit D-type transparent latch (3-State) 74ALVCH16373 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 10-99 Document order number: 1999 Sep 20 12 9397-750-06515