SILABS C8051F351-GM 50 mips, 8 kb flash, 24-bit adc, 28-pin mixed-signal mcu Datasheet

C8051F351
50 MIPS, 8 kB Flash, 24-Bit ADC, 28-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
-
24-Bit ADC
-
0.0015% nonlinearity
Programmable throughput up to 1 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 128, 64, 32, 16, 8, 4, 2, 1
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
-
Memory
-
Two 8-Bit Current DACs
Comparator
-
-
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
-
28-pin QFN (lead-free package)
Ordering Part Numbers
Temperature Range: –40 to +85 °C
AV+
AGND
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes)
2x clock multiplier to achieve 50 MHz internal clock
Can switch between clock sources on-the-fly
Package
Typical operating current: 17 mA at 50 MHz
16 µA at 32 kHz
Typical stop mode current: <0.1 µA
VDD
GND
17 port I/O; all 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
16-bit programmable counter array with three capture/compare modules,
WDT
4 general-purpose 16-bit counter/timers
Realtime clock mode using PCA or timer and external clock source
Clock Sources
Supply Voltage: 2.7 to 3.6 V
-
768 bytes data RAM
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digital Peripherals
16 Programmable hysteresis values and response time
Configurable to generate interrupts or reset
Low current (0.4 µA)
Internal Voltage Reference
VDD Monitor/Brown-out Detector
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
-
C8051F351-GM
Digital Power
Analog
Power
C2D
Debug HW
Reset
RST/C2CK
POR
BrownOut
External
Oscillator
Circuit
XTAL1
XTAL2
System
Clock
24.5 MHz 2%
Internal
Oscillator
Clock
Multiplier
P0.0
8 kB
FLASH
8
0
5
1
256 Byte
SRAM
512 Byte
XRAM
C
o SFR Bus
r
e
D
r
v
UART
Timer 0,
1, 2, 3
X
B
A
R
3-Chnl
PCA/
WDT
SMBus
VREF
+
CP0
CP0A
SPI Bus
VREF+
VREF-
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P
0
Port 0
Latch
-
Port 1
Latch
Offset
DAC
AIN3
AIN4
AIN5
AIN6
AIN7
A
M
U
X
Precision Mixed Signal
Buffer
+
+
PGA
8-bit
IDAC0
24-bit
ADC0
CP0-
AIN4-7
P
1
AIN0
AIN1
AIN2
CP0+
D
r
v
P1.0/AIN4
P1.1/AIN5
P1.2/AIN6
P1.3/AIN7
P1.4/CP0A
P1.5/CP0
P1.6/IDAC0
P1.7/IDAC1
8-bit
IDAC1
Temp
Sensor
C2D
Port 2
Latch
Copyright © 2005 by Silicon Laboratories
P2.0/C2D
5.5.2005
C8051F351
50 MIPS, 8 kB Flash, 24-Bit ADC, 28-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1x, MDCLK = 2.4567 MHz,
Decimation Ratio = 1920 unless otherwise specified)
PARAMETER
CONDITIONS
GLOBAL CHARACTERISTICS
Supply Voltage
Supply Current
Clock = 50 MHz
(CPU active)
Clock = 1 MHz
Clock = 32 kHz; VDD Monitor Enabled
Supply Current
Oscillator not running; VDD Monitor
(shutdown)
Disabled
Clock Frequency Range
24-BIT A/D CONVERTER
Resolution
(no missing codes)
Integral Nonlinearity
Single-ended Mode
Differential Mode
Offset Error
Gain Error
Common Mode Rejection
Ratio (CMRR)
Power Supply Rejection,
DC
Power Supply Current
MIN
TYP
2.7
MAX
UNITS
3.6
V
mA
mA
µA
µA
50
MHz
±15
bits
ppm FS
17
0.5
16
0.1
DC
24
±5
±0.002
110
ppm
%
dB
80
8-BIT CURRENT-MODE D/A CONVERTERS
Resolution
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
dB
230
µA
8
±0.5
±0.5
bits
LSB
LSB
±1
C8051F350DK Development Kit
Package Information
14
13
12
11
9
10
8
Bottom View
L
7
15
16
D2
D2
2
5
17
e
E2
4
2
20
21
22
23
24
25
26
27
DETAIL 1
28
1
18
19
E2
2
3
R
6xe
E
b
6
6xe
D
Side View
A
A1
A2
A3
b
D
D2
E
E2
e
L
N
ND
NE
R
AA
BB
CC
DD
MIN
0.80
0
0
0.18
2.90
2.90
0.45
MM
TYP
0.90
0.02
0.65
0.25
0.23
5.00
3.15
5.00
3.15
0.5
0.55
28
7
7
MAX
1.00
0.05
1.00
0.30
3.35
3.35
0.65
0.09
0.435
0.435
0.18
0.18
DETAIL 1
Precision Mixed Signal
CC
DD
e
A1
A3
BB
A
A2
AA
Copyright © 2005 by Silicon Laboratories
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
5.5.2005
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