Sony CXA2543R Decoder/driver/timing generator for color lcd panel Datasheet

CXA2543R
Decoder/Driver/Timing Generator for Color LCD Panels
Description
The CXA2543R is an IC designed exclusively to
drive the color LCD panel DCX501BK and LCX018AK.
This IC greatly reduces the number of circuits and
parts required to drive LCD panels by incorporating
RGB decoder functions for video signals, driver
functions, and a timing generator for driving panels
onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various mode
settings and adjustments to be performed through
direct control from an external microcomputer, etc.
Features
• Color LCD panel DCX501BK and LCX018AK driver
• Supports NTSC and PAL signals
• Supports 16:9 wide display
• Supports composite inputs, Y/C inputs and Y/color
difference inputs
• Serial interface circuit
• Electronic attenuators (D/A converter)
• BPF, trap and delay line
• Sharpness function
• 2-point γ correction circuit
• R, G, B signal delay time adjustment circuit
• Polarity inversion circuit (line inverted mode)
• Supports external RGB input
• Supports AC drive for LCD panel during no signal
Applications
• Compact LCD monitors
• LCD viewfinders
• Compact liquid crystal projectors, etc.
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC1 – GND1 6
VCC2 – GND2 14
VCC3 – GND3 14
VDD1 – VSS1 4.5
VDD1 – VSS2 4.5
•
•
•
•
•
V
V
V
V
V
Analog input pin voltage VINA
–0.3 to VCC
V
Digital input pin voltage VIND –0.3 to VDD1 + 0.3 V
Operating temperature Topr
–15 to +75 °C
Storage temperature
Tstg
–40 to +125 °C
Allowable power dissipation∗1
PD (Ta ≤ 75°C) 350 mW
Operating conditions
Supply voltage VCC1 – GND1
VCC2 – GND2
VCC3 – GND3
VDD1 – VSS1
VDD1 – VSS2
4.25 to 5.25
11.0 to 13.5
11.0 to 13.5
2.7 to 3.6
2.7 to 3.6
V
V
V
V
V
∗1 With substrate Size: 30 × 30 × 1.6mm
Material: Glass fabric base epoxy
Structure
Bipolar CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98403-PS
CXA2543R
38
GND3
SCLK
39
DATA
40
+12V
LOAD
41
RGT
42
FB PSIG
43
GND2
GND3
44
PSIG
G OUT
45
VCC3
FB G
46
B OUT
R OUT
47
FB B
FB R
48
+12V
GND2
VCC2
Block Diagram
37
36
35
34
33
Buf
Buf
VCC1 49 +4.5V
Buf
Buf
Buf
SERIAL
BUS I/F
SIG. CENTER 50
VSS2 31 VSS2
POL SW
PSIG-BRT
B-Y IN 51
CLAMP
PAL ID
32 VD
PSIGBRIGHT
30 EN
DEMOD
R-Y IN 52
POL SW
PAL
SW
COLOR
EXT COLOR
& BALANCE
HUE
C OUT 53
WIDE
VTST
R-BRT
B-BRT
BLK LIM 54
APC
VXO
HUE
27 VCK2
BRIGHT
VPAL
VWIN
BRIGHT
LPF
PS
29 XEN
28 VCK1
FRP
SUBBRIGHT
INT/EXT
APC 55
VGATE
26 VST
PALSW
HUE
VXO OUT 56
S/H
MATRIX
COLOR
25 XVST
COLOR CONT
CONTRAST
VXO IN 57
CONTRAST
ACC DET
V REG 58
R G B
γ -1
24 FLD IN
GAMMA
D/A
γ -2
REG.
HD
23 HD
KILLER
C IN 59
TEST3 60
EXT SW
BPF
22 PCG
PIC CONT
ACC AMP
21 XPCG
FILT ADJ
Y IN 61
CLP
BGP
SBLK
PIC 62
F0 ADJ 63
HAFC
PLL-COUNTER
& DECODER
HCNT
H-PULSE
19 HCK2
V SEP
CLAMP
HGATE
H-SKEW DET
DL1
TRAP
20 HCK1
PD
18 HST
SYNC SEP
17 XHST
PWRST 64
H. FILTER
GND1
S.SEP IN
EXT R
EXT G
11
12
13
14
15
16
VDD1
H.FIL OUT
10
CKO
SYNC IN
9
CKI
GND1
+3V
8
VSS1
7
RPD
6
TEST2
5
TEST1
4
VD IN
3
EXT B
2
TRAP
VSS1
1
–2–
CXA2543R
Pin Description
Pin
No.
Symbol
I/O
Description
1
TRAP
External trap connection
2
GND1
Analog (4.5V) GND
3
SYNC IN
I
Video input for sync separation
4
H.FIL OUT
O
Video output for sync input
5
S.SEP IN
I
Sync separation circuit input
6
EXT R
I
External digital input R
7
EXT G
I
External digital input G
8
EXT B
I
External digital input B
9
VD IN
I
External vertical sync input
10
TEST1
Test (Leave this pin open.)
11
TEST2
Test (Leave this pin open.)
12
RPD
13
VSS1
14
CKI
I
Oscillation cell input
15
CKO
O
Oscillation cell output
16
VDD1
17
XHST
O
XH start pulse output (HST reversed polarity)
18
HST
O
H start pulse output
19
HCK2
O
H clock pulse 2 output
20
HCK1
O
H clock pulse 1 output
21
XPCG
O
XPCG pulse output (PCG reversed polarity)
22
PCG
O
PCG pulse output
23
HD
O
HD pulse output
24
FLD IN
I
Field identification input
25
XVST
O
XV start pulse output (VST reversed polarity)
26
VST
O
V start pulse output
27
VCK2
O
V clock pulse 2 output
28
VCK1
O
V clock pulse 1 output
29
XEN
O
XEN pulse output (EN reversed polarity)
30
EN
O
EN pulse output
31
VSS2
32
VD
O
Input pin
for open
status
H
Phase comparator output
Digital (3V) GND for oscillation cell
Digital 3V power supply
H
Digital (3V) GND
O
VD pulse output
(H: Pull up)
–3–
CXA2543R
Pin
No.
Symbol
I/O
Description
Input pin
for open
status
33
SCLK
I
Serial interface clock input
H
34
DATA
I
Serial interface data input
H
35
LOAD
I
Serial interface load input
H
36
RGT
I
Switches between Normal scan (H) and Reverse scan (L)
H
37
FB PSIG
O
PSIG signal DC voltage feedback circuit capacitor connection
38
GND3
39
PSIG
40
VCC3
41
B OUT
O
B signal output
42
FB B
O
B signal DC voltage feedback circuit capacitor connection
43
GND2
44
G OUT
O
G signal output
45
FB G
O
G signal DC voltage feedback circuit capacitor connection
46
R OUT
O
R signal output
47
FB R
O
R signal DC voltage feedback circuit capacitor connection
48
VCC2
Analog 12V power supply
49
VCC1
Analog 4.5V power supply
50
SIG.CENTER
I
R, G, B and PSIG output DC voltage adjustment
51
B-Y IN
I
B-Y demodulator input (or B-Y color difference signal input)
52
R-Y IN
I
R-Y demodulator input (or R-Y color difference signal input)
53
C OUT
O
Chroma signal output
54
BLK LIM
I
Black peak limiter level adjustment
55
APC
O
APC detective filter connection
56
VXO OUT
O
VXO output
57
VXO IN
I
VXO input
58
V REG
O
Constant voltage capacitor connection
59
C IN
I
Chroma signal input
60
TEST3
I
Test (Connect to GND.)
61
Y IN
I
Y signal input
62
PIC
I
Y signal frequency response adjustment
63
F0 ADJ
O
Internal filter adjusting resistor connection
64
PWRST
—
System reset
Analog (12V) GND for PSIG
O
PSIG output
Analog 12V power supply for PSIG
Analog (12V) GND
(H: Pull up)
–4–
CXA2543R
Analog Block Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
70µA
1k
1
TRAP
—
300
1
130µA
GND1
2
GND1
External trap connection.
Connect the trap between this
pin and GND to remove the
chroma component.
Leave this pin open when
using Y/C and Y/color
difference input.
Analog (4.5V) GND.
0V
VDD1
1k
2.1V
1k
3
SYNC IN
1.5V
3
30µA
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
GND1
VDD1
20k
4
H.FIL OUT
0.8V
Outputs the video signal for
input to the sync separation
circuit.
4
20k
GND1
VDD1
17k
5
S.SEP IN
2.1V
Sync separation circuit input.
Input the H.FIL OUT (4pin)
signal.
5
10µA
GND1
–5–
1.8V 2.8V
CXA2543R
Pin
No.
6
Symbol
Pin voltage
EXT-R
Equivalent circuit
VCC1
30µA
6
7
EXT-G
—
300
7
8
50k 2.7V
8
EXT-B
37
FB PSIG
GND1
Description
External digital signal inputs.
There are two threshold
values: Vth1 (= 1.0V) and
Vth2 (= 2.0V). When one of
the RGB signals exceeds
Vth1, all of the RGB outputs
go to black level; when an
input exceeds Vth2, only the
corresponding output goes to
white level.
VCC1
42
FB B
37
2.0V
45
1k
42
45
FB G
47
Smoothing capacitor
connection for the feedback
circuit of R, G, B and PSIG
output DC level control.
Use a low-leakage capacitor
because of high impedance.
GND2
47
FB GR
38
GND3
Analog (12V) GND for the PSIG circuit.
0V
VCC3
39
PSIG
VCC2
2
39
PSIG signal outputs.
10
GND3
40
VCC3
41
B OUT
44
G OUT
12V power supply for the PSIG
circuit.
12V
VCC2
VCC2
2
41
20
RGB signal outputs.
44
46
20
40µA
46
R OUT
43
GND2
GND2
Analog (12V) GND.
0V
–6–
CXA2543R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
48
VCC2
12V
12V power supply.
49
VCC1
4.5V
4.5V power supply.
VCC2
RGB output DC voltage
control.
When used with a VCC2 and
VCC3 of 12V or more, apply
6V from an external source.
150k
50
SIG.
CENTER
6.0V
300
50
150k
GND2
VCC1
51
B-Y IN
51
—
500
500
52
10k
52
R-Y IN
30µA
50µA
GND1
VCC1
53
C OUT
1.6V
53
350µA
GND1
Color difference demodulation
circuit inputs.
Color difference signal is input
when using Y/color difference
input. At this time, the
standard signal input level is
0.3Vp-p and the clamp level is
approximately 2.8V. Pin 53
signal is input in other modes
(except D-PAL∗). At this time,
the DC level is approximately
1.6V.
Color adjusted chroma signal
output.
The burst level is 180mVp-p
(typ.).
(540mVp-p during D-PAL.)
Leave this pin open when
using Y/color difference input.
VCC1
50k
54
BLK LIM
—
54
50k
Sets the RGB output
amplitude (black-black) clip
level and the blanking black
level for during wide display.
GND1
∗ D-PAL is a demodulation method that uses an external delay line during demodulation;
S-PAL is a demodulation method that internally processes chroma demodulation.
–7–
CXA2543R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
55
APC
2.7V
APC detective filter
connection.
Leave this pin open when
using Y/color difference input.
1k
55
GND1
VCC1
56
VXO OUT
2.9V
VXO output.
Leave this pin open when
using Y/color difference input.
56
400µA
GND1
VCC1
VXO input.
Leave this pin open when
using Y/color difference input.
500
57
VXO IN
3.2V
57
2.4k
3.2V
GND1
VCC1
58
V REG
3.6V
Smoothing capacitor
connection for the internally
generated constant voltage
source circuit.
Connect a capacitor of 1µF or
more.
60k
58
30k
GND1
VCC1
500 15p
59
C IN
—
59
20k
30µA
GND1
–8–
Video signal input when using
composite input.
Chroma signal input when
using Y/C signal input.
Leave this pin open when
using Y/color difference input.
CXA2543R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
Y signal input.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
Input at low impedance (75Ω
or less).
1k
61
Y IN
3.1V
61
70µA
GND1
VCC1
20k
30k
62
PIC
—
62
10k
BIAS
50µA
Adjusts frequency response of
luminance signal.
Increasing the voltage
emphasizes contours.
50µA
GND1
VCC1
1k
63
F0 ADJ
3.0V
63
15µA
GND1
Connect resistance of 15kΩ
between this pin and GND1 to
adjust the internal filters using
the outflow current value.
Connect to +4.5V power
supply when using Y/C or
Y/color difference input.
VDD1
2µA
64
64
PWRST
—
1k
GND1
–9–
TG block system reset pin.
The system is reset when this
pin is connected to GND.
Connect a capacitor between
this pin and GND.
CXA2543R
Setting Conditions for Measuring Electrical Characteristics
Use the electrical characteristics measurement circuit on page 30 when measuring electrical characteristics.
Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below.
Setting 1. System reset
After turning on the power, set SW64 to ON and start up V64 from GND in order to activate the TG block
system reset. (See Fig. 1-1.)
The serial bus will be set to default values.
Setting 2. Horizontal AFC adjustment
Input SIG5 (VL = 0mV) to (A) and adjust V14 so that WL and WH of the TP12 output waveform are the
same. (See Fig. 1-2.)
Note) When measuring a band of 2MHz or more for Y signal frequency response or sharpness response
among the items being measured, the measurement must be made with sample-and-hold timing (serial
bus) set to through (sample-and- hold not performed).
VDD
SIG5
WS
V64 (PWRST)
TR
TP12
TR > 10µs
WL
Fig. 1-1. System reset
WH
WL = WH
Fig. 1-2. Horizontal AFC adjustment
– 10 –
CXA2543R
Electrical Characteristics — DC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C
SW54, SW62, SW64 = ON
SW6, SW7, SW8, SW59 = A
SW51, SW52 = B
V54 = 0V, V62 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified the serial bus registers
should be set to default settings.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
ICC11
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC1 current value.
COMP input mode
23
30
37
mA
ICC12
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC1 current value.
Y/C input mode
21
28
35
mA
ICC13
Input SIG4 to (A), (D) and (E).
Measure the ICC1 current value.
SW51, SW52 = A, SW59 = B
Y/color difference input mode
17
23
29
mA
ICC2A
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC2 current value.
PSIG load capacity CLP = 0pF
6
8
10
mA
ICC2B
Input SIG4 to (A) and SIG2 (0dB) to (B).
Adjust PSIG-BRT of the serial bus and measure the
ICC2 current value when TP39 output is set to 5Vp-p.
PSIG load capacity CLP = 10000pF
6
8.3
10.5
mA
IDD1
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the IDD current value.
DCX501 and LCX018 (4:3) mode
6
8
10
mA
IDD2
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the IDD current value.
LCX018 (16:9) mode
7.5
10
12.5
mA
Power supply characteristics
Current
consumption
VCC1
Current
consumption
VCC2, 3
Current
consumption VDD
– 11 –
CXA2543R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
0.3VDD
V
Digital block I/O characteristics
Low level input voltage
VIL
Digital block input pin∗1
High level input voltage
VIH
Digital block input pin∗1
Input current
II1
Input pin with pull-up resistor∗2
VIN = VSS2
–145
CKI pin low input current
II2
VIN = VSS
–10
CKI pin high input current
II3
VIN = VDD1
High level output voltage
Output pins except
CKO and RPD
VOH1
IOH = –1mA∗3
Low level output voltage
Output pins except
CKO and RPD
VOL1
IOL = 1mA∗3
High level output voltage
CKO pin
VOH2
IOH = –3mA
Low level output voltage
CKO pin
VOL2
IOL = 3mA
High level output voltage
RPD pin
VOH3
IOH = –0.5mA
Low level output voltage
RPD pin
VOL3
IOL = 0.7mA
Output off leak current
RPD pin
IOFF
High impedance status
VOUT = VSS or VOUT = VDD1
V
0.7VDD
–60
–24
µA
10
µA
V
2.8
0.3
V
V
0.5VDD
0.5VDD
V
V
VDD – 1.2
–40
µA
1.0
V
40
µA
∗1 Digital block input pins: SCLK, DATA, LOAD, VDIN, RGT, FLDIN, CKI
∗2 Input pins with pull-up resistors: SCLK, DATA, LOAD, VDIN, RGT, FLDIN
∗3 Output pins except CKO and RPD: XHST, HST, HCK1, HCK2, XPCG, PCG, HD, XVST, VST, VCK1, VCK2,
XEN, EN, VD
– 12 –
CXA2543R
Electrical Characteristics — AC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C
SW54, SW62, SW64 = ON
SW6, SW7, SW8 = A
SW51, SW52, SW59 = B
V54 = 0V, V62 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Values". Unspecified serial bus registers should
be set to default settings.
Unless otherwise specified, measure the non-inverted outputs for TP41, TP44 and TP46.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Y signal block
Video maximum
gain
GV
Input SIG4 to (A) and measure the ratio between the output
amplitude (white-black) and input amplitude at TP44.
19
22
25
dB
Contrast
characteristics TYP
GCNTTP
Input SIG4 to (A) and measure the ratio between the output
amplitude (white-black) and input amplitude at TP44.
13
17
21
dB
Contrast
characteristics MIN
GCNTMN
Input SIG4 to (A) and measure the ratio between the output
amplitude (white-black) and input amplitude at TP44.
–9
–5
–1
dB
FCYYC
Y signal frequency
response 1
FCYCMN
FCYCMP
Y signal frequency
response 2
Picture quality
adjustment
variable amount 1
(Y/C input)
Picture quality
adjustment
variable amount 2
(composite input)
Carrier leak
(residual carrier)
FCL
GSHP1X
GSHP1N
GSHP2X
GSHP2N
CRLEKY
TDYYC
Y signal I/O delay
time
TDYCMN
TDYCMP
Assume the output amplitude at
TP44 when SIG7 (0dB, no burst,
100kHz) is input to (A) as 0dB.
Vary the frequency of the input
signal to obtain the frequency with
an output amplitude of –3dB.
V62 = 1.5V
Y/C input
5.0
MHz
Composite input
(NTSC)
2.5
MHz
Composite input
(PAL)
3.0
MHz
5.0
MHz
Assume the output amplitude at TP44 when SIG7
(0dB, no burst, 100kHz) is input to (A) as 0dB.
Vary the frequency of the input signal to obtain the
frequency with an output amplitude of –3dB.
V62 = 1.5V, Load 500pF
Assume the output amplitude at TP44 when SIG7
(100kHz) is input to (A) as 0dB. Set SIG7 to 2.5MHz
and measure GSHP1X and GSHP1N as the
amounts by which the output amplitude at TP44
changes when V62 = 4V and 0V, respectively.
Assume the output amplitude at TP44 when SIG7
(100kHz) is input to (A) as 0dB. Set SIG7 to 2.0MHz
and measure GSHP2X and GSHP2N as the
amounts by which the output amplitude at TP44
changes when V62 = 4V and 0V, respectively.
10
14
–2
6
– 13 –
0
–4
dB
dB
9
Input SIG2 (0dB) to (A). Using a spectrum
analyzer, measure the input and the 3.58MHz or
4.43MHz component of TP44, and obtain
CRLEKY = 150mV × 10 ∆CLK/20 using their
difference ∆CLK.
Input SIG9 (VL = 150mV) to
(A). Measure the delay time
from the 2T pulse peak of
the input signal to the peak
of the non-inverted output at
TP44.
dB
–2
dB
30
mV
Y/C input
250
350
450
ns
Composite input
(NTSC)
570
670
770
ns
Composite input
(PAL)
570
670
770
ns
CXA2543R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
NTSC
–3
0
3
dB
PAL
–3
0
3
dB
NTSC
–4
–1
2
dB
PAL
–4
–1
2
dB
Chroma signal block
ACC amplitude
characteristics 1
ACC amplitude
characteristics 2
ACC1
ACC2
FAPCN
APC pull-in range
FAPCP
Color adjustment
characteristics
MAX
GCOLMX
Color adjustment
characteristics
MIN
GCOLMN
HUE adjustment
range
MAX
HUEMX
HUE adjustment
range
MIN
HUEMN
ACKN
Killer operation
input level
ACKP
Input SIG5 (VL = 150mV) to (A) and
SIG2 (0dB/+6dB/–20dB, 3.58MHz
burst/chroma phase = 180°, or 4.43MHz
burst/chroma phase = ±135°) to (B).
Measure the output amplitude at TP53,
assuming the output corresponding to
0dB, +6dB and –20dB as V0, V1 and V2,
respectively.
ACC1 = 20 log (V1/V0)
ACC2 = 20 log (V2/V0)
SW59 = A
Input SIG5 (VL = 150mV) to (A) and
SIG2 (0dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Changing the
SIG2 burst frequency, measure the
frequency f1 at which the TP44 output
appears (the killer mode is canceled).
NTSC: FAPCN = f1 – 3579545Hz
PAL: FAPCP = f1 – 4433619Hz
SW59 = A
NTSC
±500
Hz
PAL
±500
Hz
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz burst/chroma phase = 180°) to (B).
Assume the chroma output amplitude when serial
bus register COLOR = 80H, 0FFH and 0H as V0,
V1 and V2, respectively.
GCOLMX = 20 log (V1/V0)
GCOLMN = 20 log (V2/V0)
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
burst/chroma phase variable) to (B). Assume the
phase at which the output amplitude at TP44
reaches a minimum when serial bus register HUE
= 80H, 0FFH and 0H as θ0, θ1 and θ2,
respectively.
HUEMX = θ1 – θ0
HUEMN = θ2 – θ0
SW59 = A
Input SIG5 (VL = 150mV) to (A) and
SIG2 (level variable, 3.58MHz
burst/chroma phase = 180°, or 4.43MHz
burst/chroma phase = ±135°) to (B), and
measure the output amplitude at TP44.
Gradually reduce the SIG3 amplitude
level and measure the level at which the
killer operation is activated.
SW59 = A
– 14 –
4
6
–25
dB
–15
dB
–30
–40
deg
30
60
deg
NTSC
–37
–31
dB
PAL
–34
–28
dB
CXA2543R
Item
Demodulation
output amplitude
ratio (NTSC)
Symbol
VRBN
VGBN
θRBN
Demodulation
output phase
difference (NTSC)
Demodulation
output amplitude
ratio (PAL)
θGBN
VRBP
VGBP
θRBP
Demodulation
output phase
difference (PAL)
θGBP
Color difference
input color
adjustment
characteristics
MAX
GEXCMX
Color difference
input color
adjustment
characteristics
MIN
GEXCMN
Color difference
balance
Color difference
input balance
adjustment R
Color difference
input balance
adjustment B
VEXCBL
GEXRMX
GEXRMN
GEXBMX
GEXBMN
Conditions
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and change the chroma phase.
Assume the maximum amplitude at TP41 as VB,
the maximum amplitude at TP44 as VG, and the
maximum amplitude at TP46 as VR.
VRBN = VR/VB, VGBN = VG/VB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and change the chroma phase.
Assume the phase at which the amplitude at
TP41, TP44 and TP46 reaches a maximum as
θB, θG and θR, respectively.
θRBN = θR – θB, θGBN = θG – θB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and change the chroma phase.
Assume the maximum amplitude at TP41 as VB,
the maximum amplitude at TP44 as VG, and the
maximum amplitude at TP46 as VR.
VRBP = VR/VB, VGBP = VG/VB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and change the chroma phase.
Assume the phase at which the amplitude at
TP41, TP44 and TP46 reaches a maximum as
θB, θG and θR, respectively.
θRBP = θR – θB, θGBP = θG – θB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) when serial bus
register COLOR = 80H as VC0, when COLOR =
0H as VC2, and when SIG1 is set to -10dB and
COLOR = 0FFH as VC1.
GEXCMX = 20 log (VC1/VC0) + 10
GEXCMN = 20 log (VC2/VC0)
SW51, SW52 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D) and (E). Assume the
output amplitude at TP41 (100kHz) as VB and
the output amplitude at TP46 (100kHz) as VR.
VEXCBL = VR/VB
SW51, SW52 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB,
100kHz, no burst) to (D) and (E). Assume the
output amplitude at TP46 (100kHz) and TP41
(100kHz) when serial bus register HUE = 80H as
VR0 and VB0, respectively, when HUE = 0FFH
as VR1 and VB1, respectively, and when HUE =
0H as VR2 and VB2, respectively.
GEXRMX = 20 log (VR1/VR0)
GEXRMN = 20 log (VR2/VR0)
GEXBMX = 20 log (VB1/VB0)
GEXBMN = 20 log (VB2/VB0)
SW51, SW52 = A
– 15 –
Min.
Typ.
Max.
0.53
0.63
0.73
0.25
0.32
0.39
99
109
119
deg
230
242
254
deg
0.65
0.75
0.85
0.33
0.40
0.47
80
90
100
deg
232
244
256
deg
4
6
dB
–20
–15
0.8
1.0
1.2
2
3
2
Unit
dB
dB
–3
–2
dB
–3
–2
dB
3
dB
CXA2543R
Item
Symbol
Conditions
Min.
Typ.
Max.
VEXGBN
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) as VEXB and the
output amplitude at TP44 (100kHz) as VEXBG.
VEXGBN = VEXBG/VEXB
SW51, SW52 = A
0.22
0.25
0.28
VEXGRN
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP46 (100kHz) as VEXR and the
output amplitude at TP44 (100kHz) as VEXRG.
VEXGRN = VEXRG/VEXR
SW51, SW52 = A
0.47
0.53
0.58
VEXGBP
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) as VEXB and the
output amplitude at TP44 (100kHz) as VEXBG.
VEXGBP = VEXBG/VEXB
SW51, SW52 = A
0.16
0.19
0.22
VEXGRP
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP46 (100kHz) as VEXR and the
output amplitude at TP44 (100kHz) as VEXRG.
VEXGRP = VEXRG/VEXR
SW51, SW52 = A
0.48
0.53
0.58
VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus
register BRIGHT so that the output (black-black)
at TP44 is 9Vp-p and measure the DC voltage at
TP39, TP41, TP44 and TP46.
5.85
6.00
6.15
V
∆VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus
register BRIGHT so that the output (black-black) at
TP44 is 9Vp-p, measure the DC voltage at TP39,
TP41, TP44 and TP46, and obtain the maximum
difference between each of these values.
0
100
mV
G-Y matrix
characteristics
(NTSC)
G-Y matrix
characteristics
(PAL)
Unit
RGB signal output block
RGB signal and
PSIG output DC
voltage
RGB signal and
PSIG output DC
voltage difference
RGB and PSIG
output limiter
operation voltage
VLIMMX
VLIMMN
Input SIG3 to (A). Vary V54 and measure the maximum
value VLIMMX and minimum value VLIMMN of the
voltage range (black-black) over which the black limiter
operates for the TP39, TP41, TP44 and TP46 outputs.
Assume the value whenV54 = 0V as VLIMMX, and
when V54 = 4.5V as VLIMMN.
BRTMX
Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP41, TP44 and TP46
when serial bus register BRIGHT = 0H.
BRTMN
Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP41, TP44 and TP46
when serial bus register BRIGHT = 0FFH.
Amount of change
in brightness
– 16 –
9.0
Vp-p
5.2
9.0
Vp-p
Vp-p
4.0
Vp-p
CXA2543R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
1.5
Vp-p
PSIGMX
Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP39 when serial bus
register PSIG-BRT = 0H.
PSIGMN
Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP39 when serial bus
register PSIG-BRT = 0FFH.
9.0
Amount of change
in sub-brightness
SBBRT
Input SIG5 (VL = 0mV) to (A) and measure the difference
between the outputs (black-black) at TP41 and TP46 and
the output (black-black) at TP44 when serial bus registers
R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH.
±1.5
±2.0
Difference in gain
between RGB
output signals
∆GRGB
Input SIG4 to (A) and obtain the level difference between
the maximum and minimum non-inverted output
amplitudes (white-black) at TP41, TP44 and TP46.
–0.5
0
0.5
dB
Difference in RGB
output inverted/non- ∆GINV
inverted gain
Input SIG4 to (A) and obtain the level difference between
the non-inverted output amplitudes (white-black) and the
inverted output amplitudes at TP41, TP44 and TP46.
–0.5
0
0.5
dB
Difference in black
level potential between ∆VBL
RGB output signals
Input SIG4 to (A) and obtain the level difference between
the maximum and minimum black levels of both the inverted
and non-inverted outputs at TP41, TP44 and TP46.
300
mV
Amount of change
in PSIG
Gγ1
γ gain
Gγ2
Gγ3
V γ 1MN
γ 1 adjustment
variable range
V γ 1MX
V γ 2MN
γ 2 adjustment
variable range
V γ 2MX
tPSIGH
PSIG transition
time
RGB output white
limiter operation
voltage
Black limiter DC
voltage difference
tPSIGL
Input SIG8 to (A). Adjust the non-inverted output
black level at TP44 to 6.0 - 4.5V with serial bus
register BRIGHT and the non-inverted output
amplitude (white-black) at TP44 to 3.5V with
serial bus register CONTRAST. Measure VG1,
VG2 and VG3.
G γ 1 = 20 log (VG1/0.0357)
G γ 2 = 20 log (VG2/0.0357)
G γ 3 = 20 log (VG3/0.0357)
(See Fig. 5 for definitions of VG1, VG2 and VG3.)
Input SIG8 to (A) and adjust serial bus register
BRIGHT so that the output at TP44 is 9Vp-p
(black-black). Read the point where the gain of
the non-inverted output at TP44 changes when
serial bus register γ 1 = 0H and 0FFH from the
input signal IRE level.
V γ 1MN when γ 1 = 0H, and V γ 1MX when γ 1 =
0FFH.
Input SIG8 to (A) and adjust serial bus register
BRIGHT so that the output at TP44 is 9Vp-p
(black-black). Read the point where the gain of
the non-inverted output at TP44 changes when
serial bus register γ 2 = 0H and 0FFH from the
input signal IRE level.
V γ 2MN when γ 2 = 0H, and V γ 2MX when γ 2 =
0FFH.
Input SIG5 (VL = 350mV) to (A) and measure the voltage (whitewhite) at which the white limiter activates for inverted output and
non-inverted output at TP41, TP44 and TP46, respectively.
∆VBLIM
Input SIG5 (VL = 0mV) to (A) and adjust V54 so that
the output at TP44 is 9Vp-p (black-black). Measure the
DC voltage at TP41, TP44 and TP46 and obtain the
difference versus the RGB output voltage VOUT.
– 17 –
V
23.0
26.0
29.0
dB
12.0
15.0
18.0
dB
18.0
21.0
25.0
dB
0
IRE
100
IRE
100
IRE
Input SIG4 to (A) and adjust serial bus register
PSIG-BRT so that the output at TP39 is 9Vp-p
(black-black). Measure the time it takes to change
to an amplitude of 9Vp-p.
tPSIGH: rising edge, tPSIGL: falling edge
VWLIM
Vp-p
1.3
0
IRE
1.5
3.0
µs
1.5
3.0
µs
1.5
1.7
V
0
100
mV
CXA2543R
Item
White limiter DC
voltage difference
RGB output range
when FRP polarity
reverse is stopped
Symbol
Conditions
Min.
∆VWLIM
Input SIG5 (VL = 350mV) to (A). Measure the DC
voltage at TP41, TP44 and TP46 and obtain the
difference versus the RGB output voltage VOUT.
VDROFF
Input SIG8 to (A). Assume the black limiter level of
the output at TP41, TP44 and TP46 when serial bus
register BRIGHT = 0H as VDRB and the white
limiter level when BRIGHT = OFFH as VDRW.
VDROFF = VDRW – VDRB
Typ.
Max.
Unit
0
100
mV
3.0
V
Filter characteristics
Amount of BPF
attenuation
ATBPF
ATRAPN
Amount of TRAP
attenuation
ATRAPP
R-Y, B-Y and LPF
characteristics
Assume the chroma amplitude at TP53
when SIG5 (VL = 0mV) is input to (A)
and SIG1 (0dB at input center frequency
(3.58Hz or 4.43Hz)) is input to (B) as
0dB. Obtain the amount by which the
output at TP53 is attenuated when the
frequencies noted on the right are input.
SW59 = A
NTSC 1.5MHz
–16
–10
dB
PAL
2.0MHz
–16
–10
dB
NTSC 5.5MHz
–7
–2
dB
PAL
–8
–3
dB
–40
–30
dB
–40
–30
dB
1.0
1.3
MHz
6.8MHz
Input SIG2 (0dB, 3.58Hz and 4.43Hz) to (A)
NTSC
and measure the output at TP44. Assume
the amplitude at TP44 during Y/C input
mode as 0dB, and obtain the amount of
PAL
attenuation during COMP input mode.
Assume the amplitude of the 100kHz component of the output at
TP44 when SIG5 (VL = 150mV) is input to (A) and SIG1 (0dB,
3.58Hz + 100kHz) is input to (B) as 0dB. Obtain the frequency
which attenuates the beat component of the output by 3dB when
the SIG1 frequency is increased with respect to 3.58MHz.
SW59 = A
0.8
WSSEP
Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and
confirm that it is synchronized with the HD output at TP23.
Gradually narrow the WS of SIG5 from 4.7µs and obtain the WS
at which synchronization with the HD output at TP23 is lost.
2.0
VSSEP
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = variable) to (A) and
confirm that it is synchronized with the HD output at TP23.
Gradually reduce the VS of SIG5 from 143mV and obtain the VS
at which synchronization with the HD output at TP23 is lost.
DEMLPF
Sync separation, TG block
Input sync signal
width sensitivity
Sync separation
input sensitivity
TDSYL
Sync separation
output delay time
TDSYH
HPLLN
Horizontal pull-in
range
HPLLP
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and
measure the delay time with the RPD output at TP12. TDSYL is
from the falling edge of the input HSYNC to the falling edge of the
RPD output at TP12, and TDSYH is from the falling edge of the
input HSYNC to the rising edge of the RPD output at TP12.
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV,
horizontal frequency variable) to (A) and confirm that it NTSC
is synchronized with the HD output at TP23. Obtain the
frequency fH at which the input and output are
synchronized by changing the horizontal frequency of
SIG5 from the non-synchronized condition.
PAL
HPLLN = fH – 15734
HPLLP = fH – 15625
– 18 –
µs
40
60
mV
430
630
830
ns
4.7
5.0
5.3
µs
±500
Hz
±500
Hz
CXA2543R
Item
Output transition
time (P12∗3 pin)
Symbol
tTLH
tTHL
Conditions
Min.
Typ.
Input SIG5 (VL = 0mV) to (A).
Measure the transition time for each output.
Load = 30pF
(See Fig. 3.)
Cross-point time
difference
∆T
Input SIG5 (VL = 0mV) to (A).
Measure HCK1/HCK2.
Load = 30pF
(See Fig. 4.)
HCK duty
DTYHC
Input SIG5 (VL = 0mV) to (A).
Measure the HCK1/HCK2 duty.
Load = 30pF
Max.
Unit
30
ns
30
ns
10
ns
47
50
53
%
0.8
1.0
1.2
V
1.8
2.0
2.2
V
50
100
150
ns
50
100
150
ns
0
V
External I/O characteristics
VTEXTB
External RGB input
threshold voltage
VTEXTW
Propagation delay
time between
external RGB input
and output
Output blanking
level during
external RGB input
Output white level
during external
RGB input
Minimum pulse
width during
external RGB input
TDEXTH
TDEXTL
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C).
Raise the SIG6 amplitude (VL) from 0V and assume the voltage
where the outputs at TP41, TP44 and TP46 go to black level as
VTEXTB. Then raise the amplitude further and assume the
voltage where these outputs go to white level as VTEXTW.
SW6, SW7, SW8 = B
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V)
to (C). Measure the rise delay time TD1EXT and
the fall delay time TD2EXT of the outputs at
TP41, TP44 and TP46.
(See Fig. 2.)
SW6, SW7, SW8 = B
EXTBK
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V)
to (C). Measure the difference from the black level
of the outputs at TP41, TP44 and TP46.
SW6, SW7, SW8 = B
EXTWT
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V)
to (C). Measure the difference from the black level
of the outputs at TP41, TP44 and TP46.
SW6, SW7, SW8 = B
TEXTMIN
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C).
Measure the minimum pulse width at which each of the
outputs at TP41, TP44 and TP46 reach the white limiter.
SW6, SW7, SW8 = B
3.5
V
180
ns
Serial transfer block
ts0
LOAD setup time, activated by the rising edge of
SCLK.
(See Fig. 6.)
150
ns
ts1
DATA setup time, activated by the rising edge of
SCLK.
(See Fig. 6.)
150
ns
th0
LOAD hold time, activated by the rising edge of
SCLK.
(See Fig. 6.)
150
ns
th1
DATA hold time, activated by the rising edge of
SCLK.
(See Fig. 6.)
150
ns
tw1L
SCLK pulse width.
(See Fig. 6.)
160
ns
tw1H
SCLK pulse width.
(See Fig. 6.)
160
ns
tw2
LOAD pulse width.
(See Fig. 6.)
Data setup time
Data hold time
Minimum pulse
width
– 19 –
1
µs
– 20 –
Digital block I/O characteristics
Power supply characteristics Setting 2
COMP
COMP
COMP
COMP
COMP
COMP
IDD2
VIL
VIH
II1
II2
Low level input voltage
High level input voltage
Input current
CKI pin low input current
CKI pin high input current II3
COMP
COMP
COMP
COMP
COMP
COMP
COMP
Low level output voltage VOL1
VOH2
Low level output voltage VOL2
VOH3
Low level output voltage VOL3
IOFF
Output off leak current
High level output voltage
High level output voltage
High level output voltage
VOH1
Current
consumption VDD
COMP
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
—
NTSC
COMP
IDD1
—
NTSC
COMP
ICC2A
Current
consumption VCC2,3 ICC2B
—
—
—
—
—
—
—
—
—
—
—
—
LCX018
—
—
NTSC
Y/color
difference
—
—
ICC13
NTSC
COMP
—
Panel
NTSC
NTSC
System
COMP
Input
—
—
—
—
—
—
—
—
—
—
—
—
16:9
4:3
—
—
—
—
—
—
Aspect
Mode settings
Y/C
ICC11
Symbol
ICC12
Current
consumption VCC1
Horizontal AFC
adjustment
Item
Description of Electrical Characteristics Measurement Methods
Serial Bus Register Initial Values
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
S/H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
78H
80H
80H
80H
80H
80H
PSIG-BRT
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
DAC settings
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
Y signal block
NTSC
– 21 –
COMP
COMP
TDYCMN
TDYCMP
PAL
NTSC
—
TDYYC
Y/C
—
CRLEKY COMP
Carrier leak
Y signal I/O delay
time
NTSC
GSHP2N COMP
NTSC
NTSC
NTSC
NTSC
Y/C
Y/C
Y/C
PAL
COMP
GSHP2X
GSHP1N
GSHP1X
FCL
COMP
FCYCMP
NTSC
Picture quality
adjustment variable
amount 2
Picture quality
adjustment variable
amount 1
Y signal frequency
response 2
COMP
FCYCMN
Y/C
FCYYC
Y signal frequency
response 1
NTSC
GCNTMN COMP
Contrast
characteristics MIN
NTSC
COMP
GCNTTP
NTSC
System
Contrast
characteristics TYP
Input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Panel Aspect
Mode settings
COMP
Symbol
Video maximum gain GV
Item
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
96H
96H
96H
60H
60H
60H
60H
60H
0A0H
0A0H
0A0H
0A0H
0A0H
0A0H
0A0H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
80H
0FFH
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
PSIG-BRT
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
DAC settings
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
Chroma signal block
COMP
COMP
COMP
ACC2
ACC2
FAPCN
GCOLMN COMP
Color adjustment
characteristics MIN
—
—
—
—
PAL
NTSC
PAL
NTSC
– 22 –
—
—
NTSC
NTSC
COMP
COMP
COMP
COMP
COMP
COMP
COMP
COMP
Demodulation output VRBN
amplitude ratio NTSC VGBN
θRBN
θGBN
VRBP
VGBP
θRBP
θGBP
Demodulation output
phase difference PAL
Demodulation output
amplitude ratio PAL
Demodulation output
phase difference NTSC
—
PAL
PAL
—
—
—
PAL
PAL
—
NTSC
—
—
PAL
COMP
ACKP
NTSC
—
NTSC
COMP
ACKN
Killer operation
input level
—
NTSC
HUEMN COMP
HUE adjustment
range MIN
—
—
—
HUEMX
NTSC
NTSC
NTSC
—
—
NTSC
PAL
Panel
System
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Aspect
Mode settings
HUE adjustment
range MAX
COMP
GCOLMX COMP
COMP
COMP
ACC1
FAPCP
COMP
Input
ACC1
Symbol
Color adjustment
characteristics MAX
APC pull-in range
ACC amplitude
characteristics 2
ACC amplitude
characteristics 1
Item
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0FFH
80H
80H
80H
80H
80H
80H
80H
80H
HUE
96H
96H
96H
80H
80H
80H
60H
60H
60H
80H
80H
80H
60H
80H
80H
60H
60H
60H
80H
80H
60H
80H
60H
60H
80H
80H
96H
96H
96H
96H
80H
80H
0H
0FFH
96H
96H
80H
80H
96H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0H
0H
80H
80H
80H
0H
0H
0H
80H
80H
80H
0H
80H
80H
0H
0H
0H
80H
80H
0H
80H
0H
0H
80H
80H
0H
0H
0H
0H
80H
80H
80H
80H
0H
0H
80H
80H
0H
80H
80H
80H
80H
80H
0H
0H
0H
0H
80H
80H
80H
0H
0H
0H
80H
0H
0H
80H
80H
80H
0H
0H
80H
0H
80H
80H
0H
0H
80H
80H
80H
80H
0H
0H
0H
0H
80H
80H
0H
0H
PSIG-BRT
γ2
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
γ1
B-BRT
DAC settings
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
Chroma signal block
RGB signal output block
– 23 –
Amount of change in PSIGMX
PSIG
PSIGMN
Amount of change in BRTMX
brightness
BRTMN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PAL
PAL
NTSC
NTSC
—
—
—
—
—
—
—
—
RGB signal and PSIG output
∆VOUT
DC voltage difference
RGB and PSIG output VLIMMX
limiter operation voltage VLIMMN
—
VEXGRP
VEXGBP
VEXGRN
VEXGBN
GEXBMN
GEXBMX
RGB signal and PSIG
VOUT
output DC voltage
G-Y matrix
characteristics PAL
G-Y matrix
characteristics NTSC
Color difference input
balance adjustment B
GEXRMN
—
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
GEXRMX Y/color
difference
Color difference input
balance adjustment R
—
Color difference balance VEXCBL Y/color
difference
—
—
Panel
Through
—
Through
Through
—
Through
—
—
Through
Through
—
—
Through
Through
—
—
Through
Through
—
—
Through
—
Through
—
Through
Through
—
—
Through
Through
Through
Through
Through
S/H
—
—
—
—
—
Aspect
Mode settings
System
Color difference input
Y/color
color adjustment
GEXCMN
difference
characteristics MIN
Input
—
Symbol
Color difference input
Y/color
color adjustment
GEXCMX
difference
characteristics MAX
Item
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0FFH
0H
0FFH
80H
80H
80H
HUE
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0FFH
80H
80H
0FFH
0H
0H
0H
ADJ
ADJ
96H
96H
96H
96H
96H
96H
96H
96H
96H
96H
96H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
0H
0FFH
0FFH
0FFH
0FFH
0FFH
64H
64H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
PSIG-BRT
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
DAC settings
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
RGB signal output block
—
Difference in RGB output
inverted/non-inverted gain
– 24 –
∆VWLIM
VDROFF
White limiter DC
voltage difference
RGB output range
when FRP polarity
reverse is stopped
—
—
—
∆VBLIM
—
tPSIGH
Black limiter DC
voltage difference
—
V γ 2MX
—
—
V γ 2MN
RGB output white limiter
VWLIM
operation voltage
—
V γ 1MX
—
—
V γ 1MN
tPSIGL
PSIG transition time
γ 2 adjustment
variable range
γ 1 adjustment
variable range
—
—
Gγ3
Gγ2
—
Gγ1
γ gain
—
Difference in black
level potential between ∆VBL
RGB output signals
∆GINV
—
Difference in gain between
∆GRGB
RGB output signals
Input
—
Symbol
Amount of change in
SBBRT
sub-brightness
Item
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
System
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Panel
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Aspect
Mode settings
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
SET
0B4H
0H
0B4H
60H
60H
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
80H
80H
80H
0B4H
80H
0FFH
80H
0FFH
80H
80H
46H
46H
46H
46H
ADJ
ADJ
ADJ
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
SET
0H
0H
0H
0H
0H
0H
0H
0H
0FFH
0H
78H
78H
78H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0FFH
0H
0H
0H
0D7H
0D7H
0D7H
0H
0H
0H
0H
γ2
80H
80H
80H
80H
0FFH
0FFH
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
PSIG-BRT
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
SET
B-BRT
DAC settings
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
– 25 –
Filter characteristics
Sync separation, TG block
External I/O characteristics
SET
ATRAPN
COMP
HPLLN
EXTWT
TEXTMIN
Minimum pulse width during
external RGB input
—
—
—
—
Output white level during
external RGB input
—
—
—
—
Propagation delay time between TDEXTH
external RGB input and output
TDEXTL
—
—
—
—
—
—
—
VTEXTW
EXTBK
—
—
—
—
VTEXTB
External RGB input
threshold voltage
Output blanking level during
external RGB input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DTYHC
—
HCK duty
—
—
—
—
—
—
—
—
—
∆T
—
—
—
—
—
—
Cross-point time difference
—
PAL
NTSC
—
—
—
—
—
—
—
—
—
tTLH
COMP
COMP
TDSYH
HPLLP
COMP
TDSYL
—
—
—
—
—
—
Aspect
tTHL
Output transition time
Horizontal pull-in range
Sync separation output
delay time
—
COMP
Sync separation input sensitivity VSSEP
NTSC
—
Y/C
R-Y, B-Y and LPF characteristics DEMLPF
PAL
NTSC
—
Panel
Mode settings
System
Input sync signal width sensitivity WSSEP COMP
SET
ATRAPP
Amount of TRAP attenuation
COMP
ATBPF
Amount of BPF attenuation
Input
Symbol
Item
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
DAC settings
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
64H
80H
80H
80H
80H
80H
80H
80H
80H
80H
60H
60H
60H
60H
60H
60H
60H
60H
60H
60H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
PSIG-BRT
(–: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2543R
CXA2543R
3V
SIG6
0V
TP41, 44, 46
non-inverted output
50%
TDEXTH
TDEXTL
Fig. 2. Conditions for measuring the delay between external RGB input and output
90%
50%
10%
tTLH
∆T
tTHL
Fig. 3. Output transition time
measurement conditions
∆T
Fig. 4. Cross-point time difference
measurement conditions
White
Non-inverted output
VG3
VG2
3.5V
VG1
Black
1.5V
Input
Fig. 5. γ characteristics measurement conditions
– 26 –
CXA2543R
DATA
D15 D14 D13 D12 D11 D10 D9
ts1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
th1
SCLK
50%
tw1H
tw1L
50%
LOAD
ts0
th0
Fig. 6. Serial transfer block measurement conditions
– 27 –
tw2
CXA2543R
Input Waveforms
SG No.
Waveform
Sine wave video signal: With/without burst
Amplitude and frequency variable
SIG1
150mV
← Value noted on left: 0dB
150mV
143mV
Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz)
Chroma phase and burst frequency variable
SIG2
150mV
← Value noted on left: 0dB
143mV
Ramp waveform
357mV
SIG3
143mV
1H
5-step staircase waveform
150mV
SIG4
143mV
1H
VL amplitude variable
VS variable: 143mV unless otherwise specified
WS variable: 4.7µs unless otherwise specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL)
unless otherwise specified
VL
SIG5
VS
fH
WS
– 28 –
CXA2543R
SG No.
Waveform
30µs
5µs
VL amplitude variable
VL
SIG6
Horizontal sync signal
75mV
Frequency variable
175mV
SIG7
143mV
10-step staircase waveform
357mV
SIG8
143mV
1H
2T pulse waveform
VL amplitude variable
VS variable: 143mV unless otherwise specified
WS variable: 4.7µs unless otherwise specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL)
unless otherwise specified
VL
SIG9
VS
fH
WS
– 29 –
CXA2543R
Electrical Characteristics Measurement Circuit
+12V
TP46
ICC2
TP44
TP41
TP39
0.1µ
300p
47µ
300p
300p
10000p
TP36 TP35 TP34 TP33
+4.5V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT
LOAD
DATA
SCLK
0.47µ
R OUT
47µ
0.47µ
FB R
ICC1
0.47µ
VCC2
0.47µ
0.1µ
49 VCC1
TP32
VD 32
0.01µ
(D)
SW51
A 0.01µ
(E)
B
A 0.01µ
B
SW52
TP53
VSS2 31
50 SIG.CENTER
51 B-Y IN
EN 30
TP30
52 R-Y IN
XEN 29
TP29
53 C OUT
VCK1 28
TP28
54 BLK LIM
VCK2 27
TP27
VST 26
TP26
XVST 25
TP25
57 VXO IN
FLD IN 24
TP24
58 V REG
HD 23
TP23
PCG 22
TP22
60 TEST3
XPCG 21
TP21
61 Y IN
HCK1 20
TP20
62 PIC
HCK2 19
TP19
HST 18
TP18
XHST 17
TP17
SW54
V54
55 APC
15k
∗1
0.068µ
∗2
0.22µ
56 VXO OUT
1µ
A
(B)
SW59
59 C IN
B
TP60
1µ
SW62
15k
0.47µ
0.033µ
CKI
8
9
10
11
12
13
14
10k
∗5
(A)
3.3µ
L
VDD1
VSS1
7
CKO
RPD
6
TP12
750 SW6 SW7 SW8
B AB A B A
TP9 TP10 TP11
1k 220p
6800p
5
TEST2
4
TEST1
3
VD IN
2
EXT B
S.SEP IN
SW64
EXT G
H.FIL OUT
1
64 PWRST
V64
EXT R
SYNC IN
63 F0 ADJ
GND1
∗6
TRAP
V62
15
16
3V
ICC3
∗4
C
47µ
33k
∗3
10k
(C)
0.01µ
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
∗2 NTSC: shorted, PAL: 18pF
∗3 Variable Capcitance Diode: 1T369 (SONY)
V14
∗4 DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF
∗5 Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
∗6 Resistance value tolerance: ±2%,
temperature coefficient: ±200ppm or less
– 30 –
0.1µ
CXA2543R
Description of Operation
The CXA2543R incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using Bi-CMOS technology.
1) RGB decoder block
• Input mode switching
The input mode can be switched between composite input, Y/C input and Y/color difference input by the
serial bus settings.
During composite input:
The composite signal is input to Pins 3, 59 and 61.
During Y/C input:
The Y signal is input to Pins 3 and 61, and the C signal to Pin 59.
During Y/color difference input: The Y signal is input to Pins 3 and 61, the B-Y signal to Pin 51, and the R-Y
signal to Pin 52.
• System switching
The input system can be switched between NTSC and PAL (DPAL using external delay lines and SPAL ) by
the serial bus settings.
• Trap, BPF
The center frequency of the built-in trap and BPF can be switched to 3.58Hz during NTSC and 4.43Hz during
PAL.
During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do
not pass through the trap or BPF during Y/C input and Y/color difference input.
• ACC detection, ACC amplifier
The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is
controlled to maintain the burst signal amplitude at a constant level.
• VXO, APC detection
The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the
VXO oscillator output are compared in the APC detection block, and the detective output is used to form a
PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is
eliminated.
• External inputs
These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold
Vth1 (≈ 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 (≈ 2.0V) is exceeded, the
output for only the signal in question goes to white level, while the other outputs remain at black level.
– 31 –
CXA2543R
2) RGB driver block
• γ correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The
characteristics change as shown in Fig. 2 by adjusting the serial bus register γ 1, and as shown in Fig. 3 by
adjusting γ 2.
B'
Output
Output
Output
B'
A'
B
A
A
B
B
A
Input
Input
Fig. 1
Input
Fig. 2
Fig. 3
• Sample-and-hold circuit
As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2543R must be
sampled-and-hold in sync with the LCD panel drive pulses.
R
S/H1
G
S/H4
S/H2
HCK1
A
S/H4
B
B
S/H3
S/H4
C
SH1 SH2 SH3 SH4
DCX501
RGT = H (normal)
SH1
SH2
RGT = L (inverted)
SHS1
SHS2
SHS3
B
A
C
Through Through Through
SHS1
SHS2
SHS3
SH1
B
A
C
SH2
A
C
B
SH3
A
C
B
SH3
SH4
C
B
A
SH4
Through Through Through
B
A
SHS2
SHS3
C
SH1: R signal SH pulse
SH2: G signal SH pulse
SH3: B signal SH pulse
SH4: RGB signal SH pulse
LCX018
RGT = H (normal)
RGT = L (inverted)
SHS1
SHS2
SHS3
SH1
A
C
B
SH1
SH2
B
A
C
SH2
B
A
C
SH3
A
C
B
SH4
C
B
A
SH3
SH4
Through Through Through
C
B
A
SHS1
Through Through Through
The sample-and-hold circuit performs sample-and-hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must
be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation
timing is also generated by the TG block. The sample-and-hold timing changes according to the phase
relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual
board.
– 32 –
CXA2543R
• RGB output
RGB outputs (Pins 41, 44, and 46) are inverted each horizontal line by the FRP pulse supplied from the TG
block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output
signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 50)). In
addition, the white level output is clipped by the Vsig center ±0.7V, and the black level output is clipped by
the limiter operation point that is adjusted at the BLKLIM (Pin 54).
Video IN
FRP
Black level limiter
White level limiter
Vsig center
White level limiter
RGB OUT
Black level limiter
3) TG block
• PLL and AFC circuits
The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can
be comprised by connecting an external VCO circuit.
The PLL error detection signal is generated at the following timing. The phase comparison output of the
entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted
to DC error with the lag-lead filter, and then it changes the capacitance of variable capacitance diode to
stabilize the oscillation frequency at 1066fH in the DCX501BK and LCX018AK (4:3) mode, 1417fH in the
LCX018AK (16:9) mode. The PLL of this system is adjusted by setting the the reverse bias voltage of the
varicap diode (V14) so that the point at which RPD changes is at the center of the window depicted in the
figure below.
H SYNC
WS
RPD
WL
WH
WL = WH
• H position
The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings.
The picture center is set at the internal default value, but because there is a difference between the RGB
signal and the drive pulse delays on the actual board, the picture center may not match the design center. In
this case, adjust with the serial bus.
– 33 –
CXA2543R
• Right/left inversion
The LCD panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from
adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd
lines and even lines. HCK and S/H are also 1.5-bit offset.
When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd
lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed.
RGT = H: Right scan mode
RGT = L: Left scan mode
Left scan
(Reverse scan)
Right scan
(Normal scan)
V SCANNER
H SCANNER
Display area
LCD panel
• WIDE mode (DCX501BK mode)
Setting the WIDE mode by switching the aspect with the serial bus shifts the unit to WIDE mode. In the
DCX501BK mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE
display. During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are
performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside
the display area, black is displayed in the 28 lines, respectively at the top and bottom of this display area by
performing high-speed scanning
The method of black display is a writing method by PSIG. By setting PSIG level during high-speed scanning
to black display level and writing this black display level at the PCG timing, reliable black display is realized
within the limited V blanking period.
During this period, HST is masked and video signal input is limited.
See the attached sheets for detailed timing.
225 LINES
Vertical high-speed scanning
Display area
4:3 display
Vertical pulse eliminator scanning
DCX501BK
– 34 –
Black display area
28 LINES
Display area
169 LINES
Black display area
28 LINES
16:9 display
CXA2543R
During high-speed scanning
During normal-speed scanning
VCKn
Double-speed scanning
HST
Stop
FRP
(Internal pulse)
1H cycle
PCG
• AC driving of LCD panels during no signal
HST, XHST, HCK1, HCK2, VST, XVST, VCK1, VCK2, PCG, XPCG, EN, XEN, HD, VD, and FRP are made
to run freely so that the LCD panel is AC driven even when there is no composite sync from the SYNC IN pin.
During this time, the HSYNC separation circuit stops and the PLL counter is made to run freely. In addition,
the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse
for generating VD, VST and XVST.
The cycle of this v counter is designed to be 525/2H for NTSC and 625/2H for PAL. However, when there is
no vertical sync signal for 5 fields, the no signal state is assumed and the free running VD, VST and XVST
pulses are generated from the next field.
In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from
causing errors due to phase comparison.
– 35 –
CXA2543R
Description of Serial Control Operation
1) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This
loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15
are dummy data.)
Digital block control data is established by the vertical sync signal and the LOAD "H". If data is transferred
multiple times for the same item, the data immediately before the vertical sync signal is valid.
Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.
D15 D14 D13 D12 D11 D10 D9
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
LOAD
Serial transfer timing
2) Serial data map
The serial data map is as follows.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
∗
∗
∗
0
0
0
0
0
∗
∗
∗
0
0
0
0
1
FRP
polarity
∗
∗
∗
0
0
0
1
0
0
0
0
∗
∗
∗
0
0
0
1
1
0
0
0
H-POSITION
∗
∗
∗
0
0
1
0
0
0
0
0
HD-POSITION
∗
∗
∗
0
0
1
0
1
0
0
PCG width
0
0
PCG position
∗
∗
∗
0
0
1
1
0
0
0
EN width
0
0
EN position
∗
∗
∗
1
0
0
0
0
HUE
∗
∗
∗
1
0
0
0
1
COLOR
∗
∗
∗
1
0
0
1
0
BRIGHT
∗
∗
∗
1
0
0
1
1
CONTRAST
∗
∗
∗
1
0
1
0
0
R-BRT
∗
∗
∗
1
0
1
0
1
B-BRT
∗
∗
∗
1
0
1
1
0
γ1
∗
∗
∗
1
0
1
1
1
γ2
∗
∗
∗
1
1
0
0
0
PSIG-BRT
∗
∗
∗
1
1
1
1
1
TEST
S/H phase
D5
D4
D3
Aspect
Supported
panel
D2
D1
D0
Input
switching
System
Y/color VD
FRP256 Up/down SYNC
HD
Mode difference
inversion inversion GEN
polarity
polarity
clamp
0
PAL
External FIELD
determi
decima
V SYNC -nation
-tion
0
Note) Any data transfer performed when addresses D8, D9, D10, D11, D12 = 1, 1, 1, 1, 1 (shadowed portion)
will result in test mode regardless of other data settings.
Do not transfer data with these addresses set this way.
– 36 –
CXA2543R
3) Serial data mode settings (X: don't care)
• Input switching
D1
D0
0
X
Composite input (default)
1
0
Y/C input
1
1
Y/color difference input
• System switching
D3
D2
0
X
NTSC (default)
1
0
D-PAL
1
1
S-PAL
• Supported panel switching
D4
0
DCX501BK (default)
1
LCX018AK
• Aspect switching
D5
0
4:3 (default)
1
16:9
• Sample-and-hold timing switching
D7
D6
0
0
SHS1 (default)
0
1
SHS2
1
0
SHS3
1
1
Through (sample-and-hold not performed)
• HD output polarity switching
D0
0
Negative polarity (default)
1
Positive polarity
• VD output polarity switching
D1
0
Negative polarity (default)
1
Positive polarity
• Y/color difference clamp position switching
This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input mode.
D2
0
Pedestal position (default)
1
SYNC position
• Mode switching
This is the test mode. Set to normal mode.
D3
0
Normal mode (default)
1
Test mode
– 37 –
CXA2543R
• Sync generator function
This stops outputs other than VD and HD of the TG block.
D4
0
OFF (default)
1
ON
Note) Make sure that Vcc2, 3 (12V) and LCD panel power supply should be turned OFF during sync generator
ON.
• Up/down inversion function
This switches the up/down inverted display.
D5
0
DOWN (normal display) (default)
1
UP (up/down inverted display)
• FRP256 field inversion
This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields.
D6
0
OFF (default)
1
ON
• FRP polarity inversion function
D7
0
ON (1H inversion) (default)
1
OFF (polarity not inverted)
• External field identification input switching
Internal field identification is not performed and an externally field input source is used.
D0
0
OFF (internal identification) (default)
1
ON (external input)
• External VSYNC input switching
Internal VSYNC separation is not performed and an externally input VSYNC is used.
D1
0
OFF (internal separation) (default)
1
ON (external input)
• PAL pulse elimination switching
This switches on/off the PAL pulse elimination function during PAL mode.
D2
0
ON (elimination performed) (default)
1
OFF (elimination not performed)
– 38 –
CXA2543R
• H position setting
D4
D3
D2
D1
D0
0
0
0
0
0
:
:
:
:
:
1
0
0
0
0 (default)
:
:
:
:
:
1
1
1
1
1
Variable in 2fH (= 1 bit) increments
CLK (internal)
10001
10000
HST
01111
1 step 1 step
• HD phase setting
D4
D3
D2
D1
D0
0
0
0
0
0 (default)
:
:
:
:
:
1
1
1
1
1
Variable in 4fH (= 1 bit) increments
HSYNC
00000
HD
11111
31 steps
– 39 –
CXA2543R
• PCG pulse position
This sets the PCG pulse position (A in the figure below).
D1
D0
0
0
(default)
1
1
DCX501 and LCX018 (4:3) mode: variable in 6fH (= 1 bit) increments
LCX018 (16:9) mode: variable in 9fH (= 1 bit) increments
• PCG pulse width
This sets the PCG pulse width (B in the figure below).
D5
D4
0
0
(default)
1
1
DCX501 and LCX018 (4:3) mode: variable in 8fH (= 1 bit) increments
LCX018 (16:9) mode: variable in 12fH (= 1 bit) increments
• EN pulse position
This sets the EN pulse position (C in the figure below).
D1
D0
0
0
(default)
1
1
DCX501 and LCX018 (4:3) mode: variable in 4fH (= 1 bit) increments
LCX018 (16:9) mode: variable in 6fH (= 1 bit) increments
• EN pulse width
This sets the EN pulse width (D in the figure below).
D5
D4
0
0
(default)
1
1
DCX501 and LCX018 (4:3) mode: variable in 8fH (= 1 bit) increments
LCX018 (16:9) mode: variable in 12fH (= 1 bit) increments
HSYNC
PCG
B
A
EN
D
C
Setting Correspondence Table
Set the positions and widths for the EN and PCG pulses as follows when driving the DCX501BK and the LCX018AK.
DCX501BK
LCX018AK
Width
Position
Width
D5
D4
D1
D0
PCG pulse
0
0
0
0
EN pulse
0
0
0
0
– 40 –
Position
D5
D4
D1
D0
PCG pulse
1
0
0
0
EN pulse
0
0
1
1
CXA2543R
4) Serial data electronic attenuator (D/A converter) settings
• HUE
D7
D6
1
0
• COLOR
D7
D6
1
0
• BRIGHT
D7
D6
1
0
• CONTRAST
D7
D6
1
0
• R-BRT
D7
D6
1
0
• B-BRT
D7
D6
1
0
• γ1
D7
D6
0
0
• γ2
D7
D6
0
0
• PSIG-BRT
D7
D6
0
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
5) Test mode
Test mode results if data is sent to the following addresses.
For this reason, do not perform data transfer using these addresses.
D12
1
D11
1
D10
1
D9
1
D8
1
D7
∗
D6
∗
D5
∗
D4
∗
D3
∗
D2
∗
D1
∗
D0
∗
Note) If data transfer is performed in these addresses, the chip will enter test mode regardless of the data set.
– 41 –
CXA2543R
DCX501BK Color Coding Diagram
The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.
DCX501BK pixel arrangement
HSW1
dummy1
Vline1
Vline2
Vline3
R
B
G
B
G
HSW267
HSW268
B
G
R
R
G
B
B
G
R
B
G
B
B
G
R
R
R
B
G
G
R
B
G
B
B
G
R
R
B
Photo-shielding
area
G B R G
R
G
B
R
G
B
R
G
B
G
B
G
R
G
R
G
R
B
R
B
R
B
G
B
G
B
G
R
G
R
G
R
B
R
G
R
B
G
R
B
R
B
G
G
B
G
R
R
R
B
R
G
R
B
B
G
R
G
R
B
R
B
G
R
B
G
R
B
R
R
R
G
R
B
R
800
803
– 42 –
225 227
G
B
G
B
G
B
G
R
G
R
G
R
B
R
B
R
B
G
B
G
B
G
R
G
R
G
Precharge SW
2
1
G B R G B R G B R G B R G
Display area
B R G B R G B R G B R G B R
R
G
R
B
R
B
G
B
G
R
B
R
G
R
B
R
dummy2
B
G
B
Vline225
HSW266
A
A
A
AA
AA
AA
AA
AA
AA
A
A
AA
AA
A
A
AA
AA
AA
A
A
AA
A
AA
A
AAAA
AAA
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
A
AA
A
A
AA
AA
A
A
AA
AA
A
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
R
R
Vline224
HSW3
HSW2
1
1
– 43 –
2 dots
225 dots
(effective 8.775mm)
2 dots
225
224
4
3
2
1
DL2
1
45
46
47
311
312
313
314
356
357
DR1
DR2
EVEN = 7 dots
ODD = 7 dots
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
GATE SW GATE SW GATE SW GATE SW GATE SW
Side Black
EVEN = 133 dots
ODD = 132 dots
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
44
4:3 Area
Side Black
2
EVEN = 803 dots
ODD = 804 dots
(effective 11.651mm)
EVEN = 1083 dots
ODD = 1083 dots
EVEN = 133 dots
ODD = 132 dots
GATE SW GATE SW GATE SW GATE SW
DL1
EVEN = 7 dots
ODD = 8 dots
LCX018AK Pixel Arrangement (4:3)
CXA2543R
– 44 –
2 dots
225 dots
(effective 8.775mm)
2 dots
DL2
1
2
3
355
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
EVEN = 1069 dots
ODD = 1068 dots
(effective 15.493mm)
EVEN = 1083 dots
ODD = 1083 dots
357
DR1
DR2
GATE SW GATE SW GATE SW GATE SW
356
EVEN = 7 dots
ODD = 7 dots
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
3
225
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
224
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
2
4
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
1
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
DL1
EVEN = 7 dots
ODD = 8 dots
LCX018AK Pixel Arrangement (16:9)
CXA2543R
– 45 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
6.0µs (101fH)
1.0µs (17fH)
76fH
2.0µs (34fH)
ODD LINE
2.5µs (42fH)
1.5µs (25fH)
7.5µs (125.5fH)
4.5µs (75fH)
4.7µs (79fH)
5.0µs (83.5fH)
20.5fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
EN
(PAL)
PSIGFRP
(Internal pulse)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
DCX501BK Horizontal Direction Timing Chart
NTSC/PAL
CXA2543R
– 46 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
6.0µs (101fH)
1.0µs (17fH)
76fH
2.0µs (34fH)
EVEN LINE
2.5µs (42fH)
1.5µs (25fH)
124fH
4.5µs (75fH)
4.7µs (79fH)
82fH
19fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
EN
(PAL)
PSIGFRP
(Internal pulse)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
DCX501BK Horizontal Direction Timing Chart
NTSC/PAL
CXA2543R
– 47 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
6.0µs (101fH)
1.0µs (17fH)
76fH
2.0µs (34fH)
ODD LINE
2.5µs (42fH)
1.5µs (25fH)
7.5µs (125.5fH)
4.5µs (75fH)
4.7µs (79fH)
5.0µs (83.5fH)
20.5fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
EN
(PAL)
PSIGFRP
(Internal pulse)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
DCX501BK Horizontal Direction Timing Chart
NTSC/PAL
CXA2543R
– 48 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
6.0µs (101fH)
1.0µs (17fH)
76fH
2.0µs (34fH)
EVEN LINE
2.5µs (42fH)
1.5µs (25fH)
127fH
4.5µs (75fH)
4.7µs (79fH)
85fH
22fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
EN
(PAL)
PSIGFRP
(Internal pulse)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
DCX501BK Horizontal Direction Timing Chart
NTSC/PAL
CXA2543R
– 49 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
0.5µs (8fH)
2.0µs (34fH)
ODD LINE
1.0µs (17fH)
4.5µs (76fH)
6.0µs (101fH)
2.5µs (41fH)
4.5µs (75fH)
4.7µs (79fH)
2.2µs (37fH)
7.0µs (117.5fH)
4.5µs (75.5fH)
35.5fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan), PCG width: LH, EN position: HH
Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)
PLL Counter N: 1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
EN
(PAL)
PSIGFRP
(Internal pulse)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
FRP
(Internal pulse)
SH4
(Internal pulse)
SH1
(Internal pulse)
SH2
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (4:3)
NTSC/PAL
CXA2543R
– 50 –
0.5µs (8fH)
EVEN LINE
6.0µs (101fH)
2.5µs (41fH)
116fH
2.2µs (37fH)
4.5µs (75fH)
4.7µs (79fH)
74fH
34fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan), PCG width: LH, EN position: HH
Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)
PLL Counter N: 1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
1.0µs (17fH)
PCG
EVEN FIELD
EVEN FIELD
2.0µs (34fH)
4.5µs (76fH)
ODD FIELD
ODD FIELD
4.7µs (79fH)
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
FRP
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH1
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (4:3)
NTSC/PAL
CXA2543R
– 51 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
0.5µs (8fH)
2.0µs (34fH)
ODD LINE
1.0µs (17fH)
4.5µs (76fH)
6.0µs (101fH)
2.5µs (41fH)
2.2µs (37fH)
7.0µs (117.5fH)
4.5µs (75fH)
4.7µs (79fH)
4.5µs (75.5fH)
35.5fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan), PCG width: LH, EN position: HH
Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)
PLL Counter N: 1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
FRP
(Internal pulse)
SH1
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (4:3)
NTSC/PAL
CXA2543R
– 52 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
4.7µs (79fH)
0.5µs (8fH)
2.0µs (34fH)
EVEN LINE
1.0µs (17fH)
4.5µs (76fH)
6.0µs (101fH)
2.5µs (41fH)
4.5µs (75fH)
4.7µs (79fH)
2.2µs (37fH)
119fH
77fH
37fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan), PCG width: LH, EN position: HH
Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)
PLL Counter N: 1066fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH1
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH3
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (4:3)
NTSC/PAL
CXA2543R
– 53 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
2.0µs (45fH)
0.5µs (11fH)
4.7µs (105fH)
ODD LINE
1.0µs (22fH)
2.5µs (57fH)
6.0µs (134fH)
4.5µs (101fH)
2.2µs (51fH)
7.0µs (156.5fH)
4.5µs (100fH)
4.7µs (105fH)
4.5µs (100.5fH)
47.5fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan), PCG width: LH, EN position: HH
Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)
PLL Counter N: 1417fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
FRP
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH1
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (16:9)
NTSC/PAL
CXA2543R
– 54 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
1.0µs (22fH)
2.5µs (57fH)
2.2µs (51fH)
155fH
4.5µs (100fH)
4.7µs (105fH)
6.0µs (134fH)
4.5µs (101fH)
EVEN LINE
2.0µs (45fH)
0.5µs (11fH)
4.7µs (105fH)
AAA
99fH
46fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan), PCG width: LH, EN position: HH
Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)
PLL Counter N: 1417fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH3
(Internal pulse)
FRP
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH1
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (16:9)
NTSC/PAL
CXA2543R
– 55 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
1.0µs (22fH)
2.5µs (57fH)
4.5µs (100fH)
4.7µs (105fH)
2.2µs (51fH)
4.5µs (100.5fH)
7.0µs (156.5fH)
AAA
AAA
6.0µs (134fH)
4.5µs (101fH)
ODD LINE
2.0µs (45fH)
0.5µs (11fH)
4.7µs (105fH)
47.5fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan), PCG width: LH, EN position: HH
Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)
PLL Counter N: 1417fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH1
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH3
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (16:9)
NTSC/PAL
CXA2543R
– 56 –
ODD FIELD
ODD FIELD
EVEN FIELD
EVEN FIELD
2.0µs (45fH)
0.5µs (11fH)
4.7µs (105fH)
EVEN LINE
1.0µs (22fH)
2.5µs (57fH)
6.0µs (134fH)
4.5µs (101fH)
158fH
2.2µs (51fH)
4.5µs (100fH)
4.7µs (105fH)
102fH
49fH
6fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan), PCG width: LH, EN position: HH
Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)
PLL Counter N: 1417fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
PSIGFRP
(Internal pulse)
EN
(PAL)
EN
PCG
VST/VD
VCK2
VCK1
SH1
(Internal pulse)
SH2
(Internal pulse)
SH4
(Internal pulse)
SH3
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST1
HD
(BLK)
SYNC
MCK
LCX018AK Horizontal Direction Timing Chart (16:9)
NTSC/PAL
CXA2543R
– 57 –
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse) (1F inversion)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
DCX501BK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart
CXA2543R
– 58 –
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
DCX501BK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart
CXA2543R
– 59 –
(1F inversion)
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
DCX501BK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart
CXA2543R
– 60 –
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse) (1F inversion)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
DCX501BK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart
CXA2543R
– 61 –
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
169-line display area
DCX501BK Vertical Direction Output Pulse
NTSC WIDE Vertical Direction Timing Chart
169-line display area
1/4 pulse eliminator
CXA2543R
– 62 –
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
169-line display area
DCX501BK Vertical Direction Output Pulse
NTSC WIDE Vertical Direction Timing Chart
169-line display area
1/4 pulse eliminator
CXA2543R
– 63 –
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(1F inversion)
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
DCX501BK Vertical Direction Output Pulse
PAL WIDE Vertical Direction Timing Chart
169-line display area
1/2 and 1/4 pulse eliminator
CXA2543R
– 64 –
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(1F inversion)
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
DCX501BK Vertical Direction Output Pulse
PAL WIDE Vertical Direction Timing Chart
169-line display area
1/2 and 1/4 pulse eliminator
CXA2543R
– 65 –
(1F inversion)
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart (DOWN)
CXA2543R
– 66 –
(1F inversion)
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart (DOWN)
CXA2543R
– 67 –
(1F inversion)
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart (DOWN)
CXA2543R
– 68 –
(1F inversion)
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart (DOWN)
CXA2543R
– 69 –
(1F inversion)
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart (UP)
CXA2543R
– 70 –
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
(1F inversion)
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
NTSC Vertical Direction Timing Chart (UP)
CXA2543R
– 71 –
(1F inversion)
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart (UP)
CXA2543R
– 72 –
(1F inversion)
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
SBLK
(Internal pulse)
FLD
(Internal pulse)
FRP
(Internal pulse)
VD
PCG
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
LCX018AK Vertical Direction Output Pulse
PAL Vertical Direction Timing Chart (UP)
CXA2543R
CXA2543R
Application Circuit (NTSC/PAL, COMP and Y/C input)
+3V
To LCD panel
+12V
3.3k
+12V
0.1µ
Buff
47µ
0.47µ
0.47µ
0.47µ
IN
To Serial controller
0.47µ
OUT
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC2
FB R
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT
LOAD
DATA
SCLK
3.3k
48
+4.5V
49 VCC1
0.1µ
47µ
Sample PSIG buffer circuit
VD 32
0.01µ
50 SIG.CENTER
VSS2 31
0.01µ
51 B-Y IN
EN 30
52 R-Y IN
XEN 29
0.01µ
+4.5V
53
47k
0.01µ
VCK1 28
C OUT
VCK2 27
54 BLK LIM
55 APC
15k
0.068µ
0.22µ
VST 26
∗1
56 VXO OUT
XVST 25
∗2
57 VXO IN
FLD IN 24
58 V REG
HD 23
To LCD panel
1µ
Y/C
C IN
59 C IN
COMP
PCG 22
60 TEST3
XPCG 21
61 Y IN
HCK1 20
62 PIC
HCK2 19
1µ
+4.5V
47k
0.01µ
∗6 15k
HST 18
63 F0 ADJ
VSS1
CKI
7
8
9
10
11
12
13
14
VDD1
RPD
6
CKO
TEST2
5
TEST1
S.SEP IN
4
VD IN
H.FIL OUT
3
EXT B
SYNC IN
2
XHST 17
EXT G
GND1
1
64 PWRST
EXT R
TRAP
0.01µ
15
16
L
750
1k
220p
COMP/Y IN
+3V
∗4
C
47µ
0.1µ
10k
3.3µ
∗5
6800p
0.033µ 0.47µ
33k
∗3
10k
12V
47k
0.01µ
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545Hz
PAL: 4.433619Hz
∗2 NTSC: shorted, PAL: 18pF
∗3 Variable Capcitance Diode: 1T369 (SONY)
∗4 DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF
∗5 Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
∗6 Resistance value variation: ±2%,
temperature coefficient: ±200ppm or less
Connect to +4.5V during Y/C input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 73 –
CXA2543R
Application Circuit (NTSC/PAL, Y/color difference input)
+3V
To LCD panel
+12V
3.3k
+12V
0.1µ
Buff
47µ
0.47µ
0.47µ
0.47µ
IN
To Serial controller
0.47µ
OUT
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC2
FB R
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT
LOAD
DATA
SCLK
3.3k
48
+4.5V
49 VCC1
0.1µ
47µ
Sample PSIG buffer circuit
VD 32
0.01µ
50 SIG.CENTER
VSS2 31
0.1µ
B-Y IN
51 B-Y IN
EN 30
R-Y IN
52 R-Y IN
XEN 29
+4.5V
53 C OUT
VCK1 28
54 BLK LIM
VCK2 27
0.1µ
47k
0.01µ
55 APC
VST 26
56 VXO OUT
XVST 25
57 VXO IN
FLD IN 24
58 V REG
HD 23
1µ
To LCD panel
59 C IN
PCG 22
60 TEST3
XPCG 21
61 Y IN
HCK1 20
62 PIC
HCK2 19
1µ
+4.5V
47k
0.01µ +4.5V
HST 18
63 F0 ADJ
TRAP
GND1
SYNC IN
H.FIL OUT
S.SEP IN
EXT R
EXT G
EXT B
VD IN
TEST1
TEST2
RPD
VSS1
CKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XHST 17
L
750
1k
15
16
+3V
∗2
220p
0.033µ
C
47µ
0.1µ
0.47µ
10k
3.3µ
6800p
COMP/Y IN
VDD1
64 PWRST
CKO
0.01µ
33k
∗1
10k
+12V
47k
0.01µ
∗1 Variable Capcitance Diode: 1T369 (SONY)
∗2 DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 74 –
CXA2543R
Example of Representative Characteristics
HUE adjustment characteristics
COLOR adjustment characteristics
10
5
40
0
20
Gain [dB]
HUE adjustment angle [deg]
60
0
–5
–10
–15
–20
–20
–40
–25
–60
–30
0
20
40
60
80
0A0 0C0 0E0 0FF
DAC value
0
20
40
60
80 0A0 0C0 0E0 0FF
DAC value
NT
PAL
CONTRAST adjustment characteristics
25
5
11
20
4
10
3
9
2
8
1
7
0
0
20
40
60
80
Output gain [dB]
12
Inverted output black level [V]
Non-inverted output black level [V]
BRIGHT adjustment characteristics
6
10
5
0
–5
6
0A0 0C0 0E0 0FF
DAC value
15
0
40
Non-inverted black
Inverted black
60
80
0A0 0C0 0E0 0FF
DAC value
PSIG-BRIGHT adjustment characteristics
SUB-BRIGHT adjustment characteristics
1.5
10
1.0
8
Output level [Vp-p]
Output level with respect to G output [V]
20
0.5
0
–0.5
6
4
2
–1.0
–1.5
0
0
20
40
60
80
0A0 0C0 0E0 0FF
0
DAC value
20
40
60
80
0A0 0C0 0E0 0FF
DAC value
– 75 –
CXA2543R
Color difference COLOR adjustment characteristics
Color difference balance adjustment
10
5
4
5
3
0
Gain [dB]
Gain [dB]
2
1
0
–1
–5
–10
–2
–3
–15
–4
–20
–5
0
20
40
0
60
80 0A0 0C0 0E0 0FF
B-Y output
DAC value
20
40
60
80
0A0 0C0 0E0 0FF
DAC value
R-Y output
Sharpness characteristics (COMP, NTSC)
Sharpness characteristics (COMP, PAL)
15
15
10
10
5
5
0
Gain [dB]
0
Gain [dB]
–5
–10
–15
–5
–10
–15
–20
–20
–25
–25
–30
0
1
2
3
4
–30
5
0
1
0V
2.25V
4.5V
Frequency [MHz]
2
3
4
Frequency [MHz]
Sharpness characteristics (Y/C)
5
0V
2.25V
4.5V
Black level limiter adjustment characteristics
20
10
15
9
Limiter level [Vp-p]
10
5
Gain [dB]
0
–5
–10
8
7
6
–15
5
–20
–25
0
2
4
6
Frequency [MHz]
8
4
10
1.0
0V
2.25V
4.5V
1.5
2.0
2.5
3.0
Pin voltage [V]
– 76 –
3.5
4.0
CXA2543R
Notes on Operation
The CXA2543R contains digital circuits, so the set board pattern must be designed in consideration of
undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.
• Make the IC power supply and GND patterns as plain as possible. In particular, GND and VSS should not be
separated and should be connected to the same GND pattern as close to the pins as possible.
• Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible.
• The trap connected to Pin 1 should be located as close to the pin as possible. Also, don't pass other signal
lines close to this pin or the connected trap.
• The wiring for the crystal and capacitor connected to Pins 56 and 57 should be as short as possible in order
to prevent floating capacitance. Don't pass other signal lines close to these pins in order to prevent
interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly
according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly
investigate these items before using the set.
• The resistor connected to Pin 63 should be located as close to the pin as possible. Also, take care not to
pass other signal lines close to this pin.
The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors
connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is
received by the internal capacitor, so this signal should be directly input at low impedance.
The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current
with a small absolute value and variance.
A thorough study of the external buffer for PSIG output should be made before deciding on a circuit to
ascertain that it sufficiently brings out the characteristics of the LCD panel.
If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction
depending on the order power is supplied to the circuits. Thoroughly study the consequences of using this IC
with other circuits before deciding on its use.
Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than
the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the
order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.
Do not apply a voltage higher than VDD or lower than VSS to I/O pins.
Do not use this IC under operating conditions other than those given.
Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage
the device, leading to eventual breakdown.
This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.
– 77 –
CXA2543R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
0.15 ± 0.05
48
0.1
33
49
32
A
64
17
1
1.25
16
+ 0.08
0.18 – 0.03
0.5
1.7 MAX
0.1
M
0° to 10°
0.5 ± 0.2
(0.5)
0.1 ± 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L061
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP064-P-1010-AY
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 78 –