Confidential Draft
6/18/07
CS4352
192 kHz Stereo DAC with 2 Vrms Line Out
Features
Description
Multi-bit Delta-Sigma Modulator
The CS4352 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 Vrms line-level
driver. The advantages of this architecture include ideal
differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and
temperature, high tolerance to clock jitter, and a minimal
set of external components.
24-Bit Resolution
Supports Sample Rates up to 192 kHz
106 dB A-wt Dynamic Range
-93 dB THD+N
Integrated Line Driver
2 Vrms Output into 5 kΩ AC Load
Analog Low-Pass Filter
The CS4352 is available in a 20-pin TSSOP package in
both Commercial grade (-40°C to +85°C) and Automotive grade (-40°C to +105°C). The CDB4352 Customer
Demonstration Board is also available for device evaluation and implementation suggestions. Please see
“Ordering Information” on page 20 for complete details.
Stereo Mutes with Auto-Mute Function
Low Clock-Jitter Sensitivity
Low-Latency Digital Filtering
Popguard® Technology for Control of Clicks
and Pops
Single-Ended Outputs
+3.3 V Core, +9 to 12 V Analog, and +1.5 to
3.3 V Interface Power Supplies
Low Power Consumption
20-pin TSSOP, Lead-Free Assembly
1.5 V to 3.3 V
These features are ideal for cost-sensitive, 2-channel
audio systems including video game consoles, DVD
players, A/V receivers, set-top boxes, digital TVs and
DVD Recorders, mini-component systems, and mixing
consoles.
9 V to 12 V
3.3 V
Hardware Control
Hardware
Configuration
Serial Audio Input
Level Translator
Reset
Interpolation
Filter
Multibit
∆Σ Modulator
DAC
Amp
+
Filter
2 Vrms Line Level
Left Channel
Output
Interpolation
Filter
Multibit
∆Σ Modulator
DAC
Amp
+
Filter
2 Vrms Line Level
Right Channel
Output
PCM
Serial
Interface
Auto Speed Mode
Detect
Internal Voltage
Reference
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
External
Mute
Control
Left and Right
Mute Controls
JUN '07
DS684F2
CS4352
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................. 3
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
RECOMMENDED OPERATING CONDITIONS .................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ............................................................. 5
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) .............................................................. 6
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
................................................... 8
DIGITAL CHARACTERISTICS .............................................................................................................. 9
POWER AND THERMAL CHARACTERISTICS ................................................................................... 9
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 10
4. APPLICATIONS ................................................................................................................................... 11
4.6.1 Capacitor Placement ............................................................................................................. 13
4.7.1 Power-Up .............................................................................................................................. 14
4.7.2 Power-Down .......................................................................................................................... 14
4.7.3 Discharge Time ..................................................................................................................... 14
5. DIGITAL FILTER RESPONSE PLOTS
......................................................................................... 16
6. PARAMETER DEFINITIONS ................................................................................................................ 18
7. PACKAGE DIMENSIONS ................................................................................................................... 19
8. ORDERING INFORMATION ............................................................................................................... 20
9. REVISION HISTORY ............................................................................................................................ 20
LIST OF FIGURES
Figure 1.Serial Input Timing ........................................................................................................................ 8
Figure 2.Typical Connection Diagram ....................................................................................................... 10
Figure 3.I²S, up to 24-Bit Data .................................................................................................................. 12
Figure 4.Right-Justified Data ..................................................................................................................... 12
Figure 5.Left-Justified up to 24-Bit Data .................................................................................................... 12
Figure 6.De-Emphasis Curve .................................................................................................................... 13
Figure 7.Single-Speed Stopband Rejection .............................................................................................. 16
Figure 8.Single-Speed Transition Band .................................................................................................... 16
Figure 9.Single-Speed Transition Band (detail) ........................................................................................ 16
Figure 10.Single-Speed Passband Ripple ................................................................................................ 16
Figure 11.Double-Speed Stopband Rejection ........................................................................................... 16
Figure 12.Double-Speed Transition Band ................................................................................................. 16
Figure 13.Double-Speed Transition Band (detail) ..................................................................................... 17
Figure 14.Double-Speed Passband Ripple ............................................................................................... 17
Figure 15.Quad-Speed Stopband Rejection ............................................................................................. 17
Figure 16.Quad-Speed Transition Band ................................................................................................... 17
Figure 17.Quad-Speed Transition Band (detail) ....................................................................................... 17
Figure 18.Quad-Speed Passband Ripple ................................................................................................. 17
LIST OF TABLES
Table 1. CS4352 Auto-Detect ................................................................................................................... 11
Table 2. Single-Speed Mode Standard Frequencies ................................................................................ 11
Table 3. Double-Speed Mode Standard Frequencies ............................................................................... 11
Table 4. Quad-Speed Mode Standard Frequencies ................................................................................. 11
Table 5. Digital Interface Format ............................................................................................................... 12
2
DS684F2
CS4352
1. PIN DESCRIPTIONS
SDIN
SCLK
LRCK
MCLK
VD
GND
DIF1
DIF0
DEM
RST
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Pin Name Pin #
VL
AMUTEC
AOUTA
VA_H
GND
AOUTB
BMUTEC
VQ
VBIAS
VA
Pin Description
SDIN
1
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK
2
Serial Clock (Input) - Serial clock for the serial audio interface.
LRCK
3
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK
4
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
5
Digital Power (Input) - Positive power supply for the digital section.
GND
6
16
Ground (Input) - Ground reference.
DIF0
DIF1
8
7
Digital Interface Format (Input) - Defines the required relationship between the Left/Right Clock, Serial
Clock, and Serial Audio Data.
DEM
9
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz
sample rates
RST
10
Reset (Input) - Powers down the device and resets all internal registers to their default settings when
enabled.
VA
11
Low Voltage Analog Power (Input) - Positive power supply for the analog section.
VBIAS
12
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
VQ
13
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VA_H
17
High Voltage Analog Power (Input) - Positive power supply for the analog section.
VL
20
Serial Audio Interface Power (Input) - Positive power for the serial audio interface
BMUTEC
AMUTEC
14
19
Mute Control (Output) - Control signal for optional mute circuit.
AOUTB
AOUTA
15
18
Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table.
DS684F2
3
CS4352
2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
Ambient Operating Temperature (power applied)
-CZZ
-DZZ
VA_H
VA
VD
VL
8.40
3.13
3.13
1.43
-40
-40
9
3.3
3.3
1.5
-
12.6
3.47
3.47
3.47
+85
+105
V
V
V
V
°C
°C
DC Power Supply
TA
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Digital Interface
Symbol
Min
Max
Units
VA_H
VA
VD
VL
Iin
VIN-L
TA
Tstg
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-65
14.0
3.63
3.63
3.63
±10
VL+ 0.4
+125
+150
V
V
V
V
mA
V
°C
°C
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
4
DS684F2
CS4352
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)
Test conditions (unless otherwise specified): TA = 25 °C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+
and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz.
Parameter
All Speed Modes
Dynamic Range (Note 1)
Symbol
Min
Typ
Max
Unit
100
97
-
106
103
98
95
-
dB
dB
dB
dB
-
-93
-83
-43
-93
-75
-35
-89
-77
-37
-
dB
dB
dB
dB
dB
dB
(A-wt)
-
106
-
dB
(1 kHz)
-
99
-
dB
1.84
2.00
2.11
Vrms
Fs = 48, 96, and 192 kHz
24-bit
A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise
24-bit
16-bit
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
(Note 1)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
Analog Output - All Modes
Full Scale Output Voltage
Common Mode Voltage
Max Current draw from an AOUT pin
Max Current draw from VQ
VQ
-
4
-
Vdc
IOUTmax
-
575
-
µA
IQmax
-
1
-
µA
-
0.1
-
dB
Interchannel Gain Mismatch
Gain Drift
-
100
-
ppm/°C
ZOUT
-
50
-
Ω
AC-Load Resistance
RL
5
-
-
kΩ
Load Capacitance
CL
-
-
100
pF
Output Impedance
Notes:
1.
DS684F2
One-half LSB of triangular PDF dither is added to data.
5
CS4352
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ)
Test conditions (unless otherwise specified): TA = -40°C to 85°C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V;
VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS;
measurement bandwidth 10 Hz to 20 kHz.
Parameter
All Speed Modes
Dynamic Range (Note 2)
Symbol
Min
Typ
Max
Unit
96
93
-
106
103
98
95
-
dB
dB
dB
dB
-
-93
-83
-43
-93
-75
-35
-89
-73
-33
-
dB
dB
dB
dB
dB
dB
(A-wt)
-
106
-
dB
(1 kHz)
-
99
-
dB
1.81
2.00
2.17
Vrms
Fs = 48, 96, and 192 kHz
24-bit
A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise
24-bit
16-bit
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
(Note 2)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
Analog Output - All Modes
Full Scale Output Voltage
Common Mode Voltage
Max Current draw from an AOUT pin
Max Current draw from VQ
VQ
-
4
-
Vdc
IOUTmax
-
575
-
µA
IQmax
-
1
-
µA
-
0.1
-
dB
Interchannel Gain Mismatch
Gain Drift
-
100
-
ppm/°C
ZOUT
-
50
-
Ω
AC-Load Resistance
RL
5
-
-
kΩ
Load Capacitance
CL
-
-
100
pF
Output Impedance
Notes:
2. One-half LSB of triangular PDF dither is added to data.
6
DS684F2
CS4352
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. frequency plots of the data in the table below
are available in “Digital Filter Response Plots” on page 16.)
Parameter
Min
Typ
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
De-emphasis Error (Note 5)(Relative to 1 kHz)
to -0.01 dB corner
to -3 dB corner
(Note 4)
Fs = 44.1 kHz
0
0
-0.01
0.547
102
-
9.4/Fs
-
Max
Unit
.454
.499
+0.01
±0.56/Fs
0
±0.14
Fs
Fs
dB
Fs
dB
s
s
s
dB
.430
.499
0.01
±0.03/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
.105
.490
0.01
±0.01/Fs
0
Fs
Fs
dB
Fs
dB
s
s
s
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
to -0.01 dB corner
to -3 dB corner
(Note 4)
0
0
-0.01
.583
80
-
4.6/Fs
-
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 3)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
to -0.01 dB corner
to -3 dB corner
(Note 4)
0
0
-0.01
.635
90
-
4.7/Fs
-
Notes:
3. Response is clock-dependent and will scale with Fs.
4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
5. De-emphasis is available only in Single-Speed Mode.
DS684F2
7
CS4352
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Min
Max
Units
MCLK Frequency
1.024
48.0
MHz
MCLK Duty Cycle
45
55
%
4
84
170
54
108
216
kHz
kHz
kHz
40
60
%
Input Sample Rate (Auto selection)
Symbol
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
LRCK Duty Cycle
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
Single-Speed Mode
tsclkw
1
---------------------( 128 )Fs
-
-
Double-Speed Mode
tsclkw
1
-----------------( 64 )Fs
-
-
Quad-Speed Mode
tsclkw
2
----------------MCLK
-
-
SCLK rising to LRCK edge delay
tslrd
20
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
ns
SCLK Period
LR C K
t sclkh
t slrs
t slrd
t sclkl
S C LK
t sd lrs
t sd h
S D ATA
Figure 1. Serial Input Timing
8
DS684F2
CS4352
DIGITAL CHARACTERISTICS
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Parameters
VL = 3.3 V
VL = 2.5 V
VL = 1.5 V
VIH
VIH
VIH
2.0
1.7
1.05
-
-
V
V
V
Low-Level Input Voltage
VL = 3.3 V
VL = 2.5 V
VL = 1.5 V
VIL
VIL
VIL
-
-
0.8
0.7
0.38
V
V
V
Iin
-
8
2
VA_H
0
±10
-
µA
pF
mA
V
V
Input Leakage Current
Input Capacitance
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
VOH
VOL
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
normal operation, VA_H = 12 V
VA_H = 9 V
VA= 3.3 V
VD= 3.3 V
Interface current VL= 3.3 V
power-down state, all supplies (Note 7)
Power Dissipation (all supplies)
(Note 6)
VA_H = 12 V
normal operation
power-down (Note 7)
VA_H = 9 V
normal operation
power-down (Note 7)
Power Supply Rejection Ratio (Note 8)
(1 kHz)
(60 Hz)
IA_H
IA_H
IA
ID
IL
Ipd
-
12
10
3
12
0.02
380
21
16
4
16
0.09
-
mA
mA
mA
mA
mA
µA
-
121
1
91
1
60
60
158
122
-
mW
mW
mW
mW
dB
dB
Power Supplies
Power Supply Current
(Note 6)
PSRR
Notes:
6. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.
7. Power down mode is defined as RST pin = Low with all clock and data lines held static low. All digital
inputs have a weak pull-down which is only present during reset. Opposing this pull-down will slightly
increase the power-down current (pull-down is equivalent to a 50 kΩ resistor per pin).
8. Valid with the recommended capacitor values on VQ and VBIAS as shown in the typical connection diagram in Section 3.
DS684F2
9
CS4352
3. TYPICAL CONNECTION DIAGRAM
5.1 Ω∗
+3.3 V
+3.3 V *
*Remove this supply if
10 µF
optional resistor is present.
The decoupling caps should
remain.
*Optional
0.1 µF
0.1 µF
VD
Digital
Audio
Source
4
MCLK
3
LRCK
2
SCLK
1
SDIN
20
VL
3.3 µF
11
VA
5
10 µF
VBIAS+ 12
VA_H
17
+9 V to +12 V
0.1 µF
10 µF
AMUTEC 19
+1.5 V to VD
0.1 µF
Optional
Mute
Circuit
560 Ω
CS4352 AOUTA
18
Left Out
3.3 µF
10 k Ω
2.2 nF*
BMUTEC 14
Mode
Configuration
10
RST
7
DIF1
8
DIF0
9
DEM
Optional
Mute
Circuit
560 Ω
AOUTB 15
3.3 µF
10 k Ω
Right Out
2.2 nF*
*Shown value is
for Fc=130 kHz
6
D
N
G
G
N
D
VQ 13
3.3 µF
15
Figure 2. Typical Connection Diagram
10
DS684F2
CS4352
4. APPLICATIONS
4.1
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode is
auto-detected.
The CS4352 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for
each mode are not supported.
Input Sample Rate (FS)
Mode
4 kHz - 54 kHz
84 kHz - 108 kHz
170 kHz - 216 kHz
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 1. CS4352 Auto-Detect
4.2
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2-4.
Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and
to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies.
Sample Rate
(kHz)
256x
384x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
1024x
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
128x
88.2
96
11.2896
12.2880
192x
MCLK (MHz)
256x
384x
512x
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 3. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
128x
MCLK (MHz)
192x
256x
176.4
192
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 4. Quad-Speed Mode Standard Frequencies
DS684F2
11
CS4352
4.3
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5.
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of
SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period
in format 3.
For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
DIF1
DIF0
0
0
1
1
0
1
0
1
DESCRIPTION
I²S, up to 24-bit Data
Right-Justified, 24-bit Data
Left-Justified, up to 24-bit Data
Right-Justified, 16-bit Data
FORMAT
FIGURE
0
1
2
3
3
4
5
4
Table 5. Digital Interface Format
L e ft C h a n n e l
LR CK
R ig h t C h a n n e l
SCLK
S D IN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 3. I²S, up to 24-Bit Data
LR C K
R ig h t C h a n n e l
L e ft C h a n ne l
SC LK
SD IN
MSB
M SB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LS B
Figure 4. Right-Justified Data
L e ft C h a n n e l
LR C K
R ig h t C h a n n e l
SCLK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 5. Left-Justified up to 24-Bit Data
12
DS684F2
CS4352
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The
De-emphasis error will increase for sample rates other than 44.1 kHz
When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM
pin turns off the de-emphasis filter.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 6. De-Emphasis Curve
Note:
4.5
De-emphasis is only available in Single-Speed Mode.
Recommended Power-Up Sequence
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, VQ will remain low and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up
sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.6
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 2 shows the recommended power arrangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted
coupling into the DAC.
4.6.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements.
DS684F2
13
CS4352
4.7
Popguard Transient Control
The CS4352 uses a novel technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended, single-supply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing
the appropriate DC-blocking capacitors.
4.7.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients.
4.7.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases, and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready
for the next power-on.
4.7.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio
is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks
and pops that can occur in any single-ended, single-supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the CDB4352 data sheet for a suggested mute circuit for dual-supply systems. Alternately, the
FET muting circuit from the CS4351 data sheet may be used as well. This FET circuit must be placed in
series after the RC filter; otherwise noise may occur during muting conditions. Further ESD protection will
need to be taken into consideration for the FET used.
14
DS684F2
CS4352
4.9
Initialization and Power-Down Sequence Diagram
USER: Apply Power
VQ and outputs
ramp down
Power-Down State
VQ and outputs low
USER: Apply MCLK, SCLK, LRCK,
and release RST
USER: Apply RST
VQ and outputs ramp up
Wait State
USER: Remove
LRCK or MCLK
USER: Apply MCLK, SCLK, and LRCK
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
Analog Output
is Generated
DS684F2
15
CS4352
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
5. DIGITAL FILTER RESPONSE PLOTS
−60
−60
−80
−80
−100
−100
−120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
−120
0.4
1
Figure 7. Single-Speed Stopband Rejection
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 8. Single-Speed Transition Band
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
Figure 9. Single-Speed Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
60
80
80
100
100
120
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
Figure 11. Double-Speed Stopband Rejection
16
0.1
0
20
0.4
0.05
Figure 10. Single-Speed Passband Ripple
0
120
0
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 12. Double-Speed Transition Band
DS684F2
CS4352
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
0
Figure 13. Double-Speed Transition Band (detail)
20
40
40
Amplitude (dB)
Amplitude (dB)
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
60
60
80
80
100
100
120
0.2
0.1
Figure 14. Double-Speed Passband Ripple
0
120
0.05
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
0.2
Figure 15. Quad-Speed Stopband Rejection
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 16. Quad-Speed Transition Band
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 17. Quad-Speed Transition Band (detail)
DS684F2
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 18. Quad-Speed Passband Ripple
17
CS4352
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Intra-channel Phase Deviation
The deviation from linear phase within a given channel.
Inter-channel Phase Deviation
The difference in phase between channels.
18
DS684F2
CS4352
7. PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
A1
SIDE VIEW
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
µ
MIN
-0.002
0.03346
0.00748
0.252
0.248
0.169
-0.020
0°
INCHES
NOM
-0.004
0.0354
0.0096
0.256
0.2519
0.1732
-0.024
4°
MAX
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
MIN
-0.05
0.85
0.19
6.40
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
6.50
6.40
4.40
-0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
Parameters
Package Thermal Resistance
DS684F2
20L TSSOP
Symbol
Min
Typ
Max
Units
θJA
-
72
-
°C/Watt
19
CS4352
8. ORDERING INFORMATION
Product
Description
Package
Pb-Free
CS4352
20-pin, 192 kHz Stereo
DAC with 2 Vrms Line
Out
20-pin
TSSOP
YES
CDB4352
CS4352 Evaluation Board
-
Grade
Temp Range
Container
Rail
Commercial -40° to +85° C
Tape & Reel
Rail
Automotive -40° to +105° C
Tape & Reel
-
Order #
CS4352-CZZ
CS4352-CZZR
CS4352-DZZ
CS4352-DZZR
CDB4352
9. REVISION HISTORY
Release
PP1
F1
F2
Changes
Lowered VA_H minimum specification.
Updated Idle channel noise specification to A-wt.
Updated AOUT current draw specification.
Updated VIL for VL=1.5V.
Updated performance specifications and limits based on statistical data.
Added Automotive grade specifications and ordering information.
Updated Commercial grade idle channel noise specification.
Lowered VIL maximum specifcation.
Updated power supply current specification.
Updated MCLK maximum specification.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
20
DS684F2