TI CDC706 Programmable 3-pll clock synthesizer / multiplier / divider Datasheet

CDC706
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SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
FEATURES
•
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•
•
•
•
•
•
•
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•
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High Performance 2:6 PLL Based Clock
Synthesizer / Multiplier / Divider
User Programmable PLL Frequencies
Easy In-Circuit Programming via SMBus Data
Interface
Wide PLL Divider Ratio Allows 0-PPM Output
Clock Error
Clock Inputs Accept a Crystal or a
Single-Ended LVCMOS or a Differential Input
Signal
Accepts Crystal Frequencies from 8 MHz up
to 54 MHz
Accepts LVCMOS or Differential Input
Frequencies up to 200 MHz
Two Programmable Control Inputs [S0/S1] for
User Defined Control Signals
Six LVCMOS Outputs with Output
Frequencies up to 300 MHz
LVCMOS Outputs can be Programmed for
Complementary Signals
Free Selectable Output Frequency via
Programmable Output Switching Matrix [6x6]
Including 7-Bit Post-Divider for Each Output
PLL Loop Filter Components Integrated
Low Period Jitter (Typical 60 ps)
Features Spread Spectrum Clocking (SSC) for
Lowering System EMI
Programmable Output Slew-Rate Control
(SRC) for Lowering System EMI
3.3-V Device Power Supply
Industrial Temperature Range –40°C to 85°C
Development and Programming Kit for Easy
PLL Design and Programming
(TI Pro-Clock™)
•
•
Packaged in 20-Pin TSSOP
Factory Programmable for Customized Default
Settings are Available. Contact TI Sales for
More Details.
APPLICATIONS
•
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Wireless Base Stations
Network Line Cards
Datacom / Telecom
TERMINAL ASSIGNMENT
PW PACKAGE
(TOP VIEW)
S0/CLK_SEL
S1
VCC
GND
CLK_IN0
CLK_IN1
VCC
GND
SDATA
SCLOCK
1
2
3
4
TSSOP 20
5
Pitch 0,65 mm
6
6.6 x 6.6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y5
Y4
VCCOUT2
GND
Y3
Y2
VCCOUT1
GND
Y1
Y0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pro-Clock is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
CDC706
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SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The CDC706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its
small physical outlines, the CDC706 is very flexible. It has the capability to produce an almost independent
output frequency from a given input frequency.
The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate
input waveform can be selected via the SMBus data interface controller.
To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL
can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO
(voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any
of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic
for each output.
The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a
27-MHz).
The CDC706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and
PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm applications with wide divider
factors.
PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to
reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.
Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.
The device provides customized applications. It is preprogrammed with a factory default configuration (see
Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus Interface.
Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding
logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).
The CDC706 has three power supply pins, VCC, VCCOUT1, and VCCOUT2. VCC is the power supply for the device. It
operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs.
VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs
supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output current drive is limited.
The CDC706 is characterized for operation from –40°C to 85°C.
2
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FUNCTIONAL BLOCK DIAGRAM
VCC
GND
VCCOUT1
PLL Bypass
PFD
Filter
prg. 12 Bit
Divider N
Crystal or
Clock Input
CLK_IN0
XO
or
2 LVCMOS
or
Differential
Input
CLK_IN1
VCO
VCO2 Bypass
prg. 9 Bit
Divider M
prg. 12 Bit
Divider N
MUX
PFD
Filter
VCO
SSC
On/Off
5 x 6 Programmable Switch A
prg. 9 Bit
Divider M
PLL2
w/ SSC
MUX
SO/CLK_SEL
VCO3 Bypass
PROGRAMMING
S1
LOGIC
SDATA
SMBUS
LOGIC
SCLOCK
PLL3
prg. 9 Bit
Divider M
PFD
Filter
Factory Prg.
prg. 12 Bit
Divider N
MUX
VCO
6 x 6 Programmable Switch B
PLL1
6 x Programmable 7-Bit Divider P0, P1, P2, P3, P4, P5, and Inversion Logic
Output Switch Matrix
VCO1 Bypass
GND
LV
CMOS
Y0
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
LV
CMOS
Y4
LV
CMOS
Y5
VCCOUT2
OUTPUT SWITCH MATRIX
5x6 − Switch A
7-Bit Divider
6x6 − Switch B
P0
Y0
P1
Y1
P2
Y2
PLL 2
non SSC
P3
Y3
PLL 2
w/ SSC
P4
Y4
P5
Y5
Input CLK
(PLL Bypass)
PLL 1
PLL 3
Programming
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TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
TSSOP20
NO.
Y0 to Y5
11, 12, 15,
16, 19, 20
O
LVCMOS outputs
CLK_IN0
5
I
Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used
as LVCMOS input or as positive differential signal inputs.
CLK_IN1
6
I/O
Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be
the second LVCMOS input or the negative differential signal input.
VCC
3, 7
Power
3.3-V power supply for the device.
VCCOUT1
14
Power
Power supply for outputs Y0, Y1.
VCCOUT2
18
Power
Power supply for outputs Y2, Y3, Y4, Y5.
4, 8, 13, 17
Ground
Ground
S0,
CLK_SEL
1
I
User programmable control input S0 (PLL bypass or power-down mode) , or CLK_SEL
(selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS
inputs; internal pullup 150 kΩ.
S1
2
I
User programmable control input S1 (output enable/disable or all output low), dependent on
the SMBus settings; LVCMOS inputs; internal pullup 150 kΩ
SDATA
9
I/O
SCLOCK
10
I
GND
Serial control data input/output for SMBus controller; LVCMOS input
Serial control clock input for SMBus controller; LVCMOS input
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VCC
Supply voltage range
–0.5 to 4.6
V
VI
Input voltage range (2)
–0.5 to VCC + 0.5
V
VO
Output voltage range (2)
– 0.5 to VCC + 0.5
V
II
Input current (VI < 0, V I > VCC)
±20
mA
IO
Continuous output current
±50
mA
Tstg
Storage temperature range
–65 to 150
°C
TJ
Maximum junction temperature
125
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
PACKAGE THERMAL RESISTANCE
for TSSOP20 (PW) Package (1) (2)
PARAMETER
θJA
Thermal resistance junction-to-ambient
θJC
Thermal resistance junction-to-case
(1)
(2)
4
AIRFLOW (LFM)
°C/W
0
66.3
150
59.3
250
56.3
500
51.9
19.7
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3
3.3
3.6
V
3.6
V
3.6
V
0.3 VCC
V
VCC
Device supply voltage
VCCOUT1
Output Y0, Y1 supply voltage
2.3
VCCOUT2
Output Y2, Y3, Y4, Y5 supply voltage
2.3
VIL
Low level input voltage LVCMOS
VIH
High level input voltage LVCMOS
VIthresh
Input voltage threshold LVCMOS
VI
Input voltage range LVCMOS
|VID|
Differential input voltage
0.1
VIC
Common-mode for differential input voltage
0.2
IOH/IOL
Output current (3.3 V)
IOH/IOL
CL
TA
Operating free-air temperature
UNIT
0.7 VCC
V
0.5 VCC
V
0
3.6
V
V
Vcc - 0.6
V
±6
mA
Output current (2.5 V)
±4
mA
Output load LVCMOS
25
pF
85
°C
–40
RECOMMENDED CRYSTAL SPECIFICATIONS
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance (1) (2)
CIN
Input capacitance CLK_IN0 and CLK_IN1
(1)
(2)
MIN
NOM
MAX
UNIT
8
27
54
MHz
15
Ω
60
3
pF
For crystal frequencies above 50 MHz the effective series resistor should not exceed 50 Ω to assure stable start-up condition.
Maximum Power Handling (Drive Level) see Figure 15.
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating-free air temperature
MIN
NOM MAX
PLL mode
1
200
PLL bypass mode
0
200
40%
60%
UNIT
CLK_IN REQUIREMENTS
fCLK_IN
CLK_IN clock input frequency (LVCMOS or Differential)
tr / tf
Rise and fall time CLK_IN signal (20% to 80%)
dutyREF
Duty cycle CLK_IN at VCC / 2
4
MHz
ns
SMBus TIMING REQUIREMENTS (see Figure 11)
fSCLK
SCLK frequency
th(START)
START hold time
100
tw(SCLL)
SCLK low-pulse duration
tw(SCLH)
SCLK high-pulse duration
tsu(START)
START setup time
0.6
µs
th(SDATA)
SDATA hold time
0.3
µs
tsu(SDATA)
SDATA setup time
0.25
µs
tr
SCLK / SDATA input rise time
1000
tf
SCLK / SDATA input fall time
300
tsu(STOP)
STOP setup time
tBUS
Bus free time
tPOR
Time in which the device must be operational after power-on reset
µs
4.7
µs
4
50
µs
ns
ns
µs
4
µs
4.7
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kHz
4
500
ms
5
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SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
MIN TYP (1)
MAX
UNIT
All PLLs on, all outputs on,
fOUT = 80 MHz, fCLK_IN = 27 MHz,
f(VCO) = 160 MHz
90
115
mA
fIN = 0 MHz, VCC = 3.6 V
50
µA
2.1
V
PARAMETER
TEST CONDITIONS
OVERALL PARAMETER
(2)
ICC
Supply current
ICCPD
Power down current. Every circuit
powered down except SMBus
V(PUC)
Supply voltage VCC threshold for
power up control circuit
f(VCO)
VCO frequency of internal PLL (any
of three PLLs)
Normal speed-mode (3)
All PLLs
PLL2 with SSC
High-speed mode (3)
LVCMOS output frequency range (4),
See Figure 4
fOUT
80
200
80
167
180
300
MHz
VCC = 2.5 V
250
VCC = 3.3 V
300
VCC = 3 V, II = –18 mA
–1.2
V
±5
µA
5
µA
-10
µA
MHz
LVCMOS PARAMETER
V(IK)
LVCMOS input voltage
II
LVCMOS input current (CLK_IN0 and
VI = 0 V or VCC, VCC = 3.6 V
CLK_IN1)
IIH
LVCMOS input current (S1/S0)
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input current (S1/S0)
VI = 0 V, VCC = 3.6 V
CI
Input capacitance at CLK_IN0 and
CLK_IN1
VI = 0 V or VCC
-35
3
pF
LVCMOS PARAMETER FOR VCCOUT = 3.3-V Mode
VOH
LVCMOS high-level output voltage
VCCOUT = 3 V, IOH = –0.1 mA
2.9
VCCOUT = 3 V, IOH = –4 mA
2.4
VCCOUT = 3 V, IOH = –6 mA
2.1
V
VCCOUT = 3 V, IOL = 0.1 mA
VOL
LVCMOS low-level output voltage
VCCOUT = 3 V, IOL = 4 mA
0.5
VCCOUT = 3 V, IOL = 6 mA
0.85
All PLL bypass
9
V
tPLH,
tPHL
Propagation delay
tr0/tf0
Rise and fall time for output
slew rate 0
VCCOUT = 3.3 V (20%–80%)
1.7
3.3
4.8
ns
tr1/tf1
Rise and fall time for output
slew rate 1
VCCOUT = 3.3 V (20%–80%)
1.5
2.5
3.2
ns
tr2/tf2
Rise and fall time for output
slew rate 2
VCCOUT = 3.3 V (20%–80%)
1.2
1.6
2.1
ns
tr3/tf3
Rise and fall time for output
slew rate 3 (default configuration)
VCCOUT = 3.3 V (20%–80%)
0.4
0.6
1
ns
fOUT = 50 MHz
55
90
fOUT = 245.76 MHz
45
80
125
155
60
95
VCO bypass
1 PLL, 1 Output
tjit(cc)
Cycle-to-cycle jitter
(5) (6)
3 PLLs, 3 Outputs
(1)
(2)
(3)
(4)
(5)
(6)
6
0.1
ns
11
fOUT = 50 MHz
fOUT = 245.76 MHz
ps
All typical values are at respective nominal VCC.
For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using high-speed mode of the VCO reduces
the current consumption. See Figure 3.
Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min f(VCO) can be
lower but impacts jitter-performance.
Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow). See Figure 5
50000 cycles.
Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, f(VCO) = 245.76 MHz.
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DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER
1 PLL, 1 Output
tjit(per)
Peak-to-peak period jitter
(5) (6)
3 PLLs, 3 Outputs
tsk(o)
Output skew (see
(7)
and Table 5)
Output duty cycle (8)
odc
MIN TYP (1)
MAX
fOUT = 50 MHz
60
90
fOUT = 245.76 MHz
55
80
145
180
70
105
TEST CONDITIONS
fOUT = 50 MHz
fOUT = 245.76 MHz
1.6-ns rise/fall time at
f(VCO) = 150 MHz, Pdiv = 3
200
f(VCO) = 100 MHz, Pdiv = 1
45%
UNIT
ps
ps
55%
LVCMOS PARAMETER FOR VCCOUT = 2.5-V Mode (9)
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VCCOUT = 2.3 V, IOH = 0.1 mA
2.2
VCCOUT = 2.3 V, IOH = –3 mA
1.7
VCCOUT = 2.3 V, IOH = –4 mA
1.5
V
VCCOUT = 2.3 V, IOL = 0.1 mA
0.1
VCCOUT = 2.3 V, IOL = 3 mA
0.5
VCCOUT = 2.3 V, IOL = 4 mA
V
0.85
All PLL bypass
9
tPLH,
tPHL
Propagation delay
tr0/tf0
Rise and fall time for output
slew rate 0
VCCOUT = 2.5 V (20%–80%)
2
3.9
5.6
ns
tr1/tf1
Rise and fall time for output
slew rate 1
VCCOUT = 2.5 V (20%–80%)
1.8
2.9
4.4
ns
tr2/tf2
Rise and fall time for output
slew rate 2
VCCOUT = 2.5 V (20%–80%)
1.3
2
3.2
ns
tr3/tf3
Rise and fall time for output
slew rate 3 (default configuration)
VCCOUT = 2.5 V (20%–80%)
0.4
0.8
1.1
ns
fOUT = 50 MHz
60
105
fOUT = 245.76 MHz
50
85
130
160
VCO Bypass
1 PLL, 1 Output
tjit(cc)
Cycle-to-cycle jitter
(10) (11)
3 PLLs, 3 Outputs
1 PLL, 1 Output
tjit(per)
Peak-to-peak period jitter
(10) (11)
3 PLLs, 3 Outputs
tsk(o)
odc
Output skew (see
(12)
and Table 5)
Output duty cycle (13)
ns
11
fOUT = 50 MHz
fOUT = 245.76 MHz
60
95
fOUT = 50 MHz
65
110
fOUT = 245.76 MHz
60
90
145
180
70
105
fOUT = 50 MHz
fOUT = 245.76 MHz
2-ns rise/fall time at
f(VCO) = 150 MHz, Pdiv = 3
f(VCO) = 100 MHz, Pdiv = 1
250
45%
ps
ps
ps
55%
SMBus PARAMETER
VIK
SCLK and SDATA input clamp
voltage
VCC = 3 V, II = –18 mA
II
SCLK and SDATA input current
VI = 0 V or VCC, VCC = 3.6 V
VIH
SCLK input high voltage
VIL
SCLK input low voltage
VOL
SDATA low-level output voltage
(7)
(8)
(9)
(10)
(11)
(12)
(13)
–1.2
V
±5
µA
2.1
IOL = 4 mA, VCC = 3 V
V
0.8
V
0.4
V
The tsk(o) specification is only valid for equal loading of all outputs.
odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off.
T here is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see application report SCAA080.
50000 cycles.
Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, f(VCO) = 245.76 MHz.
The tsk(o) specification is only valid for equal loading of all outputs.
odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off.
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DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER
CI
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
Input capacitance at SCLK
VI = 0 V or VCC
3
10
pF
Input capacitance at SDATA
VI = 0 V or VCC
3
10
pF
PARAMETER MEASUREMENT INFORMATION
CDC706
1k
Yn
LVCMOS
1k
10 pF
Figure 1. Test Load
TYPICAL CHARACTERISTICS
120
110
VCC = 3.3 V,
M div = 1,
N div = 2,
P div = 1,
VCO normal-speed mode
100
90
ICC - [mA]
80
PLL 1 + PLL 2 + PLL3
70
PLL 1 + PLL 2 SSC + PLL3
60
PLL 1 + PLL 2
50
40
PLL 1
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150 160 170 180 190 200 210
fVCO - [MHz]
Figure 2. ICC vs Number of PLLs and VCO Frequency (VCO at Normal-Speed Mode, Byte 6 Bit [7:5])
8
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TYPICAL CHARACTERISTICS (continued)
120
VCC = 3.3 V,
M div = 1,
N div = 2,
P div = 1,
VCO high-speed mode
110
100
90
PLL 1 + PLL 2 + PLL3
ICC - [mA]
80
70
PLL 1 + PLL 2 SSC + PLL3
60
PLL 1 + PLL 2
50
40
PLL 1
30
20
10
0
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
fVCO - [MHz]
Figure 3. ICC vs Number of PLLs and VCO Frequency (VCO at High-Speed Mode, Byte 6 Bit [7:5])
90
85
80
VCC = 3.3 V,
M div = 1,
N div = 2,
P div = 1
75
70
6 Outputs
65
60
5 Outputs
ICC - [mA]
55
50
45
4 Outputs
40
35
3 Outputs
30
25
20
2 Outputs
15
10
5
1 Outputs
0
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
fVCO - [MHz]
Figure 4. ICCOUT vs Number of Outputs and VCO Frequency
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TYPICAL CHARACTERISTICS (continued)
3.6
3.4
3.2
VCC = 3.3 V,
M div = 4,
N div = 15,
P div = 1
3.0
2.8
2.6
VOH at VCCOUT = 3.6 V
2.4
VOUT - [V]
2.2
2.0
1.8
1.6
VOH at VCCOUT = 2.3 V
1.4
1.2
1.0
0.8
0.6
VOL at VCCOUT = 3.6 V
VOL at VCCOUT = 2.3 V
0.4
0.2
0.0
80
100
120
140
160
180
200
220
240
260
280
300
320
fOUT - [MHz]
Figure 5. Output Swing vs Output Frequency
10
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340
360
380
400
420
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APPLICATION INFORMATION
SMBus Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows
the SMBus specification Version 2.0, which is based upon the principals of operation of I2C. More details of the
SMBus specification can be found at http://www.smbus.org.
Through the SMBus, various device functions, such as individual clock output buffers, can be individually
enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting
upon power-up; therefore, using this interface is optional. The clock device register changes are normally made
upon system initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the
controller.
For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte
(most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and
Byte Read operations, the system controller can access individually addressed bytes.
Once a byte has been sent, it is written into the internal register and effective immediately with the rising edge of
the ACK bit. This applies to each transferred byte, independent of whether this is a Byte Write or a Block Write
sequence.
The offset of the indexed byte is encoded in the command code, as described in Table 1.
The Block Write and Block Read protocol is outlined in Figure 9 and Figure 10, while Figure 7 and Figure 8
outlines the corresponding Byte Write and Byte Read protocol.
Slave Receiver Address (7 bits)
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte Offset for Byte Read and Byte Write operation.
For Block Read and Block Write operation, these bits have to be 000 0000.
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1
S
7
Slave Address
1 1
Wr A
S
Start Condition
Sr
Reapeated Start Condition
8
Data Byte
1 1
A P
Rd Read (Bit Value = 1)
Wr Write (Bit Value = 0)
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
PE Packet Error
Master to Slave Transmission
Slave to Master Transmission
Figure 6. Generic Programming Sequence
Byte Write Programming Sequence
1
7
1
S
Slave Address
Wr
1
8
A
CommandCode
1
8
1
1
A
Data Byte
A
P
7
1
1
Slave Address
Rd
A
Figure 7. Byte Write Protocol
Byte Read Programming Sequence
1
7
1
1
S
Slave Address
Wr
A
8
Data Byte
8
1
CommandCode
1
1
A
P
1
A
S
Figure 8. Byte Read Protocol
Block Write Programming Sequence(1)
1
7
1
1
S
Slave Address
Wr
A
8
Data Byte 0
1
8
CommandCode
8
A
Data Byte 1
1
8
A
Byte Count N
1
8
A
-----
(1)Data
Data Byte N–1
1
A
1
1
A
P
Byte 0 is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other
than 0000 0000.
Figure 9. Block Write Protocol
12
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Block Read Programming Sequence
1
7
1
1
S
Slave Address
Wr
A
8
1
CommandCode
8
1
8
Byte Count N
A
Data Byte 0
1
A
Sr
7
1
1
Slave Address
Rd
A
1
A
-----
8
1
1
Data Byte N–1
A
P
Figure 10. Block Read Protocol
P
Bit 7 (MSB)
S
tW(SCLL)
Bit 6
tW(SCLH)
tr(SM)
Bit 0 (LSB)
A
P
tf(SM)
VIH(SM)
SCLK
VIL(SM)
th(START)
tsu(SDATA)
tsu(START)
tsu(STOP)
th(SDATA)
t(BUS)
tf(SM)
tr(SM)
VIH(SM)
SDATA
VIL(SM)
Figure 11. Timing Diagram Serial Control Interface
SMBus Hardware Interface
The following diagram shows how the CDC706 clock synthesizer is connected to the SMBus. Note that the
current through the pullup resistors (Rp) must meet the SMBus specifications (min 100 µA, max 350 µA). If the
CDC706 is not connected to SMBus, the SDATA and SCLK inputs have to be connected with 10 kΩ resistors to
VCC to avoid floating input conditions.
RP
RP
SMB Host
CDC706
9
SDATA
10
SCLK
CBUS
CBUS
Figure 12. SMBus Hardware Interface
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Table 2. Register Configuration Command Bitmap
Adr
Bit 7
Byte 0
Bit 5
Bit 4
Bit 3
Bit 2
Revision Code
PLL1 Reference Divider M 9-Bit [7:0]
Byte 2
PLL1 Feedback Divider N 12-Bit [7:0]
PLL1 Mux
PLL2 Mux
PLL3 Mux
PLL2 Reference Divider M 9-Bit [7:0]
Byte 5
PLL2 Feedback Divider N 12-Bit [7:0]
PLL1 fvco
Selection
PLL2 fvco
Selection
PLL3 fvco
Selection
PLL3 Reference Divider 9-Bit M [7:0]
Byte 8
PLL3 Feedback Divider N [12-Bit 7:0]
Byte 9
PLL Selection for P0 (Switch A)
Byte 10
PLL Selection for P1 (Switch A)
Input Signal Source
Power Down
PLL2 Ref
Dev M [8]
PLL2 Feedback Divider N 12-Bit [11:8]
Byte 7
Byte 11
Bit 0
PLL1 Ref
Dev M [8]
PLL1 Feedback Divider N 12-Bit [11:8]
Byte 4
Byte 6
Bit 1
Vendor Identification
Byte 1
Byte 3
14
Bit 6
PLL3 Ref
Dev M [8]
PLL3 Feedback Divider N 12-Bit [11:8]
Inp. Clock
Selection
Configuration Inputs S1
Configuration Inputs S0
PLL Selection for P3 (Switch A)
PLL Selection for P2 (Switch A)
PLL Selection for P5 (Switch A)
PLL Selection for P4 (Switch A)
Byte 12
Reserved
Byte 13
Reserved
7-Bit Divider P0 [6:0]
Byte 14
Reserved
7-Bit Divider P1 [6:0]
Byte 15
Reserved
7-Bit Divider P2 [6:0]
Byte 16
Reserved
7-Bit Divider P3 [6:0]
Byte 17
Reserved
7-Bit Divider P4 [6:0]
Byte 18
Reserved
7-Bit Divider P5 [6:0]
Byte 19
Reserved
Y0 Inv. or
Non-Inv
Y0 Slew-Rate Control
Y0 Enable or
Low
Y0 Divider Selection (Switch B)
Byte 20
Reserved
Y1 Inv. or
Non-Inv
Y1 Slew-Rate Control
Y1 Enable or
Low
Y1 Divider Selection (Switch B)
Byte 21
Reserved
Y2 Inv. or
Non-Inv
Y2 Slew-Rate Control
Y2 Enable or
Low
Y2 Divider Selection (Switch B)
Byte 22
Reserved
Y3 Inv. or
Non-Inv
Y3 Slew-Rate Control
Y3 Enable or
Low
Y3 Divider Selection (Switch B)
Byte 23
Reserved
Y4 Inv. or
Non-Inv
Y4 Slew-Rate Control
Y4 Enable or
Low
Y4 Divider Selection (Switch B)
Byte 24
Reserved
Y5 Inv or
Non-Inv
Y5 Slew-Rate Control
Y5 Enable or
Low
Y5 Divider Selection (Switch B)
Byte 25
Reserved
Byte 26
Reserved
Spread Spectrum (SSC) Modulation
Selection
Frequency Selection for SSC
7-Bit Byte Count
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Default Device Setting
The CDC706 is pre-programmed with a factory default configuration as shown below. This puts the device in an
operating mode without the need to program it first. The default setting appears after power is switched on or
after a power-down/up sequence until it is re-programmed by the user to a different application configuration. A
new register setting is programmed via the serial SMBUS Interface.
A different default setting can be programmed upon customer request. Contact a Texas Instruments sales or
marketing representative for more information.
fVCO1 = 216 MHz
Output Switch Matrix
PLL1
Divider M
1
PFD
Filter
Divider N
8
14 pF
XO
or
2LVCMOS
or
Differential
Input
P1-Div
20
LV
CMOS
P2-Div
8
LV
CMOS
P3-Div
9
LV
CMOS
P4-Div
32
LV
CMOS
P5-Div
4
LV
CMOS
VCO
Y0
27 MHz
Y1
PLL2
w/ SSC
Divider M
27
Divider N
250
14 pF
CLK_IN1
LV
CMOS
27 MHz
fVCO2 = 250 MHz
CLK_IN0
27 MHz
Crystal
MUX
P0-Div
10
PFD
Filter
VCO
MUX
Y2
27 MHz
Y3
27 MHz
SSC-OFF
SO/CLK_SEL
PROGRAMMING
LOGIC
fVCO3 = 225.792 MHz
S1
SDATA
Y4
PLL3
SMBUS
LOGIC
Divider M
375
27 MHz
PFD
Y5
SCLOCK
Filter
Divider N
3136
MUX
27 MHz
VCO
NOTE: All outputs are enabled and in non-inverting mode. S0, S1, and SSC comply according the default setting described
in Byte 10 and Byte 25 respectively.
Figure 13. Default Device Setting
The output frequency can be calculated:
fin x N , i.e. fout = 27 MHz x 8
fout =
= 27 MHz
M x P
(1 x 8)
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Functional Description of the Logic
All Bytes are read-/write-able, unless otherwise expressly mentioned.
Byte 0 (read only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4] (1)
Revision Code
X
(1)
X
Vendor Identification
X
X
0
0
0
1
Byte 0 is readable by "Byte Read sequency" only.
Byte 1 to 9: Reference Divider M of PLL1, PLL2, PLL3 (1)
Default (2) (3)
M8
M7
M6
M5
M4
M3
M2
M1
M0
Div by
0
0
0
0
0
0
0
0
0
Not allowed
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
1
1
3
•
•
•
1
1
1
1
1
1
1
0
1
509
1
1
1
1
1
1
1
1
0
510
1
1
1
1
1
1
1
1
1
511
By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fvco ≤ 300 MHz.
Unless customer specific setting.
Default setting of divider M for PLL1 = 1, for PLL2 = 27 and for PLL3 = 375.
(1)
(2)
(3)
Byte 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3 (1)
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Div by
0
0
0
0
0
0
0
0
0
0
0
0
Not
allowed
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
0
0
0
1
1
3
Default (2) (3)
•
•
•
(1)
(2)
(3)
1
1
1
1
1
1
1
1
1
1
0
1
4093
1
1
1
1
1
1
1
1
1
1
1
0
4094
1
1
1
1
1
1
1
1
1
1
1
1
4095
By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fvco ≤ 300 MHz.
Unless customer specific setting.
Default setting of divider N for PLL1 = 8, for PLL2 = 250 and for PLL3 = 3136.
Byte 3 Bit [7:5]: PLL (VCO) Bypass Multiplexer
(1)
PLLxMUX
PLL (VCO) MUX Output
Default (1)
0
PLLx
Yes
1
VCO bypass
Unless customer specific setting.
Byte 6 Bit [7:5]: VCO Frequency Selection Mode for each PLL (1)
(1)
(2)
16
PLLxFVCO
VCO Frequency Range
0
80-200 MHz
1
180-300 MHz
Default (2)
Yes
This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2 or PLL3. At power-up, the
high-speed mode is selected, fVCO is 180-300 MHz. In case of higher fVCO, this bit has to be set to [1].
Unless customer specific setting.
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Byte 9 to 12: Outputs Switch Matrix (5x6 Switch A) PLL Selection for P-Divider P0-P5
(1)
(2)
Default (1)
SWAPx2
SWAPx1
SWAPx0
Any Output Px
0
0
0
PLL bypass (input clock)
0
0
1
PLL1
P2, P3, P4, P5
0
1
0
PLL2 non-SSC
P0
SSC (2)
0
1
1
1
0
0
PLL2 w/
PLL3
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
P1
Unless customer specific setting.
PLL2 has a SSC output and non-SSC output. If SSC bypass is selected (see Byte 25, Bit [6:4]), the SSC circuitry of PLL2 is
powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.
Byte 10, Bit [1:0]: Configuration Settings of Input S0/CLK_SEL
(1)
(2)
(3)
Default (1)
S01
S00
Function
0
0
If S0 is low, the PLLs and the clock-input stage are going into power-down mode, outputs are in
3-state, all actual register settings will be maintained, SMBus stays active (2)
0
1
If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power-down,
all outputs are active (inv. or non-inv.), actual register settings will be maintained, SMBus stays
active; this mode is useful for production test;
1
0
CLK_SEL (input clock selection — overwrites the CLK_SEL setting in Byte 10, Bit [4]) (3)
— CLK_SEL is set low selects CLK_IN_IN0
— CLK_SEL is set high selects CLK_IN_IN1
1
1
Reserved
Yes
Unless customer specific setting.
Power-down mode overwrites 3-state or low-state of S1 setting in Byte 10, Bit [3:2].
If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (Byte 11, Bit [7:6]) then this setting is not
relevant.
Byte 10, Bit [3:2]: Configuration Settings of Input S1
(1)
S11
S10
0
0
If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.);
0
1
If S1 is set low, all outputs are switched to a 3-state
1
0
Reserved
1
1
Reserved
Default (1)
Function
Yes
Unless customer specific setting.
Byte 10, Bit [4]: Input Clock Selection (1)
(1)
(2)
CLKSEL
Input Clock
Default (2)
0
CLK_IN0
Yes
1
CLK_IN1
This bit is not relevant, if crystal input or differential clock input is selected, Byte 11, Bit [7:6].
Unless customer specific setting.
Byte 11, Bit [7:6]: Input Signal Source (1)
(1)
(2)
IS1
IS0
Function
0
0
CLK_IN0 is Crystal Oscillator Input and CLK_IN1 is serving as Crystal Oscillator Output.
0
1
CLK_IN0 and CLK_IN1 are two LVCMOS Inputs. CLK_IN0 or CLK_IN1 are selectable via
CLK_SEL control pin.
1
0
CLK_IN0 and CLK_IN1 serve as differential signal inputs.
1
1
Reserved
Default (2)
Yes
In case the crystal input or differential clock input is selected, the input clock selection, Byte 10, Bit [4], is not relevant.
Unless customer specific setting.
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Byte 12, Bit [6]: Power-Down Mode (except SMBus)
(1)
(2)
PD
Power-Down Mode
Default (1)
0
Normal Device Operation
Yes
1
Power Down (2)
Unless customer specific setting.
In power down, all PLLs and the Clock-Input-Stage are going into power-down mode, all outputs are in 3-State, all actual register
settings will be maintained and SMBus stays active. Power-Down Mode overwrites 3-State or Low-State of S0 and S1 setting in Byte 10.
Byte 13 to 18, Bit [6:0]: Outputs Switch Matrix - 6x7-Bit Divider P0-P5
DIVYx6
DIVYx5
DIVYx4
DIVYx3
DIVYx2
DIVYx1
DIVYx0
Div by
0
0
0
0
0
0
0
Not allowed
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
Default (1) (2)
•
•
•
(1)
(2)
1
1
1
1
1
0
1
125
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
Unless customer specific setting.
Default setting of divider P0 = 10, P1 = 20, P2 = 8, P3 = 9, P4 = 32, and P5 = 4
Byte 19 to 24, Bit [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0-Y5
(1)
SRCYx1
SRCYx0
Yx
0
0
Nominal +3 ns (tr0/tf0)
0
1
Nominal +2 ns (tr1/tf1)
1
0
Nominal +1 ns (tr2/tf2)
1
1
Nominal (tr3/tf3)
Default (1)
Yes
Unless customer specific setting.
Byte 19 to 24, Bit [2:0]: Outputs Switch Matrix (6 x 6 Switch B) Divider (P0-P5) Selection for Outputs Y0-Y5
(1)
SWBYx2
SWBYx1
SWBYx0
Any Output Yx
0
0
0
Divider P0
0
0
1
Divider P1
0
1
0
Divider P2
0
1
1
Divider P3
1
0
0
Divider P4
1
0
1
Divider P5
1
1
0
Reserved
1
1
1
Reserved
Default (1)
Y0, Y1, Y2, Y3, Y4, Y5
Unless customer specific setting.
Byte 19 to 24, Bit [3]: Output Y0-Y5 Enable or Low-State
(1)
Default (1)
ENDISYx
Output Yx
0
Disable to low
1
Enable
Yes
INVYx
Output Yx Status
Default (1)
0
Non-inverting
Yes
1
Inverting
Unless customer specific setting.
Byte 19 to 24, Bit [6]: Output Y0-Y5 Non-Inverting/Inverting
(1)
18
Unless customer specific setting.
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Byte 25, Bit [3:0]: SSC Modulation Frequency Selection in the Range of 30 kHz 60
kHz (1)
fvco (MHz)
FSSC3
FSSC2
FSSC1
FSSC0
Modulation
Factor
100
110
120
130
140
150
160
167
0
0
0
0
5680
17.6
19.4
21.1
22.9
24.6
26.4
28.2
29.4
0
0
0
1
5412
18.5
20.3
22.2
24.0
25.9
27.7
29.6
30.9
0
0
1
0
5144
19.4
21.4
23.3
25.3
27.2
29.2
31.1
32.5
0
0
1
1
4876
20.5
22.6
24.6
26.7
28.7
30.8
32.8
34.2
0
1
0
0
4608
21.7
23.9
26.0
28.2
30.4
32.6
34.7
36.2
0
1
0
1
4340
23.0
25.3
27.6
30.0
32.3
34.6
36.9
38.5
0
1
1
0
4072
24.6
27.0
29.5
31.9
34.4
36.8
39.3
41.0
0
1
1
1
3804
26.3
28.9
31.5
34.2
36.8
39.4
42.1
43.9
1
0
0
0
3536
28.3
31.1
33.9
36.8
39.6
42.4
45.2
47.2
1
0
0
1
3286
30.4
33.5
36.5
39.6
42.6
45.6
48.7
50.8
1
0
1
0
3000
33.3
36.7
40.0
43.3
46.7
50.0
53.3
55.7
1
0
1
1
2732
36.6
40.3
43.9
47.6
51.2
54.9
58.6
61.1
1
1
0
0
2464
40.6
44.6
48.7
52.8
56.8
60.9
64.9
67.8
1
1
0
1
2196
45.5
50.1
54.6
59.2
63.8
68.3
72.9
76.0
1
1
1
0
1928
51.9
57.1
62.2
67.4
72.6
77.8
83.0
86.6
1
1
1
1
1660
60.2
66.3
72.3
78.3
84.3
90.4
96.4
100.6
(1)
(2)
fmod
[kHz]
Default (2)
Yes
The PLL has to be bypassed (turned off) when changing SSC Modulation Frequency Factor on-the-fly. This can be done by following
programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Factor (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).
Unless customer specific setting.
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(1)
Byte 25, Bit [6:4]: SSC Modulation Amount
SSC2
(1)
(2)
(3)
SSC1
SSC0
Default (2)
Function
PLL (3)
0
0
0
SSC Modulation Amount 0% = SSC bypass for
0
0
1
SSC Modulation Amount ±0.1% (center spread)
0
1
0
SSC Modulation Amount ±0.25% (center spread)
0
1
1
SSC Modulation Amount ±0.4% (center spread)
1
0
0
SSC Modulation Amount 1% (down spread)
1
0
1
SSC Modulation Amount 1.5% (down spread)
1
1
0
SSC Modulation Amount 2% (down spread)
1
1
1
SSC Modulation Amount 3% (down spread)
Yes
The PLL has to be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by following
programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Amount (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).
Unless customer specific setting.
If SSC bypass is selected, SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of
PLL2 is not affected by this mode and can still be used.
Byte 26, Bit [6:0]: Byte Count (1)
BC6
BC5
BC4
BC3
BC2
BC1
BC0
No. of Bytes
0
0
0
0
0
0
0
Not allowed
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
0
1
1
27
Default (2)
•
•
•
0
0
1
1
•
•
•
(1)
(2)
20
1
1
1
1
1
0
1
125
1
1
1
1
1
1
0
126
1
1
1
1
1
1
1
127
Defines the number of Bytes, which will be sent from this device at the next Block Read protocol.
Unless customer specific setting.
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FUNCTIONAL DESCRIPTION
Clock Inputs (CLK_IN0 and CLK_IN1)
The CDC706 features two clock inputs which can be used as:
• Crystal oscillator input (default setting)
• Two independent single-ended LVCMOS inputs
• Differential signal input
The dedicated clock input can be selected by the input signal source Bit [7:6] of Byte 11.
Crystal Oscillator Inputs
The input frequency range in crystal mode is 8 MHz to 54 MHz. The CDC706 uses a Pierce-type oscillator
circuitry with included feedback resistance for the inverting amplifier. The user, however, has to add external
capacitors CX0, CX1) to match the input load capacitor from the crystal (see Figure 14). The required values can
be calculated:
CX0 = CX1 = 2 x CL– CICB,
where CL is the crystal load capacitor as specified for the crystal unit and CICB is the input capacitance of the
device including the board capacitance (stray capacitance of PCB).
For example, for a fundamental 27-MHz crystal with CL of 9 pF and CICB of 4 pF,
CX0 = CX1 = (2 x 9 pF) – 3 pF = 15 pF.
It is important to use a short PCB trace from the device to the crystal unit to keep the stray capacitance of the
oscillator loop to a minimum.
CLK_IN0
CX0
crystal
unit
CLK_IN1
Input source select
(from SMBUS Register)
CICB
CICB
XO
or
2LVCMOS
or
Differential
Input
CX1
Figure 14. Crystal Input Circuitry
In order to ensure a stable oscillating, a certain drive power must be applied. The CDC706 features an input
oscillator with adaptive gain control which relieves the user to manually program the gain. The drive level is the
amount of power dissipated by the oscillating crystal unit and is usually specified in terms of power dissipated by
the resonator (equivalent series resistance (ESR)). Figure 15 gives the resulting drive level vs crystal frequency
and ESR.
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100
C = 18 pF
Upk = 300 mV
90
ERS
ERS
ERS
ERS
ERS
ERS
80
Pdrive − mW
70
=
=
=
=
=
=
60
50
40
30
25
15
W
W
W
W
W
W
60
50
40
30
~21 mW
20
10
0
5
10
15
20
25
30
35
40
45
50
55
Frequency − MHz
Figure 15. Crystal Drive Power
For example, if a 27-MHz crystal with ESR of 50 Ω is used and 2 x CL is 18 pF, the drive power is 21 µW. Drive
level should be held to a minimum to avoid over driving the crystal. The maximum power dissipation is specified
for each type of crystal in the oscillator specifications, i.e., 100 µW for the example above.
Single-Ended LVCMOS Clock Inputs
When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock inputs pins and can be
driven up to 200 MHz. Both clock inputs circuitry are equal in design and can be used independently to each
other (see Figure 16). The internal clock select bit, Byte 10, Bit [4], selects one of the two input clocks. CLK_IN0
is the default selection. There is also the option to program the external control pin S0/CLK_SEL as clock select
pin, Byte 10, Bit [1:0].
The two clock inputs can be used for redundancy switching, i.e. to switch between a primary clock and
secondary clock. Note a phase difference between the clock inputs may require PLL correction. Also in case of
different frequencies between the primary and secondary clock, the PLL has to re-lock to the new frequency.
Input Source Select
(From SMBUS Register)
CLK_IN0
CLK_IN1
XO
or
2LVCMOS
or
Differential
input
CLK_SEL (A)
A.
CLK_SEL is optional and can be configured by SMBUS setting.
Figure 16. LVCMOS Clock Input Circuitry
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Differential Clock Inputs
The CDC706 supports differential signaling as well. In this mode, CLK_IN0 and CLK_IN1 pin serve as
differential signal inputs and can be driven up to 200 MHz.
The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode input
voltage range of 200 mV to VCC– 0.6. If LVDS or LVPECL signal levels are applied, ac-coupling and a biasing
structure is recommended to adjust the different physical layers (see Figure 17). The capacitor removes the dc
component of the signal (common-mode voltage), while the ac component (voltage swing) is passed on. A
resistor pull-up and/or pull-down network represents the biasing structure used to set the common-mode voltage
on the receiver side of the ac-coupling capacitor. DC coupling is also possible.
Input source select
(from SMBUS)
CLK_IN0
XO
or
2LVCMOS
or
Differential
input
CLK_IN1
Figure 17. Differential Clock Input Circuitry
PLL Configuration and Setting
The CDC706 includes three PLLs which are equal in function and performance. Except PLL2 which in addition
supports spread spectrum clocking (SSC) generation. Figure 18 shows the block diagram of the PLL.
VCO Bypass
PLLx
Input Clock
9−Bit Divider M
1 .. 511
12−Bit Divider N
1 .. 4095
PFD
Filter
VCO
MUX
SSC
(PLL2 only)
PLL output
SSC output
(PLL2 Only)
Programming
Figure 18. PLL Architecture
All three PLLs are designed for easiest configuration. The user just has to define the input and output
frequencies or the divider (M, N, P) setting respectively. All other parameters, such as charge-pump current,
filter components, phase margin, or loop bandwidth are controlled and set by the device itself. This assures
optimized jitter attenuation and loop stability.
The PLL support normal-speed mode (80 MHz ≤ fVCO ≤ 200 MHz) and high-speed mode (180 MHz ≤ fVCO ≤ 300
MHz) which can be selected by PLLxFVCO (Bit [7:5] of Byte 6). The respective speed option assures stable
operation and lowest jitter.
The divider M and divider N operates internally as fractional divider for fVCO up to 250 MHz. This allows fractional
divider ratio for zero ppm output clock error.
In case of fVCO > 250 MHz, it is recommended that integer factors of N/M are used only.
For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept
requires a PLL divider configuration, M ≤ N (or N/M ≥ 1).
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Additionally, each PLL supports two bypass options:
• PLL Bypass and
• VCO Bypass
In PLL bypass mode, the PLL completely is bypassed, so that the input clock is switched directly to the
Output-Switch-A (SWAPxx of Byte 9 to 12). In the VCO bypass mode, only the VCO of the respective PLL is
bypassed by setting PLLxMUX to 1 (Bit [7:5] of Byte 3). But the divider M still is useable and expands the output
divider by additional 9-bits. This gives a total divider range of M x P = 511 x 127 = 64897. In VCO bypass mode
the respective PLL block is powered down and minimizes current consumption.
Table 3. Example for Divide, Multiplication, and Bypass Operation
Equation (1)
fIN
[MHz]
fOUT-desired
[MHz]
fOUT-actual
[MHz]
Fractional (2)
fOUT = fIN x (N/M)/P
30.72
155.52
Integer Factor (3)
fOUT = fIN x (N/M)/P
27
270
fOUT = fIN/(M x P)
30.72
0.06
Function
VCO bypass
(1)
(2)
(3)
Divider
fVCO [MHz]
M
N
P
N/M
155.52
16
81
1
5.0625
155.52
270
1
10
1
10
270
0.06
8
—
64
—
—
P-divider of Output-Switch-Matrix is included in the calculation.
Fractional operation for fVCO≤ 250 MHz.
Integer operation for fVCO > 250 MHz.
Spread Spectrum Clocking and EMI Reduction
In addition to the basic PLL function, PLL2 supports spread spectrum clocking (SSC) as well. Thus, PLL 2
features two outputs, a SSC output and a non-SSC output. Both outputs can be used in parallel. The mean
phase of the Center Spread SSC modulated signal is equal to the phase of the non-modulated input frequency.
SSC is selected by Output-Switch-A (SWAPxx of Byte 9 to 12).
SSC also is bypass-able (Byte 25, Bit [6:4]), which powers-down the SSC output and set it to logic low state.
The non-SSC output of PLL2 is not affected by this mode and can still be used.
SSC is an effective method to reduce electro-magnetic interference (EMI) noise in high-speed applications. It
reduces the RF energy peak of the clock signal by modulating the frequency and spread the energy of the signal
to a broader frequency range. Because the energy of the clock signal remains constant, a varying frequency that
broadens the overtones necessarily lowers their amplitudes. Figure 19 shows the effect of SSC on a 54-MHz
clock signal for DSP
Down Spread 3%
9th Harmonic, fm = 60 kHz
11.3dB
11.3 dB
Center Spread + 0.4%
9th Harmonic, fm = 60 kHz
7 dB
7dB
Figure 19. Spread Spectrum Clocking With Center Spread and Down Spread
The peak amplitude of the modulated clock is 11.3 dB lower than the non-modulated carrier frequency for down
spread and radiated less electro-magnetic energy.
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In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulation
amount is the frequency deviation based to the carrier (min/max frequency), whereas the modulation frequency
determines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to 167
MHz.
SSC Modulation Amount
The CDC706 supports center spread modulation and down spread modulation. In center spread, the clock is
symmetrically shifted around the carrier frequency and can be ±0.1%, ±0.25%, and ±0.4%. At down spread, the
clock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, and 3%. The down spread
is preferred if a system can not tolerate an operating frequency higher than the nominal frequency (over-clocking
problem).
Example:
Modulation Type
Minimum
Frequency
Center
Frequency
Maximum
Frequency
54 MHz
54.135 MHz
A
±0.25% center spread
53.865 MHz
B
1% down spread
53.46 MHz
—
54 MHz
C
0.5% down spread (1)
53.73 MHz
53.865 MHz
54 MHz
(1)
A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of ±0.25%.
SSC Modulation Frequency
The modulation frequency (sweep rate) can be selected between 30 kHz and 60 kHz. It is also based on the
VCO frequency as shown in the SSC Modulation Frequency Selection. As shown in Figure 20, the damping
increases with higher modulation frequencies. It may be limited by the tracking skew of a downstream PLL. The
CDC706 uses a triangle modulation profile which is one of the common profiles for SSC.
12
3% Down Spread
EMI Reduction− dB
11
2% Down Spread
10
9
8
+0.4 Center Spread
7
6
+0.25 Center Spread
5
4
3
30
40
50
60
fmodulation − kHz
Figure 20. EMI Reduction vs fModulation and fAmount
Further EMI Reduction
The optimum damping is a combination of modulation amount, modulation frequency and the harmonics which
are considered. Note that higher order harmonic frequencies results in stronger EMI reduction because of
respective higher frequency deviation.
As seen in Figure 21 and Figure 22, a slower output slew rate and/or smaller output signal amplitude helps to
reduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDC706 allows
slew rate control in four steps between 0.6 ns and 3.3 ns (Byte 19-24, Bit [5:4]). The output amplitude is set by
the two independent output supply voltage pins, VCCOUT1 and VCCOUT2, and can vary from 2.3 V to 3.6 V. Even a
lower output supply voltage down to 1.8 V works, but the maximum frequency has to be considered.
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Slew-Rate for VCCOUT = 2.5 V
Slew-Rate for VCCOUT = 3.3 V
−2.5dB
−3dB
6.4dB
5.6dB
7dB
11.3dB
nom−1
nom−1
nom
nom
nom+2
nom+2
Figure 21. EMI Reduction vs Slew-Rate and Vccout
5
EMI Reduction − dB
(Relative to Nom)
4
3
2
1
0
−1
2.5 V
3V
3.6 V
VCCOUT
Figure 22. EMI Reduction vs Vccout
Multi-Function Control Inputs S0 and S1
The CDC706 features two user definable inputs pins which can be used as external control pins or address pins.
When programmed as control pins, they can function as clock select pin, enable/disable pin or device
power-down pin. If both pins used as address-bits, up to four devices can be connected to the same SMBus.
The respective function is set in Byte 10; Bit [3:0]. Table 4 shows the possible setting for the different output
conditions, clock select and device addresses.
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Table 4. Configuration Setting of Control Inputs
Configuration Bits
Byte 10,
Bit [3:2]
External Control Pins
S11
S10
S01
S00
S1
(Pin 2)
S0
(Pin 1)
0
X
0
X
1
0
0
0
X
0
0
1
0
X
0
X
0
0
X
0
X
(1)
(2)
Device Function
Byte 10,
Bit [1:0]
Yx Outputs
Power
Down
Pin 2
Pin 1
1
Active
No
Output ctrl
Output ctrl
1
Low/High (1)
No
Output ctrl
Output ctrl
0
1
3-State
Outputs only
Output ctrl
Output ctrl
0
X
0
3-State
PLL, inputs and outputs
Output ctrl
Output ctrl and pd
0
1
0
0
S10=0: low/high (1)
S10=1: 3-State
PLL only
Output ctrl
PLL and Div bypass
0
1
1
0
Active
PLL only
Output ctrl
PLL and Div bypass
No
Output ctrl
CLK_SEL
No
Output ctrl
CLK_SEL
0
X
1
0
0
0/1 (2)
S10=0: Low/High (1)
S10=1: 3-State
0
X
1
0
1
0/1 (2)
Active
A non-inverting output will be set to low and an inverting output will be set to high.
If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.
As shown in Table 4, there is a specific order of the different output condition: Power-down mode overwrites
3-state, 3-state overwrites low-state, and low-state overwrites active-state.
Output Switching Matrix
The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal
sources via a free-selectable post-divider to any of the six outputs.
As shown in Figure 23, the CDC706 is based on two banks of switches and six post-dividers. Switch A
comprises six 5-Input-Muxes which selects one of the four PLL clock outputs or directly selects the input clock
and feed it to one of the 7-bit post-divider (P-Divider). Switch B is made up of six 6-Input-Muxes which takes any
post-divider and feeds it to one of the six outputs, Yx.
Switch B was added to the output switch matrix to ensure that outputs frequencies derive from one P-divider are
100% phase aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle
corrected. Changing the divider value on the fly may cause a glitch on the output.
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Internal Clock Sources
Output Switch Matrix
5x6 − Switch A
7-Bit Divider
Outputs
6x6 − Switch B
P0
Y0
(1..127)
Input CLK
P1
(PLL Bypass)
Y1
(1..127)
PLL 1
P2
Y2
(1..127)
PLL 2
non SSC
P3
Y3
(1..127)
P4
PLL 2
w/ SSC
Y4
(1..127)
P5
Y5
(1..127)
PLL 3
Programming
PLL/Input_Clk
Selection
P-Divider
Setting
P-Divider
Selection
Output Selection:
Active/Low/3-State/
Inverting/Non-Inverting
Slew Rate/VCCOUT
Figure 23. CDC706 Output Switch Matrix
In addition, the outputs can be switched active, low or 3-state and/or 180 degree phase shifted. Also the outputs
slew-rate and the output-voltage is user selectable.
LVCMOS Output Configuration
The output stage of the CDC706 supports all common output setting, such as enable, disable, low-state and
signal inversion (180 degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variable
output supply voltage (2.3 V to 3.6 V).
Clock
VCCOUT1/VCCOUT2
P−div(0)
P−div(1)
P−div(2)
P−div(3)
P−div(4)
P−div(5)
output
output
output
output
output
output
P−Divider Select
Inversion Select
Slew-Rate Control
Low Select
Enable/Disable
div by 3
M
U
X
Sel
Buffer
Yx
Inverting
Slew Rate
S1
(Optional all
outputs low
or 3−State)
Low Select
Enable/Disable
Figure 24. Block Diagram of Output Architecture
All
•
•
•
•
•
28
Figure 25. Example for Output Waveforms
output settings are programmable via SMBus:
enable, disable, low-state via external control pins S0 and S1 → Byte 10, Bit[3:0]
enable or disable-to-low → Byte 19 to 24, Bit[3]
inverting/non-inverting → Byte 19 to 24, Bit[6]
slew-rate control → Byte 19 to 24, Bit[5:4]
output swing → external pins VCCOUT1 (Pin 14) and VCCOUT2 (Pin 18)
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Performance Data: Output Skew, Jitter, Cross Coupling, Noise Rejection (Spur-Suppression),
and Phase Noise
Output Skew
Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs
that are driven by the same input clock. Table 5 shows the output skew (tsk(o)) of the CDC706 for high-to-low and
low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage swing.
Table 5. Output Skew
PARAMETER
tsk(o)
Vccout
TYP
MAX
UNIT
2.5 V
130
250
ps
3.3 V
130
200
ps
Jitter Performance
Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and
timing budget decreases. The PLL and internal circuits of CDC706 are designed for lowest jitter. The
peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of
cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.
Table 6. Jitter Performance of CDC706
PARAMETER
tjit(cc)
tjit(per)
tjit(phase)
(1)
TYP (1)
fout
MAX (1)
UNIT
Peak-Peak
rms
(one sigma)
Peak-Peak
rms
(one sigma)
50 MHz
55
–
75
–
133 MHz
50
–
85
–
245.76 MHz
45
–
60
–
50 MHz
60
4
76
7
133 MHz
55
5
84
11
245.76 MHz
55
5
72
8
50 MHz
730
90
840
115
133 MHz
930
130
1310
175
245.76 MHz
720
90
930
125
ps
ps
ps
All typical and maximum values are at VCC = 3.3 V, temperature = 25°C, Vccout = 3.3 V; one output is switching, data taken over several
10000 cycles.
Figure 26, Figure 27, and Figure 28 show the relationship between cycle-to-cycle jitter, period jitter, and phase
jitter over 10000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and
period jitter show the measured value whereas the phase jitter is the accumulated period jitter.
Cycle-to-Cycle jitter (tjit(cc)) is the variation in cycle time of a clock signal between adjacent cycles, over a random
sample of adjacent cycle pairs. Cycle-to-cycle jitter will never be greater than the period jitter. It is also known as
adjacent cycle jitter.
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40
30
20
tjit(cc) [ps]
10
0
−10
−20
−30
−40
1
1001
2001
3001
4001
5001
Cycle
6001
7001
8001
9001
10001
Figure 26. Snapshot of Cycle-to-Cycle Jitter
Period jitter (tjit(per)) is the deviation in cycle time of a clock signal with respect to the ideal period (1/fo) over a
random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal
that would ever occur on the PLLs outputs. This is also referred to as short-term jitter.
25
20
15
tjit(per) [ps]
10
5
0
−5
−10
−15
−20
−25
1
1001
2001
3001
4001
5001
6001
7001
Cycle
Figure 27. Snapshot of Period Jitter
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Phase jitter (tjit(phase)) is the long-term variation of the clock signal. It is the cumulative deviation in t(Θ) for a
controlled edge with respect to a t(Θ) mean in a random sample of cycles. Phase jitter, Time Interval Error (TIE),
or Wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is
defined as phase variation at rates less than 10 Hz while jitter is defined as phase variation greater than 10 Hz.
The measurement interval must be long enough to gain a meaningful result. Wander can be caused by
temperature drift, aging, supply voltage drift, etc.
300
250
200
150
tjit(phase) [ps]
100
50
0
−50
−100
−150
−200
−250
−300
1
1001
2001
3001
4001
5001
Cycle
6001
7001
8001
9001
10001
Figure 28. Snapshot of Phase Jitter
Jitter depends on the VCO frequency (fVCO) of the PLL. A higher fVCO results in better jitter performance
compared to a lower fVCO. The VCO frequency can be defined via the M- and N-divider of the PLL
As the CDC706 supports a pretty wide frequency range, the device offers a VCO Frequency Selection Bit, Bit
[7:5] of Byte 6. This bit defines the jitter-optimized frequency range of each PLL. The user can select between
the normal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure 29
shows the jitter performance over fVCO for the two frequency ranges.
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300
280
o
TA = 25 C,
VCC = 3.3 V,
M div = 4,
N div = 15,
P div = 3
260
240
220
tjit(per)p-p − ps
200
180
fVCO Frequency Range
for Normal-Speed Mode
160
fVCO Frequency Range
for High-Speed Mode
140
120
High-Speed Mode
>180 MHz
100
80
60
40
Normal-Speed Mode
< 200 MHz
20
0
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
320
340
360
fVCO − MHz Set Point
Figure 29. Period Jitter vs fVCO for Normal-Speed Mode and High-Speed Mode
The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.
Cross Coupling, Spur Suppression and Noise Rejection
Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output
stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)
induced by output switching, leakage current, ground bouncing, power supply transients, etc.
The CDC706 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology.
This process gives excellent performance in linearity, low power consumption, best-in-class noise performance
and very good isolation characteristic between the on-chip components.
The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all
three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 30 and
Figure 31 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDC706.
Die respective measurement conditions are shown in Figure 30 and Figure 31.
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Figure 30. Noise Coupling and Spur Suppression
56 dB
w Measured Y0: 48 MHz
w Y1, Y2, Y3, Y4 & Y5 tri−stated
w Inserted 30mV 1MHz @ Vcc = 3.3V
carrier
48MHz
carrier
48MHz
spurs at
47MHz&49MHz
spur 47MHz and
fundamental at 1MHz
Figure 31. Power Supply Noise Rejection
Phase Noise Characteristic
In high-speed communication systems, the phase noise characteristic of the PLL frequency synthesizer is of
high interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter
specification in the time domain.
Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete
spurious components could be caused by known clock frequencies in the signal source, power line interference,
and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the
result of thermal noise, shot noise and/or flicker noise in active and passive devices.
Important factor for PLL synthesizer is the loop bandwidth (–3 dB cut-off frequency) — large loop bandwidth
(LBW) results in fast transient response but have less reference spur attenuation. The LBW of the CDC706 is
about 100 kHz to 250 kHz, dependent on selected PLL parameter.
For the CDC706, two phase noise characteristics are of interest: The phase noise of the crystal-input stage and
the phase noise of the internal PLL (VCO). Figure 32 shows the respective phase noise characteristic.
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−50
Phase Noise Comparison
−60
fOUT 135 MHz
fVCO 135 MHz vs 270 MHz
−70
CDC706 fOUT 135 MHz
fVCO 135 MHz
dBc/Hz
−80
CDC706 fOUT 135 MHz
fVCO 270 MHz
−90
−100
−110
−120
−130
−140
−150
1.0E+01
CDC706 Cyrstal 27 MHz Input
27 MHz Buffered Output
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
foffset - [Hz]
Figure 32. Phase Noise Characteristic - foffset - Hz
PLL Lock-Time
Some applications use frequency switching, i.e. to change frequency in TV application (switching between
channels) or change the PCI-X frequency in computers. The time spent by the PLL in achieving the new
frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another
specified frequency within a given frequency tolerance (see Figure 33). It should be low, because a long lock
time impacts the data rate of the system.
The PLL-Lock-Time depends on the device configuration and can be changed by the VCO frequency, i.e. by
changing the M/N divider values. Table 7 gives the typical lock times of the CDC706 and Figure 33 shows a
snapshot of a frequency switch.
Table 7. CDC706 PLL Lock-Times
Description
Lock Time
Unit
Frequency change via reprogramming of N/M counter
100
µs
Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1)
100
µs
Power-up lock time with system clock
50
µs
300 (1)
µs
Power-up lock time with 27 MHz Crystal at CLK_IN0 and CLK_IN1
(1)
34
Is the result of Crystal lock time (200 µs) and PLL lock time (100 µs).
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CDC706
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SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
fVCO (MHz)
Start Condition:
Acknowledge of
N-Divider Byte
Frequency
Response
Curve of Y0
297
EVM Board Configuration:
• Y0 (PLL1), Y1 3 state
• CLK_IN: Crystal 27 MHz
• measured Channel: Y0
Measurement:
• Start Condition: ƒ(M = 10, N = 30) = 81 MHz
• Byte 2 write: N = 30 (81 MHz) ³ N = 110 (297 MHz)
Result:
• 60 ms to PLL Pull In
• 90 ms to PLL Phase Lock
81
60
0
t [ms]
20 ms/div
Figure 33. Snapshot of the PLL Lock-Time
Power Supply Sequencing
The CDC706 includes three power supply pins, VCC, VCCOUT1, and VCCOUT2. There are no power supply
sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied
in any order to the three nodes.
Also, the part has a power-up circuitry which switches the device on if VCC exceeds 2.1 V (typical) and switches
the device off at VCC < 1.7 V (typical). In power-down mode, all outputs and clock inputs are switched off.
Device Behavior During Supply Voltage Drops
The CDC706 has a Power-Up-Circuit, which activates the device function at VPUC_ON (typical 2.1 V). At the same
time, the ROM information is loaded into the register. This mechanism ensures that there is a pre-defined default
after Power-Up and no need to reprogram the CDC706 in the application.
In the event of a supply-voltage-drop, the Power-Up-Circuit assures that there is always a defined setup within
the register. Figure 34 shows possible voltage drops with different amplitudes.
V
VCC
Typ 3.3 V
A
VPUC_ON
Typ 2.1 V
VPUC_OFF
Typ 1.7 V
B
C
D
GND
t
Figure 34. Different Voltage Drops on VCC During Operation
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35
CDC706
www.ti.com
SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
The CDC706 Power-Up-Circuit has an inbuilt hysteresis. If the voltage stays above VPUC_OFF, which is typically
at 1.7 V, the register content stays unchanged. If the voltage drops below VPUC_OFF, the internal register is
reloaded by the ROM after VPUC_ON is crossed again. VPUC_ON is typically 2.1 V. Table 8 show the content of the
ROM and the Register after above voltage drops scenarios.
Table 8. ROM and Register Content After VCC Drop
Power Drop
ROM Content
Register Content
A
Unchanged
Unchanged
B
Unchanged
Unchanged
C
Unchanged
Reloaded from ROM
D
Unchanged
Reloaded from ROM
EVM and Programming SW
The CDC706 EVM is a development kit consisting of a performance evaluation module, the TI Pro Clock
software, and the User's Guide. Contact Texas Instruments sales or marketing representative for more
information.
36
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDC706PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC706PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC706PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC706PWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
CDC706PWR
17-May-2007
Package Pins
PW
20
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
MLA
330
16
6.95
7.1
1.6
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CDC706PWR
PW
20
MLA
342.9
336.6
28.58
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
16
PKGORN
T1TR-MS
P
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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