Cypress CY8C4125AXI-M445 Programmable system-on-chip Datasheet

PSoC® 4: PSoC 4100M Family
Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4100M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic,
programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode,
and standard communication and timing peripherals. The PSoC 4100M products will be fully compatible with members of the PSoC 4
platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning
of the design.
Features
32-bit MCU Subsystem
Serial Communication
■
24-MHz ARM Cortex-M0 CPU with single-cycle multiply
■
Up to 128 kB of flash with Read Accelerator
■
Up to 16 kB of SRAM
■
DMA engine
Four independent run-time reconfigurable serial
communication blocks (SCBs) with reconfigurable I2C, SPI, or
UART functionality
Timing and Pulse-Width Modulation
Programmable Analog
■
Four opamps that operate in Deep Sleep mode at very low
current levels
■
All opamps have reconfigurable high current pin-drive,
high-bandwidth internal drive, ADC input buffering, and
Comparator modes with flexible connectivity allowing input
connections to any pin
■
Four current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep mode
■
12-bit SAR ADC with 806-Ksps conversion rate
Low Power 1.71 to 5.5 V Operation
■
20-nA Stop Mode with GPIO pin wakeup
■
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
■
Eight 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Package Options
■
68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin
and 44-pin TQFP packages
■
Up to 55 programmable GPIOs
■
GPIO pins can be CapSense, LCD, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Extended Industrial Temperature Operation
■
–40 °C to +105 °C operation
PSoC Creator Design Environment
■
Cypress Capacitive Sigma-Delta (CSD) technique provides
best-in-class SNR (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■
Applications Programming Interface (API component) for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■
LCD drive supported on all pins (common or segment)
■
Operates in Deep Sleep mode with 4 bits per pin memory
Cypress Semiconductor Corporation
Document Number: 001-96519 Rev. *E
■
•
■
198 Champion Court
After schematic entry, development can be done with
ARM-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 19, 2016
PSoC® 4: PSoC 4100M Family
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■
■
■
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
❐ AN73854: Introduction To Bootloaders
❐ AN89610: ARM Cortex Code Optimization
■
Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
Development Kits:
❐ CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
❐ CY8CKIT-049 is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐ CY8CKIT-001 is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The MiniProg3 device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Document Number: 001-96519 Rev. *E
Page 2 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Contents
PSoC 4100M Block Diagram............................................ 4
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Fixed Function Digital.................................................. 7
GPIO ........................................................................... 8
Special Function Peripherals....................................... 8
Pinouts .............................................................................. 9
Power............................................................................... 13
Unregulated External Supply..................................... 13
Regulated External Supply........................................ 13
Development Support .................................................... 14
Documentation .......................................................... 14
Online ........................................................................ 14
Tools.......................................................................... 14
Electrical Specifications ................................................ 15
Absolute Maximum Ratings....................................... 15
Device Level Specifications....................................... 15
Document Number: 001-96519 Rev. *E
Analog Peripherals ....................................................
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Part Numbering Conventions ....................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Page 3 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
PSoC 4100M Block Diagram
CPU Subsystem
PSoC4100M
32-bit
AHB-Lite
SWD/TC
SPCIF
Cortex M0
24 MHz
FLASH
128 KB
SRAM
16 KB
ROM
8 KB
DataWire/
DMA
FAST MUL
NVIC, IRQMX
Read Accelerator
SRAM Controller
ROM Controller
Initiator/MMIO
System Resources
Test
DFT Logic
DFT Analog
SMX
CTBm
x2
2x OpAmp
WCO
2x LP Comparator
x1
LCD
SAR ADC
(12-bit)
4x SCB-I2C/SPI/UART
Programmable
Analog
2x Capsense
Reset
Reset Control
XRES
Peripheral Interconnect (MMIO)
PCLK
8x TCPWM
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Multi Layer AHB)
Peripherals
IOSS GPIO (8x ports)
Power
Sleep Control
WIC
POR
LVD
REF
BOD
PWRSYS
NVLatches
Port Interface & Digital System Interconnect (DSI)
High Speed I/O Matrix
Power Modes
Active/Sleep
Deep Sleep
Hibernate
49x GPIO, 6x GPIO_OVT
IO Subsystem
The PSoC 4100-M devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4100-M devices. The SWD interface is fully compatible
with industry-standard third-party tools. The PSoC 4100-M
family provides a level of security not possible with multi-chip
application solutions or with microcontrollers. This is due to its
ability to disable debug features, robust flash protection, and
Document Number: 001-96519 Rev. *E
because it allows customer-proprietary functionality to be implemented in on-chip programmable blocks.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled,
PSoC 4100-M with device security enabled may not be returned
for failure analysis. This is a trade-off the PSoC 4100-M allows
the customer to make.
Page 4 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4100-M is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and execute a subset of the Thumb-2 instruction set. The
Cypress implementation includes a hardware multiplier that
provides a 32-bit result in one cycle. It includes a nested vectored
interrupt controller (NVIC) block with 32 interrupt inputs and also
includes a Wakeup Interrupt Controller (WIC), which can wake
the processor up from the Deep Sleep mode allowing power to
be switched off to the main processor when the chip is in the
Deep Sleep mode. The Cortex-M0 CPU provides a
Non-Maskable Interrupt (NMI) input, which is made available to
the user when it is not in use for system functions requested by
the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4100-M has four break-point
(address) comparators and two watchpoint (data) comparators.
Clock System
The PSoC 4100-M clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no meta-stable conditions occur.
The clock system for the PSoC 4100-M consists of a Watch
Crystal Oscillator (WCO) running at 32 kHz, the IMO (3 to
48 MHz) and the ILO (32-kHz nominal) internal oscillators, and
provision for an external clock.
Figure 2. PSoC 4100M MCU Clocking Architecture
IMO
clk_hf
clk_ext
dsi_in[0]
dsi_in[1]
dsi_in[2]
dsi_in[3]
dsi_out[3:0]
Flash
The PSoC 4100-M has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
DMA
A DMA engine, with eight channels, is provided that can do 32-bit
transfers and has chainable ping-pong descriptors.
System Resources
Power System
The power system is described in detail in the section Power on
page 13. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low voltage detect (LVD)). The
PSoC 4100M operates with a single external supply over the
range of 1.71 to 5.5 V and has five different power modes, transitions between which are managed by the power system. The
PSoC 4100M provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Document Number: 001-96519 Rev. *E
ILO
clk_lf
WCO
The clk_hf signal can be divided down to generate synchronous
clocks for the analog and digital peripherals. There are a total of
16 clock dividers for the PSoC 4100-M, each with 16-bit divide
capability. The analog clock leads the digital clocks to allow
analog events to occur before digital clock-related noise is
generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in
PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100M. It is trimmed during testing to achieve the
specified accuracy. Trim values are stored in nonvolatile
memory. Trimming can also be done on the fly to allow in-field
calibration. The IMO default frequency is 24 MHz and it can be
adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power oscillator, nominally 32 kHz, which
is primarily used to generate clocks for peripheral operation in
Deep Sleep mode. ILO-driven counters can be calibrated to the
IMO to improve accuracy. Cypress provides a software
component, which does the calibration.
Crystal Oscillator
The PSoC 4100M clock subsystem also includes a
low-frequency crystal oscillator (32-kHz WCO) that is available
during the Deep Sleep mode and can be used for Real-Time
Clock (RTC) and Watchdog Timer applications.
Page 5 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
VREF (nominally 1.024 V) as well as an external reference
through a GPIO pin. The Sample-and-Hold (S/H) aperture is
programmable allowing the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling
time, to be relaxed if required. The system performance will be
65 dB for true 12-bit precision if appropriate references are used
and system noise levels permit. To improve performance in noisy
conditions, it is possible to provide an external bypass (through
a fixed pin location) for the internal reference amplifier.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the low-frequency clock; this allows watchdog operation during
Deep Sleep and generates a watchdog reset or an interrupt if not
serviced before the timeout occurs. The watchdog reset is
recorded in the Reset Cause register.
Reset
The PSoC 4100M can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration.
The SAR is connected to a fixed set of pins through an 8-input
sequencer (expandable to 16 inputs). The sequencer cycles
through selected channels autonomously (sequencer scan) and
does so with zero switching overhead (that is, the aggregate
sampling bandwidth is equal to 1 Msps, whether it is for a single
channel or distributed over several channels). The sequencer
switching is effected through a state machine or through
firmware-driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service
requirements. To accommodate signals with varying source
impedance and frequency, it is possible to have different sample
times programmable for each channel. In addition, the signal
range specification through a pair of range registers (low and
high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
Voltage Reference
The PSoC 4100M reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and
better absolute accuracy, it is possible to add an external bypass
capacitor to the internal reference using a GPIO pin or to use an
external reference for the SAR.
Analog Blocks
12-bit SAR ADC
The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock. The SAR operating
range is 1.71 to 5.5 V.
The 12-bit SAR ADC can operate at a maximum sample rate of
806 Ksamples/second.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice of three internal voltage references: VDD, VDD/2, and
Figure 3. SAR ADC System Diagram
AHB System Bus and Programmable Logic
Interconnect
SARSEQ
vminus vplus
P7
Port 2 (8 inputs)
SARMUX
P0
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference
and
Bypass
(optional)
Reference
Selection
VDD/2
VDDD
VREF
Inputs from other Ports
Document Number: 001-96519 Rev. *E
Page 6 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Analog Multiplex Bus
The PSoC 4100M has two concentric analog buses (Analog Mux
Bus A and Analog Mux Bus B) that circumnavigate the periphery
of the chip. These buses can transport analog signals from any
pin to various analog blocks (including the opamps) and to the
CapSense blocks allowing, for instance, the ADC to monitor any
pin on the chip. These buses are independent and can also be
split into three independent sections. This allows one section to
be used for CapSense purposes, one for general analog signal
processing, and the third for general-purpose digital peripherals
and GPIO.
The opamps operate in Deep Sleep mode at very low currents
allowing analog circuits to remain operational during Deep
Sleep.
Temperature Sensor
The PSoC 4100M has one on-chip temperature sensor. This
consists of a diode, which is biased by a current source that can
be disabled to save power. The temperature sensor is connected
to the ADC, which digitizes the reading and produces a temperature value using Cypress-supplied software that includes
calibration and linearization.
Fixed Function Digital
Figure 4. Identical Opamp Pairs in Opamp Subsystem
Timer/Counter/PWM (TCPWM) Block
To SAR ADC
The PSoC 4100M has a pair of low-power comparators, which
can also operate in the Deep Sleep and Hibernate modes. This
allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during low-power
modes. The comparator outputs are normally synchronized to
avoid meta-stability unless operating in an asynchronous power
mode (Hibernate) where the system wake-up circuit is activated
by a comparator switch event.
To SAR ADC
The PSoC 4100M has four opamps with comparator modes,
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, voltage buffers,
filters, trans-impedance amplifiers, and other functions can be
realized with external passives saving power, cost, and space.
The on-chip opamps are designed with enough bandwidth to
drive the Sample-and-Hold circuit of the ADC without requiring
external buffering. The opamps can operate in the Deep Sleep
mode at very low power levels. The following diagram shows one
of two identical opamp pairs of the opamp subsystem.
Analog Mux Bus B
Low-power Comparators
Analog Mux Bus A
Four Opamps
OA0
+
P0
-
10x
1x
Internal
Out0
P1
P2
P3
P4
OA1
P5
-
P6
+
Serial Communication Blocks (SCB)
1x
10x
Internal
Out1
P7
The ovals in Figure 4 represent analog switches, which may be
controlled via user firmware, the SAR sequencer, or user-defined
programmable logic. The opamps (OA0 and OA1) are configurable via these switches to perform all standard opamp functions
with appropriate feedback components.
The opamps (OA0 and OA1) are programmable and reconfigurable to provide standard opamp functionality via switchable
feedback components, unity gain functionality for driving pins
directly, or for internal use (such as buffering SAR ADC inputs as
indicated in the diagram), or as true comparators.
The opamp inputs provide highly flexible connectivity and can
connect directly to dedicated pins or, via the analog mux buses,
to any pin on the chip. Analog switch connectivity is controllable
by user firmware.
Document Number: 001-96519 Rev. *E
The TCPWM block uses a16-bit counter with user-programmable period length. There is a Capture register to record the
count value at the time of an event (which may be an I/O event),
a period register which is used to either stop or auto-reload the
counter when its count is equal to the period register, and
compare registers to generate compare value signals, which are
used as PWM duty cycle outputs. The block also provides true
and complementary outputs with programmable offset between
them to allow use as deadband programmable complementary
PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems
when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software
intervention. The PSoC 4100M has eight TCPWM blocks.
The PSoC 4100M has four SCBs, which can each implement an
I2C, UART, or SPI interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EzI2C that creates a mailbox address range in the
memory of the PSoC 4100M and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time. The FIFO mode is available
in all channels and is very useful in the absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
Page 7 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
Special Function Peripherals
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO and also supports an EzSPI mode in which
data interchange is reduced to reading and writing an array in
memory.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
GPIO
The PSoC 4100M has 55 GPIOs in the 68-pin QFN package.
The GPIO block implements the following:
■
Eight drive strength modes including strong push-pull, resistive
pull-up and pull-down, weak (resistive) pull-up and pull-down,
open drain and open source, input only, and disabled
■
Input threshold select (CMOS or LVTTL)
■
Individual control of input and output disables
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes)
■
Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multiplexing complexity.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (8 for PSoC 4100M).
The Pins of Port 6 (up to 6 depending on the package) are
overvoltage tolerant (VIN can exceed VDD). The overvoltage cells
will not sink more than 10 µA when their inputs exceed VDDIO in
compliance with I2C specifications.
Document Number: 001-96519 Rev. *E
LCD Segment Drive
The PSoC 4100M has an LCD controller, which can drive up to
four commons and up to 51 segments. Any pin can be either a
common or a segment pin. It uses full digital methods to drive the
LCD segments requiring no generation of internal LCD voltages.
The two methods used are referred to as digital correlation and
PWM.
PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in the PSoC 4100M through
a CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense functionality can
thus be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block, which provides automatic hardware tuning (Cypress
SmartSense™), to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Each CSD block has two IDACs which can be used for general
purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available). The PSoC 4100M has two
CSD blocks which can be used independently; one for
CapSense and the other for IDACs.
The two CapSense blocks are referred to as CSD0 and CSD1.
Capacitance sensing inputs on Ports 0, 1, 2, 3, 4, 6, and 7 are
sensed by CSD0. Capacitance sensing inputs on Port 5 are
sensed by CSD1.
Page 8 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Pinouts
The following is the pin list for the PSoC 4100M. This shows the power supply and port pins (for example, P0.0 is Pin 0 of Port 0).
68-QFN
64-TQFP
48-TQFP
44-TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
42
P0.0
39
P0.0
28
P0.0
24
P0.0
43
P0.1
40
P0.1
29
P0.1
25
P0.1
44
P0.2
41
P0.2
30
P0.2
26
P0.2
45
P0.3
42
P0.3
31
P0.3
27
P0.3
46
P0.4
43
P0.4
32
P0.4
28
P0.4
47
P0.5
44
P0.5
33
P0.5
29
P0.5
48
P0.6
45
P0.6
34
P0.6
30
P0.6
49
P0.7
46
P0.7
35
P0.7
31
P0.7
50
XRES
47
XRES
36
XRES
32
XRES
51
VCCD
48
VCCD
37
VCCD
33
VCCD
52
VSSD
49
VSSD
38
VSSD
DN
VSSD
53
VDDD
50
VDDD
39
VDDD
34
VDDD
40
VDDA
35
VDDA
54
P5.0
51
P5.0
55
P5.1
52
P5.1
56
P5.2
53
P5.2
57
P5.3
54
P5.3
58
P5.4
59
P5.5
55
P5.5
60
VDDA
56
VDDA
40
VDDA
35
VDDA
61
VSSA
57
VSSA
41
VSSA
36
VSSA
62
P1.0
58
P1.0
42
P1.0
37
P1.0
63
P1.1
59
P1.1
43
P1.1
38
P1.1
64
P1.2
60
P1.2
44
P1.2
39
P1.2
65
P1.3
61
P1.3
45
P1.3
40
P1.3
66
P1.4
62
P1.4
46
P1.4
41
P1.4
67
P1.5
63
P1.5
47
P1.5
42
P1.5
68
P1.6
64
P1.6
48
P1.6
43
P1.6
1
P1.7/VREF
1
P1.7/VREF
1
P1.7/VREF
44
P1.7/VREF
1
VSSD
2
P2.0
2
P2.0
2
P2.0
2
P2.0
3
P2.1
3
P2.1
3
P2.1
3
P2.1
4
P2.2
4
P2.2
4
P2.2
4
P2.2
5
P2.3
5
P2.3
5
P2.3
5
P2.3
6
P2.4
6
P2.4
6
P2.4
6
P2.4
7
P2.5
7
P2.5
7
P2.5
7
P2.5
Document Number: 001-96519 Rev. *E
Page 9 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
68-QFN
64-TQFP
48-TQFP
44-TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
8
P2.6
8
P2.6
8
P2.6
8
P2.6
9
P2.7
9
P2.7
9
P2.7
9
P2.7
10
VSSA
10
VSSA
10
VSSD
10
VSSD
11
VDDA
11
VDDA
12
P6.0
12
P6.0
13
P6.1
13
P6.1
14
P6.2
14
P6.2
15
P6.3
16
P6.4
15
P6.4
17
P6.5
16
P6.5
18
VSSIO
17
VSSIO
10
VSSD
10
VSSD
19
P3.0
18
P3.0
12
P3.0
11
P3.0
20
P3.1
19
P3.1
13
P3.1
12
P3.1
21
P3.2
20
P3.2
14
P3.2
13
P3.2
22
P3.3
21
P3.3
16
P3.3
14
P3.3
23
P3.4
22
P3.4
17
P3.4
15
P3.4
24
P3.5
23
P3.5
18
P3.5
16
P3.5
25
P3.6
24
P3.6
19
P3.6
17
P3.6
26
P3.7
25
P3.7
20
P3.7
18
P3.7
27
VDDIO
26
VDDIO
21
VDDIO
19
VDDD
28
P4.0
27
P4.0
22
P4.0
20
P4.0
29
P4.1
28
P4.1
23
P4.1
21
P4.1
30
P4.2
29
P4.2
24
P4.2
22
P4.2
31
P4.3
30
P4.3
25
P4.3
23
P4.3
32
P4.4
31
P4.4
33
P4.5
32
P4.5
34
P4.6
33
P4.6
35
P4.7
39
P7.0
37
P7.0
26
P7.0
40
P7.1
38
P7.1
27
P7.1
41
P7.2
The pins of Port 6 are overvoltage-tolerant. Pins 36, 37, and 38 are No-Connects on the 68-pin QFN. Pins 34, 35, and 36 are
No-Connects on the 64-pin TQFP. Pins 11 and 15 are No-connects in the 48-pin TQFP. All VSS pins must be tied together.
The output drivers of I/O Ports P0 and P7 are connected to VDDD. Output drivers of I/O Ports 1, 2, and 5 are connected to VDDA.
Output drivers of I/O Ports 3, 4, and 6 are connected to VDDIO.
Document Number: 001-96519 Rev. *E
Page 10 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Each of the pins shown in the previous table can have multiple programmable functions as shown in the following table. Column headings refer to Analog and Alternate pin
functions:
Port/Pin
Analog
P0.0
lpcomp.in_p[0]
Alt. Function 1
Alt. Function 2
Alt. Function 3
Alt. Function 4
scb[0].spi_select1:0
Alt. Function 5
P0.1
lpcomp.in_n[0]
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
scb[0].spi_select3:0
P0.3
lpcomp.in_n[1]
P0.4
wco_in
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco_out
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
P0.6
ext_clk:0
P0.7
scb[1].uart_cts:0
scb[1].spi_clk:1
scb[1].uart_rts:0
wakeup
scb[1].spi_select0:1
P5.0
ctb1.oa0.inp
tcpwm.line[4]:2
scb[2].uart_rx:0
scb[2].i2c_scl:0
scb[2].spi_mosi:0
P5.1
ctb1.oa0.inm
tcpwm.line_compl[4]:2
scb[2].uart_tx:0
scb[2].i2c_sda:0
scb[2].spi_miso:0
P5.2
ctb1.oa0.out
tcpwm.line[5]:2
scb[2].uart_cts:0
lpcomp.comp[0]:1
scb[2].spi_clk:0
P5.3
ctb1.oa1.out
tcpwm.line_compl[5]:2
scb[2].uart_rts:0
lpcomp.comp[1]:1
scb[2].spi_select0:0
P5.4
ctb1.oa1.inm
tcpwm.line[6]:2
scb[2].spi_select1:0
P5.5
ctb1.oa1.inp
tcpwm.line_compl[6]:2
scb[2].spi_select2:0
P5.6
ctb1.oa0.inp_alt
tcpwm.line[7]:0
scb[2].spi_select3:0
P5.7
ctb1.oa1.inp_alt
tcpwm.line_compl[7]:0
P1.0
ctb0.oa0.inp
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
ctb0.oa0.inm
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0.oa0.out
tcpwm.line[3]:1
scb[0].uart_cts:1
scb[0].spi_clk:1
P1.3
ctb0.oa1.out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
scb[0].spi_select0:1
P1.4
ctb0.oa1.inm
tcpwm.line[6]:1
scb[0].spi_select1:1
P1.5
ctb0.oa1.inp
tcpwm.line_compl[6]:1
scb[0].spi_select2:1
P1.6
ctb0.oa0.inp_alt
tcpwm.line[7]:1
scb[0].spi_select3:1
P1.7
ctb0.oa1.inp_alt
tcpwm.line_compl[7]:1
P2.0
sarmux.0
tcpwm.line[4]:1
scb[1].i2c_scl:1
scb[1].spi_mosi:2
P2.1
sarmux.1
tcpwm.line_compl[4]:1
scb[1].i2c_sda:1
scb[1].spi_miso:2
P2.2
sarmux.2
tcpwm.line[5]:1
scb[1].spi_clk:2
P2.3
sarmux.3
tcpwm.line_compl[5]:1
scb[1].spi_select0:2
P2.4
sarmux.4
tcpwm.line[0]:1
scb[1].spi_select1:1
P2.5
sarmux.5
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
sarmux.6
tcpwm.line[1]:1
scb[1].spi_select3:1
P2.7
sarmux.7
tcpwm.line_compl[1]:1
scb[3].spi_select0:1
Document Number: 001-96519 Rev. *E
Page 11 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Port/Pin
Alt. Function 1
Alt. Function 2
Alt. Function 4
Alt. Function 5
P6.0
Analog
tcpwm.line[4]:0
scb[3].uart_rx:0
scb[3].i2c_scl:0
scb[3].spi_mosi:0
P6.1
tcpwm.line_compl[4]:0
scb[3].uart_tx:0
scb[3].i2c_sda:0
scb[3].spi_miso:0
P6.2
tcpwm.line[5]:0
scb[3].uart_cts:0
scb[3].spi_clk:0
P6.3
tcpwm.line_compl[5]:0
scb[3].uart_rts:0
scb[3].spi_select0:0
P6.4
tcpwm.line[6]:0
P6.5
tcpwm.line_compl[6]:0
P3.0
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.1
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
tcpwm.line[1]:0
scb[1].uart_cts:1
swd_data
scb[1].spi_clk:0
P3.3
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
swd_clk
P3.4
tcpwm.line[2]:0
scb[1].spi_select1:0
P3.5
tcpwm.line_compl[2]:0
scb[1].spi_select2:0
P3.6
tcpwm.line[3]:0
scb[1].spi_select3:0
P3.7
tcpwm.line_compl[3]:0
P4.0
Alt. Function 3
scb[3].spi_select1:0
scb[3].spi_select2:0
scb[0].uart_rx:0
P4.1
scb[1].spi_select0:0
scb[0].i2c_scl:1
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].uart_tx:0
scb[0].i2c_sda:1
P4.2
csd[0].c_mod
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd[0].c_sh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
P4.4
scb[0].spi_select1:2
P4.5
scb[0].spi_select2:2
P4.6
scb[0].spi_select3:2
P4.7
P7.0
tcpwm.line[0]:2
scb[3].uart_rx:1
scb[3].i2c_scl:1
scb[3].spi_mosi:1
P7.1
tcpwm.line_compl[0]:2
scb[3].uart_tx:1
scb[3].i2c_sda:1
scb[3].spi_miso:1
P7.2
tcpwm.line[1]:2
scb[3].uart_cts:1
scb[3].spi_clk:1
Descriptions of the power pin functions are as follows:
VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise
VDDD: Power supply for both analog and digital sections (where there is no VDDA
pin).
VSS: Ground pin.
VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise.
Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense
and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO
pins that can be driven by firmware or DSI signals.
VDDIO: I/O pin power domain.
Document Number: 001-96519 Rev. *E
VCCD: Regulated Digital supply (1.8 V ±5%).
Page 12 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Power
The supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
The PSoC 4100M family allows two distinct modes of power
supply operation: Unregulated External Supply and Regulated
External Supply modes.
Unregulated External Supply
In this mode, the PSoC 4100M is powered by an External Power
Supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation, for
instance, the chip can be powered from a battery system that
starts at 3.5V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100M supplies the internal logic and the
VCCD output of the PSoC 4100M must be bypassed to ground
via an external Capacitor (in the range of 1 to 1.6 µF; X5R
ceramic or better).
Power Supply
VDDD–VSS and
VDDIO-VSS
VDDA–VSSA
VCCD–VSS
VREF–VSSA
(optional)
Bypass Capacitors
0.1 µF ceramic at each pin plus bulk
capacitor 1 to 10 µF.
0.1 µF ceramic at pin. Additional 1 µF to
10 µF bulk capacitor
1 µF ceramic capacitor at the VCCD pin
The internal bandgap may be bypassed
with a 1 µF to 10 µF capacitor for better
ADC performance.
Regulated External Supply
In this mode, the PSoC 4100M is powered by an external power
supply that must be within the range of 1.71 to 1.89 V (1.8 ±5%);
note that this range needs to include power supply ripple. VCCD
and VDDD pins are shorted together and bypassed. The internal
regulator is disabled in firmware.
The grounds, VSSA and VSS, must be shorted together. Bypass
capacitors must be used from VDDD and VDDA to ground,
typical practice for systems in this frequency range is to use a
capacitor in the 1 µF range in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead
inductance, and the Bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
Document Number: 001-96519 Rev. *E
Page 13 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Development Support
The PSoC 4100M family has a rich set of documentation, development tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4100M family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using
PSoC Creator. The software user guide shows you how the
PSoC Creator build process works in detail, how to use source
control with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Document Number: 001-96519 Rev. *E
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4100M family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Page 14 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID1
VDD_ABS
Analog or digital supply relative to VSS
(VSSD = VSSA)
–0.5
–
6
V
Absolute maximum
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSSD
–0.5
–
1.95
V
Absolute maximum
SID3
VGPIO_ABS
GPIO voltage; VDDD or VDDA
–0.5
–
VDD+0.5
V
Absolute maximum
SID4
IGPIO_ABS
Current per GPIO
–25
–
25
mA
Absolute maximum
Absolute maximum
SID5
IG-PIO_injection
GPIO injection current per pin
–0.5
–
0.5
mA
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–140
–
140
mA
Device Level Specifications
All specifications are valid for –40 °C  TA  105 °C and TJ  125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID53
VDD
Power Supply Input Voltage (VDDA =
VDDD = VDD)
1.8
–
5.5
V
With regulator
enabled
SID255
VDDD
Power Supply Input Voltage unregulated
1.71
1.8
1.89
V
Internally unregulated
Supply
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
V
SID55
CEFC
External Regulator voltage bypass
1
1.3
1.6
µF
X5R ceramic or better
SID56
CEXC
Power supply decoupling capacitor
–
1
–
µF
X5R ceramic or better
Active Mode, VDD = 1.71 V to 5.5 V, –40 °C to +105 °C
SID6
IDD1
Execute from Flash; CPU at 6 MHz
–
2.2
2.8
mA
SID7
IDD2
Execute from Flash; CPU at 12 MHz
–
3.7
4.2
mA
SID8
IDD3
Execute from Flash; CPU at 24 MHz
–
6.7
7.2
mA
Sleep Mode, –40 °C to +105 °C
SID21
IDD16
I2C wakeup, WDT, and Comparators on.
Regulator Off.
–
1.75
2.1
mA
VDD = 1.71 to 1.89,
6 MHz
SID22
IDD17
I2C wakeup, WDT, and Comparators on.
–
1.7
2.1
mA
VDD = 1.8 to 5.5, 6
MHz
SID23
IDD18
I2C wakeup, WDT, and Comparators on.
Regulator Off.
–
2.35
2.8
mA
VDD = 1.71 to 1.89,
12 MHz
SID24
IDD19
I2C wakeup, WDT, and Comparators on.
–
2.25
2.8
mA
VDD = 1.8 to 5.5,
12 MHz
Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-96519 Rev. *E
Page 15 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 2. DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Deep Sleep Mode, –40 °C to + 60 °C
SID30
IDD25
I2C wakeup and WDT on. Regulator Off.
–
1.55
20
µA
VDD = 1.71 to 1.89
SID31
IDD26
I2C wakeup and WDT on.
–
1.35
15
µA
VDD = 1.8 to 3.6
SID32
IDD27
I2C wakeup and WDT on.
–
1.5
15
µA
VDD = 3.6 to 5.5
I2C wakeup and WDT on. Regulator Off.
–
–
60
µA
VDD = 1.71 to 1.89
Deep Sleep Mode, +85 °C
SID33
IDD28
2
SID34
IDD29
I C wakeup and WDT on.
–
–
45
µA
VDD = 1.8 to 3.6
SID35
IDD30
I2C wakeup and WDT on.
–
–
30
µA
VDD = 3.6 to 5.5
Deep Sleep Mode, +105 °C
SID33Q
IDD28Q
I2C wakeup and WDT on. Regulator Off.
–
–
135
µA
VDD = 1.71 to 1.89
SID34Q
IDD29Q
I2C wakeup and WDT on.
–
–
180
µA
VDD = 1.8 to 3.6
IDD30Q
I2C
–
–
140
µA
VDD = 3.6 to 5.5
–
150
3000
nA
VDD = 1.71 to 1.89
SID35Q
wakeup and WDT on.
Hibernate Mode, –40 °C to + 60 °C
Regulator Off.
SID39
IDD34
SID40
IDD35
–
150
1000
nA
VDD = 1.8 to 3.6
SID41
IDD36
–
150
1100
nA
VDD = 3.6 to 5.5
Hibernate Mode, +85 °C
SID42
IDD37
–
–
4500
nA
VDD = 1.71 to 1.89
SID43
IDD38
–
–
3500
nA
VDD = 1.8 to 3.6
SID44
IDD39
–
–
3500
nA
VDD = 3.6 to 5.5
–
–
19.4
µA
VDD = 1.71 to 1.89
Regulator Off.
Hibernate Mode, +105 °C
SID42Q
IDD37Q
Regulator Off.
SID43Q
IDD38Q
–
–
17
µA
VDD = 1.8 to 3.6
SID44Q
IDD39Q
–
–
16
µA
VDD = 3.6 to 5.5
Stop Mode, +85 °C
SID304
IDD43A
Stop Mode current; VDD = 3.6 V
–
35
85
nA
T = –40 °C to +60 °C
SID304A
IDD43B
Stop Mode current; VDD = 3.6 V
–
–
1450
nA
T = +85 °C
Stop Mode current; VDD = 3.6 V
–
–
5645
nA
Supply current while XRES asserted
–
2
5
mA
Stop Mode, +105 °C
SID304Q
IDD43AQ
XRES current
SID307
IDD_XR
Document Number: 001-96519 Rev. *E
Page 16 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 3. AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID48
FCPU
CPU frequency
DC
–
24
MHz
1.71 VDD 5.5
SID49
TSLEEP
Wakeup from sleep mode
–
0
–
µs
Guaranteed by
characterization
SID50
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
–
25
µs
24 MHz IMO.
Guaranteed by
characterization
SID51
THIBERNATE
Wakeup from Hibernate mode
–
–
0.7
ms
Guaranteed by
characterization
SID51A
TSTOP
Wakeup from Stop mode
–
–
2
ms
Guaranteed by
characterization
SID52
TRESETWIDTH
External reset pulse width
1
–
–
µs
Guaranteed by
characterization
GPIO
Table 4. GPIO DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
Min
Typ
Max
Units
0.7 ×
VDDD
–
–
V
CMOS Input
SID57
VIH[2]
Input voltage high threshold
SID57A
IIHS
Input current when Pad > VDDIO for OVT
inputs
–
–
10
µA
Per I2C Spec
SID58
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID241
VIH[2]
LVTTL input, VDDD < 2.7 V
0.7×
VDDD
–
–
V
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3 ×
VDDD
V
SID243
VIH[2]
LVTTL input, VDDD  2.7 V
2.0
–
–
V
SID244
VIL
LVTTL input, VDDD  2.7 V
–
–
0.8
V
SID59
VOH
Output voltage high level
VDDD
–0.6
–
–
V
IOH = 4 mA at
3 V VDDD
SID60
VOH
Output voltage high level
VDDD
–0.5
–
–
V
IOH = 1 mA at
1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
V
IOL = 4 mA at
1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
V
IOL = 8 mA at 3 V
VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 3 mA at 3 V
VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
25 °C, VDDD =
3.0 V.
Guaranteed by
characterization
Note
2. VIH must not exceed VDDD + 0.2 V.
Document Number: 001-96519 Rev. *E
Page 17 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 4. GPIO DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
Guaranteed by
characterization
SID65A
IIL_CTBM
Input leakage current (absolute value)
for CTBM pins
–
–
4
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
SID68
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDD
–
–
mV
SID69
IDIODE
Current through protection diode to
VDD/Vss
–
–
100
µA
Guaranteed by
characterization
SID69A
ITOT_GPIO
Maximum Total Source or Sink Chip
Current
–
–
200
mA
Guaranteed by
characterization
VDDD  2.7 V
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)[3]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO Fout;3.3 V  VDDD 5.5 V. Fast
strong mode.
–
–
24
MHz
90/10%, 25 pF
load, 60/40 duty
cycle
SID75
FGPIOUT2
GPIO Fout;1.7 VVDDD3.3 V. Fast
strong mode.
–
–
16.7
MHz
90/10%, 25 pF
load, 60/40 duty
cycle
SID76
FGPIOUT3
GPIO Fout;3.3 V VDDD 5.5 V. Slow
strong mode.
–
–
7
MHz
90/10%, 25 pF
load, 60/40 duty
cycle
SID245
FGPIOUT4
GPIO Fout;1.7 V VDDD 3.3 V. Slow
strong mode.
–
–
3.5
MHz
90/10%, 25 pF
load, 60/40 duty
cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
MHz
90/10% VIO
Note
3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several factors including PCB and decoupling
capacitor design. For applications that are very sensitive to ground perturbations, the slower GPIO slew rate setting may be used.
Document Number: 001-96519 Rev. *E
Page 18 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
XRES
Table 6. XRES DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID77
VIH
Input voltage high threshold
0.7 ×
VDDD
–
–
V
CMOS Input
SID78
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID79
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID80
CIN
Input capacitance
–
3
–
pF
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Guaranteed by
characterization
SID82
IDIODE
Current through protection diode to
VDDD/VSS
–
–
100
µA
Guaranteed by
characterization
Min
1
Typ
–
Max
–
Units
µs
Table 7. XRES AC Specifications
Spec ID#
SID83
Parameter
TRESETWIDTH
Description
Reset pulse width
Document Number: 001-96519 Rev. *E
Details/
Conditions
Guaranteed by
characterization
Page 19 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Analog Peripherals
Opamp
Table 8. Opamp Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
IDD
Description
Opamp block current. No load.
Min
–
Typ
–
Max
–
Units
–
SID269
IDD_HI
Power = high
–
1100
1850
µA
SID270
IDD_MED
Power = medium
–
550
950
µA
SID271
IDD_LOW
Power = low
–
150
350
µA
GBW
Load = 20 pF, 0.1 mA. VDDA = 2.7 V
–
–
–
–
SID272
GBW_HI
Power = high
6
–
–
MHz
SID273
GBW_MED
Power = medium
4
–
–
MHz
SID274
Details/
Conditions
GBW_LO
Power = low
–
1
–
MHz
IOUT_MAX
VDDA  2.7 V, 500 mV from rail
–
–
–
–
SID275
IOUT_MAX_HI
Power = high
10
–
–
mA
SID276
IOUT_MAX_MID
Power = medium
10
–
–
mA
SID277
IOUT_MAX_LO
Power = low
–
5
–
mA
IOUT
VDDA = 1.71 V, 500 mV from rail
–
–
–
–
SID278
IOUT_MAX_HI
Power = high
4
–
–
mA
SID279
IOUT_MAX_MID
Power = medium
4
–
–
mA
SID280
IOUT_MAX_LO
Power = low
–
2
–
mA
SID281
VIN
Input voltage range
–0.05
–
VDDA
– 0.2
V
Charge-pump on, VDDA 
2.7 V
SID282
VCM
Input common mode voltage
–0.05
–
V
Charge-pump on, VDDA 
2.7 V
VOUT
VDDA  2.7 V
–
–
VDDA
– 0.2
–
SID283
VOUT_1
Power = high, Iload=10 mA
0.5
–
VDDA
– 0.5
V
SID284
VOUT_2
Power = high, Iload=1 mA
0.2
–
VDDA
– 0.2
V
SID285
VOUT_3
Power = medium, Iload=1 mA
0.2
–
V
SID286
VOUT_4
Power = low, Iload=0.1 mA
0.2
–
VDDA
– 0.2
VDDA
– 0.2
SID288
VOS_TR
Offset voltage, trimmed
1
±0.5
1
mV
High mode
SID288A
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium mode
SID288B
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/°C
High mode. TA ≤ 85 °C.
SID290Q
VOS_DR_TR
Offset voltage drift, trimmed
15
±3
15
µV/°C
High mode. TA ≤ 105 °C
V
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Medium mode
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Low mode
SID291
CMRR
DC Common mode rejection ratio.
High-power mode. Common Model
voltage range from 0.5 V to VDDA 0.5 V.
60
70
–
dB
VDDD = 3.6 V
SID292
PSRR
At 1 kHz, 100-mV ripple
70
85
–
dB
VDDD = 3.6 V
–
–
–
–
Noise
Document Number: 001-96519 Rev. *E
Page 20 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 8. Opamp Specifications
(Guaranteed by Characterization) (continued)
Spec ID#
SID293
Parameter
VN1
Description
Input referred, 1 Hz - 1GHz, power =
high
Min
–
Typ
94
Max
–
Units
µVrms
SID294
VN2
Input referred, 1 kHz, power = high
–
72
–
nV/rtHz
SID295
VN3
Input referred, 10kHz, power = high
–
28
–
nV/rtHz
SID296
VN4
Input referred, 100kHz, power = high
–
15
–
nV/rtHz
SID297
Cload
–
–
125
pF
SID298
Slew_rate
6
–
–
V/µs
SID299
T_op_wake
–
25
–
µs
SID299A
OL_GAIN
Stable up to maximum load. Performance specs at 50 pF.
Cload = 50 pF, Power = High, VDDA 
2.7 V
From disable to enable, no external
RC dominating
Open Loop Gain
–
90
–
dB
Comp_mode
Comparator mode; 50 mV drive,
Trise = Tfall (approx.)
–
–
–
SID300
TPD1
Response time; power = high
–
150
–
ns
SID301
TPD2
Response time; power = medium
–
400
–
ns
SID302
TPD3
Response time; power = low
–
2000
–
ns
SID303
Vhyst_op
Hysteresis
–
10
–
mV
Details/
Conditions
Deep Sleep Mode
Mode 2 is lowest current range. Mode
1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
uA
25 °C
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
200
–
uA
25 °C
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
uA
25 °C
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
uA
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
uA
25 °C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
MHz
25 °C
SID_DS_8
GBW_MED_M1 Mode 1, Medium current
–
2
–
MHz
25 °C
SID_DS_9
GBW_LOW_M1 Mode 1, Low current
–
0.5
–
MHz
25 °C
–
0.5
–
MHz
20-pF load, no DC load
0.2 V to VDDA-1.5 V
SID_DS_11 GBW_MED_M2 Mode 2, Medium current
–
0.2
–
MHz
20-pF load, no DC load
0.2 V to VDDA-1.5 V
SID_DS_12 GBW_LOW_M2 Mode 2, Low current
–
0.1
–
MHz
20-pF load, no DC load
0.2 V to VDDA-1.5 V
SID_DS_13 VOS_HI_M1
–
5
–
mV
SID_DS_14 VOS_MED_M1 Mode 1, Medium current
–
5
–
mV
SID_DS_15 VOS_LOW_M1 Mode 1, Low current
–
5
–
mV
SID_DS_16 VOS_HI_M2
–
5
–
mV
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-1.5 V
With trim 25 °C, 0.2 V to
VDDA-1.5 V
With trim 25 °C, 0.2 V to
VDDA-1.5 V
With trim 25 °C, 0.2 V to
VDDA-1.5 V
With trim 25 °C, 0.2 V to
VDDA-1.5 V
SID_DS_10 GBW_HI_M2
Mode 2, High current
Mode 1, High current
Mode 2, High current
SID_DS_17 VOS_MED_M2 Mode 2, Medium current
Document Number: 001-96519 Rev. *E
Deep Sleep mode.
VDDA  2.7 V.
–
1400
–
uA
25 °C
Page 21 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 8. Opamp Specifications
(Guaranteed by Characterization) (continued)
Spec ID#
Parameter
Description
SID_DS_18 VOS_LOW_M2 Mode 2, Low current
Min
–
Typ
5
Max
–
Units
mV
–
10
–
mA
SID_DS_20 IOUT_MED_M1 Mode 1, Medium current
–
10
–
mA
SID_DS_21 IOUT_LOW_M1 Mode 1, Low current
–
4
–
mA
SID_DS_22 IOUT_HI_M2
–
1
–
mA
SID_DS_23 IOUT_MED_M2 Mode 2, Medium current
–
1
–
mA
SID_DS_24 IOUT_LOW_M2 Mode 2, Low current
–
0.5
–
mA
SID_DS_19 IOUT_HI_M1
Mode 1, High current
Mode 2, High current
Details/
Conditions
With trim 25 °C, 0.2 V to
VDDA-1.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Comparator
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID85
VOFFSET2
Input offset voltage, Common Mode
voltage range from 0 to VDD-1
–
–
±4
mV
SID85A
VOFFSET3
Input offset voltage. Ultra low-power
mode (VDDD ≥ 2.2 V for Temp < 0 °C,
VDDD ≥ 1.8 V for Temp > 0 °C).
–
±12
–
mV
SID86
VHYST
Hysteresis when enabled, Common
Mode voltage range from 0 to VDD -1.
–
10
35
mV
SID87
VICM1
Input common mode voltage in
normal mode
0
–
VDDD – 0.1
V
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
V
SID247A
VICM3
Input common mode voltage in ultra
low power mode (VDDD ≥ 2.2 V for
Temp < 0 °C, VDDD ≥ 1.8 V for Temp
> 0 °C)
0
–
VDDD –
1.15
V
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD  2.7 V.
Guaranteed by characterization
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD  2.7 V.
Guaranteed by characterization
SID89
ICMP1
Block current, normal mode
–
–
400
µA
Guaranteed by characterization
SID248
ICMP2
Block current, low power mode
–
–
100
µA
Guaranteed by characterization
SID259
ICMP3
Block current, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD
≥ 1.8 V for Temp > 0 °C)
–
6
28
µA
Guaranteed by characterization
SID90
ZCMP
DC input impedance of comparator
35
–
–
MΩ
Guaranteed by characterization
Document Number: 001-96519 Rev. *E
Guaranteed by characterization
Modes 1 and 2.
Page 22 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 10. Comparator AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID91
Spec ID#
TRESP1
Parameter
Response time, normal mode
Description
–
–
110
ns
50-mV overdrive
Details/Conditions
SID258
TRESP2
Response time, low power mode
–
–
200
ns
50-mV overdrive
SID92
TRESP3
Response time, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥
1.8 V for Temp > 0 °C)
–
–
15
µs
200-mV overdrive
Min
Typ
Max
Units
–5
±1
+5
°C
Typ
Max
Units
bits
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
Details/Conditions
–40 to +85 °C
SAR ADC
Table 12. SAR ADC DC Specifications
Spec ID#
Parameter
Description
Min
Details/Conditions
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNIS_S
Number of channels - single ended
–
–
16
8 full speed
SID96
A-CHNKS_D
Number of channels - differential
–
–
8
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
Yes. Based on
characterization
SID98
A_GAINERR
Gain error
–
–
±0.1
%
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
Based on device
characterization
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
Based on device
characterization
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
Based on device
characterization
SID104
A_INCAP
Input capacitance
–
–
10
pF
Based on device
characterization
With external
reference.
Measured with 1-V
VREF.
Table 13. SAR ADC AC Specifications
(Guaranteed by Characterization)
Spec ID#
SID106
Parameter
A_PSRR
Description
Power supply rejection ratio
Min
70
Typ
–
Max
–
Units
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID108
A_SAMP_1
Sample rate with external reference
bypass cap
–
–
806
ksps
Document Number: 001-96519 Rev. *E
Details/Conditions
Measured at 1 V
Page 23 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 13. SAR ADC AC Specifications
(Guaranteed by Characterization) (continued)
Spec ID#
SID108A
Parameter
A_SAMP_2
A_INL
Description
Sample rate with no bypass cap.
Reference = VDD
Sample rate with no bypass cap.
Internal reference
Signal-to-noise and distortion ratio
(SINAD)
Integral non linearity
Min
–
Typ
–
Max
500
Units
ksps
SID108B
A_SAMP_3
–
–
100
ksps
SID109
A_SNDR
66
–
–
dB
SID111
–1.4
–
+1.4
LSB
SID111A
A_INL
Integral non linearity
–1.4
–
+1.4
LSB
SID111B
A_INL
Integral non linearity
–1.4
–
+1.4
LSB
SID112
A_DNL
Differential non linearity
–0.9
–
+1.35
LSB
SID112A
A_DNL
Differential non linearity
–0.9
–
+1.35
LSB
SID112B
A_DNL
Differential non linearity
–0.9
–
+1.35
LSB
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
Typ
Max
Units
Details/Conditions
FIN = 10 kHz
VDD = 1.71 to 5.5,
806 Ksps, Vref = 1 to
5.5.
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD.
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
VDDD = 1.71 to 5.5,
806 Ksps, Vref = 1 to
5.5.
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD.
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
FIN = 10 kHz.
CSD
Table 14. CSD Block Specification
Spec ID#
Parameter
Description
Min
Details/
Conditions
CSD Specification
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
SID309
IDAC1
DNL for 8-bit resolution
–1
–
1
LSB
SID310
IDAC1
INL for 8-bit resolution
–3
–
3
LSB
SID311
IDAC2
DNL for 7-bit resolution
–1
–
1
LSB
SID312
IDAC2
INL for 7-bit resolution
–3
–
3
LSB
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio
SID314
IDAC1_CRT1
Output current of Idac1 (8-bits) in High
range
–
612
–
µA
SID314A
IDAC1_CRT2
Output current of Idac1(8-bits) in Low
range
–
306
–
µA
SID315
IDAC2_CRT1
Output current of Idac2 (7-bits) in High
range
–
304.8
–
µA
SID315A
IDAC2_CRT2
Output current of Idac2 (7-bits) in Low
range
–
152.4
–
µA
Document Number: 001-96519 Rev. *E
Capacitance range
of 9 to 35 pF, 0.1 pF
sensitivity
Page 24 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode.
Timer/Counter/PWM
Table 15. TCPWM Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
SID.TCPWM.1
ITCPWM1
Block current consumption at 3 MHz
–
–
45
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
Units
Details/Conditions
All modes
µA
(Timer/Counter/PWM)
All modes
µA
(Timer/Counter/PWM)
All modes
µA
(Timer/Counter/PWM)
Fc max = Fcpu.
MHz
Maximum = 24 MHz
Trigger Events can be
Stop, Start, Reload,
Count, Capture, or Kill
ns
depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and CC
ns
(Counter equals
Compare value) trigger
outputs
Minimum time between
ns
successive counts
Minimum pulse width
ns
of PWM Output
Minimum pulse width
ns between Quadrature
phase inputs.
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT
Input Trigger Pulse Width for all
Trigger Events
2/Fc
–
–
SID.TCPWM.5
TPWMEXT
Output Trigger Pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of Counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM Resolution
1/Fc
–
–
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Min
Typ
Max
Units
I2C
Table 16. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
µA
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
µA
Typ
–
Max
1
Units
Mbps
Details/Conditions
Table 17. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Document Number: 001-96519 Rev. *E
Min
–
Details/Conditions
Page 25 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
LCD Direct Drive
Table 18. LCD Direct Drive DC Specifications
(Guaranteed by Characterization)
Spec ID
SID154
Parameter
ILCDLOW
SID155
CLCDCAP
SID156
LCDOFFSET
SID157
ILCDOP1
SID158
ILCDOP2
Description
Operating current in low power mode
Min
–
Typ
5
Max
–
Units Details/Conditions
µA 16 × 4 small segment
disp. at 50 Hz
pF Guaranteed by Design
LCD capacitance per segment/common
driver
Long-term segment offset
–
500
5000
–
20
–
mV
PWM Mode current. 5-V bias.
24-MHz IMO
PWM Mode current. 3.3-V bias.
24-MHz IMO.
–
0.6
–
mA
–
0.5
–
mA
Min
10
Typ
50
Max
150
Units
Hz
32 × 4 segments.
50 Hz, 25 °C
32 × 4 segments.
50 Hz, 25 °C
Table 19. LCD Direct Drive AC Specifications
(Guaranteed by Characterization)
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Details/Conditions
Table 20. Fixed UART DC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID160
Spec ID
IUART1
Parameter
Block current consumption at
100 Kbits/sec
Description
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbits/sec
–
–
312
µA
Min
Typ
Max
Units
–
–
1
Mbps
Description
Min
Typ
Max
Units
Details/Conditions
Table 21. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Details/Conditions
SPI Specifications
Table 22. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
SID163
ISPI1
Block current consumption at 1 Mbits/sec
–
–
360
µA
SID164
ISPI2
Block current consumption at 4 Mbits/sec
–
–
560
µA
SID165
ISPI3
Block current consumption at 8 Mbits/sec
–
–
600
µA
Min
Typ
Max
Units
–
–
8
MHz
Details/Conditions
Table 23. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Description
SPI operating frequency (master; 6X
oversampling)
Document Number: 001-96519 Rev. *E
Details/Conditions
Page 26 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 24. Fixed SPI Master mode AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID167
Spec ID
TDMO
Parameter
MOSI valid after Sclock driving edge
Description
–
–
15
ns
SID168
TDSI
MISO valid before Sclock capturing edge.
Full clock, late MISO Sampling used
20
–
–
ns
SID169
THMO
Previous MOSI data hold time with
respect to capturing edge at Slave
0
–
–
ns
Details/Conditions
Table 25. Fixed SPI Slave mode AC Specifications
(Guaranteed by Characterization)
Description
Min
Typ
Max
Units
SID170
Spec ID
TDMI
Parameter
MOSI valid before Sclock capturing edge
40
–
–
ns
SID171
TDSO
MISO valid after Sclock driving edge
–
–
42 + 3 ×
(1/FCPU)
ns
SID171A
TDSO_ext
MISO valid after Sclock driving edge in
Ext. Clock mode
–
–
48
ns
SID172
THSO
Previous MISO data hold time
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
0
–
–
ns
100
–
–
ns
Min
Typ
Max
Units
1.71
–
5.5
V
Details/Conditions
Memory
Table 26. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage
Details/Conditions
Table 27. Flash AC Specifications
Min
Typ
Max
Units
SID174
Spec ID
TROWWRITE
Parameter
Row (block) write time (erase and
program)
Description
–
–
20
ms
SID175
TROWERASE
Row erase time
–
–
13
ms
SID176
TROWPROGRAM
Row program time after erase
–
–
7
ms
SID178
TBULKERASE
Bulk erase time (128 KB)
–
–
35
ms
SID179
TSECTORERASE
Sector erase time (8 KB)
–
–
15
SID180
TDEVPROG
Total device program time
–
–
15
SID181
FEND
Flash endurance
100 K
–
–
cycles
Guaranteed by
characterization
SID182
FRET
Flash retention. TA  55 °C, 100 K P/E
cycles
20
–
–
years
Guaranteed by
characterization
SID182A
Flash retention. TA  85 °C, 10 K P/E
cycles
10
–
–
years
Guaranteed by
characterization
SID182B FRETQ
Flash retention. TA  105 °C, 10K P/E
cycles,  three years at TA ≥ 85 °C
10
20
–
years
Guaranteed by
characterization.
Document Number: 001-96519 Rev. *E
Details/Conditions
Row (block) =
128 bytes
ms
seconds Guaranteed by
characterization
Page 27 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
System Resources
Power-on-Reset (POR) with Brown Out
Table 28. Imprecise Power On Reset (PRES)
Min
Typ
Max
Units
SID185
Spec ID
VRISEIPOR
Parameter
Rising trip voltage
Description
0.80
–
1.45
V
Guaranteed by characterization
Details/Conditions
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
Guaranteed by characterization
SID187
VIPORHYST
Hysteresis
15
–
200
mV
Guaranteed by characterization
Table 29. Precise Power On Reset (POR)
Min
Typ
Max
Units
SID190
Spec ID
VFALLPPOR
Parameter
BOD trip voltage in active and
sleep modes
Description
1.64
–
–
V
Guaranteed by characterization
Details/Conditions
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
V
Guaranteed by characterization
Voltage Monitors
Table 30. Voltage Monitors DC Specifications
Spec ID
SID195
Parameter
VLVI1
Description
LVI_A/D_SEL[3:0] = 0000b
Min
1.71
Typ
1.75
Max
1.79
Units
V
Details/Conditions
SID196
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
V
SID197
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
V
SID198
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
V
SID199
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
V
SID200
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
V
SID201
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
V
SID202
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
V
SID203
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
V
SID204
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
V
SID205
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
V
SID206
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
V
SID207
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
V
SID208
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
V
SID209
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
V
SID210
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
V
SID211
LVI_IDD
Block current
–
–
100
µA
Min
Typ
Max
Units
Details/Conditions
–
–
1
µs
Guaranteed by characterization
Guaranteed by characterization
Table 31. Voltage Monitors AC Specifications
Spec ID
SID212
Parameter
TMONTRIP
Description
Voltage monitor trip time
Document Number: 001-96519 Rev. *E
Page 28 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
SWD Interface
Table 32. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID213
F_SWDCLK1
3.3 V  VDD  5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V  VDD  3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
ns
Guaranteed by
characterization
SID216
T_SWDI_HOLD
0.25*T
–
–
ns
Guaranteed by
characterization
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by
characterization
SID217A
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by
characterization
Min
Typ
Max
Units
T = 1/f SWDCLK
Internal Main Oscillator
Table 33. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID218
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
SID219
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
SID220
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
SID221
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
SID222
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
Details/Conditions
Table 34. IMO AC Specifications
Min
Typ
Max
Units
Details/Conditions
SID223
Spec ID
FIMOTOL1
Parameter
Frequency variation from 3 to
48 MHz
Description
–
–
±2
%
±3% if TA > 85 °C and
IMO frequency <
24 MHz
SID226
TSTARTIMO
IMO startup time
–
–
12
µs
SID227
TJITRMSIMO1
RMS Jitter at 3 MHz
–
156
–
ps
SID228
TJITRMSIMO2
RMS Jitter at 24 MHz
–
145
–
ps
SID229
TJITRMSIMO3
RMS Jitter at 48 MHz
–
139
–
ps
Internal Low-Speed Oscillator
Table 35. ILO DC Specifications
(Guaranteed by Design)
Min
Typ
Max
Units
SID231
Spec ID
IILO1
Parameter
ILO operating current at 32 kHz
Description
–
0.3
1.05
µA
Guaranteed by
Characterization
SID233
IILOLEAK
ILO leakage current
–
2
15
nA
Guaranteed by Design
Document Number: 001-96519 Rev. *E
Details/Conditions
Page 29 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 36. ILO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID234
TSTARTILO1
ILO startup time
–
–
2
ms
Guaranteed by characterization
SID236
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by characterization
SID237
FILOTRIM1
32 kHz trimmed frequency
15
32
50
kHz
Max ILO frequency is 70 kHz
if TA > 85 °C
Table 37. External Clock Specifications
Min
Typ
Max
Units
SID305
Spec ID
ExtClkFreq
Parameter
External Clock input Frequency
Description
0
–
48
MHz
Guaranteed by characterization
Details/Conditions
SID306
ExtClkDuty
Duty cycle; Measured at VDD/2
45
–
55
%
Guaranteed by characterization
Min
Typ
Max
Units
Table 38. Watch Crystal Oscillator (WCO) Specifications
Spec ID
Parameter
Description
Details / Conditions
IMO WCO-PLL calibrated mode
SID330
IMOWCO1
Frequency variation with IMO set to
3 MHz
–0.6
–
0.6
%
Does not include WCO
tolerance
SID331
IMOWCO2
Frequency variation with IMO set to
5 MHz
–0.4
–
0.4
%
Does not include WCO
tolerance
SID332
IMOWCO3
Frequency variation with IMO set to
7 MHz or 9 MHz
–0.3
–
0.3
%
Does not include WCO
tolerance
SID333
IMOWCO4
All other IMO frequency settings
–0.2
–
0.2
%
Does not include WCO
tolerance
WCO Specifications
SID398
FWCO
Crystal frequency
–
32.768
SID399
FTOL
Frequency tolerance
–
50
kHz
250
ppm
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
SID401
PD
Drive level
–
–
1
µW
SID402
TSTART
Startup time
–
–
500
ms
SID403
CL
Crystal load capacitance
6
–
12.5
pF
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
SID405
IWCO1
Operating current (high power mode)
–
–
8
uA
With 20-ppm crystal.
Table 39. Block Specs
Spec ID
SID257
Parameter
TWS24*
Description
Number of wait states at 24 MHz
Min
1
Typ
–
Max
–
Units
SID260
VREFSAR
Trimmed internal reference to SAR
–1
–
+1
%
SID261
FSARINTREF
–
–
100
SID262
TCLKSWITCH
SAR operating speed without
external reference bypass
Clock switching from clk1 to clk2 in
clk1 periods
3
–
4
Details/Conditions
CPU execution from Flash
Percentage of Vbg (1.024 V).
Guaranteed by characterization
ksps 12-bit resolution. Guaranteed
by characterization
Periods Guaranteed by design
* TWS24 is guaranteed by design
Document Number: 001-96519 Rev. *E
Page 30 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Ordering Information
The PSoC 4100M family part numbers and features are listed in the following table.
SRAM (KB)
UDB
Opamp (CTBm)
CSD
IDAC (1X7-Bit, 1-8-Bit)
Direct LCD Drive
12-bit SAR ADC
LP Comparators
TCPWM Blocks
SCB Blocks
CAN
GPIO
44-TQFP
48-TQFP
64-TQFP (0.5-mm pitch)
64-TQFP (0.8-mm pitch)
68-QFN
32
4
0
2
–
–
–
806 ksps
2
8
4
–
38
–
✔
–
–
–
CY8C4125AZI-M443 24
32
4
0
2
✔
–
✔
806 ksps
2
8
4
–
38
–
✔
–
–
–
MPN
4125 CY8C4125AZI-M433 24
Category
Flash (KB)
Package
Max CPU Speed (MHz)
Features
CY8C4125AZI-M445 24
32
4
0
2
✔
–
✔
806 ksps
2
8
4
–
51
–
–
✔
–
–
CY8C4125LTI-M445 24
32
4
0
2
✔
–
✔
806 ksps
2
8
4
–
55
–
–
–
–
✔
CY8C4125AXI-M445 24
32
4
0
2
✔
–
✔
806 ksps
2
8
4
–
51
–
–
–
✔
–
4126 CY8C4126AZI-M443 24
64
8
0
2
✔
–
✔
806 ksps
2
8
4
–
38
–
✔
–
–
–
CY8C4126AXI-M443 24
64
8
0
2
✔
–
✔
806 ksps
2
8
4
–
36
✔
–
–
–
–
CY8C4126AZI-M445 24
64
8
0
2
✔
–
✔
806 ksps
2
8
4
–
51
–
–
✔
–
–
CY8C4126AZI-M475 24
64
8
0
4
–
✔
–
806 ksps
2
8
4
–
51
–
–
✔
–
–
CY8C4126LTI-M445 24
64
8
0
2
✔
–
✔
806 ksps
2
8
4
–
55
–
–
–
–
✔
CY8C4126LTI-M475 24
64
8
0
4
–
✔
–
806 ksps
2
8
4
–
55
–
–
–
–
✔
CY8C4126AXI-M445 24
64
8
0
2
✔
–
✔
806 ksps
2
8
4
–
51
–
–
–
✔
–
4127 CY8C4127LTI-M475 24
128
16
0
4
✔
✔
–
806 ksps
2
8
4
–
55
–
–
–
–
✔
CY8C4127AZI-M475 24
128
16
0
4
–
✔
–
806 ksps
2
8
4
–
51
–
–
✔
–
–
CY8C4127AZI-M485 24
128
16
0
4
✔
✔
✔
806 ksps
2
8
4
–
51
–
–
✔
–
–
CY8C4127AXI-M485 24
128
16
0
4
✔
✔
✔
806 ksps
2
8
4
–
51
–
–
–
✔
–
Document Number: 001-96519 Rev. *E
Page 31 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
4
A
B
Cypress Prefix
Architecture
Family
CPU Speed
C
Flash Capacity
DE
Package Code
F
Temperature Range
S
Silicon Family
XYZ
Attributes Code
Values
Meaning
4
1
4
4
5
6
7
AX, AZ
LQ
BU
FD
I
Q
N/A
L
BL
M
000-999
PSoC 4
4100 Family
48 MHz
16 KB
32 KB
64 KB
128 KB
TQFP
QFN
BGA
CSP
Industrial
Extended Industrial
PSoC 4 Base Series
PSoC 4 L-Series
PSoC 4 BLE
PSoC 4 M-Series
Code of feature set in the specific family
Part Numbering Conventions
The part number fields are defined as follows.
CY8C
4 A B C D E F -
S
XYZ
Cypress Prefix
Architecture
Family Group within Architecture
Speed Grade
Flash Capacity
Package Code
Temperature Range
Silicon Family
Attributes Code
Document Number: 001-96519 Rev. *E
Page 32 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Packaging
The description of the PSoC4100M package dimensions follows.
Spec ID#
Package
Description
Package Dwg #
PKG_1
68-pin QFN
68 QFN, 8 mm x 8 mm x 1.0 mm height
with 0.4 mm pitch
001-09618
PKG_2
64-pin TQFP
64 TQFP, 10 mm x10 mm x 1.4 mm
height with 0.5 mm pitch
51-85051
PKG_4
64-pin TQFP
64 TQFP, 14 mm x14 mm x 1.4 mm
height with 0.8 mm pitch
51-85046
PKG_5
48-pin TQFP
48 TQFP, 7 mm x 7 mm x 1.4 mm height
with 0.5 mm pitch
51-85135
PKG_6
44-pin TQFP
44 TQFP, 10 mm x 10 mm x 1.4 mm
height with 0.8 mm pitch
51-85064
Table 40. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
25
85
°C
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package θJA (68-pin QFN)
–
16.8
–
°C/Watt
TJC
Package θJC (68-pin QFN)
–
2.9
–
°C/Watt
TJA
Package θJA (64-pin TQFP, 0.5-mm pitch)
–
56
–
°C/Watt
TJC
Package θJC (64-pin TQFP, 0.5-mm pitch)
–
19.5
–
°C/Watt
TJA
Package θJA (64-pin TQFP, 0.8-mm pitch)
–
66.4
–
°C/Watt
TJC
Package θJC (64-pin TQFP, 0.8-mm pitch)
–
18.2
–
°C/Watt
TJA
Package θJA (48-pin TQFP, 0.5-mm pitch)
–
67.3
–
°C/Watt
TJC
Package θJC (48-pin TQFP, 0.5-mm pitch)
–
30.4
–
°C/Watt
TJA
Package θJA (44-pin TQFP, 0.8-mm pitch)
–
57
–
°C/Watt
TJC
Package θJC (44-pin TQFP, 0.8-mm pitch)
–
25.9
–
°C/Watt
Table 41. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All packages
260 °C
30 seconds
Table 42. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
All packages
Document Number: 001-96519 Rev. *E
MSL
MSL 3
Page 33 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Figure 5. 68-Pin 8 × 8 × 1.0 mm QFN Package Outline
001-09618 *E
Figure 6. 64-Pin 10 × 10 × 1.4 mm TQFP Package Outline
51-85051 *D
Document Number: 001-96519 Rev. *E
Page 34 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Figure 7. 64-Pin 14 × 14 × 1.4 mm TQFP Package Outline
51-85046 *G
Figure 8. 48-Pin 7 × 7 × 1.4 mm TQFP Package Outline
51-85135 *C
Document Number: 001-96519 Rev. *E
Page 35 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Figure 9. 44-Pin 10 × 10 × 1.4 mm TQFP Package Outline
51-85064 *G
Document Number: 001-96519 Rev. *E
Page 36 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Acronyms
Table 43. Acronyms Used in this Document (continued)
Table 43. Acronyms Used in this Document
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
flash patch and breakpoint
Acronym
Acronym
Description
Description
abus
analog local bus
FPB
ADC
analog-to-digital converter
FS
full-speed
AG
analog global
GPIO
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
IIR
ATM
automatic thump mode
ILO
internal low-speed oscillator, see also IMO
BW
bandwidth
IMO
internal main oscillator, see also ILO
CAN
Controller Area Network, a communications
protocol
INL
integral nonlinearity, see also DNL
CMRR
common-mode rejection ratio
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CPU
central processing unit
IPOR
initial power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
IPSR
interrupt program status register
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMIPS
Dhrystone million instructions per second
LR
link register
DMA
direct memory access, see also TD
LUT
lookup table
DNL
differential nonlinearity, see also INL
LVD
low-voltage detect, see also LVI
DNU
do not use
LVI
low-voltage interrupt, see also HVI
DR
port write data registers
LVTTL
low-voltage transistor-transistor logic
DSI
digital system interconnect
MAC
multiply-accumulate
DWT
data watchpoint and trace
MCU
microcontroller unit
ECC
error correcting code
MISO
master-in slave-out
ECO
external crystal oscillator
NC
no connect
electrically erasable programmable read-only
memory
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
EMI
electromagnetic interference
NVIC
nested vectored interrupt controller
EMIF
external memory interface
NVL
nonvolatile latch, see also WOL
EOC
end of conversion
opamp
operational amplifier
EOF
end of frame
PAL
programmable array logic, see also PLD
EPSR
execution program status register
PC
program counter
ESD
electrostatic discharge
PCB
printed circuit board
EEPROM
Document Number: 001-96519 Rev. *E
2C,
I
or IIC
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
Page 37 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
USB
Universal Serial Bus
PRES
precise power-on reset
USBIO
PRS
pseudo random sequence
USB input/output, PSoC pins used to connect to
a USB port
PS
port read data register
VDAC
voltage DAC, see also DAC, IDAC
PSoC®
Programmable System-on-Chip™
WDT
watchdog timer
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
Document Number: 001-96519 Rev. *E
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 38 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Document Conventions
Units of Measure
Table 44. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt

ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 001-96519 Rev. *E
Page 39 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4100M Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-96519
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
*A
4765455
WKA
05/20/2015 Release to web.
*B
4815539
WKA
06/29/2015 Removed note regarding hardware handshaking in the UART Mode section.
Changed max value of SID51A to 2 ms.
Added “Guaranteed by characterization” note for SID65 and SID65A
Updated Ordering Information.
*C
4941619
WKA
09/30/2015 Updated CapSense section.
Updated the note at the end of the Pinout table.
Removed Conditions for spec SID237.
*D
5026805
WKA
11/26/2015 Added Comparator ULP mode range restrictions and corrected typos.
*E
5408936
WKA
08/19/2016 Added extended industrial temperature range.
Added specs SID290Q, SID182A, and SID299A.
Updated conditions for SID290, SID223, and SID237.
Added 44-pin TQFP package details.
Updated Ordering Information
Document Number: 001-96519 Rev. *E
Page 40 of 41
PSoC® 4: PSoC 4100M Family
Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
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Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
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USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-96519 Rev. *E
Revised August 19, 2016
Page 41 of 41