AMD AM7996PC Ieee 802.3/ethernet/cheapernet transceiver Datasheet

FINAL
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver
DISTINCTIVE CHARACTERISTICS
■ Compatible with Ethernet Version 2 and
IEEE 802.3 10BASE-5 and10BASE-2
specifications
■ Pin-selectable SQE Test (heartbeat) option
■ Internal jabber controller prevents excessive
transmission time
■ Noise rejection filter ensures that only valid data
is transmitted onto the network
■ Collision detection on both transmit and receive
data
■ Collision detect threshold levels adjustable for
other networking applications
GENERAL DESCRIPTION
The Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver suppor ts Ethernet Version 2, IEEE 802.3
10BASE-5 and IEEE 802.3 10BASE-2—Cheapernet)
transceiver applications. Transmit, receive, and collision detect functions at the coaxial media interface to
the data terminal equipment (DTE) are all performed by
this single device.
In an IEEE 802.3 (10BASE-5)/Ethernet application, the
Am7996 interfaces the coaxial (0.4″ diameter) media to the
DTE through an isolating pulse transformer and the 78 Ω
attachment unit interface (AUI) cable. In IEEE 802.3
10BASE-2—Cheapernet applications, the Am7996 typically resides inside the DTE with its signals to the DTE isolated and the coaxial (0.2″ diameter) media directly
connected to the DTE. Transceiver power and ground in
both applications are isolated from that of the DTE.
The Am7996’s tap driver provides controlled skew and
current drive for data signaling onto the media. The jabber
controller prevents the node from transmitting excessively. While transmitting, collisions on the media are detected if one or more additional stations are transmitting.
The Am7996 features an optional SQE Test function
that provides a signal on the Cl pair at the end of every
transmission. The SQE Test indicates the operational
status of the Cl pair to the DTE. It can also serve as an
acknowledgment to the node that packet transmission
onto the coax was completed.
BLOCK DIAGRAM
Carrier
Detect
Circuit
DI+
Line
Driver
Control
Logic
CI+
Input
Buffer
RXT
Collision
Detect
Circuit
Line
Driver
Control
Logic
CI–
Coaxial Media Interface
AUI Interface
DI–
Receive
Data
Amplifier
Jabber
Timer
SQE Test
Generator
Transmit
Squelch
DO+
DO–
SQE TEST
Publication# 07506 Rev: E Amendment/0
Issue Date: May 1994
Input
Buffer
Transmit
Data
Amplifier
Tap
Driver
TXT
07506E-1
1
AMD
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PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Plug n’ Play Support)
Am79C965
PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses)
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PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
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PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
CONNECTION DIAGRAMS
20
VCC2
CI+
2
19
COLL OSC
CI–
3
18
VCOL
DI+
4
17
NC
DI–
5
16
RXT
VCREF
6
15
NC
SQE^TEST
7
14
TAP SHIELD
DO+
8
13
VTX–
DO–
9
12
TXT
10
11
VTX+
SQE^TEST
DO+
07506E-2
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
VCOL
NC
RXT
NC
TAP SHIELD
07506E-3
Notes:
Pin 1 is marked for orientation.
NC = No Connection
2
4
5
6
7
8
DO–
VEE
VTX+
VEE
DI+
DI–
VCREF
TXT
VTX–
1
CI–
VCC1
COLL OSC
PLCC
CI+
VCC1
VCC2
DIP
Am7996
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
AM7996
D
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
TR = Tape and Reel Packaging
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
D = 20-Pin Ceramic DIP (CD 020)
J = 20-Pin Plastic Leaded Chip Carrier (PL 020)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver
Valid Combinations
Valid Combinations
AM7996
PC, PCB, DC, DCB,
JC, JCTR
Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am7996
3
PIN DESCRIPTION
Attachment Unit Interface (AUI)
Dl+, Dl–
Global Signals
VCREF
Receive Line Output (Differential Outputs)
This pair is intended to operate into terminated 78 Ω
transmission lines. Signals at RXT meeting bandwidth
requirements and carrier sense levels are outputted at
Dl ± . Signaling at Dl ± meets requirements of
IEEE 802.3, Rev. D.
Cl+, Cl–
Collision Line Output (Differential Outputs)
This pair is intended to operate into terminated 78 Ω
transmission lines. Signal Quality Error (SQE), detected at DO ± inputs (excessive transmissions) or RXT
input (during a collision), outputs the 10 MHz internal
oscillator signal to the AUI interface. For proper component values at COLL OSC, signaling at Cl ± meets requirements of IEEE 802.3, Rev. D.
DO+, DO–
Transmit Input (Differential Inputs)
A pair of internally biased line receivers consisting of a
squelch detect receiver with offset and noise filtering
and a data receiver with zero offset for data signal processing. Signals meeting squelch requirements are
waveshaped and output at TXT.
Coaxial Media Interface (TAP)
RXT
Media Signal Receiver Input (Input)
RXT connects to the media through a 4:1 attenuator of
100 kΩ total resistance (25 kΩ and 75 kΩ in series).
Return for the attenuator is VCOL. RXT is an analog
input with internal AC coupling for Manchester data signals and direct coupling for Carrier Detect and SQE average level detection. Signals at RXT meeting carrier
squelch enable data to the Dl ± outputs. Data signals
are AC coupled to Dl ± with a 150 ns time constant,
high-pass filter. Signals meeting SQE levels enable
COLL OSC frequency to Cl ± outputs.
TXT
Tap Node Driver (Input/Output)
A controlled bandwidth current source and sense amplifier. This l/O port is to be connected to the media
through an isolation network and a low-pass filter. Signals meeting DO ± squelch and jabber timing requirements are output at TXT as a controlled rise and fall
time current pulse. When operated into a double terminated 50 Ω transmission line, signaling meets
IEEE 802.3, Rev. D recommendations for amplitude,
pulse-width distortion, rise and fall times, and harmonic
content. The sense amplifier monitors TXT faults and
inhibits transmission.
Timing Reference Set (Input)
VCREF is a compensated voltage reference input with
respect to VEE. When a resistor is connected between
VCREF and V EE , then internal transmit and receive
squelch timing, SQE oscillator frequency, and receive
and SQE output drive levels are set. SQE frequency
set is also determined by components connected between VCC1 and COLL OSC.
SQE TEST
Signal Quality Error Test Enable (Input)
The SQE Test function is enabled by connecting the
SQE TEST pin to VEE and disabled by connecting to VCC.
VTX+, VTX–
Tap Node Driver Current Set (Inputs)
A reference input for transmission level and external redundant jabber. Transmit level is set by an external resistor between VTX+ and VTX– (for an 80 mA peak level,
R = 9.09 Ω). VTX– may be operated between VEE and
VEE + 1 V. When the voltage at VTX– goes more positive
than VEE + 2 V, TXT is disabled and an SQE message
is output at the Cl pair.
TAP SHIELD
Low-Noise Media Cable Return (Input)
This input is the return for VCOL reference and the receive signal from the media. External connection is to
a positive power supply.
VCOL
SQE Reference Voltage (Bias Supply)
SQE sense voltage and RXT input amplifier reference.
An internally set analog reference for SQE level and data
signal set at –1.600 V nominal with a source resistance
of 150 Ω nominal. This reference should be filtered with
respect to TAP SHIELD (see Applications section for adjusting threshold levels for other applications).
COLL OSC
SQE Timing Set (Input)
Timing input for SQE oscillator. For a properly set input
at VCREF, SQE oscillator period is set at 2.1RC. For a
10 MHz SQE oscillator frequency, R should be 1 kΩ and
C 47 pF, including interconnect and device capacitance.
VCC1
Positive Logic Supply
VCC2
SQE Timing Reference (Positive Supply Voltage)
Timing reference return for SQE oscillator and analog
signal ground.
VEE
Negative Logic Supply and IC Substrate
4
Am7996
FUNCTIONAL DESCRIPTION
The Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver consists of four sections: 1) Transmit—receives
signals from DTE and sends it to the coaxial medium;
2) Receive—obtains data from media and sends it to
DTE; 3) Collision Detect—indicates to DTE any collision on the media; and 4) Jabber—guards medium
from node transmissions that are excessive in length.
Transmit
The Am7996 receives differential signals from the DTE
(in the case of Am7990 family applications, from the
Am7992 —serial interface adapter—SIA). For IEEE
(10BASE-5)/Ethernet applications, this signal is received through the AUI cable and isolation transformer.
In IEEE 802.3 10BASE-2—Cheapernet applications,
the AUI cable is optional.
Data is received through a noise rejection filter that rejects signals with pulse widths less than 7 ns (negative
going), or with levels less than 175 mV peak. Only signals greater than –275 mV peak from the DTE are enabled. This minimizes false starts due to noise and
ensures that no valid packets are missed.
The Am7996’s tap driver provides the driving capability
to ensure adequate signal level at the end of the maximum length network segment (500 meters) under the
worst-case number of connections (100 nodes). Required rise and fall times of data transmitted on the network are maintained by the Am7996 Tap Driver. The tap
driver’s output is connected to the media through external isolating diodes. To safeguard network integrity, the
driver is disabled whenever power falls below the minimum operation voltage.
During transmission, the Am7996 Jabber Controller
monitors the duration that the transmit tap driver is active and disables the driver if the jabber time is exceeded. This prevents network tie-up due to a
“babbling” transceiver. Once disabled, the driver is not
reset until 400 ms after the DO pair is idle and there is
no fault on TXT. During the disable time, an SQE signal
is sent on the Cl pair to the DTE.
When SQE TEST is tied to VEE, the Am7996 generates
an SQE message at the end of every transmission. This
signal is a self-test indication to the DTE that the media
attachment unit (MAU) collision pair is operational.
Receive and Carrier Detect
Signal is acquired from the tap through a highimpedance (100 kΩ) resistive divider. A high inputimpedance (low capacitance, high bandwidth, low
noise) DC-coupled input amplifier in the Am7996 receives the signal. The received signal passes through
a high-pass filter to minimize inter-symbol distortion,
and then through a data slicer. The Am7996 Carrier
Detect compares received signals to a reference.
Signals meeting carrier squelch requirements enable
data to the differential line driver within five bit times
from the start of the packet.
Received data is transmitted from the Dl pair through
an isolation transformer to the AUI cable (Ethernet/
lEEE 802.3—10BASE-5). In IEEE 802.3 10BASE-2—
Cheapernet, the AUI cable is optional. Following the
last transition of the packet, the Dl pair is held HIGH for
two bit times and then decreases to idle level within
twenty bit times.
Collision Detect
The Am7996 detects collisions on transmit if one or
more additional stations are transmitting on the network.
Received signals are compared against the collision
threshold reference. If the level is more negative than
the reference, an enable signal is generated to the Cl
pair. The collision threshold can be modified by
external components.
The collision oscillator is a 10 MHz oscillator that drives
the differential Cl pair to the DTE through an isolation
transformer.
This signal is gated to the Cl pair whenever there is a
collision, the SQE Test is in progress, or the jabber controller is activated. The oscillator is also utilized in
counting time for the jabber timer and SQE Test.
The Cl ± output meets the drive requirements for the
AUI interface. The output stays HIGH for two bit times
at the end of the packet, decreasing to the idle level
within twenty bit times.
Jabber Function
The Am7996 Jabber Timer monitors the activity on the
DO pair and senses TXT faults. It inhibits transmission
if the tap driver is active for longer than the jabber time
(26 ms). An SQE message (10 MHz collision signal), is
enabled on the Cl pair for the fault duration.
After the fault is removed, the jabber timer counts the
unjab time of 400 ms before it enables the driver.
If desired, a redundant jabber function can be implemented externally, and the output driver disabled by removing the driver supply at VTX–.The Am7996 senses
this condition and forces an SQE message on the Cl
pair during the disable time.
SQE Test
An SQE Test will occur at the end of every transmission
if the SQE TEST pin is tied to VEE. The SQE Test signal
is a gated 10 MHz signal to the Cl pair. The SQE Test ensures that the twisted-pair assigned for collision notification to the DTE is intact and operational. The SQE Test
starts eight bit times after the last transition of the transmitted signal and lasts for a duration of eight bit times.
The SQE Test can be disabled by connecting the
SQE TEST pin to VCC.
Am7996
5
AMD
APPLICATIONS
The Am7996 is compatible with Ethernet Version 2 and
IEEE 802.3 10BASE5 and 10BASE2 applications. (See
Figure 1).
MAU
Local
CPU
AUI
Cable
DTE
Ethernet
Local
Memory
Am7990
LANCE
Tap
Am7996
Transceiver
Am7992B
SIA
Power
Supply
Local Bus
AUI - Attachment Unit Interface
DTE - Data Terminal Equipment
MAU - Media Access Unit
Cheapernet
DTE
Ethernet
Coax
Local
CPU
Local
Memory
Am7990
LANCE
Am7996
Transceiver
Am7992B
SIA
RG58
BNC "T"
Power
Supply
Local Bus
07506E-4
Figure 1. Typical Ethernet Node
Table 1.
Transmit Mode Collision Detect
Function Table
MAU
Mode of Operation
Table 3.
Number of Transmitters
<2
=2
>2
Receive Mode Collision Detect
Function Table
MAU
Mode of Operation
<2
=2
>2
Transmitting
No
Yes
Yes
Transmitting
No
Yes
Yes
Not Transmitting
No
May
Yes
Not Transmitting
No
Yes
Yes
Table 2.
IEEE 802.3 Recommended Transmit
Mode Collision Detect Thresholds
Table 4.
IEEE 802.3 Recommended Receive
Mode Collision Detect Thresholds
Threshold Voltage Level
IEEE 802.3
No Detect
Threshold Voltage Level
Must Detect
10BASE5, Ethernet
–1.492 V
–
10BASE2, Cheapernet
–1.404 V
–1.782 V
6
Number of Transmitters
IEEE 802.3
No Detect
Must Detect
10BASE5, Ethernet
–1.492 V
–1.629 V
10BASE2, Cheapernet
–1.404 V
–1.581 V
Am7996
AMD
levels of the Am7996 are implemented by adding R9,
R10 and C4. For the values of the components shown in
Figure 3, a nominal receive mode collision detect
threshold of –1.5 V, for a –1.404 V to –1.581 V window,
is achieved.
Figure 2 is an external component diagram showing
how to implement the transmit mode collision detect
levels recommended by IEEE 802.3. Figure 3 on the
following page shows how to implement the receive
mode collision detect levels recommended by
IEEE 802.3. Receive mode collision detect threshold
PE64102/PE64107 (or equivalent)
(75 µH)
1:1
1
VCC2 20
VCC1
1%
R4
1.1 kΩ
C1
39 pF
C2
0.1 µF
Coax
Connector
(Note 6)
COLL
1:1
2 CI+
COLL OSC 19
3 CI–
VCOL 18
4 DI+
NC 17
CL
(Note 1)
Am7996
RCV
R3
174 Ω
1%
1:1
R5
75 kΩ
RXT 16
1%
6
NC 15
VCREF
(Note 5)
Tap 14
7 SQE^TEST
Shield
(Note 3)
8 DO+
VTX- 13
R1
40.2 Ω
1%
R2
40.2 Ω
1%
XMT
5 DI–
R6
24.9 kΩ
1%
180 pF
C3
1N4001
D3
R7
9 DO–
TXT 12
10 VEE
VTX+ 11
R8
9.09 Ω
1%
CC (Note 1)
(Note 2)
D2
9.09 Ω
1%
D1
1N4150
–9 V
Power (DTE)
GND
MAU Power Supply
(Note 4)
07506E-5
Notes:
1.
CL is the effective load capacitance across R6; CC is the compensation capacitance (CC = 1/3 CL).
2.
D2 can be eliminated in Cheapernet (IEEE 802.3, 10BASE2) applications.
3.
Shown with SQE Test disabled.
4.
Discrete Power Supply or Hybrid-Hybrid DC-DC Converter Manufacturers include:
Ethernet (IEEE 802.3, 10BASE5)
Reliability: 2E12R9
Valor Electronics: PM1001
Cheapernet (IEEE 802.3, 10BASE2)
Reliability Inc: 2VP5U9
Valor Electronics: PM7102
5.
The capacitance of C3, Am7996 package, D3 and the printed circuit board should add up to 180 pF ± 20%.
6.
The capacitance of C1, Am7996 package and the printed circuit board should add up to 39 pF.
7.
Figure 2 used for production testing of all parameters that are tested.
Figure 2. Am7996 External Component Diagram for Transmit Mode Collision Detect
Am7996
7
AMD
PE64102/PE64107 (or equivalent)
(75 µH)
1:1
1
VCC2 20
VCC1
1%
R4
1.1 kΩ
C1
39 pF
C2
0.1 µF
Coax
Connector
(Note 6)
COLL
1:1
COLL OSC 19
3 CI–
VCOL 18
4 DI+
RCV
R3
174 Ω
1%
1:1
5 DI–
6
C4 0.1 µF
R9
NC 17 499 Ω
Am7996
1%
RXT 16
(Note 7)
CL
(Note 1)
R6
24.9 kΩ
1%
180 pF
C3
1N4001
D3
R7
(Note 5)
9 DO–
TXT 12
10 VEE
VTX+ 11
9.09 Ω
1%
R5
75 kΩ
1%
R10
150 kΩ
1%
NC 15
VCREF
Tap 14
7 SQE^TEST
Shield
(Note 3)
VTX– 13
8 DO+
R1
40.2 Ω
1%
R2
40.2 Ω
1%
XMT
2 CI+
CC (Note 1)
(Note 2)
D2
9.09 Ω
1%
D1
1N4150
–9 V
Power (DTE)
GND
MAU Power Supply
(Note 4)
07506E-6
Notes:
1.
CL is the effective load capacitance across R6; CC is the compensation capacitance (CC = 1/3 CL).
2.
D2 can be eliminated in Cheapernet (IEEE 802.3, 10BASE2) applications.
3.
Shown with SQE Test disabled.
4.
Discrete Power Supply or Hybrid-Hybrid DC-DC Converter Manufacturers include:
Ethernet (IEEE 802.3, 10BASE5)
Reliability: 2E12R9
Valor Electronics: PM1001
Cheapernet (IEEE 802.3, 10BASE2)
Reliability Inc: 2VP5U9
Valor Electronics: PM7102
5.
The capacitance of C3, Am7996 package, D3 and the printed circuit board should add up to 180 pF ± 20%.
6.
The capacitance of C1, Am7996 package and the printed circuit board should add up to 39 pF.
7.
R9, R10 and C4 are for Receive Mode Collision detection only.
Figure 3. Am7996 External Component Diagram with Collision Threshold Modified
for Receive Mode Collision Detect
8
Am7996
AMD
LAYOUT CONSIDERATIONS
To protect the transceiver from the environment and to
achieve optimum performance, the Am7996 is designed
to be used with two sets of external components: the
transmitter circuit consisting of components D1, D2, D3,
R7, R8, and C3, and the receiver circuit consisting of
components R5, R6, CL, and CC, (CL is a parasitic capacitance rather than a discrete component). These two
circuits are shown in both Figure 2 and in Figure 3 respectively. The resistor tolerances for these circuits are
specified as 1% for temperature stability.
The only layout restriction for the transmitter circuit is
that the longest current path from the TXT pin (Pin 12) to
the coaxial cable’s center conductor must be no longer
than 4 inches.
The layout of the receiver circuit, however, is critical. To
minimize parasitic capacitance that can degrade the received signal, the external receiver circuit should be isolated from power and ground planes. There must be no
power or ground plane under the area of the PC board
that includes pins 15 through 20, R5, R6, and the connector for the coaxial cable. If a power or ground plane
extends under this area, the receiver will not function
properly due to excessive crosstalk and under- or overcompensation of the R5, R6 attenuator. Also, the RXT
pin (Pin 16) should be as close to the coaxial cable
connector as possible.
If the above layout rules are followed, the parasitic
capacitance in parallel with R6 will be about 6 pF. This
parasitic capacitance is shown in the schematics as CL
(Note that CL is a parasitic capacitance. Do not add a
discrete capacitor in parallel with R6). The capacitor
labeled CC in the schematics is the total capacitance in
parallel with R5 including parasitic capacitance. The
parasitic component of CC will be about 1 pF. For optimum performance, the ratio of CL to CC should be the
same as the ration of R5 to R6, which is 3 to 1. This
means that an additional 1 pF of capacitance must be
added in parallel with R5.
This additional capacitance can easily be added by
building a parallel-plate capacitor for PC traces right under resistor R5. This capacitor can consist of a 0.200 in.
by 0.200 in. square of conductor on each side of the
board as shown in Figure 4-2 (These dimensions assume that the PC board is made from 0.060 in. thick
G-10 material). The top plate of the capacitor should be
connected to one lead of R5, and the bottom plate
should be connected to the other lead. Figure 4-3 shows
an example of this suggested layout for a four layer
printed circuit board. Note that the component labeling
used in Figure 4-3 is not intended to correspond with the
component labeling used in Figure 2 and Figure 3.
Since there are no severe layout restrictions on the
transmitter circuit, the layout can be simplified by omitting power and ground planes from the whole area on
the right side of the Am7996 as shown in Figure 4-1.
R5
Circuit
Side
Component
Side
20
RXT
0.200 in x 0.200 in
two planes
R5, R6, R4
C1, C2
07506E-8
Am7996
TXT
D1, D2, D3
R7, R8
C3
Figure 4-2.
Coax
Connector
11
Area with no power or ground plane
07506E-7
Figure 4-1.
Am7996
9
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
Under Bias . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltages (VEE, VTX–) . . . . . –12.0 V to +0.5 V
DC Input Voltage (D0+, D0–) . . . . –12.0 V to +0.5 V
DC Input Voltage (RXT) . . . . . . . . . . . –6 V to +0.5 V
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . 0°C to +70°C
Supply Voltage (VEE) . . . . . . . . . . –8.1 V to –9.9 V
Operating ranges define those limits between which the functionality of the device is guaranteed
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied Exposure to absolute maximum ratings for extended periods may affect device reliability.
Am7996
11
AMD
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions (Note 10)
Commercial
Min
Typ
Max
Unit
Transmit Signals
VTXTH
Transmit Output HIGH Voltage (Note 1)
RLX = 25 Ω
0
–0.05
–0.425
V
VTXTL
Transmit Output LOW Voltage (Note 1)
RLX = 25 Ω
–1.625
–2.0
–2.2
V
VTXT
Transmit Average DC Voltage with 50%
Duty-Cycle into DO+, DO– (Note 1)
RLX = 25 Ω
–0.925
–1.0
–1.1
V
VICM
DO+, DO– Common Mode Bias
Voltage
IIN = 0
VEE
+ 1.2
VEE
+ 1.5
VEE
+ 1.8
V
VIDC
Differential Input Squelch Threshold
(DO+, DO–) (Note 9)
–175
–225
–275
mV
ITXTL
Transmit Current (Note 9)
–88
mA
VTXT = –5.5 V
IILD
IIHD
Input Current (DO+, DO–)
VEE = Max
–65
VIN = VEE Max
–2.0
VIN = 0
2.5
RIDF
Differential Input Resistance (DO+, DO–)
RICM
Common-Mode Input Resistance (DO+, DO–) VIN = 0 to VEE
VIN = 0 to VEE
mA
6
8
kΩ
1.5
2
kΩ
VOD+
VOD–
+550
–550
+670
–670
+850
–850
mV
–1.0
–2.0
–3.0
V
5
20
mV
Receive/Collision Signals
VOD
Differential Output Voltage
(DI+, DI–; CI+, CI–)
RL = 78 Ω
VCMT
Common-Mode Output
(DI+, DI–; CI+, CI–)
RL = 78 Ω
VODI
Differential Output Voltage Imbalance
(DI+, DI–; CI+, CI–) ||VOD| – |VOD|| (Note 6)
RL = 78 Ω
Differential Output Idle Voltage
(DI+, DI–; CI+, CI–)
RL = 78 Ω, VEE = Max
–20
0
+20
mV
VCAT
Carrier Sense Threshold
VIN = 5 MHz Preamble
–400
–500
–600
mV
VCOT
Collision Sense Threshold (Note 5)
–1515 –1600
–1700
mV
IRXT
RXT Input Bias Current
VIN = 1 V to –2.5 V;
VEE = Max
–0.5
0
+0.5
µA
Differential Output Idle Current
(DI+, DI–; CI+, CI–)
RL = 0
–0.5
0
+0.5
mA
–88
–105
–128
–155
Typ
Max
VOD OFF
IOD OFF
Global
Supply Current–Non-Transmitting
IEE
Supply Current–Transmitting
RLX = 25 Ω (Note 4)
mA
CAPACITANCE* (TA = 25°C; VEE = 0; Pins 15, 17—No Connections)
Parameter
Symbol
CRXT
Parameter Description
RXT Input Capacitance
Test Conditions
1.7
Plastic DIP/PLCC
1.1
Notes:
See notes following Switching Characteristics section.
*Parameters are not “Tested.”
12
Min
Ceramic DIP
Am7996
Unit
pF
AMD
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
No
Parameter
Symbol
Test Conditions
Commercial
Min
Typ
Max
Unit
DO± Input Pulse Width to Reject
(DO± ≥ VIDC, Max)
(Note 1)
15
ns
DO± Input Pulse Width to Turn On
(DO± > VIDC, Max)
(Note 1)
DO± Input Pulse Width to Stay On
(DO± ≥ VIDC, Max)
(Note 1)
DO± Input Pulse Width to Turn Off
(DO± ≥ VIDC, Max)
(Note 1)
Parameter Description
Receiver Specification
1
2
3
4
tPWREJ
tPWTON
tPWSON
tPWOFF
5
tTON
Transmit Driver Turn-On Delay
(Note 1)
7
tTSD
Transmit Static Delay (Zero Crossing
to 50% Point to Coax)
(Note 1)
20
7
15
ns
105
160
ns
ns
200
ns
30
50
ns
8
tTXTR
Transmit Driver Rise Time
(Notes 1, 7)
20
25
30
ns
9
tTXTF
Transmit Driver Fall Time
(Notes 1, 7)
20
25
30
ns
10
tDRF
Difference in Driver Rise and Fall
Times |tTXTR–tTXTF|
(Notes 1, 7)
1.0
ns
+2.0
ns
11
tSKEW
Output Driver Skew—Transmit Data
Symmetry
(Note 1)
–2.0
12
tJCT
Jabber Control Time
(Note 1)
20
26
35
ms
13
tJRT
Jabber Reset Time
(Note 1)
340
419
500
ms
14
tJREC
Jabber Recovery Time
(Note 1)
1.0
µs
500
ns
Receive/Collision Specification
15
tRON
Receiver Turn-On Delay
Vtap > VCAT Max
16
tROFF
Receiver Turn-Off Delay
Vtap < VCAT Min
1000
ns
17
tRSD
Receiver Static Delay
50% Point at RXT
at Zero Crossing
at DI± Outputs
50
ns
+2
%
20%–80%,
RL = 78 Ω
7
ns
80%–20%,
RL = 78 Ω
7
ns
18
tRS
Receive Data Symmetry
19
tRR
DI± and CI± Rise Time
20
tRF
250
–2
DI± and CI± Fall Time
21
tCON
CI± Turn-On Delay
Vtap > VCOT Max
900
ns
22
tCOFF
CI± Turn-Off Delay
Vtap < VCOT Min
2000
ns
23
tCL
CI± LOW Time
35
50
70.5
ns
24
tCH
CI± HIGH Time
35
50
70.5
ns
25
fCI
Collision Frequency
(Note 8)
8.5
10.0
11.5
MHz
26
tSTD
SQE Test Delay Time
FCI = 10.0 MHz
600
1000
ns
27
tSTL
SQE Test Length
FCI = 10.0 MHz
600
1000
ns
Am7996
800
13
AMD
Notes:
1. Parameters are measured at coax tap. In production test, parameters are measured across at 25 Ω load equivalent to the
coax tap.
2. For conditions shown as Min or Max, use the appropriate value specified under Operating Range for the applicable
device type.
3. Typical values are at VEE = –9.0 V, 25°C ambient.
4. VTX– wired to VEE.
5. This threshold can be modified externally (see Figure 3).
6. Parameter not tested.
7. Tested on a 5 Mbps preamble (continuous 1010 pattern) measured between 20% and 80% points, test limits correlated to
10% and 90% data sheet limits shown.
8. Determined by Am7966 External Component Diagrams values for R4 and C1.
9. In production test, input signal applied thru transformer to DO± inputs.
10. Figure 2 used for production testing of all parameters.
*Notes listed correspond to the respective references made in DC Characteristics and Switching Characteristics tables.
14
Am7996
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010
SWITCHING TEST CIRCUIT
+ 1/3 PE64102/PE64107 (or equivalent)
DUT
RL
–
78 Ω
75 µH
07506E-12
A. AUI Transmit (DI+, DI–,; CI+, CI–)
RLX = 25 Ω
07506E-13
B. Test Load (TXT)
Am7996
15
AMD
SWITCHING WAVEFORMS
0V
DO±
VIDC
2
90%
0V
COAX
TAP
50%
10%
(Transmit)
VTXTL
8
9
5
7
7
07506E-14
Transmit Function
NEAR END
0V
VCATmax
VCATmin
50%
COAX
TAP
(Receive)
VOD
0V
DI±
–VOD
15
17
17
17
17
16
07506E-15
Receiver Function
16
Am7996
AMD
SWITCHING WAVEFORMS
DO±
0V
0V
COAX
TAP
(Transmit)
VTXTL
VOD
CI±
0V
–VOD
26
27
07506E-16
SQE Test*
*SQE^TEST pin connected to VEE
50%
0V
DO±
0V
COAX
TAP
(Transmit)
VTXTL
50%
CI±
12
0V
13
07506E-17
Jabber Function
Am7996
17
AMD
SWITCHING WAVEFORMS
VOD
80%
DI±
CI±
0V
20%
–VOD
19
20
VOD
CI±
0V
–VOD
24
23
1/fCI
07506E-18
DI±/CI± Parameters
0V
COAX
TAP
VCOTMAX
VCOTMIN
–2 V
350 mV
CI±
VOD
0V
–VOD
21
22
07506E-19
Collision Detect Timing
Note:
This signal is used for test purposes. It represents the average value of the signal that might be seen on the coax tap when
a collision occurs.
18
Am7996