CET CED73A3 N-channel enhancement mode field effect transistor Datasheet

CED73A3/CEU73A3
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
30V, 65A, RDS(ON) = 7.8mΩ(typ) @VGS = 10V.
RDS(ON) = 10mΩ(typ) @VGS = 4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
D
Lead free product is acquired.
TO-251 & TO-252 package.
G
D
G
S
CEU SERIES
TO-252(D-PAK)
ABSOLUTE MAXIMUM RATINGS
Parameter
G
D
S
CED SERIES
TO-251(I-PAK)
Tc = 25 C unless otherwise noted
Symbol
Limit
30
Units
V
VGS
±20
V
ID
65
A
IDM
350
A
60
W
Drain-Source Voltage
VDS
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
S
PD
0.48
W/ C
Single Pulsed Avalanche Energy d
EAS
160
mJ
Single Pulsed Avalanche Current d
IAS
25
A
TJ,Tstg
-55 to 150
C
Operating and Store Temperature Range
Thermal Characteristics
Symbol
Limit
Units
Thermal Resistance, Junction-to-Case
Parameter
RθJC
2.1
C/W
Thermal Resistance, Junction-to-Ambient
RθJA
50
C/W
2005.March
http://www.cetsemi.com
6 - 122
CED73A3/CEU73A3
Electrical Characteristics
Parameter
Tc = 25 C unless otherwise noted
Symbol
Test Condition
Min
Drain-Source Breakdown Voltage
BVDSS
VGS = 0V, ID = 250µA
30
Zero Gate Voltage Drain Current
IDSS
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
Typ
Max
Units
VDS = 25V, VGS = 0V
1
µA
IGSSF
VGS = 20V, VDS = 0V
100
nA
IGSSR
VGS = -20V, VDS = 0V
-100
nA
Off Characteristics
V
On Characteristics b
Gate Threshold Voltage
VGS(th)
Static Drain-Source
RDS(on)
On-Resistance
Forwand Transconductance
Dynamic Characteristics
gFS
VGS = VDS, ID = 250µA
3
V
VGS = 10V, ID = 30A
1
7.8
9
mΩ
VGS = 4.5V, ID = 30A
10
13
mΩ
VDS = 10V, ID = 15A
20
S
2923
pF
506
pF
202
pF
c
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = 15V, VGS = 0V,
f = 1.0 MHz
Switching Characteristics c
Turn-On Delay Time
td(on)
Turn-On Rise Time
tr
Turn-Off Delay Time
td(off)
19
VDD = 15V, ID = 1A,
VGS = 10V, RGEN = 6Ω
23
ns
6.8
12
ns
71
128
ns
Turn-On Fall Time
tf
12.8
17.5
ns
Total Gate Charge
Qg
24
30
nC
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 15V, ID = 20A,
VGS = 4.5V
9.1
nC
7.5
nC
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
IS
Drain-Source Diode Forward Voltage b
VSD
VGS = 0V, IS = 20A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d.L = 0.5mH, IAS = 25A, VDD = 24V, RG = 25Ω, Starting TJ = 25 C
6 - 123
20
A
1.5
V
6
CED73A3/CEU73A3
VGS=10,8,6,5V
60
VGS=4V
80
ID, Drain Current (A)
ID, Drain Current (A)
100
60
40
VGS=3V
20
50
40
30
20
25 C
10
-55 C
TJ=125 C
0
0
1
2
3
0
4
0
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
C, Capacitance (pF)
5
6
Figure 2. Transfer Characteristics
2800
2100
1400
Coss
700
Crss
0
0
5
10
15
20
25
2.2
1.9
ID=30A
VGS=10V
1.6
1.3
1.0
0.7
0.4
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
VDS=VGS
IS, Source-drain current (A)
VTH, Normalized
Gate-Source Threshold Voltage
4
Figure 1. Output Characteristics
Ciss
ID=250µA
1.1
1.0
0.9
0.8
0.7
0.6
-50
3
VGS, Gate-to-Source Voltage (V)
3500
1.2
2
VDS, Drain-to-Source Voltage (V)
4200
1.3
1
VGS=0V
10
10
10
-25
0
25
50
75
100
125
150
2
1
0
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
6 - 124
10
10
VDS=15V
ID=20A
8
ID, Drain Current (A)
VGS, Gate to Source Voltage (V)
CED73A3/CEU73A3
6
4
2
0
RDS(ON)Limit
10
10
10
0
7
14
21
28
35
3
100µs
1ms
10ms
100ms
DC
2
1
6
TC=25 C
TJ=150 C
Single Pulse
0
10
-1
10
0
10
1
10
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
t on
RL
V IN
D
td(off)
tf
90%
90%
VOUT
VOUT
VGS
RGEN
toff
tr
td(on)
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
Figure 9. Switching Test Circuit
10
0
D=0.5
0.2
10
PDM
0.1
-1
t1
0.05
t2
0.02
0.01
Single Pulse
10
1. RθJA (t)=r (t) * RθJA
2. RθJA=See Datasheet
3. TJM-TA = P* RθJA (t)
4. Duty Cycle, D=t1/t2
-2
10
-2
10
-1
10
0
10
1
10
2
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
6 - 125
10
3
10
4
2
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