AD AD768 16-bit, 30 msps d/a converter Datasheet

a
FEATURES
30 MSPS Update Rate
16-Bit Resolution
Linearity: 1/2 LSB DNL @ 14 Bits
1 LSB INL @ 14 Bits
Fast Settling: 25 ns Full-Scale Settling to 0.025%
SFDR @ 1 MHz Output: 86 dBc
THD @ 1 MHz Output: 71 dBc
Low Glitch Impulse: 35 pV-s
Power Dissipation: 465 mW
On-Chip 2.5 V Reference
Edge-Triggered Latches
Multiplying Reference Capability
APPLICATIONS
Arbitrary Waveform Generation
Communications Waveform Reconstruction
Vector Stroke Display
PRODUCT DESCRIPTION
The AD768 is a 16-bit, high speed digital-to-analog converter
(DAC) that offers exceptional ac and dc performance. The
AD768 is manufactured on ADI’s Advanced Bipolar CMOS
(ABCMOS) process, combining the speed of bipolar transistors,
the accuracy of laser-trimmable thin film resistors, and the efficiency of CMOS logic. A segmented current source architecture
is combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Edge triggered
input latches and a temperature compensated bandgap reference
have been integrated to provide a complete monolithic DAC
solution.
The AD768 is a current-output DAC with a nominal full-scale
output current of 20 mA and a 1 kΩ output impedance. Differential current outputs are provided to support single-ended
or differential applications. The current outputs may be tied
directly to an output resistor to provide a voltage output, or fed
to the summing junction of a high speed amplifier to provide a
buffered voltage output. Also, the differential outputs may be
interfaced to a transformer or differential amplifier.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD768 can be driven by
the on-chip reference or by a variety of external reference voltages based on the selection of an external resistor. An external
capacitor allows the user to optimally trade off reference bandwidth and noise performance.
16-Bit, 30 MSPS
D/A Converter
AD768
FUNCTIONAL BLOCK DIAGRAM
VDD
DCOM
(MSB)
DB15
AD768
MSBs: SEGMENTED
CURRENT SOURCES
AND SWITCHES
MSB
DECODER
AND
EDGETRIGGERED
BIT
LATCHES
IOUTA
LSBs:
CURRENT SOURCES,
SWITCHES, AND
1kΩ R-2R
LADDERS
IOUTB
1k
1k
LADCOM
2.5V
BANDGAP
REFERENCE
DB0
(LSB)
CLOCK
NC
CONTROL
AMP
REFCOM REFOUT
IREFIN
VEE
NR
PRODUCT HIGHLIGHTS
1. The low glitch and fast settling time provide outstanding
dynamic performance for waveform reconstruction or digital
synthesis requirements, including communications.
2. The excellent dc accuracy of the AD768 makes it suitable for
high speed A/D conversion applications.
3. On-chip, edge-triggered input CMOS latches interface
readily to CMOS logic families. The AD768 can support update rates up to 40 MSPS.
4. A temperature compensated, 2.5 V bandgap reference is
included on-chip allowing for generation of the reference
input current with the use of a single external resistor. An external reference may also be used.
5. The current output(s) of the AD768 may be used singly or
differentially, either into a load resistor, external op amp
summing junction or transformer.
6. Proper selection of an external resistor and compensation
capacitor allow the performance-conscious user to optimize
the AD768 reference level and bandwidth for the target
application.
The AD768 operates on ± 5 V supplies, typically consuming
465 mW of power. The AD768 is available in a 28-pin SOIC
package and is specified for operation over the industrial temperature range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD768–SPECIFICATIONS
(TMIN to TMAX , VDD = +5.0 V, VEE = –5.0 V, LADCOM, REFCOM, DCOM = 0 V, IREFIN = 5 mA,
CLOCK = 10 MHz, unless otherwise noted)
Parameter
Min
RESOLUTION
16
Typ
Max
Units
Bits
1
DC ACCURACY
Linearity Error
TA = +25°C
TMIN to TMAX
Differential Nonlinearity
TA = +25°C
TMIN to TMAX
Monotonicity (13-Bit)
–8
–8
±4
+8
+8
LSB
LSB
–6
±2
+6
LSB
–8
+8
LSB
GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
ANALOG OUTPUT
Offset Error
Gain Error
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–0.2
–1.0
+0.2
+1.0
20
–1.2
0.8
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Reference Input Current
Reference Bandwidth4
Small Signal, IREF = 5 mA ± 0.1 mA
Large Signal, IREF = 4 mA ± 2 mA
1.0
3
+5.0
1.2
2.475
2.5
+5.0
2.525
+15
V
mA
1
5
7
mA
28
9
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift5
Gain Drift6
Reference Voltage Drift
–5
–20
–40
–30
DYNAMIC PERFORMANCE7
Maximum Output Update Rate
Output Settling Time (tST) (to 0.025%)
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (DB0–DB15 High, into 50 Ω)
Differential Gain Error
Differential Phase Error
30
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
MHz
MHz
+5
+20
+40
+30
40
25
10
35
5
5
3
0.01
0.01
35
3.5
1.5
+10
+10
–10
–10
10
10
5
10
AC LINEARITY7
Spurious-Free Dynamic Range (SFDR Within a Window)
FOUT = 1.002 MHz; CLOCK = 10 MHz; 2 MHz Span
FOUT = 1.002 MHz; CLOCK = 20 MHz; 2 MHz Span
FOUT = 5.002 MHz; CLOCK = 30 MHz; 10 MHz Span
Spurious-Free Dynamic Range (SFDR to Nyquist)
FOUT = 1.002 MHz; CLOCK = 10 MHz
FOUT = 1.002 MHz; CLOCK = 20 MHz
FOUT = 5.002 MHz; CLOCK = 30 MHz
Total Harmonic Distortion (THD)
FOUT = 1.002 MHz; CLOCK = 10 MHz
FOUT = 1.002 MHz; CLOCK = 20 MHz
FOUT = 5.002 MHz; CLOCK = 30 MHz
–2–
% of FSR
% of FSR
mA
V
kΩ
pF
ppm of FSR/oC
ppm of FSR/oC
ppm of FSR/oC
ppm/oC
MSPS
ns
ns
pV-s
ns
ns
nV/√Hz
%
Degree
V
V
µA
µA
pF
ns
ns
ns
86
85
78
79
dB
dB
dB
74
73
67
70
dB
dB
dB
–71
–66
–61
–68
dB
dB
dB
REV. B
AD768
Parameter
POWER SUPPLY
Positive Voltage Range
Negative Voltage Range
Positive Supply Current
Negative Supply Current
Nominal Power Dissipation
Power Supply Rejection Ratio (PSRR)
OPERATING RANGE
Min
Typ
Max
Units
4.75
–5.25
5
–5
30
63
465
5.25
–4.75
40
73
600
+0.2
+85
V
V
mA
mA
mW
% of FSR/V
°C
–0.2
–40
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal FS output current is 4× the current at IREFIN. Therefore, nominal FS current is 20 mA when IREFIN = 5 mA.
3
Output current is defined as total current available for IREFIN and any external load.
4
Reference bandwidth is a function of external cap at NR pin. Refer to compensation section of data sheet for details.
5
Excludes internal reference drift.
6
Includes internal reference drift.
7
Measured as unbuffered voltage output (1 V range) with FS current into 50 Ω load at IOUTB.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS *
Parameter
with Respect to
Min
Max
Units
Positive Supply Voltage (V DD)
Negative Supply Voltage (VEE)
Analog-to-Other Grounds (REFCOM)
Digital-to-Other Grounds (DCOM)
Reference Output (REFOUT)
Reference Input Current (IREFIN)
Digital Inputs (DB0–DB15, CLOCK)
Analog Outputs (IOUTA, IOUTB)
Maximum Junction Temperature
Storage Temperature
Lead Temperature
DCOM, REFCOM, LADCOM
DCOM, REFCOM, LADCOM
DCOM, LADCOM
LADCOM, REFCOM
REFCOM
–0.5
–6.0
–0.5
–0.5
DCOM
LADCOM
–0.5
–2.0
+6.0
+0.5
+0.5
+0.5
VDD + 0.5
+7.5
VDD + 0.5
+5.0
+150
+150
+300
V
V
V
V
V
mA
V
V
°C
°C
°C
–65
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device
reliability.
DB0–DB15
ORDERING GUIDE
Model
Package Description
AD768AR
AD768ACHIPS
AD768-EB
28-Pin 300 mil SOIC
Die
AD768 Evaluation Board
tS
Package
Option
tH
CLOCK
tLPW
tPD
R-28
IOUTA
OR
IOUTB
tST
0.025%
0.025%
Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD768 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
AD768
WAFER TEST LIMITS1
(TA = +258C, VDD = +5.0 V, VEE = –5.0 V, IREFIN = 5 mA, unless otherwise noted)
Parameter
2
Integral Nonlinearity
Differential Nonlinearity2
Offset Error
Gain Error
Reference Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
AD768ACHIPS Limit
Units
±8
±6
± 0.2
± 1.0
± 1.0
40
73
600
LSB max
LSB max
% FSR max
% FSR max
% of nom. 2.5 V max
mA max
mA max
mW max
NOTES
1
Electrical test are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal
yield loss, yield after packaging is not guaranteed for standard product dice.
2
Limits extrapolated from testing of individual bit errors.
3
Die offers latch control pad. Edge triggered latches become level triggered when latch control and clock pads are high.
4
Die substrate is connected to V EE.
PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8–14
15
16
17–23
24
25
26
27
28
Symbol
IOUTA
NR
REFOUT
NC
REFCOM
IREFIN
DB0
DB1–DB7
DCOM
CLOCK
DB8–DB14
DB15
VDD
VEE
IOUTB
LADCOM
Type
Name and Function
AO
AI
AO
NC
P
AI
DI
DI
P
DI
DI
DI
P
P
AO
P
DAC Current Output. Full-scale current when all data bits are 1s.
Noise Reduction Node. Add capacitor for noise reduction.
Reference Output Voltage. Nominal value is 2.5 V.
No Connect. Reserved for internal use.
Reference Ground.
Reference Input Current. Nominal is 5 mA. DAC full-scale is 4× this current.
Data Bit 0 (LSB).
Data Bits 1–7.
Digital Ground.
Clock Input. Data latched on positive edge of clock.
Data Bits 8–14.
Data Bit 15 (MSB).
Positive Supply Voltage. Nominal is +5 V.
Negative Supply Voltage. Nominal is –5 V.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Ladder Common.
Type: AI = Analog Input; DI = Digital Input; AO = Analog Output; P = Power.
DICE CHARACTERISTICS 3, 4
PIN CONFIGURATION
VDD
NR 2
27 IOUTB
REFOUT 3
26 VEE (–5V)
NC 4
25 VDD (+5V)
REFCOM 5
IREFIN 6
VDD
DB15
DB14 DB13
DB12 DB11
DB10
28 LADCOM
IOUTA 1
VEE
DB9
VEE
DB8
24 DB15 (MSB)
AD768
23 DB14
TOP VIEW 22 DB13
(Not to Scale)
DB1 8
21 DB12
(LSB) DB0 7
DB2 9
20 DB11
DB3 10
19 DB10
DB4 11
18 DB9
DB5 12
17 DB8
DB6 13
16 CLOCK
DB7 14
15 DCOM
IOUTB
CLOCK
LATCH CONTROL
LADCOM
DCOM
IOUTA
DB7
NR
DB6
REFOUT
DB5
NC
REFCOM IREFIN
DB0
DB1
DB2
DB3 DB4
NC = NO CONNECT
Die Size:
0.1106 × 0.1417 inch, 15,672 sq. mils
(2.81 × 3.60 mm, 10.116 sq. mm)
–4–
REV. B
AD768
DEFINITIONS OF SPECIFICATIONS
Temperature Drift
Linearity Error (Also Called Integral Nonlinearity or INL)
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C.
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal over the specified
bandwidth.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s. The ideal
output current span is 4× the current applied to the IREFIN pin.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients which are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
CREFCOMP
RREF
500Ω
1µF
NC
MSB DECODE
& LATCHES
1
IOUTA
27
IOUTB
50Ω
RLOAD
50Ω
28
CURRENT SOURCES
AND R-2R LADDER
22
21
20
19
18
17
14
13
12
11
10
9
8
7
DB1
23
DB0
24
DB2
LATCHES – LOWER 12 BITS
DB3
16
DB5
CLOCK
SEGMENTED
CURRENT
SOURCES
AD768
DB4
DCOM
DB7
CLOCK
RLAD
1kΩ
LADCOM
VEE
DB6
15
NR
DB9
26
RLAD
1kΩ
DB8
–5V
IOUTB
REFCOM
DB11
CNR
IOUTA
5mA
DB10
2
1µF
REFIN
+2.5V REF
DB13
5
1µF
6
DB12
1µF
3
REFOUT
DB15
25
4
DB14
+5V
VDD
Figure 1. Functional Block Diagram and Basic Hookup
FUNCTIONAL DESCRIPTION
The digital interface offers CMOS compatible edge-triggered
input latches that interface readily to CMOS logic and supports
clock rates up to 40 MSPS. A temperature compensated 2.5 V
bandgap reference is integrated on-chip to drive the AD768 reference input current with the use of a single external resistor.
The functional block diagram in Figure 1 is a simple representation of the internal circuitry to aid the understanding of the
AD768’s operation. The DAC transfer function is described,
and followed by a detailed description of each key portion of the
circuit. Typical circuit configurations are shown in the section
APPLYING THE AD768.
The AD768 is a current-output DAC with a nominal full-scale
current of 20 mA and a 1 kΩ output impedance. Differential
outputs are provided to support single-ended or differential
applications. The DAC architecture combines segmented current sources for the top four bits (MSBs) and a 1 kΩ R-2R ladder for the lower 12 bits (LSBs). The DAC current sources are
implemented with laser-trimmable thin film resistors for excellent dc linearity. A proprietary switching technique is utilized to
reduce glitch energy and maximize dynamic accuracy.
REV. B
–5–
AD768
DAC TRANSFER FUNCTION
550
The AD768 may be used in either current-output mode with the
output connected to a virtual ground, or voltage-output mode
with the output connected to a resistive load.
500
In current output mode,
POWER – mW
IOUT = (DAC CODE/65536) × (IREFIN × 4)
In voltage output mode,
VOUT = IOUT × RLOADiRLAD
450
400
where:
DAC CODE is the decimal representation of the DAC inputs;
an integer between 0 and 65535.
350
IREFIN is the current applied at the IREFIN pin, determined by
VREF/RREF.
300
1.0
2.0
3.0
4.0
IREFIN – mA
5.0
6.0
7.0
Substituting for IOUT and IREFIN,
VOUT = –VREF × (DAC CODE/65536) × 4 × [(RLOADiRLAD)/RREF]
Figure 3. Power Dissipation vs. IREFIN Current
These equations clarify an important aspect of the AD768
transfer function; the full-scale current output of the DAC is
proportional to a current input. The voltage output is then a
function of the ratio of (RLOADiRLAD)/RREF, allowing for cancellation of resistor drift by selection of resistors with matched
characteristics.
Note the AD768 is optimized for operation at an input current
of 5 mA. Both linearity and dynamic performance at other input
currents may be somewhat degraded. Figure 4 shows typical dc
linearity over a range of input currents. Figure 5 shows typical
SFDR (to Nyquist) performance over a range of input currents
and CLOCK input rates for a 1 MHz output frequency.
10
REFERENCE INPUT
The IREFIN pin is a current input node with low impedance to
REFCOM. This input current sets the magnitude of the DAC
current sources such that the full-scale output current is exactly
four times the current applied at IREFIN. For the nominal input current of 5 mA, the nominal full-scale output current is
20 mA.
9
8
ERROR – LSB
7
The 5 mA reference input current can be generated from the
on-chip 2.5 V reference with an external resistor of 500 Ω from
REFOUT to IREFIN. If desired, a variety of external reference
voltages may be used based on the selection of an appropriate
resistor. However, to maintain stability of the reference amplifier, the external impedance at IREFIN must be kept below
1 kΩ.
REFCOM
5
IREFIN
6
6
5
INL
4
3
2
DNL
1
0
1.0
2.0
3.0
4.0
IREFIN – mA
5.0
6.0
7.0
Figure 4. INL/DNL vs. IREFIN Current
–85
IFB
5mA
VEE
CLOCK = 10 MSPS
–80
VEE
–75
SFDR – dB
Figure 2. Equivalent Reference Input Circuit
The IREFIN current can be varied from 1 mA to 7 mA which
subsequently will result in a proportional change in the DAC
full-scale. Since the operating currents within the DAC vary
with IREFIN, so does the power dissipation. Figure 3 illustrates
that relationship.
CLOCK = 20 MSPS
–70
CLOCK = 30 MSPS
–65
CLOCK = 40 MSPS
–60
–55
1.0
2.0
3.0
4.0
IREFIN – mA
5.0
6.0
7.0
Figure 5. SFDR (to Nyquist) vs. IREFIN @ FOUT = 1 MHz
–6–
REV. B
AD768
REFERENCE OUTPUT
100M
The internal 2.5 V bandgap reference is provided for generation
of the IREFIN current, and must be compensated externally with
a capacitor of 0.1 µF or greater from REFOUT to REFCOM. If
an external reference is used, REFOUT should be tied directly
to the positive supply voltage, VDD. This effectively turns off the
internal reference, eliminating the need for the external capacitor at REFOUT. The reference is specified to drive a nominal
load of 5 mA with a maximum of 15 mA. Operation with a
heavier load will result in degradation of supply rejection and
reference voltage accuracy. Therefore, the reference output
should be buffered with an amplifier when additional load current is required. A properly sized pull-up resistor can also be
used to source additional current to the load. The resistors value
should be selected such that REFOUT will always source a
minimum of 5 mA to IREFIN and the additional load.
500Ω
BANDWIDTH – Hz
10M
1M
100k
10k
1k
10p
100p
1n
10n
100n
Figure 7. External Noise Reduction Capacitor vs. –3 dB
Bandwidth
AD768
6 IREFIN
The sensitivity of the NR node requires that care be taken in
capacitor placement. The capacitor should be located as physically close to the package pins as possible and lead lengths
should be minimized. For this purpose, the use of a chip
capacitor is recommended. For applications that do not require
high frequency modulation at IREFIN, it is recommended that
a capacitor on the order of 1 µF be connected from NR to VEE.
If the reference input is purely dc, noise may be minimized with
multiple capacitors, such as 1 µF and 0.1 µF, to more effectively
filter both high and low frequency disturbances.
3 REFOUT
CREFCOMP
1µF
5 REFCOM
Figure 6. Typical Reference Hookup
TEMPERATURE CONSIDERATIONS
Note that the reference plays a key role in the overall temperature performance of the AD768. Any drift of IREFIN shows up
directly in IOUT. When the output is taken as a current, the drift
of IREFIN (which depends on both VREF and RREF) must be minimized. This can be done by using the internal temperature compensated reference for VREF and a low temperature coefficient
resistor for RREF. If the output is taken as a voltage, it is a function of a resistor ratio, not an absolute resistor value. By selecting resistors with matched temperature coefficients for RREF
and RLOAD, the drift in the resistor values will cancel, providing
optimal drift performance.
ANALOG OUTPUTS
The AD768 offers two analog outputs; IOUTA is trimmed for
optimal INL and DNL performance and has a full-scale output
when all bits are high. For applications that require the specified
dc accuracy, IOUTA should be used. IOUTB is the complementary output with full-scale output when all bits are low.
Both IOUTA and IOUTB provide similar dynamic performance. Refer to Figures 8 and 9 for typical INL and DNL performance curves. The outputs can also be used differentially.
Refer to the section “Applying the AD768” for examples of various output configurations.
REFERENCE NOISE REDUCTION AND MULTIPLYING
BANDWIDTH
8
For application flexibility and multiplying capabilities, the reference amplifier is designed to offer adjustable bandwidth that can
be reduced by connecting an external capacitor from the NR
node to the negative supply pin, VEE. This capacitor limits the
bandwidth and acts as a filter to reduce the noise contribution
from the reference amplifier.
6
INL ERROR – LSB
4
The noise reduction capacitor, CNR, is not required for stability
and does not affect the settling time of the DAC output. Without this capacitor, the IREFIN bandwidth is 15 MHz allowing
high frequency modulation of the DAC full-scale range through
the reference input node. Figure 7 shows the relationship between the external noise reduction capacitor and the –3 dB
bandwidth of the reference amplifier.
2
0
–2
–4
–6
–8
0
5
10
15
20 25 30 35 40 45
DIGITAL INPUT CODE – k
50
55
Figure 8. Typical INL Performance
REV. B
1µ
NOISE REDUCTION CAPACITOR – F
–7–
60
65
AD768
8
IOUTA
LADCOM
1
28
6
DNL ERROR – LSB
4
2
IOUTB
27
1kΩ
1kΩ
3pF
3pF
IOUT
IOUT
IREFIN
x2.75
0
26
–2
VEE
–4
–6
–8
Figure 10. Equivalent Analog Output Circuit
0
5
10
15
20 25 30 35 40 45
DIGITAL INPUT CODE – k
50
55
60
DIGITAL INPUTS
65
The AD768 digital inputs consist of 16 data input pins and a
clock pin. The 16-bit parallel data inputs follow standard positive binary coding, where DB15 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA produces full-scale output current when all data bits are at logic 1.
IOUTB is the complementary output, with full-scale when all
data bits are at logic 0. The full-scale current is split between
the two outputs as a function of the input code.
Figure 9. Typical DNL Performance
The outputs have a compliance range of –1.2 V to +5.0 V with
respect to LADCOM. The current steering output stages will
remain functional over this range. Operation beyond the maximum compliance limits may cause either output stage saturation
or breakdown, resulting in nonlinear performance. The rated dc
and ac performance specifications are for an output voltage of
0 V to –1 V.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock, and is designed to support a clock rate
as high as 40 MSPS. The clock can be operated at any duty
cycle that meets the specified minimum latch pulse width. The
setup and hold times can also be varied within the clock cycle as
long as the specified minimums are met, although the location
of these transition edges may affect digital feedthrough. The
digital inputs are CMOS compatible with logic thresholds set to
approximately half the positive supply voltage. The small input
current requirements allow for easy interfacing to unbuffered
CMOS logic. Figure 11 shows the equivalent digital input
circuit.
The current in LADCOM is proportional to IREFIN and has been
carefully configured to be independent of digital code when the
output is connected to a virtual ground. This minimizes any detrimental effects of ladder ground resistance on linearity. For
optimal dc linearity, IOUTA should be connected directly to a
virtual ground, and IOUTB should be grounded. An example of
this configuration is provided in the section “Buffered Voltage
Output.” If IOUTA is driving a resistive load directly, then
IOUTB should be terminated with an equal impedance. This
will ensure the current in LADCOM remains constant with digital code, and is recommended for improved dc linearity in the
unbuffered voltage output configuration.
VCC
As shown in Figure 10, there is an equivalent output impedance
of 1 kΩ in parallel with 3 pF at each output terminal. If the output voltage deviates from the ladder common voltage, an error
current flows through this 1 kΩ impedance. This is a linear effect
which does not change with input code, so it appears as a gain
error. With 50 Ω output termination, the resulting gain error is
approximately –5%. An example of this configuration is provided in the section Unbuffered Voltage Output.
VCC
DIGITAL
INPUT
VEE
DCOM
Figure 11. Equivalent Digital Input Circuit
Digital input signals to the DAC should be isolated from the
analog output as much as possible. Interconnect distances to the
DAC inputs should be kept as short as possible. Termination
resistors may improve performance if the digital lines become
too long. To minimize digital feedthrough, the inputs should be
free from glitches and ringing, and may be further improved
with a reduction of edge speed.
–8–
REV. B
Typical Performance Curves––AD768
AD768
–0.472
RL = 50Ω
VOUT = 0 TO –1V
0.80
–0.9443
0.60
–0.9453
0.50
–0.9462
0.40
–0.9472
0.30
–0.9481
0.20
–0.9498
0.10
–0.474
–0.2
–0.476
–0.4
–0.6
–0.478
–0.8
–0.480
0.05
0.025
–0.9500
12 14 16 18 20 22 24 26 28 30 32 34 36
TIME – ns
–1.0
–0.482
TIME – 5ns/Div
TIME – 2ns/Div
Figure 14. Rise and Fall
Characteristics
Figure 13. Glitch Impulse at Major
Carry
Figure 12. Settling Time
0
RL = 50Ω
VOUT = 0 TO –1V
–75
0
CLOCK = 10MHz
FOUT = 1.002MHz
AMPLITUDE = 0dBm
OUTPUT IOUTB
RL = 50Ω
–20
OUTPUT – dB
–70
–65
–60
–40
–60
–50
4
5 6 7 8 9 10
20
FREQUENCY – MHz
30
40
–100
0.1
Figure 15. THD vs. Clock Frequency
at FOUT = 1 MHz
–40
–60
–80
–80
–55
1
2
3
FREQUENCY – MHz
4
5
–100
10k
Figure 16. Typical Spectral
Performance
1.0M
FREQUENCY – Hz
0
CLOCK = 30MHz
CLOCK = 10 MHz
FOUT1 = 240 kHz
FOUT2 = 260 kHz
AMPLITUDE = –6.0 dB FS
PER TONE
OUTPUT IOUTB
RL = 50Ω
CLOCK = 1MHz
–82
–75
CLOCK = 10MHz
–20
–78
THD – dB
SFDR
CLOCK = 10MHz
–70
–66
CLOCK = 20MHz
–65
CLOCK = 30MHz
–60
–62
–40
–60
CLOCK = 40MHz
–58
–80
–55
–54
CLOCK = 20MHz
–50
10
1
–50
0.01
0.1
1
FREQUENCY – MHz
FREQUENCY – MHz
Figure 18. SFDR (Within a Window)
vs. FOUT
REV. B
OUTPUT – dB
–70
–74
2.0M
Figure 17. Typical SFDR
(With a Window)
–80
–86
CLOCK = 10MHz
FOUT = 1.002MHz
AMPLITUDE = 0dBm
–20
OUTPUT – dB
–80
THD – dB
RL = 50Ω
VOUT = 0 TO –1V
0.0
VOLTS
0.70
OUTPUT – V
–0.9433
ERROR BAND – %
–0.9424
0.2
RL = 50Ω
VOUT = 0 TO –1V
0.90
–0.9415
OUTPUT – dB
–0.470
1.00
–0.9405
Figure 19. THD vs. FOUT
–9–
10
–100
150
190
230
270
FREQUENCY – Hz
310
Figure 20. Intermodulation
Distortion
350
AD768
APPLYING THE AD768
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD768. While most figures take the output at
IOUTA, IOUTB can be interchanged in all cases. Unless otherwise noted, it is assumed that IREFIN and full-scale currents are
set to nominal values.
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tolerances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of RFB
may cause a change in gain, producing a bow in the INL curve.
This effect can be minimized by selection of a low temperature
coefficient resistor.
DAC output is the parallel combination of the AD768’s output
impedance, RL, and bias resistor RB. The nominal output swing
with the values given in Figure 22 is ± 0.5 V assuming RB >> RL.
The gain of the circuit will be a function of the tolerances of the
impedances RLAD, RB, and RL.
Choosing the value of RB and C will depend primarily on the
desired –3 dB high pass cutoff frequency and the bias current,
IB, of the subsequent stage connected to RB. The –3 dB frequency can be approximated by the equation,
f–3 dB = 1/[2 × π × (RB + RLiRLAD) × C].
The dc offset of the output is a function of the bias current of
the subsequent stage and the value of RB. For example, if
C = 390 pF, RB = 20 kΩ, and IB = 1.0 µA, the –3 dB frequency
is approximately 20.4 kHz and the dc offset would be 20 mV.
UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS
AD768
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0 V to –1 V. The nominal fullscale current of 20 mA flows through the parallel combination
of the 50 Ω RL resistor and the 1 kΩ DAC output resistance
(from the R-2R ladder), for a combined 47.6 Ω. This produces
an ideal full-scale voltage of –0.952 V with respect to LADCOM.
In addition, the 1 kΩ DAC output resistance has a tolerance of
± 20% which may vary the full-scale gain by ± 1%. This linear
variation results in a gain error which can be easily compensated
for by adjusting IREFIN.
AD768
IOUTA
1
RL
49.9Ω
VA
RL
49.9Ω
VB
LADCOM 28
IOUTB 27
Figure 21. 0 V to –1 V Unbuffered Voltage Output
In this configuration, it is important to note the restrictions from
the output compliance limits. The maximum negative voltage
compliance is –1.2 V, prohibiting use of a 100 Ω load to produce
a 0 V to –2 V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
The INL is also slightly dependent on the termination of the
unused output (IOUTB) as described in the ANALOG OUTPUT section. To eliminate this effect, IOUTB should be terminated with the same impedance as IOUTA, so both outputs see
the same resistive divider to ground. This will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
IOUTA
C
IB
1
IOUTB 27
RL
49.9Ω
RL
49.9Ω
RB
LADCOM 28
Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output
BUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Unipolar Configuration
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. The
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10 MHz. Figure 23
shows the implementation of 0 V to +2 V full-scale unipolar
buffered voltage output. The amplifier establishes a summing
node at ground for the DAC output. The buffered output voltage results from the DAC output current flowing through the
amplifier’s feedback resistor, RFB. In this case, the 20 mA fullscale current across RFB (100 Ω) produces an output voltage
range of 0 V through +2 V. The same configuration using a precision amplifier such as the AD845 is recommended for optimal
dc linearity.
RFB
100Ω
AD768
IOUTA
1
A1
IOUTB 27
LADCOM 28
Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output
Buffered Output Using a Current Divider
AC-Coupled Output
Configuring the output as shown in Figure 22 provides a bipolar
output signal from the AD768 without requiring the use of a
summing amplifier. The ac load impedance presented to the
The configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20 mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. The values of
RFF and RL are chosen to limit the current, I3, which must be
supplied by A1. Current, I2, is shunted to ground through resistor, RL. The parallel combination of RFF and RL should not exceed 60 Ω to avoid exceeding the specified compliance voltage.
–10–
REV. B
AD768
For the values given in Figure 24, I3 equals 4 mA, which results
in a nominal unipolar output swing of 0 V to 2 V. Note, since
A1 has an inverting gain of approximately –4 and a noise gain of
+5, A1’s distortion and noise performance should be considered.
In order to comply with the minimum voltage compliance of
–1.2 V, the maximum differential resistance seen between
IOUTA and IOUTB should not exceed 240 Ω. Note that the
differential resistance consists of the load RL, referred to the
primary side of the transformer in parallel with any added differential resistance, RDIFF, across the two outputs. RDIFF is typically
added to the primary side of the transformer to match the effective primary source impedance to the load (i.e., in this case
200 Ω).
RFB
500Ω
AD768
IOUTA
RFF
100Ω
I3
I1
1
I2
A1
RL
24.9Ω
IOUTB 27
RP
20Ω
primary side is multiplied by a factor of 4 (i.e., in this case
200 Ω). To avoid dc current from flowing into the R-2R ladder
of the DAC, the center tap of the transformer should be connected to LADCOM.
LADCOM 28
Figure 24. 0 V to 2 V Buffered Unipolar Output Using a
Current Divider
AD768
IOUTA
Bipolar Configuration
Bipolar mode is accomplished by providing an offset current,
IBIPOLAR, to the I/V amplifier’s (A1) summing junction. By setting IBIPOLAR to exactly half the full-scale current flowing
through RFB, the resulting output voltage will be symmetrical
about the summing junction voltage, typically ground. Figure 25
shows the implementation for a bipolar ± 2.5 V buffered voltage
output. The resistor divider sets the full-scale current for IDAC to
5 mA. The internal 2.5 V reference generates a 2.5 mA IBIPOLAR
current across RBIP. An output voltage of 0 V is produced when
the DAC is set to half scale (100. . .0) such that the 2.5 mA current, IDAC, is exactly offset by IBIPOLAR. As the DAC is varied
from zero to full-scale, the output voltage swings from –2.5 V to
+2.5 V. Note, in configurations that require more than 15 mA
of total current from REFOUT, an external buffer is required.
Op amps such as the AD811, AD8001, and AD9631 are good
selections for superior dynamic performance. In dc applications,
op amps such as the AD845 or AD797 may be more appropriate.
RBIP
1kΩ
AD768
REFOUT
3
C
IBIPOLAR
75Ω
IOUTA
RDIFF
200Ω
IOUTB 27
T1 = MINI-CIRCUITS T4-6T
Figure 26. Differential Output Using a Transformer
DC COUPLING VIA AN AMPLIFIER
A dc differential to single-ended conversion can be easily accomplished using the circuit shown in Figure 27. This circuit
will attenuate both ac and dc common-mode error sources due
to the differential nature of the circuit. Thus, common-mode
noise (i.e., clock feedthrough) as well as dc unipolar offset errors
will be significantly reduced. Also, excellent temperature stability can be obtained by using temperature tracking, thin film
resistors for R and RREF. The design equations for the circuit are
provided such that the voltage output swing and IREF can be
optimized for a given application.
R*
RFB
1kΩ
AD768
IOUTA
IDAC
1
A1
1
IOUTB 27
RL
50Ω
T1
4:1 IMPEDANCE
RATIO
LADCOM 28
A1
IOUTB 27
24.9Ω
R*
RP
20Ω
REFIN
6
REFOUT
3
RREF*
Figure 25. Bipolar ± 2.5 V Buffered Voltage Output
DIFFERENTIAL OUTPUT CONFIGURATIONS
AC Coupling via a Transformer
VOUT = ±4 IREF R
VOUT
WHERE IREF =
2.5V
RREF
VOUT ± 2V
R = 200Ω
RREF = 5 x 200Ω
LADCOM 28
LADCOM 28
IREF
*OHMTEK TDP-1403
Figure 27. DC Differential to Single-Ended Conversion
Applications that do not require baseband operation typically
use transformer coupling. Transformer coupling the complementary outputs of the AD768 to a load has the inherent benefit
of providing electrical isolation while consuming no additional
power. Also, a properly applied transformer should not degrade
the AD768’s output signal with respect to noise and distortion,
since the transformer is a passive device. Figure 26 shows a
center-tapped output transformer that provides the necessary dc
load conditions at the outputs IOUTA and IOUTB to drive a
± 0.5 V signal into a 50 Ω load. In this particular circuit, the center-tapped transformer has an impedance ratio of 4 that corresponds to a turns ratio of 2. Hence, any load, RL, referred to the
REV. B
1
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high accuracy, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD768. Figure 28 provides an illustration of the recommended printed circuit board
ground plane layout which is implemented on the AD768 evaluation board.
–11–
AD768
Figure 28. Printed Circuit Board Ground Plane Layout
Figure 29. Printed Circuit Board Power Plane Layout
–12–
REV. B
AD768
A clean digital supply may be generated using the circuit shown
in Figure 30. The circuit consists of a differential LC filter with
separate power supply and return lines. Lower noise can be attained using low ESR (Equivalent Series Resistance) type electrolytic and tantalum capacitors.
If properly implemented, ground planes can perform a host of
functions on high speed circuit boards: bypassing, shielding,
current transport, etc. In mixed signal design, the analog and
digital portions of the board should be distinct from each other,
with the analog ground plane confined to the areas covering
analog signal traces and the digital ground plane confined to
areas covering the digital interconnects.
All analog ground pins of the DAC, reference, and other analog
output components, should be tied directly to the analog ground
plane. The two ground planes should be connected by a path
1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC
as shown in Figure 28. Care should be taken to ensure that the
ground plane is uninterrupted over crucial signal paths. On the
digital side, this includes the digital input lines running to the
DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal, and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as, providing
some “free” capacitive decoupling to the appropriate ground
plane. Figure 29 illustrates the power plane layout used in the
AD768 evaluation board. The AD768 evaluation board uses a
four layer P.C. board which illustrates good layout practices as
discussed above.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
VDD
100µF
ELECT.
10–20µF
TANT.
0.1µF
CER.
DCOM
+5V
DGND
+5V
POWER SUPPLY
Figure 30. Differential LC Filter for Single +5 V
Applications
APPLICATIONS
USING THE AD768 AS A MULTIPLYING DAC
The AD768 can be easily configured as a multiplying DAC
since IREFIN can be modulated from 1 mA to 7 mA. The reference amplifier sets the maximum multiplying bandwidth to 15
MHz, while any external capacitor to the NR node serves to
limit the bandwidth according to Figure 7. IREFIN can be easily
modulated by properly scaling and summing into the IREFIN
node the modulating signal. Figure 31 demonstrates how the
modulating signal VMOD can be properly scaled and converted
to a current via RREFMOD such that its peak current does not exceed 3.0 mA. Figure 32 shows the AD768’s typical distortion
versus the reference channel frequency.
It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the package as possible, in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, some type of termination resistor should be considered.
The necessity and value of this resistor will be dependent upon
the logic family used.
AD768
RREFMOD
VMOD
6
IREFIN
3
REFOUT
RREF
625Ω
For maximum ac performance, the DAC should be mounted
directly to the circuit board; sockets should be avoided since
they introduce unwanted capacitive coupling between adjacent
pins of the device.
1µF
VMOD
≤ ±3.0mA
RREFMOD
POWER SUPPLY AND DECOUPLING
It is recommended that each power supply to the AD768 be decoupled by a 0.1 µF capacitor located as close to the device pins
as possible. Surface-mount chip capacitors, by virtue of their
low parasitic inductance, are preferable to through-hole types.
Some series inductance between the DAC supply pins and the
power supply plane may help to provide additional filtering of
high frequency power supply noise. This inductance can be generated by using small ferrite beads.
Figure 31. Typical Multiplying DAC Application
–75
–70
IREF = 5.0+/–1 mA
–65
THD – dB
One of the most important external components associated with
high speed designs are the capacitors used to bypass the power
supplies. Both selection and placement of these capacitors can
be critical and, to a large extent, dependent upon the specifics of
the system configuration. The dominant consideration in the
selection of bypass capacitors for the AD768 is the minimization
of the series resistance and inductance. Many capacitors will
begin to look inductive at 20 MHz and above. Ceramic and film
type capacitors generally feature lower series inductance than
tantalum or electrolytic types.
IREF = 4.0+/–2 mA
–60
–55
IREF = 4.0+/–3 mA
–50
–45
–40
250
500
750
1000 1250 1500 1750
FREQUENCY – kHz
2000
2250 2500
Figure 32. Reference Channel Distortion vs. Frequency
REV. B
–13–
AD768
1.5
AD768 IN MULTITONE TRANSMITTERS (FOR ADSL)
Communications applications frequently require aspects of
component performance that differ significantly from the
simple, single tone signals used in typical SNR and THD tests.
This is particularly true for spread-spectrum and frequency division multiplexed (FDM) type signals, where information content is held in a number of small signal components spread
across the frequency band. In these applications, a combination
of wide dynamic range, good fine-scale linearity, and low intermodulation distortion is required. Unfortunately, a part’s full
scale SNR and THD performance may not be a reliable indicator of how it will perform in these multitone applications.
OUTPUT – Volts
1.0
–1.0
–1.5
TIME – 25µs/DIV
Figure 34b. Time Domain Output Signal of ADSL Test
Vector
The digital bits are used to QAM modulate each of approximately 200 discrete tones. An inverse FFT turns this modulated frequency domain information into 512 time points at a
2.2 MSPS sample rate. These time points are then put through
an FIR interpolation filter to upsample (in this case to 4.4 MSPS).
The bit stream is run through the AD768, which is followed by
a 4th order analog smoothing filter, then run to the line-driving
circuitry
Table I and II show the available SNR and THD at the output
of the filter vs. frequency bin for the ADSL application. The
AD768’s combination of 16-bit dynamic range and 14-bit linearity provides excellent performance for the DMT signal. Its
fast input rate would support even faster rates of oversampling,
if one were interested in trading off digital filter complexity in
the interpolator for a simplified analog filter.
1024 TIME
POINTS
@
4.4MSPS
2X
INVERSE
QAM
INTERPOLATOR
FFT
ENCODER FREQUENCY
@ 2.2MSPS
FIR
BINS
256
MODULATED
AD768
+BUFFER
0
–0.5
One example of an FDM communications system is the DMT
(discrete multitone) ADSL (Asymmetrical Digital Subscriber
Line) standard currently being considered by ANSI. Figure 33
shows a block diagram of a transmitter function.
BIT
STREAM
0.5
512 TIME
POINTS
4TH ORDER
SMOOTHING
FILTER
TO
TRANSMITTER
Figure 33. Typical DMT ADSL Transmit Chain
Figure 34a shows a frequency domain representation of a test
vector run through this system, while 34b shows the time domain representation. (Clearly the frequency domain picture is
more informative.) We wish to optimize the SINAD of each
4 kHz frequency band: this is a function of both noise
(wideband and quantization) and distortion (simple harmonic
and intermod).
Table I. SNR vs. Frequency
Frequency
SNR
151 kHz
349 kHz
500 kHz
1 MHz
70.1 dB
69.7 dB
69.4 dB
69.8 dB
Table II. THD vs. Frequency
0
Frequency
THD
160 kHz
418 kHz
640 kHz
893 kHz
–68.9 dBc
–64.0 dBc
–64.3 dBc
–63.8 dBc
OUTPUT – dB
–20
–40
–60
–80
0
FREQUENCY – Hz
1.1M
Figure 34a. Output Spectrum of ADSL Test Vector
–14–
REV. B
AD768
AD768 EVALUATION BOARD
GENERAL DESCRIPTION
The AD768-EB is an evaluation board for the AD768 16-bit
30 Msps D/A converter. Careful attention to layout and circuit
design combined with analog and digital prototyping areas allows the user to easily and effectively evaluate the AD768 in any
application where high resolution, high speed conversion is
required.
The digital inputs to the AD768-EB may be driven directly using the standard 40-pin IDC connector. An external clock is
also required. These signals may be applied from a user’s
bench, or they can be generated from a circuit built on the
prototyping area. The analog outputs from the AD768-EB are
available on BNC connectors. These outputs may be configured
to use either resistors, op amps, or a transformer.
OPERATING PROCEDURE AND FUNCTIONAL
DESCRIPTION
Power
Power may be supplied to the AD768-EB by applying either
wires or banana plugs to the metal binding posts included on the
printed circuit board.
DGND. Digital Ground. The digital ground and the analog
ground are connected together underneath the AD768. Optimal
performance can be obtained with separate analog and digital
supplies. For evaluation purposes, a single-supply which makes
a second analog and digital ground connection at the supply is
acceptable.
+5D. The +5 V (± 5%) digital supply should be capable of supplying 50 mA.
–5A. The –5 V (± 5%) analog supply should be capable of supplying –75 mA.
AGND. Analog ground. The analog ground and the digital
ground are connected together underneath the AD768. Optimal
performance can be obtained with separate analog and digital
supplies. For evaluation purposes, a single-supply which makes
a second analog and digital ground connection at the supply is
acceptable.
–VEE. Negative analog supply; typically –5 V to –15 V. This
supply is used as the negative supply rail for the external op
amps. For the AD811 supplied with the AD768-EB, a supply
capable of supplying –20 mA (excluding external load requirements) is required.
JP2. Bipolar 50 Ω transformer output. If jumper JP2 is installed, a transformer coupled output is available on the “A”
connector. When JP2 is installed, JP1 and JP3 must be removed for proper operation. The transformer acts both as a
differential-to-single-ended converter and as an impedance
transformer. For proper operation, the transformer must be
terminated with a 50 Ω resistor. R2 must be replaced with
the 100 Ω resistor, R7. An additional 100 Ω resistor and the
transformer are included with the AD768-EB. The additional
100 Ω resistor must be soldered into the appropriate position labeled “R3” and the transformer must be inserted into the
socket labeled “T1.” The nominal output voltage into a 50 Ω
load is 1 V p-p centered on a common-mode voltage of 0 V.
JP3. Resistor output “A.” JP3 is used to connect the resistor
R2 to the “A” output. U2 should be removed from its socket.
Using a 24.9 Ω resistor for R2, the output is an unbuffered 0 V
to –0.5 V output that is out of phase with the digital input. Resistor R2 may be replaced with other values, but careful attention to the recommended output compliance range should be
observed. When JP3 is installed, JP1 and JP2 must be removed for proper operation.
JP4. Resistor output “B.” JP4 is used to connect the resistor
R3 to the “A” output. U3 should be removed from its socket.
The AD768-EB is shipped from the factory with resistor R3
shorted to ground. A different value selected by the user can be
installed for R3 to generate an unbuffered output that is inphase with the digital input. Careful attention to the recommended output compliance range should be observed when
selecting the value of R3. When JP4 is installed, JP5 must
be removed for proper operation.
JP5. Buffered op amp output “B.” Jumper JP5 should be installed if the buffered op amp output is desired. When JP5 is
installed, JP4 must be removed for proper operation.
The output is available on the “B” connector and has a nominal
voltage swing determined by the combination of resistors R3,
R9, and R10. This op amp is not provided with the AD768-EB.
Reference
Either the internal reference of the AD768 or an external reference may be selected on the AD768-EB. R12 is used to adjust
the full-scale output current of the AD768.
+VCC. Positive analog supply; typically +5 V to +15 V. This
supply is used as the positive supply rail for the external op
amps. For the AD811 supplied with the AD768-EB, a supply
capable of supplying +20 mA (excluding external load requirements) is required.
Analog Outputs
The analog output(s) from the AD768-EB are available on BNC
jacks “A” and “B.” The complementary current outputs from
the AD768 can be configured using either resistors, op amps, or
a transformer. Only the “A” portion of the AD768-EB is populated and shipped from the factory. The “B” side, or complementary output, may be populated by the user if so desired.
REV. B
JP1. Buffered op amp output “A”. Jumper JP1 should be
installed if the buffered op amp output is desired. When JP1
is installed, JP2 and JP3 must be removed for proper
operation. The output, available on the “A” connector, has a
nominal voltage swing of 0 V to 2 V and is in-phase with the
digital input. This is the factory default setting.
SW2. Internal/External reference select switch. When SW2 is
in position 1, the internal reference of the AD768 is selected.
When SW2 is in position 2, an external reference must be provided by the user.
Level-Shifting the Analog Output
Resistor sockets R8 and R6 can be populated with an appropriately valued resistor to add dc offset current to an output which
uses the op amp configuration. As an example, to generate a
bipolar output signal, a 1.25 kΩ resistor installed into the “R8”
socket level-shifts the normally unipolar output by –1 V. The
factory defaults for R8 and R6 are open circuits.
–15–
AD768
Clock Input
Table III. Summary of Jumper Functionality
An external sample clock must be provided to either the BNC
connector labeled “CLOCK” or on Pin 33 of the IDC connector. This clock must comply with the logic levels outlined in the
AD768 data sheet. The “CLOCK” input is terminated with a
removable 51 Ω resistor. The IDC connector clock connection
is unterminated.
SW1. Clock source select switch. When SW1 is in position 1, Pin
33 of the IDC connected is applied to the CLOCK input of the
AD768. When SW2 is in position 2, the “CLOCK” BNC connector is applied to the CLOCK input of the AD768.
Installed
Jumper Function
Jumper
JP1
JP2
JP3 (STBY)
JP4
JP5
Buffered Output A
50 Ω Transformer Output
Unbuffered Output A
Unbuffered Output B
Buffered Output B
Table IV. AD768-EB Parts List
Digital Inputs
The digital inputs of the AD768, DB0–DB15, are available via
J1, a 40-pin IDC connector. These inputs should comply with
the specifications given in the AD768 data sheet.
Reference
Value / Part Type Package
Qty/Bd
U1
AD768
28-Pin SOIC
1
Layout Considerations
U2
AD811
8-Pin DIP
1
T1
Mini-Circuits
T4–6T
Not Installed
1
A, B, CLOCK BNC JACKs,
Small
Small, Vertical
3
JP1–5
Header
2-Pin
5
SW1, 2
SPDT, Secme
0.1" × 0.3"
2
J1
40-Pin IDC
Connector
R.A., Male,
w/ Latches
1
R1
500 Ω
1/4 W, 0.01%,
Vishay
1
R2
25 Ω
1/4 W, 0.01%,
Vishay
1
Figures 28 and 29 show the AD768-EB ground and power
plane layouts. Figures 35–38 show the schematic diagram, trace
routing, silk screening, and component layout for the AD768 4
layer evaluation board.
Separate ground and power planes have several advantages for
high speed layouts. (For further information outlining these
advantages, see the application note “Design and Layout of a
Video Graphics System for Reduced EMI” [E1309] available
from Analog Devices [(617) 461-3392].) A solid ground plane
can be used if the digital return current can be routed such that
it does not modulate the analog ground plane. If this is not possible, it may be necessary to split the ground plane in order to
force currents to flow in a controlled direction. This type of
grounding scheme is shown in the Figure 28. The ground plane
is separated into analog and digital planes that are joined
together under the AD768. In any case, the AD768 should be
treated as an analog component and a common ground connection should be made underneath the AD768 despite some pins
being labeled “digital” ground and some as “analog” ground.
A complete parts list for the AD768 evaluation board is given in
Table IV.
R3, R13–21, &
R23–29
Wire Jumpers
17
R5
500 Ω
1/4 W, 0.01%,
Vishay
1
R7
100 Ω
1/4 W, 0.01%,
Vishay
1
R11
51 Ω
1/8 W, 5%, Carbon 1
R12
10 kΩ Pot.
3266 W
1
C1–4
1 µF Ceram. Cap. Leaded
4
C5–8, C10, 12,
14, & C16–19
0.1 µF Chip Cap,
1206
C9, 11, 13, 15 22 µF Tant. Cap., Teardrop,
25 V
0.1" Spacing
–16–
11
4
REV. B
AD768
R5
499
+VCC
3
7
50
A
6
AD811
50
JP5
R10
499
2
+VCC
JP1
C6
0.1µF
4
B
1
2
C5
0.1µF
U2
2
A
1
U3
JP2
2
A
3
A
–VEE
T1
1
3
A
7
4
5
6
A
6
AD811
4:1
4
C7
0.1µF
C8
0.1µF
A
JP3
–VEE
A
JP4
R7
100
R2
24.9
R3
24.9
R8
∞
C9
47µF, 25V
R9
100
A
–VEE
C10
0.1µF
R6
∞
+VCC
C11
47µF, 25V
A
C12
0.1µF
–5A
A
R12
10k
C2
1µF
U1
C18
0.1µF
AD768
1
2
A
1
SW2
2
TP1
J1
31
J1
29
J1
27
J1
25
J1
23
J1
21
J1
19
J1
17
J1
33
R1
499
3
C1
1µF
4
5
6
R13
0
7
R14
0
8
R15
0
9
R16
0
10
R17
0
11
R18
0
12
R19
0
13
R20
0
14
LADCOM
IOUTA
IOUTB
NR
(–5V) VEE
REFOUT
NC
(+5V) VDD
REFCOM
(MSB) DB15
IREFIN
DB14
DB0 (LSB)
DB13
DB1
DB12
DB2
DB11
DB3
DB10
DB4
DB9
DB5
DB8
DB6
CLOCK
DB7
DCOM
C3
1µF
C17
0.1µF
C4
1µF
C19
0.1µF
C14
0.1µF
28
27
A
A
26
25
+5D
C15
47µF, 25V
C16
0.1µF
24
R21
0
23
R23
0
22
R24
0
21
R25
0
20
R26
0
19
R27
0
18
R28
0
17
R29
0
16
1
J1
3
J1
5
J1
7
J1
9
J1
11
J1
13
J1
15
J1
15
1
CLOCK
1
2
SW1
2
R11
50
J1
2
J1
16
J1
30
J1
4
J1
18
J1
32
J1
6
J1
20
J1
34
J1
8
J1
22
J1
36
J1
10
J1
24
J1
38
J1
12
J1
26
J1
40
J1
14
J1
28
Figure 35. AD768 Evaluation Board Schematic
REV. B
C13
47µF, 25V
–17–
DGND
AGND CONNECTED TO DGND
ON GND PLANE UNDER U1
IN BETWEEN PINS 5 AND 25
AGND
A
AD768
Figure 36. Silkscreen Layer (Not to Scale)
–18–
REV. B
AD768
Figure 37. Component Side PCB Layout (Not to Scale)
Figure 38. Solder Side PCB Layout (Not to Scale)
REV. B
–19–
AD768
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
R-28
300 Mil 28-Pin SOIC
28
C1941a–5–6/96
0.7125 (18.10)
0.6969 (17.70)
15
0.2992 (7.60)
0.2914 (7.40)
1
14
PIN 1
0.0500
(1.27)
BSC
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING 0.0125 (0.32)
0.0138 (0.35)
PLANE 0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
PRINTED IN U.S.A.
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
0.4193 (10.65)
0.3937 (10.00)
–20–
REV. B
Similar pages