Data Sheet Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC1 Operates from 1.65 V to 3.6 V supply rails Bidirectional level translation, unidirectional signal path 8-lead SOT-23 and MSOP packages Bypass or normal operation Short circuit protection VCC2 VCC1 A1 Y1 VCC1 APPLICATIONS VCC1 VCC2 VCC2 0 JTAG chain bypassing Daisy-chain bypassing Digital switching Y2 1 A2 EN GND 03297-001 ADG3233 Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3233 is a bypass switch designed on a submicron process that operates from supplies as low as 1.65 V. The device is guaranteed for operation over the supply range 1.65 V to 3.6 V. It operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. The signal path is unidirectional, meaning data may only flow from A → Y. 1. 1 This type of device may be used in applications that require a bypassing function. It is ideally suited to bypassing devices in a JTAG chain or in a daisy-chain loop. One switch could be used for each device or a number of devices, thus allowing easy bypassing of one or more devices in a chain. This may be particularly useful in reducing the time overhead in testing devices in the JTAG chain or in daisy-chain applications where the user does not wish to change the settings of a particular device. 2. 3. 4. Bidirectional level translation matches any voltage level from 1.65 V to 3.6 V. The bypass switch offers high performance and is fully guaranteed across the supply range. Short circuit protection. Tiny 8-lead SOT-23 package and 8-lead MSOP. Table 1. Truth Table EN L H Signal Path A1 → Y2, Y1 → VCC1 A1 → Y1, A2 → Y2 Function Enable bypass mode Enable normal mode The bypass switch is packaged in two of the smallest footprints available for its required pin count. The 8-lead SOT-23 package requires only 2.9 mm × 2.8 mm board space, while the MSOP package occupies approximately 3 mm × 4.9 mm board area. 1 U.S. Patent Number: 7,369,385 B2. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG3233 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Product Highlights ........................................................................... 1 A1 and EN Input ........................................................................ 13 Revision History ............................................................................... 2 Normal Operation ...................................................................... 13 Specifications..................................................................................... 3 Bypass Operation ....................................................................... 14 Test Waveforms ............................................................................. 5 Outline Dimensions ....................................................................... 15 Absolute Maximum Ratings ............................................................ 6 Ordering Guide .......................................................................... 16 REVISION HISTORY 7/13—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 7/11—Rev. 0 to Rev. A Changes to Patent Number, General Description Section, and Product Highlights Section ............................................................. 1 Changes to VCC = VCC1 = VCC2 = 2.5 V ± 0.2 V, ENABLE Time EN → Y1, Table 2 ............................................................................. 4 Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 5/03—Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet ADG3233 SPECIFICATIONS VCC1 = VCC2 = 1.65 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 LOGIC INPUTS/OUTPUTS 3 Input High Voltage 4 Symbol VIH Input Low Voltage4 VIL Output High Voltage (Y1) VOH Output Low Voltage (Y1) VOL LOGIC OUTPUTS3 Output High Voltage (Y2) VOH Output Low Voltage (Y2) VOL SWITCHING CHARACTERISTICS 4, 5 VCC = VCC1 = VCC2 = 3.3 V ± 0.3 V Propagation Delay, tPD A1 → Y1 Normal Mode A2 →Y2 Normal Mode A1 → Y2 Bypass Mode ENABLE Time EN → Y1 Test Conditions/Comments VCC2 = 1.65 V to 3.6 V, GND = 0 V VCC1 = 3.0 V to 3.6 V VCC1 = 2.3 V to 2.7 V VCC1 = 1.65 V to 1.95 V VCC1 = 3.0 V to 3.6 V VCC1 = 2.3 V to 2.7 V VCC1 = 1.65 V to 1.95 V IOH = −100 µA, VCC1 = 3.0 V to 3.6 V IOH = −100 µA, VCC1 = 2.3 V to 2.7 V IOH = −100 µA, VCC1 = 1.65 V to 1.95 V IOH = −4 mA, VCC1 = 2.3 V to 2.7 V IOH = −4 mA, VCC1 = 1.65 V to 1.95 V IOH = −8 mA, VCC1 = 3.0 V to 3.6 V IOL = 100 µA, VCC1 = 3.0 V to 3.6 V IOL = 100 µA, VCC1 = 2.3 V to 2.7 V IOL = 100 µA, VCC1 = 1.65 V to 1.95 V IOL = 4 mA, VCC1 = 2.3 V to 2.7 V IOL = 4 mA, VCC1 = 1.65 V to 1.95 V IOL = 8 mA, VCC1 = 3.0 V to 3.6 V VCC1 = 1.65 V to 3.6 V, GND = 0 V IOH = −100 µA, VCC2 = 3.0 V to 3.6 V IOH = −100 µA, VCC2 = 2.3 V to 2.7 V IOH = −100 µA, VCC2 = 1.65 V to 1.95 V IOH = −4 mA, VCC2 = 2.3 V to 2.7 V IOH = −4 mA,VCC2 = 1.65 V to 1.95 V IOH = −8 mA, VCC2 = 3.0 V to 3.6 V IOL = 100 µA, VCC2 = 3.0 V to 3.6 V IOL = 100 µA, VCC2 = 2.3 V to 2.7 V IOL = 100 µA, VCC2 = 1.65 V to 1.95 V IOL = 4 mA, VCC2 = 2.3 V to 2.7 V IOL = 4 mA, VCC2 = 1.65 V to 1.95 V IOL = 8 mA, VCC2 = 3.0 V to 3.6 V Min Typ 2 Max 1.35 1.35 0.65 × VCC Unit 0.40 0.40 0.45 0.40 0.45 0.40 V V V V V V V V V V V V V V V V V V 0.40 0.40 0.45 0.40 0.45 0.40 V V V V V V V V V V V V 0.8 0.7 0.35 × VCC 2.4 2.0 VCC − 0.45 2.0 VCC – 0.45 2.4 2.4 2.0 VCC − 0.45 2.0 VCC – 0.45 2.4 tPHL, tPLH tPHL, tPLH tPHL, tPLH tEN CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 3.5 3.5 4 4 5.4 5.4 6.5 6 ns ns ns ns DISABLE Time EN → Y1 tDIS CL = 30 pF, VT = VCC/2 2.8 4 ns ENABLE Time EN → Y2 tEN CL = 30 pF, VT = VCC/2 4.5 6.5 ns DISABLE Time EN → Y2 tDIS CL = 30 pF, VT = VCC/2 4 6.5 ns Rev. B | Page 3 of 16 ADG3233 Parameter 1 VCC = VCC1 = VCC2 = 2.5 V ± 0.2 V Propagation Delay, tPD A1 → Y1 Normal Mode A2 → Y2 Normal Mode A1 → Y2 Bypass Mode ENABLE Time EN → Y1 Data Sheet Symbol Test Conditions/Comments tPHL, tPLH tPHL, tPLH tPHL, tPLH tEN DISABLE Time EN → Y1 Typ 2 Max Unit CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 4.5 4.5 4.5 5 6.2 6.2 6.5 7.2 ns ns ns ns tDIS CL = 30 pF, VT = VCC/2 3.2 4.7 ns ENABLE Time EN → Y2 tEN CL = 30 pF, VT = VCC/2 5 7.7 ns DISABLE Time EN → Y2 VCC = VCC1 = VCC2 = 1.8 V ± 0.15 V Propagation Delay, tPD A1 → Y1 Normal Mode A2 → Y2 Normal Mode A1 → Y2 Bypass Mode ENABLE Time EN → Y1 tDIS CL = 30 pF, VT = VCC/2 4.8 7.2 ns tPHL, tPLH tPHL, tPLH tPHL, tPLH tEN CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 CL = 30 pF, VT = VCC/2 6.7 6.5 6.5 7 10 10 10.25 10.5 ns ns ns ns DISABLE Time EN → Y1 tDIS CL = 30 pF, VT = VCC/2 4.4 6.5 ns ENABLE Time EN → Y2 tEN CL = 30 pF, VT = VCC/2 7 12 ns DISABLE Time EN → Y2 Input Leakage Current Output Leakage Current POWER REQUIREMENTS Power Supply Voltages tDIS CL = 30 pF, VT = VCC/2 6.5 II IO 0 ≤ VIN ≤ 3.6 V 0 ≤ VIN ≤ 3.6 V Quiescent Power Supply Current Increase in ICC per Input VCC1 VCC2 ICC1 ICC2 ΔICC1 Min 1.65 1.65 Digital inputs = 0 V or VCC Digital inputs = 0 V or VCC VCC = 3.6 V, one input at 3.0 V; others at VCC or GND 10.5 ns ±1 ±1 µA µA 3.6 3.6 2 2 0.75 V V µA µA µA Temperature range is as follows: B Version: −40°C to +85°C. All typical values are at VCC = VCC1 = VCC2, TA = 25°C, unless otherwise stated. 3 VIL and VIH levels are specified with respect to VCC1, VOH, and VOL levels for Y1 are specified with respect to VCC1, and VOH, and VOL levels are specified for Y2 with respect to VCC2. 4 Guaranteed by design, not subject to production test. 5 See the Test Waveforms section. 1 2 Rev. B | Page 4 of 16 Data Sheet ADG3233 TEST WAVEFORMS VCC1 INPUT VT 0V tPHL VOH OUTPUT VT VOL 03297-032 tPLH Figure 2. Propagation Delay VCC1 VT EN 0V tEN tDIS VT VT VOL 03297-033 VOH Y1 (A1 AT GND) Figure 3. Y1 Enable and Disable Times VCC1 VT EN 0V tEN tDIS VCC1 A1 0V VCC1 A2 0V Y2 VT VT VOL Figure 4. Y2 Enable and Disable Times Rev. B | Page 5 of 16 03297-034 VOLH ADG3233 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Digital Inputs to GND A1, EN A2 DC Output Current Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 8-Lead MSOP θJA Thermal Impedance θJC Thermal Impedance 8-Lead SOT-23 θJA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Soldering (Pb-Free) Reflow, Peak Temperature Time at Peak Temperature Rating –0.3 V to +4.6 V –0.3 V to +4.6 V –0.3 V to +4.6 V –0.3 V to VCC1 + 0.3 V 25 mA –40°C to +85°C –65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION 206°C/W 43°C/W 211°C/W 300°C 235°C 260(+0/−5)°C 20 sec to 40 sec Rev. B | Page 6 of 16 Data Sheet ADG3233 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC2 EN 4 VCC2 1 7 5 GND Y1 2 ADG3233 Y2 3 TOP VIEW (Not to Scale) GND 4 Figure 5. 8-Lead SOT-23 Package (RJ-8) 8 VCC1 7 A1 6 A2 5 EN 03297-003 8 ADG3233 Y1 TOP VIEW A2 3 (Not to Scale) 6 Y2 A1 2 03297-002 VCC1 1 Figure 6. 8-Lead MSOP Package (RM-8) Table 4. Pin Function Descriptions Pin No. RJ-8 RM-8 1 8 8 1 2 7 3 6 7 2 6 3 Mnemonic VCC1 VCC2 A1 A2 Y1 Y2 4 5 EN GND 5 4 Description Supply Voltage 1, can be any supply voltage from 1.65 V to 3.6 V. Supply Voltage 2, can be any supply voltage from 1.65 V to 3.6 V. Input Referred to VCC1. Input Referred to VCC2. Output Referred to VCC1. Output Referred to VCC2. Voltage levels appearing at Y2 will be translated from a VCC1 voltage level to a VCC2 voltage level. Active Low Device Enable. When low, bypass mode is enabled; when high, the device is in normal mode. Device Ground. Rev. B | Page 7 of 16 ADG3233 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 30 5.0 VCC1 = 3.3V TA = 25°C 4.5 25 4.0 20 3.0 ICC2 (nA) ICC1 (nA) 3.5 2.5 2.0 VCC2 = 3.3V 15 VCC2 = 2.5V VCC2 = 1.8V 10 1.5 5 VCC2 = 2.5V VCC2 = 3.3V 1.0 VCC2 = 1.8V 0 2.0 3.0 2.5 3.5 4.0 VCC1 (V) –5 03297-004 0 1.5 0 20 30 40 50 TEMPERATURE (°C) 60 70 80 Figure 10. ICC2 vs. Temperature Figure 7. ICC1 vs. VCC1 2000 5.0 TA = 25°C TA = 25°C 4.5 1800 4.0 1600 3.5 1400 3.0 1200 ICC1 (µA) 2.5 VCC1 = VCC2 = 3.3V 1000 VCC1 = VCC2 = 1.8V 800 2.0 600 1.5 VCC1 = 3.3V VCC1 = 2.5V 400 1.0 200 0.5 VCC1 = 1.8V 2.5 2.0 3.5 3.0 4.0 VCC2 (V) 0 10k 03297-005 0 1.5 100k 1M 10M 03297-008 ICC2 (nA) 10 03297-007 0.5 100M FREQUENCY (Hz) Figure 11. ICC1 vs. Frequency, Normal Mode Figure 8. ICC2 vs. VCC2 80 30 TA = 25°C VCC2 = 3.3V 70 25 VCC1 = VCC2 = 3.3V 60 50 ICC1 (µA) VCC1 = 3.3V VCC1 = 2.5V 15 VCC1 = 1.8V 40 VCC1 = VCC2 = 1.8V 30 10 20 5 0 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 0 10k 100k 1M 10M FREQUENCY (Hz) Figure 12. ICC1 vs. Frequency, Bypass Mode Figure 9. ICC1 vs. Temperature Rev. B | Page 8 of 16 100M 03297-009 10 03297-006 ICC1 (nA) 20 Data Sheet ADG3233 2000 10 TA = 25°C 1800 1600 8 1400 TIME (ns) 1000 VCC1 = VCC2 = 1.8V 800 6 tEN 4 tDIS 600 400 2 TA = 25°C VCC1 = VCC2 200 1M 100k 10M 100M FREQUENCY (Hz) 0 1.5 03297-010 0 10k 2.0 Figure 13. ICC2 vs. Frequency, Normal Mode 2.5 3.0 SUPPLY (V) 3.5 4.0 03297-013 ICC2 (µA) VCC1 = VCC2 = 3.3V 1200 Figure 16. Y2 Enable, Disable Time vs. Supply 2000 6 TA = 25°C 1800 5 1600 1400 TIME (ns) 1000 VCC1 = VCC2 = 1.8V 3 tDIS 2 600 400 1 VCC1 = VCC2 = 3.3V 200 100k 1M 10M 100M FREQUENCY (Hz) 0 –40 03297-011 0 10k Figure 14. ICC2 vs. Frequency, Bypass Mode 0 –20 20 40 TEMPERATURE (°C) 60 80 03297-014 ICC2 (µA) 1200 800 tEN 4 VCC1 = VCC2 = 3.3V Figure 17. Y1 Enable, Disable Time vs. Temperature 10 6 5 8 tEN TIME (ns) tEN tDIS 4 tDIS 3 2 2 1 TA = 25°C VCC1 = VCC2 2.0 VCC1 = VCC2 = 3.3V 2.5 3.0 SUPPLY (V) 3.5 4.0 0 –40 Figure 15. Y1 Enable, Disable Time vs. Supply –20 0 20 40 TEMPERATURE (°C) 60 Figure 18. Y2 Enable, Disable Time vs. Temperature Rev. B | Page 9 of 16 80 03297-015 0 1.5 03297-012 TIME (ns) 4 6 ADG3233 Data Sheet 16 10 VCC1 = 3.3V VCC2 = 1.8V TA = 25°C DATA RATE = 10Mbps 14 VCC1 = 1.8V VCC2 = 3.3V TA = 25°C DATA RATE = 10Mbps 9 8 RISE/FALL TIME (ns) 10 8 tPLH, LOW-TO-HIGH TRANSITION 6 7 tPLH, LOW-TO-HIGH TRANSITION 6 5 4 3 4 tPHL, HIGH-TO-LOW TRANSITION 2 tPHL, HIGH-TO-LOW TRANSITION 22 32 42 72 52 62 CAPACITIVE LOAD (pF) 82 92 102 0 22 Figure 19. Rise/Fall Time vs. Capacitive Load, A1 → Y1, A2 → Y2 72 52 62 CAPACITIVE LOAD (pF) 82 92 102 8 VCC1 = 3.3V VCC2 = 1.8V TA = 25°C DATA RATE = 10Mbps 12 10 tPLH, LOW-TO-HIGH TRANSITION 8 6 4 tPHL, HIGH-TO-LOW TRANSITION 32 42 72 52 62 CAPACITIVE LOAD (pF) tPLH, LOW-TO-HIGH TRANSITION 5 4 tPHL, HIGH-TO-LOW TRANSITION 3 2 82 92 102 0 22 Figure 20. Rise/Fall Time vs. Capacitive Load, A1 → Y2, Bypass Mode 32 42 72 52 62 CAPACITIVE LOAD (pF) 82 92 102 03297-020 0 22 6 1 03297-017 2 VCC1 = 3.3V VCC2 = 3.3V TA = 25°C DATA RATE = 10Mbps 7 PROPAGATION DELAY (ns) 14 RISE/FALL TIME (ns) 42 Figure 22. Rise/Fall Time vs. Capacitive Load, A1 → Y2, Bypass Mode 16 Figure 23. Propagation Delay vs. Capacitive Load A1 → Y1 10 8 VCC1 = 1.8V VCC2 = 3.3V TA = 25°C DATA RATE = 10Mbps 8 7 PROPAGATION DELAY (ns) 9 RISE/FALL TIME (ns) 32 03297-019 1 0 03297-016 2 7 tPLH, LOW-TO-HIGH TRANSITION 6 5 4 3 tPHL, HIGH-TO-LOW TRANSITION tPLH, LOW-TO-HIGH TRANSITION 6 5 tPHL, HIGH-TO-LOW TRANSITION 4 3 2 VCC1 = 3.3V VCC2 = 3.3V TA = 25°C DATA RATE = 10Mbps 2 1 1 22 32 42 72 62 52 CAPACITIVE LOAD (pF) 82 92 102 0 03297-018 0 22 Figure 21. Rise/Fall Time vs. Capacitive Load, A1 → Y1, A2 → Y2 32 42 72 62 52 CAPACITIVE LOAD (pF) 82 92 102 Figure 24. Propagation Delay vs. Capacitive Load A2 → Y2 Rev. B | Page 10 of 16 03297-021 RISE/FALL TIME (ns) 12 Data Sheet ADG3233 8 4.0 7 3.5 PROPAGATION DELAY (ns) 6 tPLH, LOW-TO-HIGH TRANSITION 5 tPHL, HIGH-TO-LOW TRANSITION 3 2 VCC1 = 3.3V VCC2 = 3.3V TA = 25°C DATA RATE = 10Mbps 1 32 42 2.0 tPLH, A1 → Y1 tPLH, A2 → Y2 1.5 1.0 0.5 VCC1 = VCC2 = 3.3V 0 22 2.5 72 52 62 CAPACITIVE LOAD (pF) 82 92 102 0 –40 Figure 25. Propagation Delay vs. Capacitive Load A1 → Y2, Bypass Mode –20 0 20 40 TEMPERATURE (°C) 60 03297-025 4 tPHL, A1 → Y1 3.0 03297-022 PROPAGATION DELAY (ns) tPHL, A2 → Y2 80 Figure 28. Propagation Delay vs. Temperature, Normal Mode 8 4 tPHL, A1 → Y2 7 PROPAGATION DELAY (ns) 6 tPHL, A2 → Y2 4 3 tPHL, A1 → Y1 tPLH, A2 → Y2 2 2 1 TA = 25°C VCC1 = VCC2 1 VCC1 = VCC2 = 3.3V 0 1.5 2.0 tPLH, A1 → Y2 3.0 2.5 SUPPLY (V) 3.5 4.0 0 –40 Figure 26. Propagation Delay vs. Supply, Normal Mode –20 0 20 40 TEMPERATURE (°C) 60 03297-026 5 3 03297-023 PROPAGATION DELAY (ns) tPLH, A1 → Y1 80 Figure 29. Propagation Delay vs. Temperature, Bypass Mode 8 6 3.3V A1 Y1 1.8V tPHL, A1 → Y2 4 3 1 tPLH, A1 → Y2 3.3V A2 Y2 2 TA = 25°C VCC1 = VCC2 2 1.5 2.0 2.5 3.0 SUPPLY (V) 3.5 4.0 4 CH1 1.00V CH2 500mV CH3 1.00VΩ CH4 1.00VΩ Figure 27. Propagation Delay vs. Supply, Bypass Mode M5.00ns CH1 1.48V Figure 30. Normal Mode VCC1 = 3.3 V, VCC2 = 1.8 V Rev. B | Page 11 of 16 03297-027 DATA RATE = 10MHz 0 03297-024 PROPAGATION DELAY (ns) TA = 25°C EN = HIGH ADG3233 Data Sheet 1.8V TA = 25°C DATA RATE = 10MHz 3.3V A1 A1 3 1.8V 3.3V Y2 2 1.8V Y2 Y1 3 2 1 M5.00ns CH2 1.47V CH1 1.00V CH2 2.00V CH3 1.00VΩ Figure 31. Bypass Mode, VCC1 = 3.3 V, VCC2 = 1.8 V M5.00ns CH3 900mV 03297-030 CH2 1.00VΩ CH2 500mV 03297-028 TA = 25°C DATA RATE = 10MHz Figure 33. Bypass Mode, VCC1 = 1.8 V, VCC2 = 3.3 V 3.5 VCC = 3.3V 3.3V TA = 25°C VCC = VCC1 = VCC2 3.0 1.8V A1 3 VCC = 2.5V 2.5 Y1 VOLTAGE (V) SOURCE 1 1.8V A2 3.3V 2.0 VCC = 1.8V 1.5 1.0 Y2 TA = 25°C DATA RATE = 10MHz CH1 1.00V CH2 2.00V CH3 5.00VΩ CH4 1.00VΩ M5.00ns CH1 1.48V VCC = 3.3V VCC = 2.5V SINK 0 03297-029 2 VCC = 1.8V 0.5 0 Figure 32. Normal Mode, VCC1 = 1.8 V, VCC2 = 3.3 V 5 10 CURRENT (mA) 15 Figure 34. Y1 and Y2 Source and Sink Current Rev. B | Page 12 of 16 20 03297-031 4 Data Sheet ADG3233 THEORY OF OPERATION NORMAL OPERATION The ADG3233 is a bypass switch designed on a submicron process that operates from supplies as low as 1.65 V. The device is guaranteed for operation over the supply range 1.65 V to 3.6 V. It operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. The signal path is unidirectional, meaning data may only flow from A → Y. Figure 35 shows the bypass switch being used in normal mode. In this mode, the signal paths are from A1 → Y1 and A2 → Y2. The device will level translate the signal applied to A1 to a VCC1 logic level (this level translation can be either to a higher or lower supply) and route the signal to the Y1 output, which will have standard VOL/VOH levels for VCC1 supplies. The signal is then passed through Device 1 and back to the A2 input pin of the bypass switch. A1 AND EN INPUT The A1 and enable (EN) inputs have VIL/VIH logic levels so that the part can accept logic levels of VOL/VOH from Device 0 or the controlling device independent of the value of the supply being used by the controlling device. These inputs (A1, EN) are capable of accepting inputs outside the VCC1 supply range. For example, the VCC1 supply applied to the bypass switch could be 1.8 V while Device 0 could be operating from a 2.5 V or 3.3 V supply rail, there are no internal diodes to the supply rails, so the device can handle inputs above the supply but inside the absolute maximum ratings. The logic level inputs of A2 are with respect to the VCC1 supply. The signal will be level translated from VCC1 to VCC2 and routed to the Y2 output pin of the bypass switch. Y2 output logic levels are with respect to the VCC2 supply. VCC0 VCC1 DEVICE 0 VCC2 DEVICE 1 DEVICE 2 SIGNAL INPUT SIGNAL OUTPUT VCC1 VCC2 Y1 A2 Y2 03297-035 A1 EN LOGIC 1 BYPASS SWITCH Figure 35. Bypass Switch in Normal Mode Rev. B | Page 13 of 16 ADG3233 Data Sheet BYPASS OPERATION The three supplies in Figure 35 and Figure 36 may be any combination of supplies, that is., VCC0, VCC1, and VCC2 may be any combination of supplies, for example, 1.8 V, 2.5 V, and 3.3 V. Figure 36 illustrates the device as used in bypass mode. The signal path is now from A1 directly to Y2, thus bypassing Device 1 completely. The signal will be level translated to a VCC2 logic level and available on Y2, where it may be applied directly to the input of Device 2. In bypass mode, Y1 is pulled up to VCC1. VCC0 VCC1 DEVICE 0 VCC2 DEVICE 1 DEVICE 2 SIGNAL INPUT SIGNAL OUTPUT VCC1 VCC2 Y1 A2 Y2 03297-036 A1 EN LOGIC 0 BYPASS SWITCH Figure 36. Bypass Switch in Bypass Mode Rev. B | Page 14 of 16 Data Sheet ADG3233 OUTLINE DIMENSIONS 3.20 3.00 2.80 5.15 4.90 4.65 5 8 3.20 3.00 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6° 0° 0.40 0.25 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 37. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 38. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters Rev. B | Page 15 of 16 0.60 0.45 0.30 12-16-2008-A 1.30 1.15 0.90 ADG3233 Data Sheet ORDERING GUIDE Model 1 ADG3233BRJ-REEL ADG3233BRJ-REEL7 ADG3233BRJZ-REEL7 ADG3233BRM ADG3233BRM-REEL ADG3233BRM-REEL7 ADG3233BRMZ ADG3233BRMZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Z = RoHS Compliant Part. ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03297-0-7/13(B) Rev. B | Page 16 of 16 Branding W1B W1B S1S W1B W1B W1B S1S S1S Package Option RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8