APA2613 6W Stereo Class-D Audio Power Amplifier Features • • General Description Supply Voltage is 8V ~ 26V The APA2613 is a stereo, high efficiency, Class-D audio Class D operation eliminates heat sink & reduce power supply requirement amplifier available in TSSOP-28Pand QFN4x4-28A pins packages. 20,26, 32, 36, 4 steps gain setting 6W per channel (THD+N=10%)output power into The Class-D power amplifier has higher efficiency compare to the tradition Class-AB power amplifier. The filter- • 8Ω load at 10V, Class D output MONO function combines two channels’output to free Class-D architecture eliminates the external low pass filters. The internal gain setting can minimum the exter- • supply 12W into a 4Ω load at 12V (THD+N=10%) Adjustable Power limit function plus DC Protec- nal component counts, and for the flexible application the gain can be set to 4-step 20, 26, 32, 36dB by gain control • tion Thermal and Over-Current Protections with Auto- ins (GAIN0 and GAIN1). The power limit function cans protection the speaker when output signal excess the Recovery option TSSOP-28P with thermal pad packages speaker limit rating. The integration of Class-D power amplifier is a best so- QFN4x4-28 with thermal pad packages lution for power efficiency and lower the total BOM costs. The operating voltage is from 8V to 26V. The APA2613 • • • • power amplifiers are capable of driving 6 W at VDD=10V into 8Ω speaker, and provides thermal and over-current protections also can detection the DC that prevent to destroy the speaker voice coil. Applications • • Pin Configuration LCD Monitor AIO Simplified Application Circuit SD 1 28 LPVDD FLAG 2 27 LPVDD 26 LBSP LINP 3 25 LOUTP LINN 4 GAIN0 5 APA2613 LOUTP Left Channel Input Right Channel Input LINP LINN RINN LOUTN ROUTN RINP ROUTP 24 PGND 23 LOUTN GAIN1 6 FERRITE BEAD FILTER FERRITE BEAD FILTER AVDD 7 Left Channel Speaker AGND 8 VCLAMP 9 Right Channel Speaker APA2613 TSSOP-28P 22 LBSN 21 RBSN 20 ROUTN PLIMT 10 19 PGND RINN 11 18 ROUTP RINP 12 17 RBSP NC 13 16 RPVDD MONO 14 15 RPVDD ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 1 www.anpec.com.tw APA2613 22 PGND 23 ROUTN 24 RBSN 25 NC 26 LBSN 28 PGND 27 LOUTN Pin Configuration(Cont.) 21 ROUTP LOUTP 1 LBSP 2 LPVDD 3 20 RBSP 19 RPVDD APA2613 QFN4x4-28 SD 4 FLAG 5 LINP 6 18 MONO 17 NC 16 RINP PLIMIT 14 AGND 12 VCLAMP 13 GAIN1 10 AVDD 11 NC 8 15 RINN GAIN0 9 LINN 7 Ordering and Marking Information APA2613 Package Code R : TSSOP-28P QA : QFN4x4-28 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APA2613 R : APA2613 QA : APA2613 XXXXX XXXXX - Date Code XXXXX - Date Code APA2613 XXXXX Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 2 www.anpec.com.tw APA2613 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD Parameter Rating Supply Voltage (PVDD, AVDD) Unit -0.3 to 30 -0.3 to VDD+0.3 Input Voltage ( SD , GAIN0 and GAIN1, MONO and FLAG ) VI PLIMIT -0.3 to 6.3 LINP, LINN, RINP, RINN -0.3 to 6.3 TJ Maximum Junction Temperature V ο 150 TSTG Storage Temperature Range TSDR Soldering Temperature Range, 10 Seconds 260 STEREO Mode : VDD＞15V 4.8 RL STEREO Mode: VDD ≦15V 3.2 PD Power Dissipation C -65 to +150 MONO mode Ω 3.2 Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Unit Thermal Resistance -Junction to Ambient (Note 2) TSSOP-28P QFN4x4-28 45 40 TSSOP-28P QFN4x4-28 8 7 ο C/W Thermal Resistance -Junction to Case (Note 3) Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TSSOP-28P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package. Recommended Operating Conditions Symbol Parameter Min. Max. 8.0 26.0 SD 2.2 - GAIN0, GAIN1, MONO 2.0 - SD - 0.8 GAIN0, GAIN1, MONO - 0.8 Unit VDD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage TA Ambient Temperature Range -40 85 o TJ Junction Temperature Range -40 125 o RL Speaker Resistance 3.5 - Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 3 V C C Ω www.anpec.com.tw APA2613 Electrical Characteristics VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA2613 Min. Typ. Max. Unit Regulated Voltage IO=2mA, VDD=8~26V TJ = -40oC ~ 125oC 4.5 5 5.5 Maximum Output Voltage Under PLIMIT Control VPLIMIT = 1V, Vl = 1Vrms 4.6 5.5 6.1 TSD(ON) Shutdown Turn-On Time SD =2.2V - 16 - ms TSD(OFF) Shutdown Turn-Off Time SD =0.8V - 2 - µs IDD Quiescent Supply Current No Load - 20 35 mA ISD Quiescent Supply Current in shutdown mode SD = 0V - 10 100 Input Current SD , GAIN0, GAIN1, MONO - 5 50 400 500 600 kHz VDD = 12V, IL= 0.5A - 400 - mΩ Gain 0 = 0, Gain 1 = 0 - 20 - Gain 0 = 1, Gain 1 = 0 - 26 - Gain 0 = 0, Gain 1 = 1 - 32 - Gain 0 = 1, Gain 1 = 1 - 36 - VCLAMP VO II FOSC Internal Oscillator Frequency RDSON Static Drain-Source On-State Resistance AV Gain V µA dB Stereo Mode VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA2613 Min. Typ. Max. Unit VDD = 24V, TA = 25° C Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -85 - SNR Signal-To-Noise Ratio Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - 95 - Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - -100 - Offset Voltage AV=20dB - - 15 mV Noise Output Voltage With A-weighted Filter (AV = 20dB) - 120 - µV (rms) RL=8Ω - 7 - RL=8Ω - 8.5 - RL = 8Ω PO = 4W - 0.1 - Crosstalk I VOS I Vn dB dB VDD = 12V TA = 25° C PO THD+N Output Power Total Harmonic Distortion Plus Noise THD+N = 1% FIN=1kHz THD+N = 10% FIN=1kHz FIN=1kHz W % Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -90 - SNR Signal-To-Noise Ratio Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - 95 - Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - -100 - Offset Voltage AV=20dB - - 15 mV Noise Output Voltage With A-weighted Filter (AV = 20dB) - 120 - µV (rms) Crosstalk I VOS I Vn Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 4 dB www.anpec.com.tw APA2613 Mono Mode VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA2613 Min. Typ. Max. RL = 4Ω - 9 - RL = 4Ω - 12 - RL = 4Ω PO = 6W Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - 0.1 - - 95 - Unit VDD = 12V TA = 25° C PO THD+N Output Power Total Harmonic Distortion Plus Noise THD+N = 1% FIN=1kHz THD+N = 10% FIN=1kHz W FIN=1kHz % SNR Signal-To-Noise Ratio Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1Vrms - -100 - VOS Offset Voltage AV = 20dB - - 15 mV Vn Noise Output Voltage With A-weighted Filter (AV = 20dB) - 120 - µV (rms) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 5 dB www.anpec.com.tw APA2613 Typical Operating Characteristics 10 10 PO=5W PO=2.5W 0.01 VDD=18V RL=8Ω Ci=1µF Gain=20dB AES-17(20kHz) 1 THD+N (%) THD+N (%) 0.1 THD+N vs. Frequency THD+N vs. Frequency VDD=12V RL=8Ω Ci=1µF Gain=20dB 1 AES-17(20kHz) PO=5W 0.1 0.01 PO=0.5W PO=1W 0.001 20 0.001 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 20 10 1 THD+N vs. Frequency VDD=24V RL=8Ω Ci=1µF Gain=20dB AES-17(20kHz) 1 THD+N (%) 0.1 0.01 VDD=12V RL=6Ω Ci=1µF Gain=20dB AES-17(20kHz) 0.1 PO=2.5W 0.01 50 100 200 500 1k PO=0.5W 2k 0.001 20 5k 10k 20k THD+N vs. Frequency 2k 5k 10k 20k 10 VDD=12V RL=4Ω Ci=1µF Gain=20dB 1 AES-17(20kHz) VDD=18V RL=6Ω Ci=1µF Gain=20dB AES-17(20kHz) THD+N (%) PO=5W 0.1 0.01 0.1 PO=5W 0.01 PO=1W PO=1W 0.001 20 500 1k THD+N vs. Frequency 10 THD+N (%) 50 100 200 Frequency (Hz) Frequency (Hz) 1 5k 10k 20k PO=5W PO=1W 0.001 20 2k THD+N vs. Frequency 10 PO=5W THD+N (%) 500 1k Frequency (Hz) Frequency (Hz) 50 100 200 500 1k 2k 0.001 20 5k 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 6 www.anpec.com.tw APA2613 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 VDD=12V RL=8Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) fin=1kHz THD+N (%) THD+N (%) 1 10 fin=20Hz 1 VDD=18V RL=8Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) fin=1kHz fin=10kHz 0.1 0.01 0.01 1 0.1 0.01 0.01 10 10 Output Power (W) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=24V RL=8Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) VDD=12V RL=6Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) 1 THD+N (%) THD+N (%) fin=20Hz 1 0.1 Output Power (W) 1 fin=10kHz 0.1 fin=20Hz fin=1kHz fin=10kHz 0.1 fin=20Hz fin=1kHz fin=10kHz 0.1 0.01 0.01 0.01 0.1 1 0.006 0.01 10 0.1 THD+N vs. Output Power THD+N vs. Output Power VDD=18V RL=6Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) 1 THD+N (%) THD+N (%) 10 10 10 1 1 Output Power (W) Output Power (W) fin=20Hz fin=1kHz fin=10kHz 0.1 VDD=12V RL=4Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) fin=20Hz fin=1kHz fin=10kHz 0.1 0.01 0.006 0.01 0.1 1 0.01 0.01 10 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 0.1 1 10 Output Power (W) 7 www.anpec.com.tw APA2613 Typical Operating Characteristics Frequency Response THD+N vs. Output Power +28 10 Gain, AV=26dB +24 VDD=24V Gain, AV=20dB +20 +0 +18 Phase, AV=26dB +16 0.1 VDD=12V RL=8Ω PO=0.6W Ci=1µF AUX-0025 +14 VDD=12V VDD=18V +12 0.01 0.01 0.1 10 1 +10 20 40 Frequency Response 90 VDD=12V RL=8Ω PO=0.6W Ci=1µF AUX-0025 +20 20 Phase, AV=20dB Efficiency (%) Phase, AV=26dB Phase (Degree) Gain (dB) 70 +0 +22 80 +100 Gain, AV=32dB +30 +24 VDD=12V 60 VDD=18V 50 VDD=24V 40 RL=8Ω+33µH fin=1kHz THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) 30 -100 20 10 100 1k -200 100k 10k 20k 0 0 1 2 Frequency (Hz) 100 90 90 80 80 Efficiency (%) VDD=12V 60 VDD=18V RL=6Ω+33µH fin=1kHz THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) 30 20 10 5 6 7 8 9 10 VDD=12V 70 70 40 4 Efficiency vs. Output Power Efficiency vs. Output Power Efficiency (%) 3 Output Power (W) 100 50 -200 100k 100 Gain, AV=32dB +34 +26 10k 20k Efficiency vs. Output Power +200 +28 1k -100 Frequency (Hz) +38 +32 Phase, AV=20dB 100 Output Power (W) +36 +100 +22 Gain (dB) THD+N (%) +26 Phase (Degree) 1 RL=4Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) mono mode +200 60 50 40 RL=4Ω+33µH fin=1kHz THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) 30 20 10 0 0 0 1 2 3 4 5 6 7 8 9 0 10 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 1 2 3 4 5 6 7 8 9 10 Output Power (W) 8 www.anpec.com.tw APA2613 Typical Operating Characteristics Crosstalk vs. Frequency Efficiency vs. Output Power 100 +0 90 -10 80 -20 -30 VDD=12V 60 Crosstalk Efficiency (%) 70 VDD=18V 50 RL=4Ω+33µH fin=1kHz THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) Mono mode 40 30 20 10 2 4 6 8 10 12 14 -50 -60 L-ch to R-ch -70 -80 R-ch to L-ch -90 -100 -110 -120 20 0 0 -40 VDD=12V VO=1V RL=8Ω AV=20dB AUX-0025 AES-17(20kHz) 16 100 Output Power (W) PSRR vs. Frequency +0 -20 VDD=12V RL=8Ω AV=20dB Vrr=0.2Vrms AUX-0025 AES-17(20kHz) -20 -30 L-channel -40 -50 VDD=12V RL=4Ω AV=20dB Vrr=0.2Vrms AUX-0025 AES-17(20kHz) Mono mode -10 PSRR (dB) -10 PSRR (dB) 10k 20k PSRR vs. Frequency +0 R-channel -30 -40 -50 -60 -60 -70 20 100 1k -70 20 10k 20k 100 Shutdown Attenuation vs. Frequency -50 10k 20k 1k Frequency (Hz) Frequency (Hz) Supply Current vs. Supply Voltage 24 No Load -60 20 -70 Supply Current (mA) Shutdown Attenuation (dB) 1k Frequency (Hz) -80 L-channel -90 -100 R-channel -110 16 12 8 4 -120 0 20 100 1k 10k 20k Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Supply Voltage (V) Frequency (Hz) 9 www.anpec.com.tw APA2613 Typical Operating Characteristics 5 Shutdown Current vs. Supply Voltage No Load Shutdown Current (µA) 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 10 www.anpec.com.tw APA2613 Pin Description PIN I/O/P FUNCTION NO. TSSOP -28P QFN4x4 -28 NAME 1 4 SD I 2 5 FLAG O 3 6 LINP I Positive audio input for left channel. Biased at VCLAMP/2. 4 7 LINN I Negative audio input for left channel. Biased at VCLAMP/2. 5 9 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVDD. 6 10 GAIN1 I Gain select least significant bit. TTL logic levels with compliance to AVDD. Shutdown logic input for audio amp (Low=outputs disabled, High=output enabled). TTL logic levels with compliance to AVDD. Protection flag output (open drain). Connecting FLAG and SD can be set to auto-recovery. Otherwise need to reset by cyding AVDD 7 11 AVDD P Analog supply. 8 12 AGND P Analog signal ground. Connect to the thermal pad. 9 13 VCLAMP O 10 14 PLIMIT I Regulated voltage, Nominal voltage is 5V. Power limit level adjust. Connect a resistor divider from VCLAMP to GND to set power limit. Connect directly to VCLAMP for no power limit. 11 15 RINN I Negative audio input for right channel. Biased at VCLAMP/2. 12 16 RINP I Positive audio input for right channel. Biased at VCLAMP/2. 13 8, 17 NC 14 18 MONO I Parallel BTL mode switch. 15,16 19 RPVDD P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally. 17 20 RBSP I Bootstrap I/O for right channel, positive high-side FET. 18 21 ROUTP O Class-D H-bridge positive output for right channel. 19, 24 22, 28, 25 PGND P Power ground for the H-bridges. 20 23 ROUTN O Class-D H-bridge negative output for right channel. 21 24 RBSN I Bootstrap I/O for right channel, negative high-side FET. 22 26 LBSN I Bootstrap I/O for left channel, negative high-side FET. 23 27 LOUTN O Class-D H-bridge negative output for left channel. 25 1 LOUTP O Class-D H-bridge positive output for left channel. 26 2 LBSP I Bootstrap I/O for left channel, positive high-side FET. 27,28 3 LPVDD P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 Not connected. 11 www.anpec.com.tw APA2613 Block Diagram LBSP VCLAMP LPVDD LPVDD LOUTP FB MONO Select Gate Drive LOUTP FB LOUTP LINP Gain Control PWM Logic PLIMIT PGND VCLAMP LPVDD LINN LBSN LPVDD LOUTN FB LOUTN FB Gate Drive LOUTN FLAG Biases and References SD TTL Buffer GAIN0 GAIN1 GAIN Control PLIMIT Reference PLIMIT PGND SD Detect DC Detect LPVDD Thermal Detect RPVDD Startup Protection Logic RAMP GEN. UVLO/OCL O RBSN VCLAMP LDO Regulator AVDD RPVDD RPVDD VCLAMP VCLAMP Gate Drive ROUTN FB ROUTN ROUTN FB RINN Gain Control PLIMIT PWM Logic PGND VCLAMP RPVDD RBSP RPVDD RINP ROUTP FB MONO Select Gate Drive ROUTP ROUTP FB MONO TTL Buffer MONO Select PGND AGND Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 12 www.anpec.com.tw APA2613 Typical Application Circuit VDD 100µF 0.1µF 1000pF 100kΩ (Recommmanded) 1kΩ (Recommmanded) Shutdown Control 1µF Left Channel Input Signal 1µF Gain Setting SD 1 28 LPVDD FLAG 2 LINP 3 27 LPVDD 26 LBSP LINN 4 25 LOUTP GAIN0 5 24 PGND GAIN1 6 23 LOUTN AVDD 7 22 LBSN 1µF AGND 8 1µF 1µF 10kΩ 10kΩ 1µF Right Channel Input Signal VCLAMP 9 APA2613 1000pF BEAD 0.22µF 0.22µF 21 RBSN BEAD 1000pF BEAD 20 ROUTN PLIMIT 10 1000pF 19 PGND RINN 11 18 ROUTP RINP 12 17 RBSP 1µF 0.22µF NC 13 16 RPVDD MONO 14 15 RPVDD BEAD 1000pF 0.22µF 100µF 0.1µF 1000pF 29 GND Stereo VDD VDD 100µF 1kΩ (Recommmanded) Shutdown Control Gain Setting SD 1 28 LPVDD FLAG 2 27 LPVDD LINP 3 26 LBSP LINN 4 25 LOUTP GAIN0 5 24 PGND GAIN1 6 23 LOUTN AVDD 7 22 LBSN 1µF AGND 8 1µF VCLAMP 9 APA2613 1000pF 0.47µF BEAD 1000pF 21 RBSN BEAD 20 ROUTN PLIMIT 10 Right Channel Input Signal 0.1µF 100kΩ (Recommmanded) 10Ω 1000pF 19 PGND 1µF RINN 11 18 ROUTP 1µF RINP 12 17 RBSP NC 13 16 RPVDD MONO 14 15 RPVDD 0.47µF 100µF 0.1µF 1000pF MONO VDD Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 13 www.anpec.com.tw APA2613 Function Description Class-D Operation the switching period, reducing the switching current, which reduces any I2R losses in the load. Output = 0 Gain Setting Operation VOUTP VOUTN VOUT (VOUTP-VOUTN) GAIN1 GAIN0 Gain Ri(Ω) 0 0 20dB 60k 0 1 26dB 30k 1 0 32dB 15k 1 1 36dB 9k Table 1 : The Gain Setting The APA2613’s gain can be set by GAIN0, GAIN1. The detail gain setting value is list at table 1. IOUT Output > 0 Shutdown Operation VOUTP In order to reduce power consumption while not in use, the APA2613 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature VOUTN turns the amplifier off when logic low is placed on the SD pin for APA2613. The trigger point between a logic high VOUT (VOUTP-VOUTN) and logic low level is typically 2.2V. It is best to switch between ground and the supply voltage VDD to provide IOUT maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consumption- cur- Output < 0 VOUTP rent state, IDD for APA2613 is in shutdown mode. On normal operating, APA2613’s SD pin should pull to high level VOUTN to keeping the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changes. VOUT (VOUTP-VOUTN) Power Limit Operation The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. IOUT Add a resistor divider from Vclamp to ground to set the voltage at the PLIMIT pin. An external reference may also Figure1. The APA2613 Output Waveform be used if tighter tolerance is required. Also add a 1µF capacitor from pin 10 to ground. The APA2613 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The VOUTP and VOUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of VOUTP is greater than 50% and VOUTN is less than 50% for positive output voltages. The duty cycle of VOUTP is less than 50% and VOUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 14 www.anpec.com.tw APA2613 Function Description (Cont.) Power Limit Operation (Cont.) DC Detect The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to When a DC signal applies to the input of APA2613 and the time excesses 500ms, the APA2613’s DC detect fault fixed maximum value. This limit can be thought of as a “virtual” voltage rail which is lower than the supply con- will be reported on the FLAG pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by nected to PVDD. This “virtual” rail is 5.6 times the voltage at the PLIMIT pin. This output voltage can be used to changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVDD supply. Cycling calculate the maximum output power for a given maximum input voltage and speaker impedance. SD will NOT clear a DC detect fault. . Over-Current Protection APA2613 has protection from over-current conditions VP = 5.6 × PLIMIT voltage if PLIMIT < 2.5 V PVDD=12V, Rl=8Ω PLIMIT Voltage 1.05V MAX Output Power @ THD+N=10% 2W caused by a short circuit on the output stage. The short circuit protection fault is reported on the FLAG pin as a PVDD=12V, Rl=8 Ω 1.37V 3W PVDD=12V, Rl=8 Ω 1.59V 4W low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. PVDD=12V, Rl=8 Ω 1.78V 5W PVDD=12V, Rl=4 Ω 0.77V 2W PVDD=12V, Rl=4 Ω 0.96V 3W PVDD=12V, Rl=4 Ω 1.15V 4W PVDD=12V, Rl=4 Ω 1.3V 5W Test Conditions The latch can be cleared by cycling the SD pin through the low state. Connect FLAG to SD pin, the over current protection will be auto recovery. Thermal Protection Table2. PLIMIT Typical Operation Thermal protection on the APA2613 prevents damage to VCLAMP Supply the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from The VCLAMP is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown voltage divider circuit. Add a 1µF capacitor to ground at this pin. state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of Stereo/mono switching Operation the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction. APA2613 offers the feature of Stereo operation with two outputs of each channel connected directly. If the MONO pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in Thermal protection faults are NOT reported on the FLAG terminal. phase. To operate in this mono mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. MONO mode can increase more output power compare to the stereo mode single channel’s output power. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 15 www.anpec.com.tw APA2613 Application Information Input Resistance, Ri A ferrite bead may need if it’s failing the test for FCC or CE tested without the LC filter. The figure 2 is the sample for Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the added ferrite bead; the ferrite show choosing high impedance in high frequency. largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Ferrite OUTP Bead Input Capacitor, Ci 1nF In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to the proper Ferrite OUTN Bead dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (RI) form a high-pass 4Ω 1nF filter with the corner frequency determined in Equation 1. fC(hipass ) = 1 2πRiCi (1) Figure 3. Ferrite Bead Output Filter The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the Figure 4 and Figure 5 are examples for added the LC filter (Butterworth), it’s recommended for the situation that the trace form amplifier to speaker is too long, and needs example where RI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 1 is to eliminate the radiated emission or EMI. reconfigured as Equation 2. Ci = 1 2πRi fc (2) In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 µF as this value is commonly used. If the OUTP 33µH 1µF gain is known and is constant, use RI from Table 1 to calculate CI. A further consideration for this capacitor is OUTN 33µH the leakage path from the input source through the input network CI and the feedback network to the load. This 8Ω 1µF leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially Figure 4. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8Ω in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at V /2, which is CLAMP likely higher than the source dc level. Note that it is impor- OUTP 2.2µF tant to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset volt- OUTN 15µH ages and it is important to ensure that boards are cleaned properly. 4Ω 2.2µF Output Low-Pass Filter If the traces form APA2613 to speaker are short, it doesn’t require output filter for FCC & CE standard. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 15µH Figure 5. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4Ω 16 www.anpec.com.tw APA2613 Application Information (Cont.) 1.The high frequency decoupling capacitors should be Power-Supply Decoupling Capacitor, CS placed as close to the PVDD and AVDD terminals as possible. Large (100µF or greater) bulk power supply The APA2613 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to decoupling capacitors should be placed near the APA2613 on the LPVDD and RPVDD supplies. Local, ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents high-frequency bypass capacitors should be placed as close to the PVDD pins as possible. These caps the oscillations being caused by long lead length between the amplifier and the speaker. can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, The optimum decoupling is achieved by using two different types of capacitors that target on different types of good quality low ESR ceramic capacitor between 1000 pF and 10nF and a larger mid-frequency cap of value noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low between 0.1µF and 1µF also of good quality to the PVDD connections at each end of the chip. equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF placed as close as possible to the device 2.Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to AVDD pin . PGND as small and tight as possible. The size of this current loop determines its effectiveness as an BSN and BSP Capactiors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors antenna. 3.Grounding— The AVDD (pin 7) decoupling capacitor for the high side of each output to turn on correctly. A 0. 22µF ceramic capacitor, rated for at least 25 V, must be should be grounded to analog ground (AGND). The PVDD decoupling capacitors should connect to PGND. connected from each output to its corresponding bootstrap input. Specifically, one 0.22µF capacitor must be connected from OUTP to BSP, and one 0.22µF capacitor Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the APA2613. must be connected from OUTN to BSN. The bootstrap capacitors connected between the BSP or 4.Output filter— The ferrite EMI filter (Figure 3) should be placed as close to the output terminals as possible for BSN pins and corresponding output function as a floating power supply for the high-side N-channel power the best EMI performance. The LC filter (Figure 4 and Figure 5) should be placed close to the outputs. The MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source capacitors used in both the ferrite and LC filters should be grounded to power ground. voltage high enough to keep the high-side MOSFETs turned on. 5.Thermal Pad— The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows Layout Recommendation of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the The APA2613 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is neces- thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom sary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. EMC requirements. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 17 www.anpec.com.tw APA2613 Package Information TSSOP-28P D SEE VIEW A E2 EXPOS ED PAD E1 E D1 c 0.25 b S Y M B O L VIEW A L GAUGE PLANE SEATING PLANE 0 A1 A2 A e TSSOP-28P INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 0.008 c 0.09 0.20 0.004 D 9.60 9.80 0.378 0.386 D1 4.50 6.00 0.177 0.236 0.260 E 6.20 6.60 0.244 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 0.75 0.018 8o 0o e 0.65 BSC L 0.45 0 0o 0.026 BSC 0.030 8o Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 18 www.anpec.com.tw APA2613 Package Information QFN4x4-28 D b E A Pin 1 A1 A3 D2 L K E2 Pin 1 Corner e S Y M B O L A A1 QFN4x4-28 MILLIMETERS INCHES MIN. MAX. 0.80 0.00 A3 MIN. MAX. 1.00 0.031 0.039 0.05 0.000 0.002 0.008 REF 0.20 REF b 0.17 0.27 0.007 0.011 D 3.90 4.10 0.154 0.161 D2 2.10 2.50 0.083 0.098 E 3.90 4.10 0.154 0.161 E2 2.10 2.50 0.083 0.098 0.45 0.014 e 0.45 BSC L 0.35 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 0.016 BSC 0.018 0.008 19 www.anpec.com.tw APA2613 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN4x4-28 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type QFN4x4-28 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 Unit Tape & Reel Quantity 3000 20 www.anpec.com.tw APA2613 Carrier Tape & Reel Dimensions P1 P2 P0 D0 B0 W F E1 A D1 K0 A0 B A B SECTION A-A SECTION B-B H A d T1 Application TSSOP-28P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 4.00±0.10 12.00±0.10 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 10.20.±0.20 1.50±0.20 (mm) Devices Per Unit Package Type TSSOP-28P Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 Unit Tape & Reel Quantity 2000 21 www.anpec.com.tw APA2613 Taping Direction Information TSSOP-28P USER DIRECTION OF FEED QFN4x4-28 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 22 www.anpec.com.tw APA2613 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 23 www.anpec.com.tw APA2613 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 24 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2613 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2012 25 www.anpec.com.tw