Product Folder Sample & Buy Technical Documents Support & Community Tools & Software DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 DAC5675A-SP Radiation-Tolerant, 14-Bit, 400-MSPS Digital-to-Analog Converter 1 Features 3 Description • The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs). 1 • • • • • • • • • QMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-07204 – 5962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C) – 5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic Performance High-Performance 52-Pin Ceramic Quad Flat Pack (HFG) 400-MSPS Update Rate LVDS-Compatible Input Interface Spurious-Free Dynamic Range (SFDR) to Nyquist – 69 dBc at 70 MHz IF, 400 MSPS W-CDMA Adjacent Channel Power Ratio (ACPR) – 73 dBc at 30.72 MHz IF, 122.88 MSPS – 71 dBc at 61.44 MHz IF, 245.76 MSPS Differential Scalable Current Outputs: 2 to 20 mA On-Chip 1.2-V Reference Single 3.3-V Supply Operation Power Dissipation: 660 mW at ƒCLK = 400 MSPS, ƒOUT = 20 MHz 2 Applications • • • • Radiation Hardened Digital to Analog (DAC) Applications Space Satellite RF Data Transmission Cellular Base Transceiver Station Transmit Channel: – CDMA: WCDMA, CDMA2000, IS-95 – TDMA: GSM, IS-136, EDGE/GPRS – Supports Single-Carrier and Multicarrier Applications Engineering Evaluation (/EM) Samples are Available (1) The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ƒCLK = 400 MSPS, ƒOUT = 70 MHz. The DAC5675ASP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD. The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)). Device Information(1) PART NUMBER DAC5675A-SP PACKAGE HFG (52 CQFP) BODY SIZE (NOM) 19.05 mm × 19.05 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic SLEEP DAC5675A Bandgap Reference 1.2V EXTIO BIASJ Current Source Array Output Current Switches Decoder DAC Latch + Drivers Control Amp 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches 14 (1) 1 These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life. CLK Clock Distribution CLKC AVDD(4x) AGND(4x) DVDD(2x) DGND(2x) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 2 3 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 DC Electrical Characteristics (Unchanged After 100 kRad).......................................................................... 6 AC Electrical Characteristics (Unchanged After 100 kRad).......................................................................... 8 Digital Specifications (Unchanged After 100 kRad) 10 Electrical Characteristics ........................................ 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 14 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 14 14 14 20 Application and Implementation ........................ 21 9.1 Application Information............................................ 21 9.2 Typical Application ................................................. 21 10 Power Supply Recommendations ..................... 24 11 Layout................................................................... 24 11.1 Layout Guidelines ................................................. 24 11.2 Layout Example .................................................... 24 11.3 Thermal Considerations ........................................ 25 12 Device and Documentation Support ................. 27 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 13 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (January 2014) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Updated supply voltage absolute maximum ratings for AVDD to DVDD .................................................................................. 5 Changes from Revision E (April 2013) to Revision F Page • Added /EM bullet to Features ................................................................................................................................................. 1 • Deleted Ordering Information table ........................................................................................................................................ 3 2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 5 Description (continued) LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for highspeed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edgetriggered input latches provide for minimum setup and hold times, thereby relaxing interface timing. The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doublyterminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V. An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW. The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 3 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 6 Pin Configuration and Functions NC SLEEP BIASJ EXTIO AVDD AGND IOUT2 IOUT1 AVDD AGND AGND AVDD AGND HFG Package 52-Pin CQFP (Top View) 52 51 50 49 48 47 46 45 44 43 42 41 40 D13A 1 39 AGND D13B 2 38 D0B D12A 3 37 D0A D12B D11A 4 36 D1B 5 35 D1A D11B 6 D2B D10A 7 34 33 D10B D9A 8 32 D3B 9 31 D3A D9B 10 30 D4B D8A 11 29 D4A D8B 12 28 D5B AGND 13 27 D5A D2A D6B AGND CLK D6A CLKC AGND AVDD DGND DVDD DVDD DGND D7B D7A 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Functions PIN NAME NO. AGND 13, 20, 26, 39, 44, 49, 50, 52 AVDD BIASJ I/O DESCRIPTION I Analog negative supply voltage (ground). Pin 13 is internally connected to the heat slug and lid (lid is also grounded internally). 21, 45, 48, 51 I Analog positive supply voltage 42 O Full-scale output current bias CLK 23 I External clock input CLKC 22 I Complementary external clock D[13:0]A 1, 3, 5, 7, 9, 11, 14, 24, 27, 29, 31, 33, 35, 37 I LVDS positive input, data bits 13–0. D13A is the most significant data bit (MSB). D0A is the least significant data bit (LSB). D[13:0]B 2, 4, 6, 8, 10, 12, 15, 25, 28, 30, 32, 34, 36, 38 I LVDS negative input, data bits 13–0. D13B is the most significant data bit (MSB). D0B is the least significant data bit (LSB). DGND 17, 19 I Digital negative supply voltage (ground) DVDD 16, 18 I Digital positive supply voltage EXTIO 43 I/O Internal reference output or external reference input. Requires a 0.1-μF decoupling capacitor to AGND when used as reference output. IOUT1 46 O DAC current output. Full-scale when all input bits are set '0'. Connect the reference side of the DAC load resistors to AVDD. IOUT2 47 O DAC complementary current output. Full-scale when all input bits are '1'. Connect the reference side of the DAC load resistors to AVDD. NC 41 SLEEP 40 4 Not connected in chip. Can be high or low. I Asynchronous hardware power-down input. Active high. Internal pulldown. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted) (1) MIN MAX AVDD (2) –0.3 3.6 DVDD (3) –0.3 3.6 AVDD to DVDD –3.6 3.6 –0.3 0.5 V –0.3 AVDD + 0.3 V –0.3 DVDD + 0.3 V IOUT1, IOUT2 (2) –1 AVDD + 0.3 V (2) –1 Supply voltage Voltage between AGND and DGND CLK, CLKC (2) Digital input D[13:0]A, D[13:0]B (3), SLEEP, DLLOFF EXTIO, BIASJ UNIT V AVDD + 0.3 V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Lead temperature 1.6 mm (1/16 inch) from the case for 10 s 260 °C 150 °C Storage temperature, Tstg (1) (2) (3) –65 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to AGND Measured with respect to DGND 7.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) VALUE UNIT ±4000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 3.15 3.3 3.6 V DVDD Digital supply voltage 3.15 3.3 3.6 V TJ Operating junction temperature range 5962-0720401 –55 125 5962-0720402 –55 115 °C 7.4 Thermal Information DAC5675A-SP THERMAL METRIC (1) HFG (CQFP) UNIT 52 PINS RθJA Junction-to-free-air thermal resistance (2) 21.813 (3) RθJC(bot) Junction-to-case (bottom) thermal resistance RθJB Junction-to-board thermal resistance N/A ψJT Junction-to-top characterization parameter N/A ψJB Junction-to-board characterization parameter N/A (1) (2) (3) 0.849 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Board mounted, per JESD 51-5 methodology MIL-STD-883 test method 1012 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 5 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 7.5 DC Electrical Characteristics (Unchanged After 100 kRad) over operating junction temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS Resolution 5962-0720401 MIN TYP 5962-0720402 MAX 14 MIN TYP MAX 14 UNIT bit DC ACCURACY (1) INL Integral nonlinearity TMIN to TMAX –4 ±1.5 4.6 –4 ±1.5 4.6 DNL Differential nonlinearity T25°C to TMAX –2 ±0.6 2.2 –2 ±0.6 2.2 TMIN –2 ±0.6 2.5 –2 ±0.6 2.5 Monotonicity Monotonic 12b Level LSB LSB Monotonic 12b Level ANALOG OUTPUT IO(FS) Full-scale output current Output compliance range AVDD = 3.15 to 3.45 V, IO(FS) = 20 mA 2 20 2 20 AVDD – 1 AVDD + 0.3 AVDD – 1 AVDD + 0.3 Offset error Gain error 0.01 0.01 –10 5 10 –10 5 10 With internal reference –10 2.5 10 –10 2.5 10 Output capacitance V %FSR Without internal reference Output resistance mA %FSR 300 300 kΩ 5 5 pF REFERENCE OUTPUT V(EXTIO) Reference voltage 1.17 Reference output current (2) 1.23 1.30 1.17 100 1.23 1.30 100 V nA REFERENCE INPUT V(EXTIO) Input reference voltage 0.6 Input resistance 1.2 1.25 0.6 1.2 1.25 V 1 1 MΩ Small-signal bandwidth 1.4 1.4 MHz Input capacitance 100 100 pF 12 12 ppm of FSR/°C ±50 ±50 ppm/°C TEMPERATURE COEFFICIENTS Offset drift ΔV(EXTIO) Reference voltage drift POWER SUPPLY AVDD Analog supply voltage 3.15 3.3 3.6 3.15 3.3 3.6 V DVDD Digital supply voltage 3.15 3.3 3.6 3.15 3.3 3.6 V I(AVDD) Analog supply current (3) 115 148 115 138 mA (1) (2) (3) 6 Measured differential at IOUT1 and IOUT2: 25 Ω to AVDD Use an external buffer amplifier with high impedance input to drive any external load. Measured at ƒCLK = 400 MSPS and ƒOUT = 70 MHz Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 DC Electrical Characteristics (Unchanged After 100 kRad) (continued) over operating junction temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted) PARAMETER I(DVDD) Digital supply current (3) PD Power dissipation APSRR DPSRR Analog and digital powersupply rejection ratio TEST CONDITIONS 5962-0720401 MIN Sleep mode MAX 85 130 MIN 18 AVDD = 3.3 V, DVDD = 3.3 V AVDD = 3.15 to 3.45 V 5962-0720402 TYP TYP MAX 85 120 UNIT mA 18 660 900 –0.9 ±0.1 0.9 –0.9 ±0.1 0.9 660 850 –0.9 ±0.1 0.9 –0.9 ±0.1 0.9 mW %FSR/V Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 7 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 7.6 AC Electrical Characteristics (Unchanged After 100 kRad) over operating junction temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential transformer-coupled output, 50-Ω doubly-terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS 5962-0720401 MIN TYP 5962-0720402 MAX MIN TYP MAX UNIT ANALOG OUTPUT ƒCLK Output update rate ts(DAC) Output setting time to 0.1% tPD Output propagation delay tr(IOUT) tf(IOUT) 400 12 12 1 1 Output rise time, 10% to 90% 300 300 Output fall time, 90% to 10% 300 300 IOUTFS = 20 mA 55 55 IOUTFS = 2 mA 30 30 ƒCLK = 100 MSPS, ƒOUT = 19.9 MHz 70 70 ƒCLK = 160 MSPS, ƒOUT = 41 MHz 72 72 ƒCLK = 200 MSPS, ƒOUT = 70 MHz 68 Output noise Transition: code x2000 to x23FF 400 MSPS ns ns ps ps pA/√Hz AC LINEARITY THD SFDR SFDR Total harmonic distortion Spurious-free dynamic range to Nyquist Spurious-free dynamic range within a window, 5 MHz span SNR Signal-to-noise ratio ACPR Adjacent channel power ratio WCDM A with 3.84 MHz BW, 5 MHz channel spacing 8 ƒCLK = 400 MSPS ƒOUT = 20.0 MHz 60 ƒOUT = 20.0 MHz, for TMIN 57 68 68 62 68 ƒOUT = 70 MHz 67 67 ƒOUT = 140 MHz 55 55 ƒCLK = 100 MSPS, ƒOUT = 19.9 MHz 70 70 ƒCLK = 160 MSPS, ƒOUT = 41 MHz 73 73 ƒCLK = 200 MSPS, ƒOUT = 70 MHz 70 ƒCLK = 400 MSPS ƒOUT = 20.0 MHz 62 ƒOUT = 20.0 MHz, for TMIN 61 68 70 63 68 69 69 ƒOUT = 140 MHz 56 56 ƒCLK = 100 MSPS, ƒOUT = 19.9 MHz 82 82 ƒCLK = 160 MSPS, ƒOUT = 41 MHz 77 77 ƒCLK = 200 MSPS, ƒOUT = 70 MHz 82 82 ƒOUT = 20.0 MHz 82 82 ƒOUT = 70 MHz 82 82 ƒOUT = 140 MHz 75 75 ƒCLK = 400 MSPS, ƒOUT = 20.0 MHz 60 67 60 67 ƒCLK = 122.88 MSPS, IF = 30.72 MHz, see Figure 9 73 73 ƒCLK = 245.76 MSPS, IF = 61.44 MHz, 71 71 ƒCLK = 399.36 MSPS, IF = 153.36 MHz, see Figure 11 65 65 Submit Documentation Feedback dBc 61 ƒOUT = 70 MHz ƒCLK = 400 MSPS dBc 57 dBc dBc dB Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 AC Electrical Characteristics (Unchanged After 100 kRad) (continued) over operating junction temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential transformer-coupled output, 50-Ω doubly-terminated load (unless otherwise noted) PARAMETER IMD TEST CONDITIONS 5962-0720401 MIN TYP 5962-0720402 MAX MIN TYP Two-tone intermodulation to Nyquist (each tone at –6 dBfs) ƒCLK = 400 MSPS, ƒOUT1 = 70 MHz, ƒOUT2 = 71 MHz 73 73 ƒCLK = 400 MSPS, ƒOUT1 = 140 MHz, ƒOUT2 = 141 MHz 62 62 Four-tone intermodulation, 15-MHz span, missing center tone (each tone at –16 dBfs) ƒCLK = 156 MSPS, ƒOUT = 15.6, 15.8, 16.2, 16.4 MHz 82 82 ƒCLK = 400 MSPS, ƒOUT = 68.1, 69.3, 71.2, 72 MHz 74 74 MAX Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP UNIT dBc 9 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 7.7 Digital Specifications (Unchanged After 100 kRad) over operating junction temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS 5962-0720401 MIN TYP 5962-0720402 MAX MIN TYP MAX UNIT LVDS INTERFACE: NODES D[13:0]A, D[13:0]B VITH+ Positive-going differential input voltage threshold 100 100 mV VITH– Negative-going differential input voltage threshold –100 –100 mV ZT Internal termination impedance CI Input capacitance 90 110 132 90 2 110 132 Ω 2 pF 3.3 V CMOS INTERFACE (SLEEP) VIH High-level input voltage 2 3.3 VIL Low-level input voltage 0.8 V IIH High-level input current 10 100 10 100 μA IIL Low-level input current –10 10 –10 10 μA 0 Input capacitance 2 0.8 0 2 2 pF CLOCK INTERFACE (CLK, CLKC) |CLK-CLKC| Clock differential input voltage tw(H) Clock pulse width high 1.25 1.25 tw(L) Clock pulse width low 1.25 1.25 0.4 Clock duty cycle 40% Common-mode voltage range VCM 0.8 1.6 2 0.4 60% 40% 2.4 1.6 0.8 VPP ns ns 60% 2 2.4 V Input resistance Node CLK, CLKC 670 670 Ω Input capacitance Node CLK, CLKC 2 2 pF Input resistance Differential 1.3 1.3 kΩ Input capacitance Differential 1 1 pF TIMING tSU Input setup time 1.5 1.5 tH Input hold time 0.0 0.0 tDD Digital delay time (DAC latency) 3 ns ns 3 clk Figure 1. Timing Diagram 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 7.8 Electrical Characteristics (1) over operating junction temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted) APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE LOGICAL BIT BINARY EQUIVALENT VA (V) VB (V) VA,B (mV) VCOM (V) 1.25 1.15 100 1.2 1 1.15 1.25 –100 1.2 0 2.4 2.3 100 2.35 1 2.3 2.4 –100 2.35 0 (1) 0.1 0 100 0.05 1 0 0.1 –100 0.05 0 1.5 0.9 600 1.2 1 0.9 1.5 –600 1.2 0 2.4 1.8 600 2.1 1 1.8 2.4 –600 2.1 0 0.6 0 600 0.3 1 0 0.6 –600 0.3 0 COMMENT Operation with minimum differential voltage (±100 mV) applied to the complementary inputs versus common-mode range Operation with maximum differential voltage (±600 mV) applied to the complementary inputs versus common-mode range Specifications subject to change. DVDD DAC5675A VA 1.4 V VB 1V VA, B VA, B 0.4 V 0V − 0.4 V VCOM = VA + VB 2 VA Logical Bit Equivalent VB DGND 1 0 Figure 2. LVDS Timing Test Circuit and Input Test Levels Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 11 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 7.9 Typical Characteristics 1.5 1.0 0.8 1.0 0.6 0.5 INL (LSB) DNL (LSB) 0.4 0.2 0 −0.2 0 −0.5 −0.4 −0.6 −1.0 −0.8 −1.0 −1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 0 2000 4000 6000 Input Code Figure 3. Differential Nonlinearity (DNL) vs Input Code 0 −20 Power (dBFS) −30 −40 Figure 4. Integral Nonlinearity (INL) vs Input Code Two-Tone IMD3 (dBc) f1 = 69.5 MHz, −6 dBFS f2 = 70.5 MHz, −6 dBFS IMD3 = 77.41 dBc VCC = VAA = 3.3 V fCLK = 200 MHz −10 −50 −60 −70 −80 −90 −100 67 65 69 71 73 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 75 f2 − f1 = 1 MHz (–6 dBFS each) VCC = VAA = 3.3 V fCLK = 200 MHz 5 15 25 Frequency (MHz) 45 55 65 75 85 Figure 6. Two-Tone IMD3 vs Frequency 85 VCC = VAA = 3.3 V fCLK = 400 MHz fOUT = 20.1 MHz, 0 dBFS SFDR = 74.75 dBc 20.1 MHz −10 −20 -3 dBFS VCC = VAA = 3.3 V fclk= 200 MHz 80 -6 dBFS 75 −30 SFDR (dBFS) Power (dBFS) 35 Center Frequency (MHz) Figure 5. Two-Tone IMD (Power) vs Frequency 0 8000 10000 12000 14000 16000 Input Code −40 −50 40.06 MHz −60 60.25 MHz −70 0 dBFS 70 65 60 −80 55 −90 0 20 40 60 80 100 120 140 160 180 200 50 10 Frequency (MHz) 20 30 40 50 60 70 80 90 100 110 120 Output Frequency (MHz) Figure 7. Single-Tone Spectrum Power vs Frequency 12 Figure 8. Spurious-Free Dynamic Range vs Frequency Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 Typical Characteristics (continued) −25 −30 fCLK = 368.64 MHz −40 fCENTER = ACLR = 65 dBc 92.16 MHz −50 Power (dBm/30kHz) −45 Power (dBm/30kHz) V CC = V AA = 3.3 V VCC = VAA = 3.3 V fCLK = 122.88 MHz fCENTER = 30.72 MHz ACLR = 72.29 dB −35 −55 −65 −75 −85 −60 −70 −80 −90 −95 −100 −105 −110 82.2 −115 18 23 28 33 38 43 87.2 92.2 Frequency 97.2 10.2 Frequency Figure 9. W-CDMA TM1 Single Carrier Power vs Frequency Figure 10. W-CDMA TM1 Dual Carrier Power vs Frequency 80 VCC = VAA = 3.3 V fCLK = 399.36 MHz Single Channel 78 76 ACLR (dBc) 74 72 70 68 66 64 62 60 10 30 50 70 90 110 130 150 Output Frequency (MHz) Figure 11. W-CDMA TM1 Single Carrier ACLR vs Output Frequency Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 13 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 8 Detailed Description 8.1 Overview Functional Block Diagram shows a simplified block diagram of the current steering DAC5675A-SP. The DAC5675A-SP consists of a segmented array of NPN-transistor current sources, capable of delivering a fullscale output current up to 20 mA. Differential current switches direct the current of each current source to either one of the complementary output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order distortion components, and doubling signal output power. The full-scale output current is set using an external resistor (RBIAS) with an on-chip bandgap voltage reference source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 16 × IBIAS. The full-scale current is adjustable from 20 to 2 mA by using the appropriate bias resistor value. 8.2 Functional Block Diagram SLEEP DAC5675A Bandgap Reference 1.2V EXTIO BIASJ Current Source Array Output Current Switches Decoder DAC Latch + Drivers Control Amp 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches 14 CLK Clock Distribution CLKC AVDD(4x) AGND(4x) DVDD(2x) DGND(2x) 8.3 Feature Description 8.3.1 Digital Inputs The DAC5675A-SP uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low differential voltage swing with low constant power consumption (4 mA per complementary data input) across frequency. The differential characteristic of LVDS allows for high-speed data transmission with low electromagnetic interference (EMI) levels. Figure 12 shows the equivalent complementary digital input interface for the DAC5675A-SP, valid for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-Ω resistors for proper termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs. Figure 13 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A-SP, valid for the SLEEP pin. 14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 Feature Description (continued) DVDD DAC5675A D[13..0]A DAC5675A 110 Ω Termination Resistor Internal Digital In D[13..0]B D[13:0]A D[13:0]B Internal Digital In DGND Figure 12. LVDS Digital Equivalent Input DVDD DAC5675A Internal Digital In Digital Input DGND Figure 13. CMOS/TTL Digital Equivalent Input 8.3.2 Clock Input The DAC5675A-SP features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 14 shows the equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage to approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupled to the device, including a sine-wave source (see Figure 15). Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 15 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com Feature Description (continued) AVDD DAC5675A R1 1 kΩ R1 1 kΩ Internal Clock CLK CLKC R2 2 kΩ R2 2 kΩ AGND Figure 14. Clock Equivalent Input Optional, may be bypassed for sinewave input Swing Limitation CAC 0.1 µF 1:4 CLK RT 200 Ω DAC5675A CLKC Termination Resistor Figure 15. Driving the DAC5675A-SP With a Single-Ended Clock Source Using a Transformer To obtain best ac performance, the DAC5675A-SP clock input should be driven with a differential LVPECL or sine-wave source as shown in Figure 16 and Figure 17. Here, the potential of VTT should be set to the termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675A-SP clock input can also be driven single ended (see Figure 18). Single-Ended ECL or (LV)PECL Source CAC 0.01 µF ECL/PECL Gate CLK CAC 0.01 µF DAC5675A CLKC RT 50 Ω RT 50 Ω VTT Figure 16. Driving the DAC5675A-SP With a Single-Ended ECL/PECL Clock Source 16 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 Feature Description (continued) CAC 0.01 µF Differential ECL or (LV)PECL Source CLK + CAC 0.01 µF DAC5675A − RT 50 Ω CLKC RT 50 Ω VTT Figure 17. Driving the DAC5675A-SP With a Differential ECL/PECL Clock Source TTL/CMOS Source DAC5675A CLK ROPT 22 Ω CLKC 0.01 µF Node CLKC Internally Biased to AVDD/2 Figure 18. Driving the DAC5675A-SP With a Single-Ended TTL/CMOS Clock Source 8.3.3 Supply Inputs The DAC5675A-SP comprises separate analog and digital supplies, AVDD and DVDD, respectively. These supply inputs can be set independently from 3.6 to 3.15 V. 8.3.4 DAC Transfer Function The DAC5675A-SP has a current sink output. The current flow through IOUT1 and IOUT2 is controlled by D[13:0]A and D[13:0]B. For ease of use, D[13:0] is denoted as the logical bit equivalent of D[13:0]A and its complement D[13:0]B. The DAC5675A-SP supports straight binary coding with D13 being the MSB and D0 the LSB. Full-scale current flows through IOUT2 when all D[13:0] inputs are set high and through IOUT1 when all D[13:0] inputs are set low. The relationship between IOUT1 and IOUT2 can be expressed as Equation 1. ,287 ,2(FS) ± ,287 (1) IO(FS) is the full-scale output current sink (2 to 20 mA). Because the output stage is a current sink, the current can only flow from AVDD through the load resistors RL into the IOUT1 and IOUT2 pins. The output current flow in each pin driving a resistive load can be expressed as shown in Figure 19, Equation 2, and Equation 3. Figure 19. Relationship Between D[13:0], IOUT1 and IOUT2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 17 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com Feature Description (continued) IOUT1 = IOUT2 ,2(FS) u ± &2'( IO(FS) 16384 u CODE (2) 16384 where • CODE is the decimal representation of the DAC input word (3) This would translate into single-ended voltages at IOUT1 and IOUT2, as shown in Equation 4 and Equation 5. VOUT1 = AVDD – IOUT1 × RL VOUT2 = AVDD – IOUT2 × RL (4) (5) Assuming that D[13:0] = 1 and the RL is 50 Ω, the differential voltage between pins IOUT1 and IOUT2 can be expressed as shown in Equation 6 through Equation 8. VOUT1 = 3.3 V – 0 mA × 50 = 3.3 V VOUT2 = AVDD – 20 mA × 50 = 2.3 V VDIFF = VOUT1 – VOUT2 = 1 V (6) (7) (8) If D[13:0] = 0, then IOUT2 = 0 mA, IOUT1 = 20 mA, and the differential voltage VDIFF = –1 V. The output currents and voltages in IOUT1 and IOUT2 are complementary. The voltage, when measured differentially, is doubled compared to measuring each output individually. Take care not to exceed the compliance voltages at the IOUT1 and IOUT2 pins to keep signal distortion low. 8.3.5 Reference Operation The DAC5675A-SP has a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor, RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals 16× this bias current. The full-scale output current IO(FS) is thus expressed as Equation 9. 16 V EXTIO I O(FS) + 16 I BIAS + RBIAS where • VEXTIO is the voltage at pin EXTIO (9) The bandgap reference voltage delivers a stable voltage of 1.2 V. This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference can additionally be used for external reference operation. In such a case, select an external buffer amplifier with high-impedance input to limit the bandgap load current to less than 100 nA. The capacitor CEXT may be omitted. Pin EXTIO serves as either an input or output node. The full-scale output current is adjustable from 20 to 2 mA by varying resistor RBIAS. 8.3.6 Analog Current Outputs Figure 20 shows a simplified schematic of the current source array output with corresponding switches. Differential NPN switches direct the current of each individual NPN current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches and is >300 kΩ in parallel with 5-pF output capacitance. The external output resistors are referred to the positive supply, AVDD. 18 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 Feature Description (continued) 3.3 V AVDD RLOAD RLOAD IOUT1 IOUT2 DAC5675A S(1) S(1)C S(2) S(2)C S(N) S(N)C Current Sink Array AGND Figure 20. Equivalent Analog Current Output Figure 21(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a 20-mA full-scale output current. The output impedance of the DAC5675A-SP slightly depends on the output voltage at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, choose the configuration of Figure 21(b). In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of the DAC determine the value of the feedback resistor, RFB. The capacitor CFB filters the steep edges of the DAC5675A-SP current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the operational amplifier should operate at a supply voltage higher than the resistor output reference voltage AVDD as a result of its positive and negative output swing around AVDD. Select node IOUT1 if a single-ended unipolar output is desired. 3.3 V AVDD DAC5675A CFB 200 Ω (RFB) DAC5675A 25 Ω IOUT1 VOUT1 IOUT2 VOUT2 25 Ω IOUT1 VOUT IOUT2 Optional, for singleended output referred to AVDD 3.3 V AVDD (a) 3.3 V AVDD (b) Figure 21. Output Configurations Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 19 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 8.4 Device Functional Modes 8.4.1 Sleep Mode The DAC5675A-SP features a power-down mode that turns off the output current and reduces the supply current to approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled down internally. 20 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DAC5675A-SP is a 14-bit resolution high-speed DAC. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency DDS, and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular BTSs. 9.2 Typical Application The DAC5675A-SP consists of a segmented array of NPN-transistor current sources, capable of delivering a fullscale output current up to 20 mA. Differential current switches direct the current of each current source to either one of the complementary output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out common-mode noise sources (digital feed through, on-chip, and PCB noise), dc offsets, and even order distortion components, and doubling signal output power. SLEEP 3.3 V (AVDD) DAC5675A Bandgap Reference 1.2 V 50 Ω IOUT Output 1:1 EXTIO Current Source Array BIASJ CEXT 0.1 µF Output Current Switches Control Amp RBIAS 1 kΩ IOUT 50 Ω RLOAD 50 Ω 3.3 V (AVDD) 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches Decoder 14 DAC Latch + Drivers 3.3 V (AVDD) CLK 1:4 Clock Input 100 Ω RT 200 Ω Clock Distribution CLKC AVDD(4x) AGND(4x) DVDD(2x) DGND(2x) Figure 22. Typical Application Schematic 9.2.1 Design Requirements For this design example, use the parameters listed in Table 1 as the input parameters. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 21 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com Table 1. Design Parameters Design Parameter Example Value Cest 0.1 µF Rbias 1 kΩ RT 200 Ω Rload 50 Ω 9.2.2 Detailed Design Procedure The DAC5675A-SP can be easily configured to drive a doubly-terminated 50-Ω cable using a properly selected transformer. Figure 23 and Figure 24 show the 1:1 and 4:1 impedance ratio configuration, respectively. These configurations provide maximum rejection of common-mode noise sources and even-order distortion components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac performance of the DAC5675A-SP is optimum and specified using a 1:1 differential transformer-coupled output. 3.3 V AVDD DAC5675A 50 Ω 1:1 IOUT1 RLOAD 50 Ω 100 Ω IOUT2 50 Ω 3.3 V AVDD Figure 23. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer 3.3 V AVDD DAC5675A 100 Ω 4:1 IOUT1 RLOAD 50 Ω IOUT2 15 Ω 100 Ω 3.3 V AVDD Figure 24. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer 22 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 9.2.3 Application Curve 80 - 3 dBFS VCC = VAA = 3.3 V fclk = 400 MHz SFDR (dBFS) 75 70 -6 dBFS 65 0 dBFS 60 55 50 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz) Figure 25. Spurious-Free Dynamic Range vs Frequency Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 23 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com 10 Power Supply Recommendations The DAC5675 uses a single 3.3-V power supply simplifying design requirements. The power supply should be filtered from any other system noise that may be present. The filtering should pay particular attention to frequencies of interest for output. 11 Layout 11.1 Layout Guidelines • • • • • DAC output termination should be placed as close as possible to outputs. Keep routing for RBIAS short. Decoupling capacitors should be placed as close as possible to supply pins. Digital differential inputs must be 50 Ω to ground loosely coupled, or 100-Ω differential tightly coupled. Digital differential inputs must be length matched. 11.2 Layout Example Figure 26. Top Layer 24 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 Layout Example (continued) Figure 27. Bottom Layer 11.3 Thermal Considerations This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly under the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11.9-mm 2-board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically ground potential. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 25 DAC5675A-SP SGLS387G – JULY 2007 – REVISED MARCH 2015 www.ti.com Thermal Considerations (continued) 70.00 60.00 Years estimated life 50.00 40.00 30.00 20.00 10.00 0.00 100 105 110 115 120 125 130 135 140 145 150 155 160 Continuous Tj (°C) Figure 28. Estimated Device Life at Elevated Temperatures Electromigration Fail Modes 26 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387G – JULY 2007 – REVISED MARCH 2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 Definitions of Specifications and Terminology ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a 3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio. APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the analog power supply AVDD from the nominal. This is a dc measurement. DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the digital power supply DVDD from the nominal. This is a dc measurement. Gain error is as the percentage error in the ratio between the measured full-scale output current and the value of 16 × V(EXTIO)/RBIAS. A V(EXTIO) of 1.25 V is used to measure the gain error with an external reference voltage applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap reference voltage) from the typical value of 1.25 V. Offset error is as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and half of the full-scale output current for input code 8192. SINAD is the ratio of the RMS value of the fundamental output signal to the RMS sum of all other spectral components below the Nyquist frequency, including noise and harmonics, but excluding dc. SNR is the ratio of the RMS value of the fundamental output signal to the RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc. THD is the ratio of the RMS sum of the first six harmonic components to the RMS value of the fundamental output signal. 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-0720401VXC ACTIVE CFP HFG 52 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-0720401VX C DAC5675AMHFG-V 5962-0720402VXC ACTIVE CFP HFG 52 1 TBD Call TI N / A for Pkg Type -55 to 115 5962-0720402VX C DAC5675AWHFG-V DAC5675AHFG/EM ACTIVE CFP HFG 52 TBD Call TI N / A for Pkg Type 25 Only DAC5675AHFG/EM EVAL ONLY (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Apr-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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