Cypress CY8CNP102E Nonvolatile programmable system-on-chip(psocâ® nv) Datasheet

PRELIMINARY
CY8CNP102B, CY8CNP102E
Nonvolatile Programmable System-on-Chip
(PSoC® NV)
Overview
■
The Cypress nonvolatile Programmable System-on-Chip
(PSoC® NV) processor combines a versatile Programmable
System-on-Chip™ (PSoC) core with an infinite endurance
nvSRAM in a single package. The PSoC NV combines an 8-bit
MCU core (M8C), configurable analog and digital functions, a
uniquely flexible IO interface, and a high density nvSRAM. This
creates versatile data logging solutions that provide value
through component integration and programmability. The flexible
core and a powerful development environment work to reduce
design complexity, component count, and development time.
Precision, Programmable Clocking
❐ Internal ±2.5% 24 and 48 MHz Oscillator
❐ 24 and 48 MHz with optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage
❐ 2K Bytes SRAM Data Storage
❐ 256K Bytes secure store nvSRAM with data throughput between 100 KBPS and 1 MBPS
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐ 33 GPIOs
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIOs
❐ Analog Outputs with 40 mA on 4 GPIOs
❐ Configurable Interrupt on all GPIOs
■
Additional System Resources
2
❐ I C Slave, Master, and MultiMaster to 100 Kbps
and 400 Kbps
❐ Watchdog and Sleep Timers
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured, In Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ C Compilers, Assembler, and Linker
■
Temperature and Packaging
❐ Industrial Temperature Range: -40°C to +85°C
❐ Packaging: 100-pin TQFP
Features
■
Powerful Harvard Architecture Processor
❐ M8C processor speeds
• Up to 12 MHz for 3.3V operation
• Up to 24 MHz for 5V operation
❐ Two 8x8 multiply, 32 bit accumulate
❐ Low power at high speed
■
Operating Voltage
❐ 3.3V (CY8CNP102B)
❐ 5V (CY8CNP102E)
■
Advanced Peripherals
❐ 12 Rail-to-Rail Analog PSoC blocks provide:
• Up to 14 bit ADCs
• Up to 9 bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• 8 Analog channels for simultaneous sampling
• Up to 820 SPS for each channel with 8 channel sampling
and logging
❐ 16 Digital PSoC Blocks provide:
• 8 to 32 bit timers, counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full Duplex UARTs
• Multiple SPI™ Masters and Slaves
❐ Complex Peripherals by Combining Blocks
Cypress Semiconductor Corporation
Document #: 001-43991 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 20, 2008
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Logic Block Diagram
Document #: 001-43991 Rev. *D
Page 2 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Pinouts
Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)
Table 1. Pin Definitions - 100-Pin TQFP
Pin Number
Pin Name
1
Type
Pin Definition
Digital
Analog
P0_5
IO
IO
Analog Column Mux Input and Column Output
2
P0_3
IO
IO
Analog Column Mux Input and Column Output
3
P0_1
IO
I
4
P2_7
IO
GPIO
5
P2_5
IO
GPIO
6
P2_3
IO
I
Direct Switched Capacitor Block Input
7
P2_1
IO
I
Direct Switched Capacitor Block Input
8
Vcc
9
DNU
Power
Analog Column Mux Input, GPIO
Supply Voltage
Reserved for test modes - Do Not Use
10
DNU
Reserved for test modes - Do Not Use
11
DNU
Reserved for test modes - Do Not Use
12
DNU
Reserved for test modes - Do Not Use
13
DNU
Reserved for test modes - Do Not Use
14
NC
15
P3_5
16
EN_W
17
P3_1
Document #: 001-43991 Rev. *D
Not connected on the die
IO
GPIO
Connect to Pin 26 (EN_W to NV_W)
IO
GPIO
Page 3 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 1. Pin Definitions - 100-Pin TQFP (continued)
Type
Pin Number
Pin Name
18
P5_7
IO
GPIO
19
P5_5
IO
GPIO
20
P5_3
IO
GPIO
Digital
Pin Definition
Analog
21
P5_1
IO
GPIO
22
P1_7
IO
I2C Serial Clock (SCL), GPIO
23
P1_5
IO
I2C Serial Data (SDA), GPIO
24
P1_3
IO
GPIO
25
P1_1
IO
Serial Clock (SCL), Crystal (XTALin), GPIO
26
NV_W
27 - 34
NC
35 - 39
Vss
Connect to pin 16 (NV_W to EN_W)
Not connected on the die
Power
Ground
40 - 47
NC
48
DNU
Reserved for test modes - Do Not Use
49
NV_A1
Connect to pin 58 (NV_A1 to EN_A1)
50
NV_A2
Connect to pin 59 (NV_A2 to EN_A2)
51
P1_0
IO
Serial Data (SDA), Crystal (XTALout), GPIO
52
P1_2
IO
GPIO
53
P1_6
IO
GPIO
54
P5_0
IO
GPIO
55
P5_2
IO
GPIO
56
P5_4
IO
GPIO
57
P5_6
IO
58
EN_A1
59
EN_A2
Connect to Pin 50 (EN_A2 to NV_A2)
60
EN_O
Connect to Pin 76 (EN_O to NV_O)
Not connected on the die
GPIO
Connect to Pin 49 (EN_A1 to NV_A1)
61
EN_C
62
XRES
Connect to Pin 99 (EN_C to NV_C)
63
VCAP
Power
External Capacitor connection for nvSRAM
64
Vcc
Power
Supply Voltage
65
P2_0
IO
I
Direct Switched Capacitor Block Input, GPIO
66
P2_2
IO
I
Direct Switched Capacitor Block Input, GPIO
67
P2_4
IO
External Analog GND, GPIO
68
P2_6
IO
External Voltage Ref, GPIO
69
P0_0
IO
I
70
P0_2
IO
IO
Analog Column Mux Input and Column Output
IO
IO
Analog Column Mux Input and Column Output
Input
Active high external reset (Internal Pull down)
Analog Column Mux Input, GPIO
71
P0_4
72-73
NC
74
P0_6
75
Vcc
76
NV_O
Connect to Pin 60 (NV_O to EN_O)
77
DNU
Reserved for test modes - Do Not Use
78
NC
Document #: 001-43991 Rev. *D
Not connected on the die
IO
I
Power
Analog Column Mux Input, GPIO
Supply Voltage
Not connected on the die
Page 4 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 1. Pin Definitions - 100-Pin TQFP (continued)
Pin Number
Pin Name
79
HSB#
80
Vcc
81 - 85
NC
86 - 90
Vss
91 - 98
NC
99
NV_C
100
P0_7
Type
Digital
Pin Definition
Analog
Weak Pull up. Connect 10kΩ to Vcc.
Power
Supply Voltage
Not connected on the die
Power
Ground
Not connected on the die
Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.
IO
I
Analog Column Mux Input, GPIO
PSoC NV Functional Overview
The PSoC NV provides a versatile microcontroller core (M8C),
Flash program memory, nvSRAM data memory, and
configurable analog and digital peripheral blocks in a single
package. The flexible digital and analog IOs and routing matrix
create a powerful embedded and flexible mixed signal
System-on-Chip (SoC).
The device incorporates configurable analog and digital blocks,
interconnect circuitry around an MCU subsystem, and an infinite
endurance nvSRAM. This enables high level integration in
consumer, industrial, and automotive applications, where
preventing data loss under all conditions is vital.
PSoC NV Core
The PSoC NV core is a powerful PSoC engine that supports a
rich feature set. The core includes a M8C CPU, memory, clocks,
and configurable GPIO (General Purpose IO). The M8C CPU
core is a powerful processor with speeds up to 24 MHz, providing
a four MIPS 8-bit Harvard architecture microprocessor. The CPU
uses an interrupt controller with 25 vectors, to simplify
programming of real time embedded events. Program execution
is timed and protected using the included Sleep and Watch Dog
Timers (WDT).
On-chip memory encompasses 32 KB Flash for program
storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data
logging, and up to 2 KB EEPROM emulated using Flash.
Program Flash uses four protection levels on blocks of 64 bytes,
allowing customized software IP protection. The nvSRAM
combines a static RAM cell and a SONOS cell to provide an
infinite endurance nonvolatile memory block. The memory is
random access and is accessed using a user module provided
with the device.
The device incorporates flexible internal clock generators,
including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz Internal Low speed Oscillator (ILO) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC NV
device.
GPIOs provide connection to the CPU, and digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
Document #: 001-43991 Rev. *D
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
nvSRAM Data Memory
The nvSRAM memory block is byte addressable fast static RAM
with a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap® technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, when independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down, and
data is restored to the SRAM (the RECALL operation) from the
nonvolatile memory on power up. All cells store and recall data
in parallel.
Both the STORE and RECALL operations may be initiated under
software control. The PSoC NV user module embedded in the
PSoC Designer Tool provides all necessary APIs to initiate
software STORE and RECALL function from the user program.
nvSRAM Operation
The nvSRAM is made up of an SRAM memory cell, and a
nonvolatile QuantumTrap cell paired in the same physical cell.
The SRAM memory cell operates as a standard fast static, and
all READ and WRITE takes place from the SRAM during normal
operation.
During the STORE and RECALL operations, SRAM READ and
WRITE operations are inhibited, and internal operations transfer
data between the SRAM and nonvolatile cells. The nvSRAM
provides infinite RECALL operations from the nonvolatile cells
and up to 200,000 STORE operations.
To reduce unnecessary nonvolatile stores, AutoStore® is ignored
unless at least one WRITE operation is complete after the most
recent STORE or RECALL cycle. Software initiated STORE
cycles are performed regardless of whether a WRITE operation
has taken place. Embedded APIs provide a seamless interface
to the nvSRAM.
During normal operation, the embedded nvSRAM draws current
from Vcc to charge a capacitor connected to the VCAP pin. This
stored charge is used by the chip to perform a STORE operation.
If the voltage on the Vcc pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from Vcc and STORE
operation is initiated.
Page 5 of 38
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PRELIMINARY
Programmable Digital System
The digital system contains 16 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. The digital peripheral configurations
are:
■
PWMs (8 to 32 bit)
■
PWMs with dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 4)
■
SPI master and slave (up to 4 each)
■
I2C slave and multimaster (1 available as a System Resource)
■
Cyclical Redundancy Checker and Generator (8 to 32 bit)
■
IrDA (up to 4)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks connect to any GPIO through a series of global
buses that route any signal to any pin. The buses also enable
signal multiplexing and performing logic operations. This
configurability frees your designs from the constraints of a fixed
peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies with PSoC device family. This gives you the
optimum choice of system resources for your application.
Programmable Analog System
CY8CNP102B, CY8CNP102E
■
Peak Detectors
■
Other possible topologies
■
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. The merits of
each system resource are:
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■
Multiply Accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
The decimator provides a custom hardware filter for digital
signal, and processing applications including the creation of
Delta Sigma ADCs.
■
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
The analog system consists 12 configurable blocks, each having
an opamp circuit enabling the creation of complex analog signal
flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common analog functions (most available as user
modules) are:
■
Analog-to-digital converters (up to 4, with 6 to 14 bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band pass, low pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6 to 9 bit resolution)
■
Multiplying DACs (up to 4, with 6 to 9 bit resolution)
■
High current output drivers (four with 40 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
Document #: 001-43991 Rev. *D
Page 6 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Development Tools
PSoC Designer Software Subsystems
PSoC Designer is a Microsoft® Windows based, integrated
development environment for Programmable System-on-Chip
(PSoC) devices. The PSoC Designer IDE and application run on
Windows NT 4.0, Windows 2000, Windows Millennium (Me),
Microsoft Vista, and Windows XP.
Device Editor
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration enables changing configurations at run time.
PSoC Designer also supports a high level C language compiler
developed specifically for the devices in this family.
Figure 2. PSoC Designer Subsystem
G ra phical D e signer
Interface
C o n te xt
S e nsitive
H e lp
Results
Commands
PSoC
D esign er
A pp licatio n
D a ta b ase
P S oC
D esigner
C ore
E ngine
P ro je ct
D a ta b ase
P S oC
C o n figu ra tio n
S he e t
The Design Browser enables users to select and import
preconfigured designs into their project. Users can easily browse
a catalog of preconfigured designs to facilitate time to design.
Examples provided in the tools include a 300 baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
M a n ufactu ring
In fo rm a tio n
F ile
In the Application Editor you can edit C language and Assembly
language source code. You can also assemble, compile, link,
and build.
Assembler. The macro assembler seamlessly merges the
assembly code with C code. The link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
U se r
M o d u le s
Lib ra ry
E m u la tion
Pod
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components. Also, if the project uses more
than one operating configuration, the framework contains
routines to switch between different sets of PSoC block
configurations at run time. PSoC Designer can print out a
configuration sheet for a given project configuration, for use
during application programming in conjunction with the Device
Data Sheet. After the framework is generated, the user can add
application specific code to flesh out the framework. It is also
possible to change the selected components and regenerate the
framework.
Design Browser
Im p orta b le
D e sign
D a ta b ase
D e vice
D a ta b ase
The Device Editor subsystem enables the user to select different
onboard analog and digital components called user modules,
using the PSoC blocks. Examples of user modules are ADCs,
DACs, nvSRAM, Amplifiers, and Filters.
In -C ircuit
E m u la to r
D e vice
P ro g ra m m e r
C Language Compiler. A C language compiler that supports
Cypress PSoC family devices is available. Even if you have
never worked in the C language before, the product quickly
enables you to create complete C programs for the PSoC family
devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It is complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, which enables the designer to test the
program in a physical system while providing an internal view of
the PSoC device. Debugger commands enable the designer to
read and program, read and write data memory, read and write
IO registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also enables the designer to create a trace buffer of
registers and memory locations of interest.
Document #: 001-43991 Rev. *D
Page 7 of 38
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PRELIMINARY
Online Help System
The online help system displays online, context sensitive help for
the user. Designed for procedural and quick reference, each
functional subsystem has its own context sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC
through the USB port. The base unit is universal and operates
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that manages specification change during
development and lowers inventory costs. These configurable
resources, called PSoC Blocks, implement a wide variety of
user-selectable functions. Each block has several registers that
determine its function and connectivity to other blocks,
multiplexers, buses, and to the IO pins. Iterative development
cycles permit you to adapt the hardware and the software. This
substantially lowers the risk of selecting a different part to meet
the final design requirements.
To speed the development process, the PSoC Designer IDE
provides a library of prebuilt, pretested hardware peripheral
functions, called “User Modules.” User modules simplify
selecting and implementing peripheral devices, and come in
analog, digital, and mixed signal varieties. The standard User
Module library contains over 50 peripherals such as ADCs,
DACs, Timers, Counters, UARTs, nvSRAM, DTMF Generators,
and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
enable you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module Application Programming Interface (API) provides high
level functions to control and respond to hardware events at run
time. The API also provides optional interrupt service routines
that you can adapt as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
Document #: 001-43991 Rev. *D
CY8CNP102B, CY8CNP102E
The development process starts when you open a new project
and bring up the Device Editor, which is a graphical user
interface (GUI) for configuring the hardware. Pick the user
modules required for your project and map them onto the PSoC
blocks with point and click simplicity. Next, build signal chains by
interconnecting user modules to each other and to the IO pins.
At this stage, configure the clock source connections and enter
parameter values directly or by selecting values from drop down
menus. When you are ready to test the hardware configuration
or develop code for the project, perform the “Generate
Application” step. PSoC Designer generates source code that
automatically configures the device to your specification and
provides high level user module API functions.
User Module and Source Code Development Flows
The next step is to write the main program, and any subroutine
using PSoC Designer’s Application Editor subsystem. The
Application Editor includes a Project Manager that enables you
to open the project source code files (including all generated
code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for C and
assembly language. File search capabilities include simple string
searches and recursive “grep-style” patterns. A single mouse
click invokes the Build Manager.
It employs a professional strength “makefile” system to
automatically analyze all file dependencies and run the compiler
and assembler as necessary. Project level options control
optimization strategies used by the compiler and linker. Syntax
errors are displayed in a console window. Double clicking the
error message takes you directly to the offending line of source
code. After correction, the linker builds a HEX file image suitable
for programming.
Figure 3. User Module and Source Code Development Flows
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
Page 8 of 38
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PRELIMINARY
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. The Debugger capabilities rival those of
systems costing much more. In addition to traditional single step,
run to breakpoint, and watch variable features, the Debugger
provides a large trace buffer enabling you to define complex
breakpoint events that include monitoring address and data bus
values, memory locations, and external signals.
CY8CNP102B, CY8CNP102E
Cypress nvSRAM user Module
The nvSRAM user module is integrated with the PSoC Designer
tool and contains APIs that facilitate nvSRAM access and
control. The user module provides high level access to the
nvSRAM without user developed code. The user module API
also provides the ability to read and write arbitrary data structures to or from the nvSRAM, and initiate nvSRAM Store or
Recall operations.
Electrical Specifications
This section lists the PSoC NV device DC and AC electrical specifications.
Specifications are valid for -40oC ≤ TA ≤ 85oC, and TJ ≤ 100oC, except where noted.
Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator (IMO) using SLIMO mode.
Figure 4. Voltage versus CPU Frequency
Figure 5. IMO Frequency Trim Options
5.25
Operating Region
(CY8CNP102E)
4.75
4.75
Vdd Voltage
on
gi
Re
Vdd Voltage
3.60
Operating Region
(CY8CNP102B)
3.60
3.00
3.00
93 kHz
12 MHz
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO Mode = 0
5.25
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this data sheet.
Table 2. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
degree Celsius
μW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
μA
microampere
pp
peak-to-peak
μF
microfarad
μH
microhenry
ps
picosecond
μs
microsecond
sps
samples per second
μV
microvolts
σ
sigma: one standard deviation
microvolts root-mean-square
V
volts
μVrms
Document #: 001-43991 Rev. *D
ppm
parts per million
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PRELIMINARY
CY8CNP102B, CY8CNP102E
3.3V Operation
Absolute Maximum Ratings
Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
o
TSTG
Storage Temperature
-55
25
+100
C
TA
Ambient Temperature with Power Applied
-40
–
+85
oC
Vcc
Supply Voltage on Vcc Relative to Vss
-0.5
–
+4.1
V
VIO
DC Input Voltage
Vss - 0.5
–
Vcc + 0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vcc + 0.5
V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin
Configured as Analog Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
Min
Typ
Max
Units
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is ± 25oC.
Extended duration storage
temperatures above 65oC
degrade reliability.
Human Body Model ESD.
Operating Temperature
Table 4. 3.3V Operating Temperature (CY8CNP102B)
Symbol
Description
TA
Ambient Temperature
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
Document #: 001-43991 Rev. *D
Notes
Page 10 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Electrical Characteristics
The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature
range: 3.0V to 3.6V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design
guidance only.
DC Chip Level Specifications
Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
Notes
Vcc
Supply Voltage
3.00
–
3.6
V
IDD
Supply Current
–
36
40
mA
TA = 25 oC, CPU = 3 MHz,
SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz, continuous
nvSRAM access
IDDP
Supply current when IMO = 6 MHz
using SLIMO mode.
–
27
28
mA
TA = 25 oC, CPU = 0.75 MHz,
SYSCLK doubler disabled,
VC1=0.375 MHz, VC2=23.44 kHz,
VC3 = 0.09 kHz, continuous
nvSRAM access
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
–
–
5
mA
nvSRAM in standby.
VREF
Reference Voltage (Bandgap)
1.28
1.3
1.32
V
Trimmed for appropriate Vcc.
Vcap
Storage Capacitor between Vcap and
Vss
61
68
82
uF
5V rated (minimum)
Min
Typ
Max
Units
DC General Purpose IO Specifications
Table 6. 3.3V DC GPIO Specifications (CY8CNP102B)
Symbol
Description
Notes
RPU
Pull up Resistor
4
5.6
8
KΩ
RPD
Pull down Resistor
4
5.6
8
KΩ
VOH
High Output Level
Vcc - 1.0
–
–
V
IOH = 10 mA, Vcc = 3.0 to 3.6V. 8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3],
P1[5]). 80 mA maximum combined
IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vcc = 3.0 to 3.6V
8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5]). 150 mA maximum
combined IOL budget.
VIL
Input Low Level
–
–
0.8
VIH
Input High Level
1.6
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Pin dependent.
Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Pin dependent.
Temp = 25oC.
Document #: 001-43991 Rev. *D
V
Vcc = 3.0 to 3.6
V
Vcc = 3.0 to 3.6
Page 11 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Operational Amplifier Specifications
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 7. 3.3V DC Operational Amplifier Specifications (CY8CNP102B)
Symbol
VOSOA
Description
Min
Typ
Max
Units
Input Offset Voltage (absolute value)
Notes
High Power is 5 Volts Only
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog
Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0
–
Vcc
V
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (internal
signals)
Vcc - 0.01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal
signals)
–
–
0.01
V
ISOA
Supply Current
(including associated AGND buffer)
–
150
200
μA
Power = Low, Opamp Bias = Low
PSRROA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
–
–
μA
Not Allowed for 3.3V operation
Supply Voltage Rejection Ratio
54
80
–
dB
Vss ≤ VIN ≤ (Vcc - 2.25) or
(Vcc - 1.25V) ≤ VIN ≤ Vcc
DC Low Power Comparator Specifications
Table 8. 3.3V DC Low Power Comparator Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
VREFLPC
Low power comparator (LPC) reference voltage range
0.2
–
Vcc - 1.0
V
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document #: 001-43991 Rev. *D
Page 12 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Analog Output Buffer Specifications
Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B)
Symbol
Description
VOSOB
Input Offset Voltage (Absolute Value)
TCVOSOB
Average Input Offset Voltage Drift
VCMOB
Common-Mode Input Voltage Range
ROUTOB
Output Resistance
VOHIGHOB
VOLOWOB
ISOB
Typ
Max
Units
–
3
12
mV
–
+6
–
μV/°C
0.5
-
Vcc - 1.0
V
Power = Low
–
–
10
Ω
Power = High
–
–
10
Ω
Power = Low
0.5 x Vcc + 1.0
–
–
V
Power = High
0.5 x Vcc + 1.0
–
–
V
Power = Low
–
–
0.5 x Vcc - 1.0
V
Power = High
–
–
0.5 x Vcc - 1.0
V
–
0.8
1
mA
Power = High
–
2.0
5
mA
Supply Voltage Rejection Ratio
60
64
–
dB
High Output Voltage Swing
(Load = 1KΩ to Vcc/2)
Low Output Voltage Swing
(Load = 1KΩ to Vcc/2)
Supply Current Including Bias Cell
(No Load)
Power = Low
PSRROB
Min
Document #: 001-43991 Rev. *D
Page 13 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Analog Reference Specifications
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 10. 3.3V DC Analog Reference Specifications (CY8CNP102B)
Symbol
VBG33
Description
Bandgap Voltage Reference 3.3V
[1]
–
AGND = Vcc/2
–
AGND = 2 x BandGap[1]
–
AGND = P2[4] (P2[4] = Vcc/2)
–
AGND = BandGap[1]
BandGap[1]
Min
Typ
Max
Units
1.28
1.30
1.32
V
Vcc/2 - 0.02
Vcc/2
Vcc/2 + 0.02
V
Not Allowed
P2[4] - 0.009
P2[4]
P2[4] + 0.009
V
1.27
1.30
1.34
V
–
AGND = 1.6 x
–
AGND Block to Block Variation (AGND = Vcc/2)[1]
2.03
2.08
2.13
V
-0.034
0.000
0.034
mV
–
RefHi = Vcc/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vcc/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042
V
–
RefHi = 2 x BandGap
V
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vcc/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vcc/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.036
2.50
2.60
2.70
P2[4] - P2[6] P2[4] - P2[6] + 0.036
V
DC Analog PSoC NV Block Specifications
Table 11. 3.3V DC Analog PSoC NV Block Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
Note
1. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Document #: 001-43991 Rev. *D
Page 14 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC POR, SMP, and LVD Specifications
Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R PORLEV[1:0] = 00b
2.91
V
2.82
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
92
mV
VPH1
PORLEV[1:0] = 01b
0
mV
VPH2
PORLEV[1:0] = 10b
0
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98[2]
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
V
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
V
Vdd Value for SMP Trip
VPUMP0
VM[2:0] = 000b
2.96
3.02
3.08
V
VPUMP1
VM[2:0] = 001b
3.03
3.10
3.16
V
VPUMP2
VM[2:0] = 010b
3.18
3.25
3.32
V
Note
2. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
Document #: 001-43991 Rev. *D
Page 15 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Programming Specifications
Table 13. 3.3V DC Programming Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
–
10
30
mA
Input Low Voltage During Programming or Verify
–
–
0.8
V
Input High Voltage During Programming or Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1]
During Programming or Verify
–
–
0.2
mA
Driving internal pull
down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1]
During Programming or Verify
–
–
1.5
mA
Driving internal pull
down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or Verify
Vcc - 1.0
–
Vcc
V
50,000
–
–
–
Erase/write cycles
per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
IDDPV
Supply Current During Programming or Verify
VILP
VIHP
FlashENPB Flash Endurance (per block)
FlashENT
Flash Endurance (total)[3]
FlashDR
Flash Data Retention
Notes
Note
3. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single lock ever sees
more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (Flash Temp) and feed the result to the temperature
argument before timing. Refer to the Flash APIs Application Note AN2015 at http//www.cypress.com under Application Notes for more information.
Document #: 001-43991 Rev. *D
Page 16 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Electrical Characteristics
The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature
range: 3.0V to 3.6V over the temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design
guidance only.
AC Chip Level Specifications
Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B)
Min
Typ
Max
Units
Notes
FIMO24
Symbol
Internal Main Oscillator Frequency for
24 MHz
Description
23.4
24
24.6[4, 5, 6]
MHz
Trimmed for 3.3V operation using
factory trim values. See the figure
on page 10. SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Frequency for
6 MHz
5.75
6
6.35[4 , 5, 6]
MHz
Trimmed for 3.3V operation using
factory trim values. See the figure
on page 10.
SLIMO Mode = 1.
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3[5, 6]
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2[4, 5, 7]
MHz
F24M
Digital PSoC Block Frequency
0
24
24.6[5, 7]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal
frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
0.5
–
50
ms
TPLLSLEWLOW PLL Lock Time for Low Gain Setting
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to
100 ppm
–
300
600
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2[4,6]
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input
or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Refer to section AC Digital Block
Specifications on page 19.
The crystal oscillator frequency is
within 100 ppm of its final value
by the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 uW maximum
drive level 32.768 kHz crystal.
ns
Trimmed. Using factory trim
values.
ps
Notes
4. 4.75V < Vcc < 5.25V.
5. Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range.
6. 3.0V < Vcc < 3.6V. See Application Note AN2012 “Adjusting PSoC Micro controller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
7. See individual user module data sheets for information on maximum frequencies for user modules.
Document #: 001-43991 Rev. *D
Page 17 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last
nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum.
Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B)
Parameter
nvSRAM
Description
tHRECALL
Power Up RECALL Duration
tSTORE
STORE Cycle Duration
VSWITCH
Low Voltage Trigger Level
tVccRISE
VCC Rise Time
Min
Unit
Max
20
ms
12.5
ms
2.65
V
μs
150
AC General Purpose IO Specifications
Table 16. 3.3V AC GPIO Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
Notes
MHz Normal Strong Mode
FGPIO
GPIO Operating Frequency
0
–
12.3
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vcc = 3V to 3.6V
10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vcc = 3V to 3.6V
10% - 90%
Figure 6. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document #: 001-43991 Rev. *D
TFallF
TFallS
Page 18 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Operational Amplifier Specifications
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B)
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Rising Settling Time to 0.1% of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Notes
Power = High and
Opamp Bias = High is
not supported at
3.3V.
Falling Settling Time to 0.1% of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
5.41
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Rising Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.31
–
–
V/μs
Power = Medium, Opamp Bias = High
2.7
–
–
V/μs
Falling Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.24
–
–
V/μs
Power = Medium, Opamp Bias = High
1.8
–
–
V/μs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
–
100
–
nV/rt-Hz
Min
Typ
Max
Units
24.6
MHz
Gain Bandwidth Product
Noise at 1 kHz
(Power = Medium, Opamp Bias = High)
AC Digital Block Specifications
Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B)
Function
Description
All Functions Maximum Block Clocking Frequency
Timer
Counter
Dead Band
Notes
3.0V ≤ Vcc ≤ 3.6V
50[8]
–
–
ns
Maximum Frequency, No Capture
–
–
24.6
MHz
3.0V ≤ Vcc ≤ 3.6V.
Maximum Frequency, With Capture
–
–
24.6
MHz
3.0V ≤ Vcc ≤ 3.6V.
Capture Pulse Width
Enable Pulse Width
50
[8]
–
–
ns
Maximum Frequency, No Enable Input
–
–
24.6
MHz
3.0V ≤ Vcc ≤3.6V.
Maximum Frequency, Enable Input
–
–
24.6
MHz
3.0V ≤ Vcc ≤ 3.6V.
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[8]
–
–
ns
[8]
–
–
ns
–
24.6
MHz
Kill Pulse Width:
Disable Mode
Maximum Frequency
50
–
3.0V ≤ Vcc ≤ 3.6V
Note
8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document #: 001-43991 Rev. *D
Page 19 of 38
[+] Feedback
PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued)
Function
Description
Min
Typ
Max
Units
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
–
–
24.6
MHz
3.0V ≤ Vcc ≤ 3.6V
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
3.0V ≤ Vcc ≤ 3.6V.
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
Maximum data rate at
4.1 MHz due to 2 x
over clocking.
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
Transmitter
Receiver
–
–
ns
–
–
24.6
MHz
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
–
–
49.2
MHz
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
Vcc ≥ 3.0V, 2 Stop Bits
–
–
49.2
MHz
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
Maximum Input Clock Frequency
Vcc ≥ 3.0V, 2 Stop Bits
50
[8]
Notes
AC Analog Output Buffer Specifications
Table 19. 3.3V AC Analog Output Buffer Specifications (CY8CNP102B)
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Power = Low
–
–
4.7
μs
Power = High
–
–
4.7
μs
Power = Low
–
–
4
μs
Power = High
–
–
4
μs
Power = Low
0.36
–
–
V/μs
Power = High
0.36
–
–
V/μs
Power = Low
0.4
–
–
V/μs
Power = High
0.4
–
–
V/μs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Document #: 001-43991 Rev. *D
Page 20 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Programming Specifications
Table 20. 3.3V AC Programming Specifications (CY8CNP102B)
Symbol
Description
Min
Typ
Max
Units
1
–
20
ns
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
10
–
ms
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
TRSCLK
Rise Time of SCLK
TFSCLK
TSSCLK
Notes
3.0V ≤ Vcc ≤ 3.6V
AC I2C Specifications
Table 21. 3.3V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102B)
Symbol
Description
Standard Mode
Min
Max
Fast Mode
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Setup Time
250
–
100[9]
–
ns
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
Note
9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.
Document #: 001-43991 Rev. *D
Page 21 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
5V Operation
Absolute Maximum Ratings
Table 22. 5V Absolute Maximum Ratings (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
25
+100
o
TA
Ambient Temperature with
Power Applied
-40
–
+85
o
Vcc
Supply Voltage on Vcc
Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vcc + 0.5
V
VIOZ
DC Voltage Applied to
Tri-state
Vss - 0.5
–
Vcc + 0.5
V
IMIO
Maximum Current into any
Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any
Port Pin Configured as
Analog Driver
-50
–
+50
mA
ESD
Electro Static Discharge
Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
Typ
Max
Units
C
C
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is ± 25oC. Extended
duration storage temperatures
above 65oC degrade reliability.
Human Body Model ESD.
Operating Temperature
Table 23. 5V Operating Temperature (CY8CNP102E)
Symbol
Description
Min
TA
Ambient Temperature
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
Document #: 001-43991 Rev. *D
Notes
Page 22 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Electrical Characteristics
The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature
ranges: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design
guidance only.
DC Chip Level Specifications
Table 24. 5V DC Chip-Level Specifications (CY8CNP102E)
Min
Typ
Max
Units
Vcc
Symbol
Supply Voltage
Description
4.75
–
5.25
V
Notes
IDD
Supply Current
–
39
45
mA
TA = 25 oC, CPU = 3 MHz,
SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz, continuous
nvSRAM access
IDDP
Supply current when IMO = 6 MHz
using SLIMO mode.
–
27
28
mA
TA = 25 oC, CPU = 0.75 MHz,
SYSCLK doubler disabled,
VC1=0.375 MHz, VC2=23.44
kHz, VC3 = 0.09 kHz, continuous
nvSRAM access
ISB
Sleep (Mode) Current with POR,
LVD, Sleep Timer, WDT, and
internal slow oscillator active.
–
–
5
mA
nvSRAM in standby.
VREF
Reference Voltage (Bandgap)
1.28
1.3
1.32
V
Trimmed for appropriate Vcc.
Vcap
Storage Capacitor between Vcap
and Vss
61
68
82
uF
5V rated (minimum)
Min
4
4
Vcc - 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
–
–
0.75
V
–
2.1
–
–
–
–
–
–
60
1
3.5
3.5
0.8
V
V
mV
nA
pF
pF
DC General Purpose IO Specifications
Table 25. 5V DC GPIO Specifications (CY8CNP102E)
Symbol
RPU
RPD
VOH
Description
Pull up Resistor
Pull down Resistor
High Output Level
VOL
Low Output Level
VIL
VIH
VH
IIL
CIN
COUT
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
Document #: 001-43991 Rev. *D
–
–
10
10
Notes
IOH = 10 mA, Vcc = 4.75 to 5.25V.
8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5]). 80 mA maximum
combined IOH budget.
IOL = 25 mA, Vcc = 4.75 to 5.25V
8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5]). 150 mA maximum
combined IOL budget.
4.75 to 5.25.
4.75 to 5.25.
Gross tested to 1 μA.
Pin dependent. Temp = 25oC.
Pin dependent. Temp = 25oC.
Page 23 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Operational Amplifier Specifications
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 26. 5V DC Operational Amplifier Specifications (CY8CNP102E)
Symbol
VOSOA
Description
Min
Typ
Max
Units
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
–
7.0
35.0
μV/oC
Notes
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range.
All Cases, except highest.
0.0
–
Vcc
V
Power = High, Opamp Bias = High
0.5
–
CMRROA
Common Mode Rejection Ratio
60
–
GOLOA
Open Loop Gain
Vcc - 0.5
V
–
dB
80
–
–
dB
VOHIGHOA High Output Voltage Swing (internal signals)
Vcc - 0.01
–
–
V
VOLOWOA Low Output Voltage Swing (internal signals)
–
–
0.1
V
Power = Low, Opamp Bias = Low
–
150
200
μA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
ISOA
PSRROA
Supply Current
(including associated AGND buffer)
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
67
80
–
dB
Vss ≤ VIN ≤ (Vcc - 2.25) or
(Vcc - 1.25V) ≤ VIN ≤ Vcc.
DC Low Power Comparator Specifications
Table 27. 5V DC Low Power Comparator Specifications (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
VREFLPC
Low power comparator (LPC) reference voltage range
0.2
–
Vcc - 1.0
V
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document #: 001-43991 Rev. *D
Page 24 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Analog Output Buffer Specifications
Table 28. 5V DC Analog Output Buffer Specifications (CY8CNP102E)
Symbol
VOSOB
Description
Min
Typ
Max
–
3
12
mV
–
+6
–
μV/°C
0.5
–
Vcc - 1.0
V
Power = Low
–
–
1
Ω
Power = High
–
–
1
Ω
Power = Low
0.5 x Vcc + 1.3
–
–
V
Power = High
0.5 x Vcc + 1.3
–
–
V
Power = Low
–
–
0.5 x Vcc - 1.3
V
Power = High
–
–
0.5 x Vcc - 1.3
V
–
1.1
2
mA
Power = High
–
2.6
5
mA
Supply Voltage Rejection Ratio
40
64
–
dB
Input Offset Voltage (Absolute Value)
TCVOSOB Average Input Offset Voltage Drift
VCMOB
Common-Mode Input Voltage Range
ROUTOB
Output Resistance
Units
VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vcc/2)
VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vcc/2)
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
DC Analog Reference Specifications
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 29. 5V DC Analog Reference Specifications (CY8CNP102E)
Symbol
VBG5
Description
Bandgap Voltage Reference 5V
Vcc/2[1]
–
AGND =
–
AGND = 2 x BandGap[1]
–
AGND = P2[4] (P2[4] = Vcc/2)
–
AGND = BandGap[1]
[1]
BandGap[1]
–
AGND = 1.6 x
–
AGND Block to Block Variation (AGND = Vcc/2)[1]
–
RefHi = Vcc/2 + BandGap
–
RefHi = 3 x BandGap
–
–
–
RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V)
–
RefHi = 2 x BandGap
–
RefHi = 3.2 x BandGap
–
RefLo = Vcc/2 – BandGap
–
RefLo = BandGap
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
–
RefLo = P2[4] – BandGap (P2[4] = Vcc/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V)
Min
Typ
Max
Units
1.28
1.30
1.32
V
Vcc/2 - 0.02
Vcc/2
Vcc/2 + 0.02
V
2.52
2.60
2.72
V
P2[4] - 0.013
P2[4]
P2[4] + 0.013
V
1.27
1.3
1.34
V
2.03
2.08
2.13
V
-0.034
0.000
0.034
V
Vcc/2 + 1.21
Vcc/2 + 1.3
Vcc/2 + 1.382
V
3.75
3.9
4.05
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
P2[6] + 2.478
P2[6] + 2.6
P2[6] + 2.722
V
RefHi = P2[4] + BandGap (P2[4] = Vcc/2)
P2[4] + 1.218
P2[4] + 1.3
P2[4] + 1.382
V
Document #: 001-43991 Rev. *D
P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058
2.50
2.60
V
2.70
V
4.02
4.16
4.29
V
Vcc/2 - 1.369
Vcc/2 - 1.30
Vcc/2 - 1.231
V
1.20
1.30
1.40
V
2.489 - P2[6]
2.6 - P2[6]
2.711 - P2[6]
V
P2[4] - 1.368
P2[4] - 1.30
P2[4] - 1.232
V
P2[4] - P2[6] - 0.042 P2[4] - P2[6] P2[4] - P2[6] + 0.042
V
Page 25 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Analog PSoC NV Block Specifications
Table 30. 5V DC Analog PSoC NV Block Specifications (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
Min
Typ
Max
Units
DC POR, SMP, and LVD Specifications
Table 31. 5V DC POR, SMP, and LVD Specifications (CY8CNP102E)
Symbol
Description
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
2.91
V
VPPOR1R
PORLEV[1:0] = 01b
4.39
V
VPPOR2R
PORLEV[1:0] = 10b
4.55
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
2.82
V
VPPOR1
PORLEV[1:0] = 01b
4.39
V
VPPOR2
PORLEV[1:0] = 10b
4.55
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
92
mV
VPH1
PORLEV[1:0] = 01b
0
mV
VPH2
PORLEV[1:0] = 10b
0
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98[2]
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
V
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
V
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
V
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
V
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74
V
VLVD6
VM[2:0] = 110b
4.63
4.73
4.82
V
VLVD7
VM[2:0] = 111b
4.72
4.81
4.91
V
Vdd Value for SMP Trip
VPUMP0
VM[2:0] = 000b
2.96
3.02
3.08
V
VPUMP1
VM[2:0] = 001b
3.03
3.10
3.16
V
VPUMP2
VM[2:0] = 010b
3.18
3.25
3.32
V
VPUMP3
VM[2:0] = 011b
4.11
4.19
4.28
V
VPUMP4
VM[2:0] = 100b
4.55
4.64
4.74
V
VPUMP5
VM[2:0] = 101b
4.63
4.73
4.82
V
VPUMP6
VM[2:0] = 110b
4.72
4.82
4.91
V
VPUMP7
VM[2:0] = 111b
4.90
5.00
5.10
V
Document #: 001-43991 Rev. *D
Page 26 of 38
[+] Feedback
PRELIMINARY
CY8CNP102B, CY8CNP102E
DC Programming Specifications
Table 32. 5V DC Programming Specifications (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
–
10
30
mA
Input Low Voltage During Programming or Verify
–
–
0.8
V
Input High Voltage During Programming or Verify
2.2
–
–
V
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull
down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull
down resistor.
VOLV
Output Low Voltage During Programming or
Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or
Verify
Vcc - 1.0
–
Vcc
V
50,000
–
–
–
Erase/write cycles per
block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
IDDPV
Supply Current During Programming or Verify
VILP
VIHP
IILP
FlashENPB Flash Endurance (per block)
FlashENT
Flash Endurance (total)[3]
FlashDR
Flash Data Retention
Document #: 001-43991 Rev. *D
Notes
Page 27 of 38
[+] Feedback
PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Electrical Characteristics
The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature
range: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design
guidance only.
AC Chip Level Specifications
Table 33. 5V AC Chip Level Specifications (CY8CNP102E)
Description
Min
Typ
Max
Units
FIMO24
Symbol
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6[4, 5, 6]
MHz
Trimmed for 5V operation
using factory trim values.
See Figure 5 on page 9.
SLIMO Mode = 0.
Notes
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[4 , 5, 6]
MHz
Trimmed for 5V operation
using factory trim values.
See Figure 5 on page 9.
SLIMO Mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6[4, 5]
MHz
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2[4, 5, 7]
F24M
Digital PSoC Block Frequency
0
24
24.6[5, 7]
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal
frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
0.5
–
50
ms
TPLLSLEWLOW PLL Lock Time for Low Gain Setting
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
300
600
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2[4,6]
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Document #: 001-43991 Rev. *D
Refer to AC Digital Block
Specifications on page 30.
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the Tosacc period. Correct
operation assumes a
properly loaded 1 uW
maximum drive level 32.768
kHz crystal.
ns
Trimmed. Using factory trim
values.
ps
Page 28 of 38
[+] Feedback
PRELIMINARY
CY8CNP102B, CY8CNP102E
In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last
nonvolatile cycle, no STORE takes place. Industrial grade devices require 15 ms maximum.
Table 34. 5V nvSRAM AutoStore/Power Up RECALL (CY8CNP102E)
Parameter
nvSRAM
Description
tHRECALL
Power Up RECALL Duration
tSTORE
STORE Cycle Duration
VSWITCH
Low Voltage Trigger Level
tVccRISE
VCC Rise Time
Min
Unit
Max
20
ms
12.5
ms
4.4
V
μs
150
AC General Purpose IO Specifications
Table 35. 5V AC GPIO Specifications (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
Notes
MHz Normal Strong Mode
FGPIO
GPIO Operating Frequency
0
–
12.3
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vcc = 4.75V to 5.25V
10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vcc = 4.75V to 5.25V
10% - 90%
Figure 7. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document #: 001-43991 Rev. *D
TFallF
TFallS
Page 29 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Operational Amplifier Specifications
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 36. 5V AC Operational Amplifier Specifications (CY8CNP102E)
Symbol
TROA
Description
SRFOA
–
–
3.9
μs
–
–
0.72
μs
–
–
0.62
μs
–
–
5.9
μs
Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)
Power = Medium, Opamp Bias = High
–
–
0.92
μs
Power = High, Opamp Bias = High
–
–
0.72
μs
Rising Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.15
–
–
V/μs
Power = Medium, Opamp Bias = High
1.7
–
–
V/μs
Power = High, Opamp Bias = High
6.5
–
–
V/μs
0.01
–
–
V/μs
Falling Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Medium, Opamp Bias = High
0.5
–
–
V/μs
Power = High, Opamp Bias = High
4.0
–
–
V/μs
0.75
–
–
MHz
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
ENOA
Units
Power = High, Opamp Bias = High
Power = Low, Opamp Bias = Low
BWOA
Max
Power = Medium, Opamp Bias = High
Power = Low, Opamp Bias = Low
SRROA
Typ
Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
TSOA
Min
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
–
100
–
nV/rt-Hz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
AC Digital Block Specifications
Table 37. 5V AC Digital Block Specifications (CY8CNP102E)
Function
Description
All
Functions
Maximum Block Clocking Frequency
Timer
Capture Pulse Width
Counter
Dead Band
CRCPRS
(PRS Mode)
Min
Typ
Max
Units
Notes
49.2
MHz
4.75V ≤ Vcc ≤ 5.25V.
50[8]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
4.75V ≤ Vcc ≤ 5.25V.
Maximum Frequency, With Capture
–
–
24.6
MHz
4.75V ≤ Vcc ≤ 5.25V.
50[8]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
4.75V ≤ Vcc ≤ 5.25V.
Maximum Frequency, Enable Input
–
–
24.6
MHz
4.75V ≤ Vcc ≤ 5.25V.
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[8]
–
–
ns
Disable Mode
50[8]
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V ≤ Vcc ≤ 5.25V
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V ≤ Vcc ≤ 5.25V
Enable Pulse Width
Kill Pulse Width:
Document #: 001-43991 Rev. *D
Page 30 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 37. 5V AC Digital Block Specifications (CY8CNP102E) (continued)
Function
Description
Min
Typ
Max
Units
Notes
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
4.75V ≤ Vcc ≤ 5.25V.
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
Maximum data rate at
4.1 MHz due to 2 x
over clocking.
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
50
–
–
ns
–
–
24.6
MHz
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
–
–
49.2
MHz
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
–
–
24.6
MHz
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
–
–
49.2
MHz
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
Min
Typ
Max
Units
Power = Low
–
–
4
μs
Power = High
–
–
4
μs
Power = Low
–
–
3.4
μs
Power = High
–
–
3.4
μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.55
–
–
V/μs
Power = High
0.55
–
–
V/μs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Width of SS_ Negated Between Transmissions
Transmitter
Receiver
Maximum Input Clock Frequency
Vcc ≥ 4.75V, 2 Stop Bits
Maximum Input Clock Frequency
Vcc ≥ 4.75V, 2 Stop Bits
[8]
AC Analog Output Buffer Specifications
Table 38. 5V AC Analog Output Buffer Specifications (CY8CNP102E)
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Document #: 001-43991 Rev. *D
Page 31 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
AC Programming Specifications
Table 39. 5V AC Programming Specifications (CY8CNP102E)
Symbol
Description
Min
Typ
Max
Units
1
–
20
ns
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
10
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
TRSCLK
Rise Time of SCLK
TFSCLK
TSSCLK
Notes
4.75V ≤ Vcc ≤ 5.25V
AC I2C Specifications
Table 40. 5V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102E)
Symbol
Description
Standard Mode
Min
Max
Fast Mode
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Setup Time
250
–
100[9]
–
ns
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
Document #: 001-43991 Rev. *D
Page 32 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Switching Waveforms
Figure 8. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Figure 9. PLL Lock Timing Diagram
PLL
E n a b le
TP LLS LE W
24 MHz
FPLL
PLL
G a in
0
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
PLL
E n a b le
TPLLS LE W LO W
24 MHz
FPLL
PLL
G a in
1
Document #: 001-43991 Rev. *D
Page 33 of 38
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PRELIMINARY
Switching Waveforms
CY8CNP102B, CY8CNP102E
(continued)
Figure 11. External Crystal Oscillator Startup Timing Diagram
32K
S e le c t
3 2 kHz
TO S
F32K2
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram
J it t e r 2 4 M 1
F
24M
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram
J it t e r 3 2 k
F
32K2
~
~
~
~
Figure 14. Definition of Timing for Fast/Standard Mode on the I2C Bus
tf
t LOWI2C
tr
t SUDATI2C
~
~
~
~
SDA
tf
t HDSTAI2C
t SPI2C
t BUFI2C
tr
S
t HDSTAI2C
Document #: 001-43991 Rev. *D
t HDDATI2C
t HIGHI2C
t SUSTAI2C
~
~
~
~
SCL
Sr
t SUSTOI2C
P
S
Page 34 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Part Numbering Nomenclature
C
Y
8
C
N
P
1
0
2
B
-
A
X
Cypress
I
Temp:
C = Commercial
I = Industrial
Microcontroller
X = Pb free
C = CMOS
A = 100TQFP
B = 3.3V
E = 5V
NP = PSoC NV Family
Processor Type:
1 = M8C (PSoC1 Based)
Density:
01 = 1Mb
02 = 2Mb
12 = 512Kb
Ordering Information
Ordering Code
Package Diagram
Package Type
Operating Range
CY8CNP102B-AXI
51 - 85048
100-pin TQFP
Industrial
CY8CNP102E-AXI
51 - 85048
100-pin TQFP
All the above mentioned parts are of “Pb-free” type and contain preliminary information. Please contact your local Cypress sales representative for
availability of these parts.
Document #: 001-43991 Rev. *D
Page 35 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Packaging Information
This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package.
Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation
tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161.
Package Diagrams
Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm
51-85048 *C
Thermal Impedance
Table 41. Thermal Impedance
Package[10]
100 TQFP
Typical θJA *
26.14
oC/W
Typical θJC *
5.81 oC/W
Note
10. * TJ = TA + POWER x θJA
Document #: 001-43991 Rev. *D
Page 36 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Document History Page
Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV)
Document Number: 001-43991
REV.
ECN
Orig. of Change
Submission
Date
**
1941108
vsutmp8/AESA
See ECN
New Data Sheet
*A
2378513
PYRS
See ECN
Move to external web
*B
2512803
GVCH/PYRS
06/05/2008
*C
2571208
GVCH/PYRS
09/23/08
Changed Title from nvPSoC to PSoC NV
Updated “Features”
*D
2594976
GVCH/PYRS
10/22/08
Added M8C processor speeds for 3.3V and 5V operation in “Features”
Updated Logic block diagram
Changed total GPIOs from 27 to 33
Changed pin number 53 name from P1_4 to P1_6
Changed pin definition of pin 79 and 99
Table 5: Changed ISB from 3 mA to 5 mA
Updated Table 12
Table 24: Changed ISB from 3 mA to 5 mA
Document #: 001-43991 Rev. *D
Description of Change
Features: Added total no. of GPIO information in Programmable Pin
configurations
Changed Pin no.14 from P3_7 to NC in the Pin diagram
Table 1: Updated Pin definitions
Table 5: Changed Typ and max value of IDD from 25 mA and 29mA to 36 mA
and 40 mA resp.
Table 5: Changed Typ and max value of IDDP from 15 mA and 16 mA to
27 mA and 28 mA respectively.
Table 5: Changed Min and Max value of VCAP from 56 uF and 100 uF to
61 uF and 82 uF resp.
Table 6: Changed VIH min value from 2.1 mV to 1.6 mV
Added Table 12: DC POR,SMP, and LVD specifications
Table 13: Changed IDDP naming convention to IDDPV
Table 14: Updated note references
Table 17: Updated Timer, Counter, deadband and CRCPS (PRS mode)
values
Table 23: Changed Typ and max value of IDD from 28 mA and 34 mA to
39 mA and 45 mA resp.
Table 23: Changed Typ and max value of IDDP from 15 mA and 16 mA to
27 mA and 28 mA resp.
Table 23: Changed Min and Max value of VCAP from 56 uF and 100 uF to
61 uF and 82 uF resp.
Added Table 30: DC POR,SMP, and LVD specifications
Table 31: Changed IDDP naming convention to IDDPV
table 32: Updated note references
Updated Figure 14: Definition for Timing for Fast/Standard Mode on the I2C
bus
Updated part Numbering Nomenclature
Updated Thermal Impedance table
Updated data sheet template
Page 37 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
Wireless
Memories
Image Sensors
PSoC Solutions
psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
wireless.cypress.com
Precision Analog
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
image.cypress.com
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43991 Rev. *D
Revised October 20, 2008
Page 38 of 38
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned
in this document are the trademarks of their respective holders.
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