TI ADS4222 Dual-channel, 14-bit, 250-msps ultralow-power adc with analog input buffer Datasheet

ADS42B49
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SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013
Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC with Analog Input Buffer
Check for Samples: ADS42B49
FEATURES
APPLICATIONS
•
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1
23
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Maximum Sample Rate: 250 MSPS
Ultralow Power:
– 850-mW Total Power at 250 MSPS
Integrated Analog Input Buffer:
– Input Capacitance: 2.2 pF at 170 MHz
– Input Resistance: 1.1 kΩ at 170 MHz
High Dynamic Performance:
– 85-dBc SFDR at 170 MHz
– 70.7-dBFS SNR at 170 MHz
Crosstalk: > 85 dB at 185 MHz
Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
DC Offset Correction
Output Interface Options:
– 1.8-V Parallel CMOS Interface
– Double Data Rate (DDR) LVDS with
Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
Supports Low Input Clock Amplitude
Down to 200 mVPP
Package: 9-mm × 9-mm, 64-Pin Quad Flat NoLead (QFN) Package
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
DESCRIPTION
The ADS42B49 is an ultralow-power dual-channel,
14-bit analog-to-digital converter (ADC) featuring
integrated analog input buffers. It uses innovative
design techniques to achieve high dynamic
performance, while consuming extremely low power.
The presence of analog input buffers makes this
device easy to drive and helps achieve high
performance over a wide frequency range. The
ADS42B49 is well-suited for multi-carrier, wide
bandwidth communications applications.
The ADS42B49 has gain options that can be used to
improve SFDR performance at lower full-scale input
ranges. This device also includes a dc offset
correction loop that can be used to cancel the ADC
offset. Both DDR LVDS and parallel CMOS digital
output interfaces are available in a compact QFN-64
PowerPAD™ package.
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS42B49 is
specified over the industrial temperature range
(–40°C to +85°C).
ADS424x and ADS422x Family Comparison (1)
(1)
65 MSPS
125 MSPS
160 MSPS
250 MSPS
ADS422x
12-bit family
ADS4222
ADS4225
ADS4226
ADS4229
ADS424x
14-bit family
ADS4242
ADS4245
ADS4246
ADS4249,
ADS42B49 (with analog
input buffers)
See Table 1 for details on migrating from the ADS62P49 family.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
ADS42B49
SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
ADS42B49
(1)
(2)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
QFN-64
RGC
–40°C to +85°C
ECO PLAN (2)
GREEN (RoHS,
no Sb/Br)
LEAD AND BALL
FINISH
Cu/NiPdAu
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA
ADS42B49IRGCT
Tape and Reel
ADS42B49IRGCR
Tape and Reel
AZ42B49
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS42B49 is pin-compatible with the previous generation ADS62P49 data converter; this similar
architecture enables easy migration. However, there are some important differences between the two device
generations, summarized in Table 1.
Table 1. Migrating from the ADS62P49 and ADS4249
ADS62P49
ADS4249
ADS42B49
PINS
Pin 22 is NC (not connected).
Must float.
Pin 22 is AVDD (1.8 V)
Pin 22 is AVDD (1.9 V)
Pin 34 is AVDD (3.3 V)
Pin 34 is AVDD (1.8 V)
Pin 34 is AVDD_BUF (3.3 V)
Pin 38 is DRVDD (1.8 V)
Pin 38 is NC. Must float.
Pin 38 is DRVDD (1.8 V)
Pin 39 is DRGND
Pin 39 is NC. Must float.
Pin 39 is DRGND
Pin 58 is DRVDD (1.8 V)
Pin 58 is NC. Must float.
Pin 58 is DRVDD (1.8 V)
Pin 59 is DRGND
Pin 59 is NC. Must float.
Pin 59 is DRGND
AVDD is 3.3 V
AVDD is 1.8 V
AVDD is 1.9 V
DRVDD is 1.8 V
DRVDD is 1.8 V
DRVDD is 1.8 V
SUPPLY
AVDD_BUF is 3.3 V
INPUT COMMON-MODE VOLTAGE
CM is 1.5 V
CM is 0.95 V
CM is 1.9 V
NP and INM must be externally biased at 0.95 V
INP and INM do not require external
biasing. Device internally biases these
pins to 1.9 V.
Not supported
Not supported
SCLK pin enables low-speed mode
SCLK pin enables low-speed mode
BIASING FOR INPUT PINS (INP, INM)
INP and INM must be externally
biased at 1.5 V
EXTERNAL REFERENCE
Supported
PARALLEL CONFIGURATION
SCLK pin controls internal and
external reference mode
2
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE
Supply voltage range
Voltage between:
Voltage applied to
Temperature range
MIN
MAX
AVDD
–0.3
2.1
V
AVDD_BUF
–0.3
3.6
V
DRVDD
–0.3
2.1
V
AGND and DRGND
–0.3
0.3
V
AVDD to DRVDD
(when AVDD leads DRVDD)
–2.4
2.4
V
DRVDD to AVDD
(when DRVDD leads AVDD)
–2.4
2.4
V
AVDD_BUF to DRVDD and AVDD
–3.9
3.9
V
INP, INM
–0.3
Minimum
(3, AVDD_BUF + 0.3)
V
CLKP, CLKM (2)
–0.3
AVDD + 0.3
V
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
–0.3
3.9
V
Operating free-air, TA
–40
+85
°C
+125
°C
Operating junction, TJ
Storage, Tstg
Electrostatic discharge (ESD) rating
(1)
(2)
–65
UNIT
+150
°C
2
kV
Human body model (HBM)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|).
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS42B49
THERMAL METRIC
(1)
RGC
UNIT
64 PINS
θJA
Junction-to-ambient thermal resistance
23.9
θJCtop
Junction-to-case (top) thermal resistance
10.9
θJB
Junction-to-board thermal resistance
4.3
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
4.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.6
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
AVDD_BUF
Analog buffer supply voltage
DRVDD
Digital supply voltage
1.8
1.9
2
V
3.15
3.3
3.45
V
1.7
1.8
2
V
ANALOG INPUTS
VID
Differential input voltage range
VICR
Input common-mode voltage
2
VPP
VCM ± 0.05
Maximum analog input frequency with 2-VPP input amplitude
(1)
Maximum analog input frequency with 1.6-VPP input amplitude (1)
V
400
MHz
500
MHz
CLOCK INPUT
Input clock sample rate
Low-speed mode enabled (2)
Low-speed mode disabled (2) (by default after reset)
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
1
80
MSPS
80
250
MSPS
0.2
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.5
V
Input clock duty cycle
Low-speed mode disabled
45
50
55
%
Low-speed mode enabled
40
50
60
%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
3.3
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
100
TA
Operating free-air temperature
(1)
(2)
–40
pF
Ω
+85
°C
See the Analog Input section in the Application Information.
See the Serial Interface Configuration section for details on programming the low-speed mode.
HIGH-PERFORMANCE MODES (1) (2)
PARAMETER
High-performance modes
(1)
(2)
4
DESCRIPTION
Set the HIGH PERF MODE[0] to improve SNR in CMOS mode by approximately 0.5 dB at 170 MHz.
Register Address = 03h, data = 02h
Set the HIGH PERF MODE[1:11] bits to obtain best performance across input signal frequencies.
Register Address = 06h, data = 06h
Register Address = BAh, data = 08h
Register Address = D5h, data = 20h
Register Address = D9h, data = 22h
Register Address = DBh, data = E0h
Register Address = DCh, data = 22h
TI recommends using these modes to obtain best performance.
See the Serial Interface Configuration section for details on register programming.
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ELECTRICAL CHARACTERISTICS: ADS42B49 (250 MSPS)
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full
temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
SNR
SINAD
SFDR
THD
HD2
HD3
Signal-to-noise ratio
Signal-to-noise and
distortion ratio
Spurious-free dynamic
range
Total harmonic distortion
Second-harmonic
distortion
Third-harmonic distortion
Worst spur
(other than second and
third harmonics)
IMD
Two-tone intermodulation
distortion
MAX
14
UNIT
Bits
fIN = 10 MHz
71.3
dBFS
fIN = 70 MHz
71.2
dBFS
fIN = 100 MHz
71.1
dBFS
70.7
dBFS
fIN = 170 MHz, 3-dB gain
67.8
dBFS
fIN = 300 MHz
69.5
dBFS
fIN = 10 MHz
71
dBFS
fIN = 70 MHz
71
dBFS
70.9
dBFS
70.4
dBFS
fIN = 170 MHz, 3-dB gain
67.7
dBFS
fIN = 300 MHz
67.7
dBFS
fIN = 170 MHz, 0-dB gain
68
fIN = 100 MHz
fIN = 170 MHz, 0-dB gain
67
fIN = 10 MHz
83
dBc
fIN = 70 MHz
87
dBc
fIN = 100 MHz
86
dBc
85
dBc
fIN = 170 MHz, 3-dB gain
89
dBc
fIN = 300 MHz
73
dBc
fIN = 10 MHz
82
dBc
fIN = 70 MHz
84
dBc
fIN = 100 MHz
85
dBc
83
dBc
fIN = 170 MHz, 3-dB gain
86
dBc
fIN = 300 MHz
72
dBc
fIN = 10 MHz
95
dBc
fIN = 70 MHz
93
dBc
fIN = 100 MHz
98
dBc
89
dBc
fIN = 170 MHz, 3-dB gain
94
dBc
fIN = 300 MHz
80
dBc
fIN = 10 MHz
83
dBc
fIN = 70 MHz
87
dBc
fIN = 100 MHz
86
dBc
85
dBc
fIN = 170 MHz, 3-dB gain
89
dBc
fIN = 300 MHz
73
dBc
fIN = 10 MHz
100
dBc
fIN = 70 MHz
100
dBc
fIN = 100 MHz
100
dBc
95
dBc
fIN = 170 MHz, 3-dB gain
97
dBc
fIN = 300 MHz
94
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
88
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
83
dBFS
fIN = 170 MHz, 0-dB gain
fIN = 170 MHz, 0-dB gain
fIN = 170 MHz, 0-dB gain
fIN = 170 MHz, 0-dB gain
fIN = 170 MHz, 0-dB gain
73
70
73
73
84
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ELECTRICAL CHARACTERISTICS: ADS42B49 (250 MSPS) (continued)
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full
temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
Crosstalk
10-MHz full-scale signal on channel under observation;
170-MHz full-scale signal on other channel
Input overload recovery
Recovery to within 1%
(of full-scale) for 6-dB overload with sine-wave input
PSRR
AC power-supply rejection
ratio
For 50-mVPP signal on AVDD supply
ENOB
Effective number of bits
fIN = 170 MHz
MIN
TYP
MAX
UNIT
> 85
dB
1
Clock cycle
30
dB
11.4
LSBs
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS
differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN =
–40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VID
Differential input voltage range
VCM
2
VPP
Differential input resistance (at 170 MHz)
1.2
kΩ
Differential input capacitance (at 170 MHz)
2.2
pF
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)
700
MHz
Common-mode output voltage
(1)
V
10
mA
1.9
VCM output current capability
DC ACCURACY
Offset error
–20
EGREF
Gain error as a result of internal reference inaccuracy alone
EGCHAN
Gain error of channel alone
3
–2
20
mV
2
%FS
–5
Temperature coefficient of EGCHAN
%FS
Δ%/°C
0.005
POWER SUPPLY
IAVDD
Analog supply current
IAVDD_BUF
Analog buffer supply current
IDRVDD
186
225
mA
67
90
mA
LVDS interface, 350-mV swing with 100-Ω external termination,
fIN = 2.5 MHz
151
180
mA
CMOS interface, 8-pF external load capacitance,
fIN = 2.5 MHz (2)
128
mA
Analog power
353
mW
Analog buffer power
224
mW
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
272
mW
Digital power, CMOS interface, 8-pF external load capacitance, (2) fIN = 2.5 MHz
230
Total power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
850
Output buffer supply current
Global power-down
(1)
(2)
6
mW
925
mW
20
mW
After the HIGH PERF MODE[10:0] bits are set.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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DIGITAL CHARACTERISTICS
At AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition
where the digital outputs do not switch, but are permanently at a valid logic level '0' or '1'.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3) (1)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
All digital inputs support
1.8-V and 3.3-V CMOS
logic levels
SDATA, SCLK
(2)
1.3
V
0.4
V
VHIGH = 1.8 V
10
µA
SEN (3)
VHIGH = 1.8 V
0
µA
SDATA, SCLK
VLOW = 0 V
0
µA
SEN
VLOW = 0 V
10
µA
DRVDD
V
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
CO
Output capacitance (internal to device)
DRVDD –
0.1
0
0.1
V
pF
DIGITAL OUTPUTS, LVDS INTERFACE
VODH
High-level output differential voltage
With an external
100-Ω termination
275
350
425
mV
VODL
Low-level output differential voltage
With an external
100-Ω termination
–425
–350
–275
mV
VOCM
Output common-mode voltage
0.9
1.05
1.25
V
(1)
(2)
(3)
SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
SDATA and SCLK have an internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V
CMOS buffers.
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TIMING REQUIREMENTS: LVDS and CMOS Modes
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine
wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the
full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.7 V to 2 V.
PARAMETER
tA
DESCRIPTION
Aperture delay
tJ
Aperture delay matching
Between two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
MIN
TYP
MAX
0.5
0.8
1.1
ns
±70
ps
±150
ps
120
fS rms
50
µs
100
µs
Default latency after reset
11
Clock
cycles
Digital functions enabled (EN DIGITAL = 1)
19
Clock
cycles
Aperture jitter
Wakeup time
UNIT
Time to valid data after coming out of STANDBY
mode
Time to valid data after coming out of GLOBAL
power-down mode
ADC latency (1)
DDR LVDS MODE (2) (3)
tSU_RISE
Data setup time on rising
edge of CLKOUTP
Data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (4)
0.32
0.68
ns
tHO_RISE
Data hold time on rising
edge of CLKOUTP
Zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (4)
0.5
0.82
ns
tSU_FALL
Data setup time on falling
edge of CLKOUTP
Data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (4)
0.63
1.04
ns
tHO_FALL
Data hold time on falling
edge of CLKOUTP
Zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (4)
0.18
0.58
ns
tPDI
Clock propagation delay
Input clock rising edge cross-over to output clock
(CLKOUTP – CLKOUTM) rising edge cross-over
7.6
8.9
LVDS bit clock duty cycle
Duty cycle of differential clock
(CLKOUTP – CLKOUTM)
tFALL,
tRISE
Data fall time,
Data rise time
tCLKRISE,
tCLKFALL
10.2
ns
57
%
Rise time measured from –100 mV to +100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to +100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
PARALLEL CMOS MODE
Clock propagation delay
Input clock rising edge cross-over to output clock
rising edge cross-over
Output clock duty cycle
Duty cycle of output clock, CLKOUT
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
50
%
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
0.7
ns
tCLKRISE,
tCLKFALL
Output clock rise time
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
0.7
ns
tPDI
(1)
(2)
(3)
(4)
8
5.9
8.3
10.6
ns
Overall latency = ADC latency + tPDI. At 250 MSPS, tPDI is greater than two clock periods. Therefore, overall latency at 250 MSPS =
ADC latency + 2 clock cycles.
Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Setup and hold values in DDR LVDS mode are taken with a delayed output clock by writing register 42h, value 30h.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
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Table 2. LVDS Timings at Lower Sampling Frequencies (1)
SETUP TIME (ns)
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
100
0.36
125
150
(1)
tSU_RISE
HOLD TIME (ns)
tSU_FALL
MAX
CLOCK
PROPAGATION
DELAY (ns)
MIN
TYP
0.72
0.67
0.35
0.72
0.35
0.70
175
0.35
200
230
tHO_RISE
MAX
MIN
TYP
1.10
3.37
0.66
1.08
0.66
1.07
0.70
0.63
0.38
0.70
0.33
0.69
tHO_FALL
MAX
MIN
TYP
3.80
3.02
2.43
2.82
1.77
2.15
1.07
1.32
0.68
1.08
0.67
1.06
tPDI
MAX
MIN
TYP
MAX
3.48
10.4
11.8
13.1
2.09
2.51
9.4
10.8
12.1
1.47
1.86
8.8
10.1
11.5
1.67
1.00
1.40
8.3
9.7
11.0
0.93
1.29
0.66
1.04
8.0
9.4
10.8
0.63
0.97
0.35
0.74
7.7
9.1
10.5
Setup and hold values in DDR LVDS mode belong to delayed output clock by writing register 42h, value 30h.
Table 3. CMOS Timings at Lower Sampling Frequencies
SETUP TIME (1)
(tSU, ns)
HOLD TIME (1)
(tHO, ns)
CLOCK PROPAGATION DELAY
(tPDI, ns)
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
MIN
TYP
MIN
TYP
MAX
100
3.91
4.40
3.68
4.18
9.5
11.5
13.3
125
2.81
3.40
2.73
3.14
8.5
10.5
12.3
150
2.00
2.64
2.09
2.52
7.9
9.9
11.7
175
1.43
2.14
1.67
2.06
7.6
9.4
11.4
200
1.01
1.76
1.25
1.68
6.4
8.9
11.1
(1)
MAX
MAX
In CMOS mode, setup time is measured from the beginning of data valid to the mid-point of the CLKOUT rising edge, whereas hold time
is measured from the mid-point of the CLKOUT rising edge to data becoming invalid.
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PARAMETER MEASUREMENT INFORMATION
DAn_P
DBn_P
Logic 0
Logic 1
VODL = -350 mV
(1)
VODH = +350 mV
(1)
DAn_M
DBn_M
VOCM
GND
(1) With an external 100-Ω termination.
Figure 1. LVDS Output Voltage Levels
N+3
N+2
N+1
Sample
N
N+4
N+13
N+12
N+11
Input
Signal
tA
Input
Clock
CLKM
CLKP
CLKOUTM
CLKOUTP
11 Clock Cycles(1)
DDR
LVDS
tPDI
Output Data(2)
DxP, DxM
E
O
N-11
E
O
E
N-10
O
N-9
E
O
E
O
E
O
N-8
E
O
E
N
O
N+1
E
O
E
O
N+2
CLKOUT
tPDI
11 Clock Cycles(1)
Parallel
CMOS
Output Data
D[13:0]
N-11
N-10
N-9
N-8
N-1
N
N+1
N+2
(1) The ADC latency after reset is 11 clock cycles. Overall latency = ADC latency + tPDI.
(2) E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).
Figure 2. Latency Timing Diagram
10
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PARAMETER MEASUREMENT INFORMATION (continued)
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
tH
DAn,
DBn
Output
Data
Dn
(1)
(1) Dn = bits D0, D1, D2, and so forth of channels A and B.
Figure 3. CMOS Interface Timing Diagram
CLKM
Input Clock
CLKP
tPDI
CLKOUTP
Output Clock
CLKOUTM
tsu_fall
Output Data Pair
Dn_Dn+1P,
Dn_Dn+1M
tho_fall
tsu_rise
Dn(1)
tho_rise
Dn+1(1)
(1) Dn = D0, D2, D4, and so forth. Dn+1 = D1, D3, D5, and so forth.
Figure 4. LVDS Interface Timing Diagram
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PARAMETER MEASUREMENT INFORMATION (continued)
CLKOUTP
CLKOUTM
Dx0P, Dx1P,
Dx0M, Dx1M
D0
D1
D0
D1
Dx2P, Dx3P,
Dx2M, Dx3M
D2
D3
D2
D3
Dx4P, Dx5P,
Dx4M, Dx5M
D4
D5
D4
D5
Dx6P, Dx7P,
Dx6M, Dx7M
D6
D7
D6
D7
Dx8P, Dx9P,
Dx8M, Dx9M
D8
D9
D8
D9
Dx10P, Dx11P,
Dx10M, Dx11M
D10
D11
D10
D11
Dx12P, Dx13P,
Dx12M, Dx13M
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 5. LVDS Bit Order
12
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PIN CONFIGURATION: LVDS MODE
49 DRGND
50 DA8M
51 DA8P
52 DA10M
53 DA10P
54 DA12M
55 DA12P
56 CLKOUTM
57 CLKOUTP
58 DRVDD
59 DRGND
60 DB0M
61 DB0P
62 DB2M
63 DB2P
64 SDOUT
RGC PACKAGE(1)
QFN-64
(TOP VIEW)
DRVDD
1
48
DRVDD
DB4M
2
47
DA6P
DB4P
3
46
DA6M
DB6M
4
45
DA4P
DB6P
5
44
DA4M
DB8M
6
43
DA2P
DB8P
7
42
DA2M
DB10M
8
41
DA0P
DB10P
9
40
DA0M
DB12M 10
39
DRGND
DB12P 11
38
DRVDD
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD_BUF
AVDD 16
33
AVDD
AGND 32
AGND 31
INM_A 30
INP_A 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
(1) The PowerPAD is connected to DRGND.
Figure 6. LVDS Mode
PIN DESCRIPTIONS: LVDS Mode
PIN NAME
PIN NUMBER
# OF PINS
FUNCTION
AGND
17, 18, 21, 24, 27, 28,
31, 32
DESCRIPTION
8
Input
Analog ground
AVDD
16, 22, 33
3
Input
Analog power supply
AVDD_BUF
34
1
Input
Analog buffer supply
CLKM
26
1
Input
Differential clock negative input
CLKP
25
1
Input
Differential clock positive input
CLKOUTM
56
1
Output
Differential output clock, complement
CLKOUTP
57
1
Output
Differential output clock, true
CTRL1
35
1
Input
Digital control input pins.
Together, these pins control the various power-down modes.
CTRL2
36
1
Input
Digital control input pins.
Together, these pins control the various power-down modes.
CTRL3
37
1
Input
Digital control input pins.
Together, these pins control the various power-down modes.
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PIN DESCRIPTIONS: LVDS Mode (continued)
PIN NAME
PIN NUMBER
# OF PINS
FUNCTION
DA0P, DA0M
Refer to Figure 6
2
Output
Channel A differential output data pair, D0 and D1 multiplexed
DA2P, DA2M
Refer to Figure 6
2
Output
Channel A differential output data D2 and D3 multiplexed
DA4P, DA4M
Refer to Figure 6
2
Output
Channel A differential output data D4 and D5 multiplexed
DA6P, DA6M
Refer to Figure 6
2
Output
Channel A differential output data D6 and D7 multiplexed
DA8P, DA8M
Refer to Figure 6
2
Output
Channel A differential output data D8 and D9 multiplexed
DA10P,
DA10M
Refer to Figure 6
2
Output
Channel A differential output data D10 and D11 multiplexed
DA12P,
DA12M
Refer to Figure 6
2
Output
Channel A differential output data D12 and D13 multiplexed
DB0P, DB0M
Refer to Figure 6
2
Output
Channel B differential output data pair, D0 and D1 multiplexed
DB2P, DB2M
Refer to Figure 6
2
Output
Channel B differential output data D2 and D3 multiplexed
DB4P, DB4M
Refer to Figure 6
2
Output
Channel B differential output data D4 and D5 multiplexed
DB6P, DB6M
Refer to Figure 6
2
Output
Channel B differential output data D6 and D7 multiplexed
DB8P, DB8M
Refer to Figure 6
2
Output
Channel B differential output data D8 and D9 multiplexed
DB10P,
DB10M
Refer to Figure 6
2
Output
Channel B differential output data D10 and D11 multiplexed
DB12P,
DB12M
Refer to Figure 6
2
Output
Channel B differential output data D12 and D13 multiplexed
DRGND
39, 49, 59, PAD
4
Input
Output buffer ground, should be shorted on-board to analog ground.
DRVDD
1, 38, 48, 58
4
Input
Output buffer supply
INM_A
30
1
Input
Differential analog negative input, channel A
INP_A
29
1
Input
Differential analog positive input, channel A
INM_B
20
1
Input
Differential analog negative input, channel B
INP_B
19
1
Input
Differential analog positive input, channel B
14
DESCRIPTION
RESET
12
1
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK
and SEN are used as parallel control pins in this mode. This pin has an internal
150-kΩ pull-down resistor.
SCLK
13
1
Input
This pin functions as a serial interface clock input when RESET is low. SCLK
controls the low-speed mode selection when RESET is tied high; see Table 5 for
detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
1
Input
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
1
Output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
SEN
15
1
Input
This pin functions as a serial interface enable input when RESET is low. SEN
controls the output interface and data format selection when RESET is tied high;
see Table 6 for detailed information. This pin has an internal 150-kΩ pull-up
resistor to AVDD.
VCM
23
1
Output
This pin outputs the common-mode voltage (1.9 V) that can be used externally to
bias the analog input pins
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PIN CONFIGURATION: CMOS MODE
49 DRGND
50 DA8
51 DA9
52 DA10
53 DA11
54 DA12
55 DA13
56 UNUSED
57 CLKOUT
58 DRVDD
59 DRGND
60 DB0
61 DB1
62 DB2
63 DB3
64 SDOUT
RGC PACKAGE(2)
QFN-64
(TOP VIEW)
DRVDD
1
48
DRVDD
DB4
2
47
DA7
DB5
3
46
DA6
DB6
4
45
DA5
DB7
5
44
DA4
DB8
6
43
DA3
DB9
7
42
DA2
DB10
8
41
DA1
DB11
9
40
DA0
DB12 10
39
DRGND
DB13 11
38
DRVDD
RESET 12
37
CTRL3
SCLK 13
36
CTRL2
SDATA 14
35
CTRL1
SEN 15
34
AVDD_BUF
AVDD 16
33
AVDD
AGND 32
AGND 31
INM_A 30
INP_A 29
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 18
AGND 17
Thermal Pad
(Connected to DRGND)
(2) The PowerPAD is connected to DRGND.
Figure 7. CMOS Mode
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PIN DESCRIPTIONS: CMOS Mode
16
# OF
PINS
FUNCTION
PIN NAME
PIN NUMBER
AGND
17, 18, 21, 24, 27,
28, 31, 32
DESCRIPTION
8
Input
Analog ground
AVDD
16, 22, 33
3
Input
Analog power supply
AVDD_BUF
34
1
Input
Analog buffer supply
CLKM
26
1
Input
Differential clock negative input
CLKP
25
1
Input
Differential clock positive input
CLKOUT
57
1
Output
CTRL1
35
1
Input
Digital control input pins. Together, these pins control various power-down modes.
CTRL2
36
1
Input
Digital control input pins. Together, these pins control various power-down modes.
Digital control input pins. Together, these pins control various power-down modes.
CMOS output clock
CTRL3
37
1
Input
DA0 to DA13
Refer to Figure 7
14
Output
Channel A ADC output data bits, CMOS levels
DB0 to DB13
Refer to Figure 7
14
Output
Channel B ADC output data bits, CMOS levels
DRGND
39, 49, 59, PAD
4
Input
Output buffer ground, should be shorted on-board to analog ground.
DRVDD
1, 38, 48, 58
4
Input
Output buffer supply
INM_A
30
1
Input
Differential analog negative input, channel A
INP_A
29
1
Input
Differential analog positive input, channel A
INM_B
20
1
Input
Differential analog negative input, channel B
INP_B
19
1
Input
Differential analog positive input, channel B
RESET
12
1
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA
and SEN are used as parallel control pins in this mode.
This pin has an internal 150-kΩ pull-down resistor.
SCLK
13
1
Input
This pin functions as a serial interface clock input when RESET is low. SCLK
controls the low-speed mode when RESET is tied high; see Table 5 for detailed
information. This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
1
Input
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
1
Output
SEN
15
1
Input
UNUSED
56
1
—
VCM
23
1
Output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
This pin functions as a serial interface enable input when RESET is low. SEN
controls the output interface and data format selection when RESET is tied high; see
Table 6 for detailed information. This pin has an internal 150-kΩ pull-up resistor to
AVDD.
This pin is not used in the CMOS interface
This pin outputs the common-mode voltage (1.9 V) that can be used externally to
bias the analog input pins
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DRGND
DRVDD
AGND
AVDD
AVDD_BUF
FUNCTIONAL BLOCK DIAGRAM
LVDS INTERFACE
DA0P/M
DA2P/M
INP_A
SAMPLING
CIRCUIT
DA4P/M
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_A
DA6P/M
DA8P/M
DA10P/M
DA12P/M
CLKP
CLKM
OUTPUT
CLOCK
BUFFER
CLOCKGEN
CLKOUTP/M
DB0P/M
DB2P/M
INP_B
SAMPLING
CIRCUIT
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_B
DB4P/M
DB6P/M
DB8P/M
DB10P/M
DB12P/M
VCM
CONTROL
INTERFACE
REFERENCE
SDOUT
CTRL2
CTRL3
CTRL1
SCLK
SEN
SDATA
RESET
ADS42B49
Figure 8. Block Diagram
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DEVICE CONFIGURATION
The ADS42B49 can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 4 describes the modes controlled by the parallel pins.
Table 4. Parallel Pin Definition
PIN
CONTROL MODE
SCLK
Low-speed mode selection
SEN
Output data format and output interface selection
CTRL1
CTRL2
Together, these pins control the power-down modes and multiplexedmode selection ( in CMOS interface)
CTRL3
SERIAL INTERFACE CONFIGURATION ONLY
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Register Map section describes the register programming and the register
reset process in more detail.
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control
pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the
voltage settings on these pins (see Table 7). SEN, SDATA, and SCLK function as serial interface digital pins and
are used to access the internal registers of the ADC. The registers must first be reset to the default values either
by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must be kept
low. The Serial Register Map section describes register programming and the register reset process in more
detail.
18
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PARALLEL CONFIGURATION DETAILS
The functions controlled by each parallel pin are described in Table 5, Table 6, and Table 7. A simple way of
configuring the parallel pins is shown in Figure 9.
Table 5. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low
Low-speed mode is disabled
High
Low-speed mode is enabled
Table 6. SEN Control Pin
VOLTAGE APPLIED ON SEN
0
(+50 mV / 0 mV)
DESCRIPTION
Twos complement and parallel CMOS output
(3 / 8) AVDD
(±50 mV)
Offset binary and parallel CMOS output
(5 / 8) AVDD
(±50 mV)
Offset binary and DDR LVDS output
AVDD
(0 mV / –50 mV)
Twos complement and DDR LVDS output
Table 7. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
CTRL2
CTRL3
Low
Low
Low
Normal operation
DESCRIPTION
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Partial power-down
High
Low
High
Channel A is powered down, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
3R
(3/8) AVDD
To Parallel Pin
Figure 9. Simple Scheme to Configure the Parallel Pins
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SERIAL INTERFACE DETAILS
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight
bits are the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds
(of a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Through a hardware reset by applying a high pulse on the RESET pin (of width greater than 10 ns), as
shown in Figure 10 and Table 8; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low. See Figure 11 and Table 9 for reset timing.
Register Address
SDATA
A6
A7
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
D4
D3
tDSU
tSCLK
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 10. Serial Interface Timing
Table 8. Serial Interface Timing Characteristics (1)
PARAMETER
MIN
MAX
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
(1)
20
> dc
TYP
fSCLK
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted.
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Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 11. Reset Timing Diagram
Table 9. Reset Timing (Only when Serial Interface is Used) (1)
PARAMETER
CONDITIONS
MIN
t1
Power-on delay
Delay from AVDD and DRVDD power-up to active RESET
pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
(1)
TYP
MAX
UNIT
1
ms
10
ns
1
100
µs
ns
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on pin 64. A serial readout timing
diagram is shown in Figure 12.
Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT
bits. When READOUT is disabled, the SDOUT pin is in a high-impedance state.
Register Address A[7:0] = 00h
SDATA
0
0
0
0
0
0
Register Data D[7:0] = 01h
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
Figure 12. Serial Readout Timing Diagram
22
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SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013
TYPICAL CHARACTERISTICS: ADS42B49
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
0
FIN = 10 MHz
SFDR = 81.29 dBc
SNR = 71.83 dBFS
SINAD = 70.6 dBFS
THD = 81 dBc
SFDR Non HD2, HD3
= 96.3 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
15
30
45
60
75
90
105
−120
120
Frequency (MHz)
FIN = 170 MHz
SFDR = 83.59 dBc
SNR = 70.94 dBFS
SINAD = 70.2 dBFS
THD = 83 dBc
SFDR Non HD2, HD3
= 88.7 dBc
0
30
45
60
75
90
105
120
Frequency (MHz)
G001
Figure 13. INPUT SIGNAL (10 MHz)
G002
Figure 14. INPUT SIGNAL (170 MHz)
0
0
FIN = 300 MHz
SFDR = 75.25 dBc
SNR = 69.7 dBFS
SINAD = 68 dBFS
THD = 73.2 dBc
SFDR Non HD2, HD3
= 90 dBc
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Two-Tone IMD
= 88.8 dBFS
−10
−20
−30
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
15
−60
−80
−50
−60
−70
−80
−90
−100
−100
−110
−120
0
15
30
45
60
75
90
105
Frequency (MHz)
−120
120
0
G003
Figure 15. INPUT SIGNAL (300 MHz)
15
30
45
60
75
90
105
Frequency (MHz)
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G004
Figure 16. TWO-TONE INPUT SIGNAL
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Two-Tone IMD
= 96.3 dBFS
−10
−20
−30
−20
−30
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−50
−60
−70
−50
−60
−70
−80
−80
−90
−90
−100
−100
−110
−110
−120
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
Two-Tone IMD
= 82.3 dBFS
−10
0
15
30
45
60
75
90
105
−120
120
Frequency (MHz)
0
15
45
60
75
90
105
120
Frequency (MHz)
G005
Figure 17. TWO-TONE INPUT SIGNAL
G006
Figure 18. TWO-TONE INPUT SIGNAL
0
−86
fIN1 = 46 MHz
fIN2 = 50 MHz
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
Two-Tone IMD
= 102 dBFS
−10
−20
−30
−89
−92
Two-Tone IMD (dB)
−40
Amplitude (dBFS)
30
−50
−60
−70
−80
−90
−95
−98
−101
−104
−100
−107
−110
−120
0
15
30
45
60
75
90
105
Frequency (MHz)
−33
−30
−27
−24
−21
−18
−15
−12
−9 −7
Each Tone Amplitude (dBFS)
G007
Figure 19. TWO-TONE INPUT SIGNAL
24
−110
−36
120
G008
Figure 20. TWO-TONE IMD3 vs INPUT AMPLITUDE
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
95
−80
fIN1 = 185 MHz
fIN2 = 190 MHz
−83
90
−86
85
80
−92
SFDR (dBc)
Two-Tone IMD (dB)
−89
−95
−98
75
70
−101
65
−104
60
−107
−110
−36
−33
−30
−27
−24
−21
−18
−15
−12
55
−9 −7
Each Tone Amplitude (dBFS)
100
150
200
250
300
350
400
Input Frequency (MHz)
G010
Figure 22. SPURIOUS-FREE DYNAMIC RANGE vs
INPUT FREQUENCY
72
105
71.5
100
10 MHz
70 MHz
130 MHz
170 MHz
220 MHz
270 MHz
300 MHz
400 MHz
95
71
90
SFDR (dBc)
70.5
SNR (dBFS)
50
G009
Figure 21. TWO-TONE IMD3 vs INPUT AMPLITUDE
70
69.5
69
85
80
75
70
68.5
65
68
67.5
0
60
0
50
100
150
200
250
Input Frequency (MHz)
300
350
400
55
0
0.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Digital Gain (dB)
G011
Figure 23. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY
1
6
G012
Figure 24. SPURIOUS-FREE DYNAMIC RANGE vs
GAIN AND INPUT FREQUENCY
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
130
75.5
10 MHz
70 MHz
130 MHz
170 MHz
72
71
Input Frequency = 40 MHz
220 MHz
270 MHz
300 MHz
400 MHz
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
75
120
74.5
110
74
100
SNR (dBFS)
70
SNR (dBFS)
69
68
67
66
73.5
90
73
80
72.5
70
72
60
71.5
50
71
40
70.5
30
SFDR (dBc, dBFS)
73
65
64
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Digital Gain (dB)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
90
72.5
80
72
70
71.5
60
71
50
70.5
40
70
30
−10
0
20
Amplitude (dBFS)
SNR (dBFS)
73
−20
88
73
87
72.5
86
72
85
71.5
84
71
83
70.5
82
70
81
69.5
1.85
1.87
G015
Figure 27. PERFORMANCE vs INPUT AMPLITUDE
26
20
89
SNR (dBFS)
SFDR (dBc)
73.5
SFDR (dBc, dBFS)
SNR (dBFS)
100
−30
0
74
120
73.5
−40
−10
G014
Input Frequency = 40 MHz
110
−50
−20
Figure 26. PERFORMANCE vs INPUT AMPLITUDE
74
−60
−30
Amplitude (dBFS)
130
69.5
−70
−40
G013
75
74.5
−50
6
Figure 25. SIGNAL-TO-NOISE RATIO vs
GAIN AND INPUT FREQUENCY
Input Frequency = 170 MHz
−60
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1.89
1.91
1.93
1.95
1.97
1.99
Input Common-Mode Voltage (V)
SFDR (dBc)
63
70
−70
80
2.01
G016
Figure 28. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
91
89
89
88
73
87
87
72.5
85
72
83
71.5
81
71
79
70.5
77
70
75
69.5
73
SNR (dBFS)
SFDR (dBc)
SNR (dBFS)
73.5
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2.0 V
AVDD = 2.05 V
86
SFDR (dBc)
Input Frequency = 170 MHz
SFDR (dBc)
74
85
84
83
82
81
69
1.85
1.87
1.89
1.91
1.93
1.95
1.97
1.99
80
71
2.01
Input Frequency = 170 MHz
Input Common-Mode Voltage (V)
79
−40
G017
−15
10
35
60
85
Temperature (°C)
Figure 29. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE
72.5
93
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
AVDD = 2.05 V
AVDD_BUF = 3.15 V
AVDD_BUF = 3.2 V
AVDD_BUF = 3.25 V
AVDD_BUF = 3.3 V
91
71.5
89
71
87
SFDR (dBc)
SNR (dBFS)
72
70.5
70
83
81
69
79
68.5
77
Input Frequency = 170 MHz
−15
10
AVDD_BUF = 3.35 V
AVDD_BUF = 3.4 V
AVDD_BUF = 3.45 V
85
69.5
68
−40
G018
Figure 30. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE AND AVDD SUPPLY
Input Frequency = 170 MHz
35
60
Temperature (°C)
85
75
−40
10
35
60
Temperature (°C)
G019
Figure 31. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE AND AVDD SUPPLY
−15
85
G020
Figure 32. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE AND AVDD_BUF SUPPLY
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
72
89
AVDD_BUF = 3.15 V
AVDD_BUF = 3.2 V
AVDD_BUF = 3.25 V
AVDD_BUF = 3.3 V
71.7
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
88
87
71.1
86
70.8
85
SFDR (dBc)
70.5
70.2
84
83
69.9
82
69.6
81
69.3
80
Input Frequency = 170 MHz
69
−40
−15
10
Input Frequency = 170 MHz
35
60
79
−40
85
Temperature (°C)
−15
10
35
60
85
Temperature (°C)
G021
Figure 33. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE AND AVDD_BUF SUPPLY
G022
Figure 34. SPURIOUS-FREE DYNAMIC RANGE vs
TEMPERATURE AND DRVDD SUPPLY VOLTAGE
88
76
71.6
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
71.3
Input Frequency = 170 MHz
DRVDD = 1.9 V
DRVDD = 1.95 V
DRVDD = 2.0 V
SNR (dBFS)
SFDR (dBc)
75
71
SNR (dBFS)
70.7
SNR (dBFS)
DRVDD = 1.9 V
DRVDD = 1.95 V
DRVDD = 2 V
70.4
70.1
69.8
87
74
86
73
85
72
84
71
83
70
82
69
81
68
80
67
79
SFDR (dBc)
SNR (dBFS)
71.4
AVDD_BUF = 3.35 V
AVDD_BUF = 3.4 V
AVDD_BUF = 3.45 V
69.5
66
0.1
Input Frequency = 170 MHz
69.2
−40
−15
10
35
60
Temperature (°C)
85
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Differential Clock Amplitude (Vpp)
1.9
78
2.1
G024
G023
Figure 35. SIGNAL-TO-NOISE RATIO vs
TEMPERATURE AND DRVDD SUPPLY VOLTAGE
28
0.3
Figure 36. PERFORMANCE vs INPUT CLOCK AMPLITUDE
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
90
75
Input Frequency = 170 MHz
SNR (dBFS)
SFDR (dBc)
74
0
FIN = 40 MHz
SFDR = 78.36 dBc
fCM = 5 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fCM Amplitude = −86 dBFS
fIN + fCM Amplitude = −79.4 dBFS
fIN − fCM Amplitude = −81 dBFS
88
72
84
71
82
70
80
69
78
68
76
67
74
−40
Amplitude (dBFS)
86
SFDR (dBc)
SNR (dBFS)
−20
73
−60
−80
66
40
45
50
55
60
−100
72
−120
Input Clock Duty Cycle (%)
G025
0
15
30
45
60
75
90
105
120
Frequency (MHz)
Figure 37. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
0
0
FIN = 10 MHz
SFDR = 68.2 dBc
fPSRR = 3 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fPSRR Amplitude = −92.4 dBFS
fIN + fPSRR Amplitude = −69.2 dBFS
fIN − fPSRR Amplitude = −69 dBFS
Input Frequency = 40 MHz
50 mVPP Signal Superimposed on VCM
−5
−10
−20
−15
−20
−40
Amplitude (dBFS)
CMRR (dB)
G026
Figure 38. COMMON-MODE REJECTION RATIO PLOT
−25
−30
−35
−40
−60
−80
−45
−50
−100
−55
−60
−65
0
50
100
150
200
250
300
Common-Mode Test Signal Frequency (MHz)
Figure 39. COMMON-MODE REJECTION RATIO vs
TEST SIGNAL FREQUENCY
−120
0
15
30
45
60
75
90
105
Frequency (MHz)
G027
120
G028
Figure 40. POWER-SUPPLY REJECTION RATIO PLOT
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TYPICAL CHARACTERISTICS: ADS42B49 (continued)
At TA = +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
1
−10
0.9
−20
0.8
−30
0.7
Total Power (W)
PSRR (dB)
Input Frequency = 10 MHz
50 mVPP Signal Superimposed on AVDD Supply
−40
−50
0.6
0.5
−60
0.4
−70
0.3
−80
0
50
100
150
200
250
0.2
300
Test Signal Frequency on Supply (MHz)
0
50
150
200
250
Sampling Speed (MSPS)
G029
Figure 41. POWER-SUPPLY REJECTION RATIO vs
TEST SIGNAL FREQUENCY
G030
Figure 42. TOTAL POWER vs SAMPLING FREQUENCY
0.39
0.5
AVDD Power
AVDD_BUF Power
0.45
Default
EN Digital = 1
EN Digital = 1,Offset Correction Enabled
0.36
0.33
0.4
0.3
0.35
0.27
DRVDD Power (W)
Analog Power (W)
100
0.3
0.25
0.2
0.24
0.21
0.18
0.15
0.12
0.15
0.09
0.1
0.06
0.05
0
0.03
0
50
100
150
Sampling Speed (MSPS)
200
250
0
50
100
150
Sampling Speed (MSPS)
G031
Figure 43. ANALOG POWER vs SAMPLING FREQUENCY
30
0
200
250
G032
Figure 44. DIGITAL POWER vs SAMPLING FREQUENCY
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TYPICAL CHARACTERISTICS: Contour
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
250
87
Sampling Frequency (MSPS)
83
79
70
75
65
83
87
200
91
79
83
65
75
70
91
87
91
91
83
83
79
65
70
75
150
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
65
70
75
80
85
90
SFDR (dBc)
Figure 45. SPURIOUS-FREE DYNAMIC RANGE (0-dB Gain)
250
90
84
87
81
78
Sampling Frequency (MSPS)
90
93
93
200
84
87
90
93
78
81
93
93
87
90
84
78
81
150
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
76
78
80
82
84
86
88
90
92
SFDR (dBc)
Figure 46. SPURIOUS-FREE DYNAMIC RANGE (6-dB Gain)
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TYPICAL CHARACTERISTICS: Contour (continued)
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
250
Sampling Frequency (MSPS)
71.4
70.5
70.8
71.1
69.7
70.1
69.3
68.5
68.9
200
71.4
70.8
70.5
70.1
69.7
69.3
68.5
68.9
71.1
71.4
71.1
70.5
70.8
69.7
70.1
69.3
68.5
68.9
68.1
150
0
50
100
150
200
250
300
350
400
70
70.5
71
64.8
64.6
Input Frequency (MHz)
68
69
68.5
69.5
SNR (dBFS)
Figure 47. SIGNAL-TO-NOISE RATIO (0-dB Gain)
250
Sampling Frequency (MSPS)
65.2
65.2
65.4
65
65.4
65.4
65.6
200
65.4
64.6
64.8
65
65.2
65.4
65.4
65.4
65.2
64.8
65
64.6
64.4
150
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
64.2
64.4
64.6
64.8
65
65.2
65.4
SNR (dBFS)
Figure 48. SIGNAL-TO-NOISE RATIO (6-dB Gain)
32
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DEVICE CONFIGURATION
SERIAL REGISTER MAP
Table 10 summarizes the functions supported by the serial interface.
Table 10. Serial Interface Register Map (1)
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
03
0
0
0
0
0
0
HP[0]
0
06
0
0
0
0
0
HP[2]
HP[1]
0
01
LVDS SWING
25
29
CH A GAIN
0
0
2B
0
0
3D
0
0
3F
0
0
0
0
ENABLE
OFFSET
CORR
0
0
0
0
CH B TEST PATTERNS
0
0
0
CUSTOM PATTERN D[13:8]
40
CUSTOM PATTERN D[7:0]
41
LVDS CMOS
42
CMOS CLKOUT STRENGTH
CLKOUT DELAY PROG
0
0
0
0
0
DIS OBUF
0
44
0
0
0
0
0
0
0
EN DIGITAL
45
STBY
LVDS
CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
BA
0
0
0
0
HP[3]
0
0
0
BF
CH A OFFSET PEDESTAL
0
0
0
0
C1
CH B OFFSET PEDESTAL
0
0
0
0
0
0
0
CF
FREEZE
OFFSET
CORR
0
D5
0
0
HP[4}
0
0
0
0
D9
0
0
HP[6]
0
0
0
HP[5]
0
OFFSET CORR TIME CONSTANT
0
0
0
0
LOW SPEED
MODE CH B
HP[11]
0
0
0
HP[10]
0
0
0
0
0
DB
HP[9]
HP[8]
HP[7]
DC
0
0
EF
0
0
0
EN LOW
SPEED MODE
F1
0
0
0
0
0
0
EN LVDS SWING
0
LOW SPEED
MODE CH A
0
0
F2
(1)
DATA FORMAT
CH B GAIN
CH A TEST PATTERNS
0
0
0
0
Multiple functions in a register can be programmed in a single write operation. All registers default to '0' after reset.
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DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
RESET
READOUT
Bits D[7:2]
Always write '0'
Bit D1
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit D0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS
logic levels running from the DRVDD supply. See the Serial Register Readout section.
Register Address 01h (Default = 00h)
D7
D6
D5
D4
D3
D2
LVDS SWING
Bits D[7:2]
D1
D0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350 mV with external 100-Ω termination
011011 = LVDS swing ±410 mV
110010 = LVDS swing ±465 mV
010100 = LVDS swing ±570 mV
111110 = LVDS swing ±200 mV
001111 = LVDS swing ±125 mV
Bits D[1:0]
Always write '0'
Register Address 03h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
HP[0]
0
Bits D[7:2]
Always write '0'
Bit D1
HP[0]
This bit improves SNR in CMOS mode, increases AVDD supply current by approximately 3
mA.
0 = Default after reset
1 = HP[0] is enabled
Bit 0
34
Always write '0'
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Register Address 06h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
HP[2]
HP[1]
0
D1
D0
Bits D[7:3]
Always write '0'
Bits D[2:1]
HP[2:1]
Set bits HP[11:1] for best performance.
00 = Default after reset
11 = HP[2:1] are enabled
Bit D0
Always write '0'
Register Address 25h (Default = 00h)
D7
D6
D5
D4
CH A GAIN
Bits D[7:4]
D3
0
D2
CH A TEST PATTERNS
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5-dB steps for channel A.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit D3
Always write '0'
Bits D[2:0]
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
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Register Address 29h (Default = 00h)
D7
D6
D5
0
0
0
D4
Bits D[7:5]
Always write '0'
Bits D[4:3]
DATA FORMAT: Data format selection
00
01
10
11
Bits D[2:0]
=
=
=
=
D3
DATA FORMAT
D2
D1
D0
0
0
0
D2
D1
D0
Twos complement
Twos complement
Twos complement
Offset binary
Always write '0'
Register Address 2Bh (Default = 00h)
D7
D6
D5
D4
CH B GAIN
Bits D[7:4]
D3
0
CH B TEST PATTERNS
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5-dB steps for channel B.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit D3
Always write '0'
Bits D[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[11:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
36
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Register Address 3Dh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ENABLE OFFSET CORR
0
0
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
ENABLE OFFSET CORR: Offset correction setting
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits D[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
Bits D[7:6]
Always write '0'
Bits D[5:0]
CUSTOM PATTERN D[13:8]
These are the six upper bits of the custom pattern available at the output instead of ADC
data.
The ADS42B49 custom pattern is 14-bit.
Register Address 40h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
Bits D[7:0]
CUSTOM PATTERN D[7:0]
These are the eight lower bits of the custom pattern available at the output instead of ADC
data.
The ADS42B49 custom pattern is 14-bit; use the CUSTOM PATTERN D[13:0] register bits.
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Register Address 41h (Default = 00h)
D7
D6
LVDS CMOS
Bits D[7:6]
D5
D4
CMOS CLKOUT STRENGTH
D3
D2
0
0
D1
D0
DIS OBUF
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits D[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits D[3:2]
Always write '0'
Bits D[1:0]
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output
interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
38
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Register Address 42h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
CLKOUT DELAY PROG
Bits D[7:4]
CLKOUT DELAY PROG
These bits are useful to delay output clock in LVDS mode to optimize setup and hold time.
Typical delay in output clock obtained by these bits in LVDS mode is given below:
0000 = Default
0001 = 190 ps
0010 = 350 ps
0011 = 700 ps
0111 = 1000 ps
1011 = 1250 ps
1111 = 1450 ps
Others = Do not use
Bits D[3:0]
Always write '0'
Register Address 44h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
EN DIGITAL
Bits D[7:1]
Always write '0'
Bit D0
EN DIGITAL: Digital function enable
0 = Default
1 = Digital functions including test pattern are enabled
Register Address 45h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
STBY
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
Bit D7
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wake-up time from this mode is fast (typically 50 µs).
Bit D6
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination
Bit D5
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100-Ω external termination
1 = All LVDS data buffers have double strength to be used with 50-Ω external termination
Bits D[4:3]
Always write '0'
Bit D2
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wake-up time from this mode is slow (typically 100 µs).
Bits D[1:0]
Always write '0'
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Register Address BAh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
HP[3]
0
0
0
D2
D1
D0
0
0
Bits D[7:4]
Always write '0'
Bit D3
HP[3]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[3] is enabled
Bits D[2:0]
Always write '0'
Register Address BFh (Default = 00h)
D7
D6
D5
D4
D3
CH A OFFSET PEDESTAL
Bits D[7:4]
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is
the ADC midcode value. A pedestal can be added to the final converged value by programming
these bits. See the Offset Correction section. Channels can be independently programmed for
different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D[7:2].
Program bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits D[3:0]
40
Always write '0'
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Register Address C1h (Default = 00h)
D7
D6
D5
D4
D3
D2
CH B OFFSET PEDESTAL
Bits D[7:4]
D1
D0
0
0
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is
the ADC midcode value. A pedestal can be added to the final converged value by
programming these bits; see the Offset Correction section. Channels can be independently
programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program Bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits D[3:0]
Always write '0'
Register Address CFh (Default = 00h)
D7
D6
FREEZE OFFSET CORR
0
Bit D7
D5
D4
D3
OFFSET CORR TIME CONSTANT
D2
D1
D0
0
0
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when
frozen, the last estimated value is used for offset correction of every clock cycle. See the Offset
Correction section.
Bit D6
Always write '0'
Bits D[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset
Correction section.
Bits D[1:0]
Always write '0'
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Register Address D5h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HP[4]
0
0
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
HP[4]
Set bits HP[11:1] for best performance.
0 = Default after Reset
1 = HP[4] is enabled
Bits D[4:0]
Always write '0'
Register Address D9h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HP[6]
0
0
0
HP[5]
0
Bits D[7:6]
Always write '0'
Bit D5
HP[6]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[6] is enabled
Bits D[4:2]
Always write '0'
Bit D1
HP[5]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[5] is enabled
Bit D0
Always write '0'
Register Address DBh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
HP[9]
HP[8]
HP[7]
0
0
0
0
LOW SPEED MODE CH B
Bits D[7:5]
HP[9:7]
Bit D5
HP[6]
Set bits HP[11:1] for best performance.
000 = Default after reset
111 = HP[9:7] are enabled
Bits D[4:1]
Always write '0'
Bit D0
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to
'1' before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
42
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Register Address DCh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HP[11]
0
0
0
HP[10]
0
Bits D[7:6]
Always write '0'
Bit D5
HP[11]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[11] is enabled
Bits D[4:2]
Always write '0'
Bit D1
HP[10]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[10] is enabled
Bit D0
Always write '0'
Register Address EFh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
EN LOW SPEED MODE
0
0
0
0
Bits D[7:5]
Always write '0'
Bit D4
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and
LOW SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits D[3:0]
Always write '0'
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Register Address F1h (Default = 00h)
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
Bits D[7:2]
Always write '0'
Bits D[1:0]
EN LVDS SWING: LVDS swing enable
D1
D0
EN LVDS SWING
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
Register Address F2h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
LOW SPEED MODE CH A
0
0
0
Bits D[7:4]
Always write '0'
Bit D3
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to
'1' before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits D[2:0]
44
Always write '0'
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS42B49 belongs to a family of buffered analog input and ultralow-power analog-to-digital converters
(ADCs) with maximum sampling rates up to 250 MSPS. The conversion process is initiated by a rising edge of
the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by
a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock
edge the sample propagates through the pipeline, resulting in a data latency of 11 clock cycles. The output is
available as 14-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary
twos complement format.
ANALOG INPUT
The analog input pins have analog buffers (running off the AVDD_BUF supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 2.5-pF input capacitance). The buffer helps to isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier
than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and
VCM – 0.5 V, resulting in a 2-V PP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured with 50-Ω source
driving 50-Ω termination between INP and INM).
The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 400
MHz (with 2-VPP amplitude) and to approximately 500 MHz (with 1.6-VPP amplitude) before the performance
degrades. This offset is separate from the full-power analog bandwidth of 700 MHz, which is only an indicator of
signal amplitude versus frequency.
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 49, Figure 50, and Figure 51 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The
presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INP_X(1)
RIN
ZIN(2)
CIN
INM_X(1)
(1) X = A or B.
(2) ZIN = RIN || (1/jωCIN).
Figure 49. ADC Equivalent Input Impedance
10
5
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kΩ)
4
1
3
2
1
0.1
0
200
400
600
Frequency (MHz)
800
1000
0
0
G033
Figure 50. ADC Analog Input Resistance (RIN)
Across Frequency
46
200
400
600
Frequency (MHz)
800
1000
G034
Figure 51. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
Example driving circuit configuration is shown in Figure 52. Notice that the board circuitry is simplified compared
to the non-buffered ADS4249.
To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of
back-to-back transformers is recommended, as shown in Figure 52. Note that the drive circuit is terminated by 50
Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required
common-mode voltage.
5W
T2
T1
INP
0.1 mF
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
1:1
5W
Device
Figure 52. Drive Circuit for High Input Frequencies
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 52. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance).
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CLOCK INPUT
The ADS42B49 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 53, Figure 54 and Figure 55. See
Figure 56 details the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
Differential
Sine-Wave
Clock Input
CLKP
RT
Typical LVDS
Clock Input
0.1 mF
100 W
CLKM
Device
0.1 mF
Zo
NOTE: RT = termination resistor, if necessary.
CLKM
Figure 53. Differential Sine-Wave Clock Driving
Circuit
Zo
Device
Figure 54. LVDS Clock Driving Circuit
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 55. LVPECL Clock Driving Circuit
48
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
RESR
100 W
LPKG
2 nH
5 kW
CEQ
2 pF
20 W
CEQ
VCM
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 56. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 57. For best performance, the clock inputs must be driven differentially, thereby
reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
VCM
0.1 mF
CLKM
Device
Figure 57. Single-Ended Clock Driving Circuit
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DIGITAL FUNCTIONS
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device. These
digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with
a latency of 16 clock cycles. Figure 58 shows more details of the processing after the ADC. In order to use any
of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be
programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
14-Bit
ADC
14-Bit
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
Figure 58. Digital Processing Block
GAIN FOR SFDR AND SNR TRADE-OFF
The ADS42B49 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally, as shown in Table 11.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0 dB.
Table 11. Full-Scale Range Across Gains
50
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
Default after reset
1.9
1
Fine, programmable
1.69
2
Fine, programmable
1.51
3
Fine, programmable
1.35
4
Fine, programmable
1.2
5
Fine, programmable
1.07
6
Fine, programmable
0.95
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OFFSET CORRECTION
The ADS42B49 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV.
The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the
correction loop is a function of the sampling clock frequency. The time constant can be controlled using the
OFFSET CORR TIME CONSTANT register bits, as described in Table 12.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
Table 12. Time Constant of Offset Correction Algorithm
(1)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1 / fS
(ms) (1)
0000
1M
4
0001
2M
8
0010
4M
16.7
0011
8M
33.5
0100
16 M
67
0101
32 M
134
0110
64 M
268
0111
128 M
537
1000
256 M
1010
1001
512 M
2150
1010
1G
4300
1011
2G
8600
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
Sampling frequency, fS = 250 MSPS.
POWER-DOWN
The ADS42B49 has two power-down modes: global power-down and channel standby. These modes can be set
using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 13).
Table 13. Power-Down Settings
CTRL1
CTRL2
CTRL3
Low
Low
Low
Default
DESCRIPTION
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Partial power-down
High
Low
High
Channel A powered down, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[10:0] pins
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Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of typically less than 10 mW when the PDN GLOBAL serial register bit is used.
The output buffers are in high-impedance state. The wake-up time from global power-down to data becoming
valid in normal mode is typically 100 µs.
Channel Standby
In this mode, each ADC channel is powered down. The internal references are active, resulting in a quick wakeup time of 50 µs. The total power dissipation in standby is approximately 240 mW at 250 MSPS.
Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1 MSPS. The power dissipation is approximately 190 mW.
DIGITAL OUTPUT INFORMATION
The ADS42B49 provides 14-bit digital data for each channel and an output clock synchronized with the data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel
configuration mode.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 59.
Pins
CLKOUTP
CLKOUTM
DB0_P
LVDS Buffers
DB0_M
DB2_P
DB2_M
DB4_P
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
DB8_P
DB8_M
DB10_P
DB10_M
DB12_P
DB12_M
Output
Clock
Data Bits
D0, D1
Data Bits
D2, D3
Data Bits
D4, D5
Data Bits
D6, D7
Data Bits
D8, D9
Data Bits
D10, D11
Data Bits
D12, D13
Figure 59. LVDS Interface
52
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Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be
used to capture all the data bits, as shown in Figure 60.
CLKOUTM
CLKOUTP
DA0, DB0
D0
D1
D0
D1
DA2, DB2
D2
D3
D2
D3
DA4, DB4
D4
D5
D4
D5
DA6, DB6
D6
D7
D6
D7
DA8, DB8
D8
D9
D8
D9
DA10, DB10
D10
D11
D10
D11
DA12, DB12
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 60. DDR LVDS Interface Timing
LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 61. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
VDIFF
High
Low
OUTP
External
100-W Load
OUTM
VOCM
ROUT
VDIFF
Low
High
NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.
Figure 61. LVDS Buffer Equivalent Circuit
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The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as
shown in Figure 62. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1
100 W
CLKIN2
100 W
CLKOUTP
CLKOUTM
DBnP/M
Receiver Chip # 2
Device
Make LVDS CLKOUT STRENGTH = 1
Figure 62. LVDS Buffer Differential Termination
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Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as
Figure 63 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. TI
recommends minimizing the load capacitance of the data and clock output pins by using short traces to the
receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
¼
¼
DB1
14-Bit ADC Data,
Channel B
DB12
DB13
SDOUT
CLKOUT
DA0
¼
¼
DA1
14-Bit ADC Data,
Channel A
DA12
DA13
Figure 63. CMOS Outputs
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CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal. This relationship is shown by the formula:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[11:0] pins), as
shown in Figure 64. The channel A output pins (DA[11:0]) are in 3-state. Because the output data rate on the DB
bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 125 MSPS).
This mode can be enabled by the CTRL[3:1] parallel pins.
CLKM
Input Clock
CLKP
tPDI
Output Clock
CLKOUT
(1)
Output Data
(Channel B Bus)
Channel A
DAn
(2)
Channel B
DBn
Channel A
(2)
DAn
(2)
(1) In multiplexed mode, the output of both channels comes on the channel B output pins.
(2) Dn = bits D0, D1, D2, and so forth
Figure 64. Multiplexed Mode Timing Diagram
Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 3FFFh for the ADS42B49 in offset binary output format; the output code is 1FFFh
for the ADS42B49 in twos complement output format. For a negative input overdrive, the output code is 0000h in
offset binary output format and 2000h for the ADS42B49 in twos complement output format.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
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Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) x FSideal to (1 + 0.5 / 100) x FSideal.
Offset Error: The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
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Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(3)
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD).
THD = 10Log10
PS
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR): The ratio of the power of the fundamental to the highest other spectral
component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies
f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply
voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC
output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). Crosstalk is
usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. Crosstalk is typically expressed in dBc.
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and
grounding.
Supply Decoupling
Because the ADS42B49 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the
optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed
very close to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
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Routing Analog Inputs
TI advises routing differential analog input pairs (INP_x and INM_x) close to each other. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
should be routed perpendicular to the sampling clock; see the ADS4226 Evaluation Module (SLAU333) for
reference routing. Figure 65 shows a snapshot of the PCB layout from the ADS42xxEVM.
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
ADS42xx
Channel B
Channel A
Clock
Figure 65. ADS42xxEVM PCB Layout
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2012) to Revision B
Page
•
Changed first two sentences in Description of High-Performance Modes table .................................................................. 4
•
Changed footnote for Table 3 ............................................................................................................................................... 9
•
Changed D2 and D1 bit names in address 03h of Table 10 .............................................................................................. 33
•
Changed Register Address 03h .......................................................................................................................................... 34
Changes from Original (December 2012) to Revision A
Page
•
Changed product status from Product Preview to Production Data ..................................................................................... 1
•
Changed Analog Inputs, VID parameter nominal specification in Recommended Operating Conditions table .................... 4
•
Changed Analog Inputs, Maximum analog input frequency parameter rows in Recommended Operating conditions
table ...................................................................................................................................................................................... 4
•
Changed footnote 1 in Recommended Operating Conditions table ..................................................................................... 4
•
Changed PSRR parameter test conditions in Electrical Characteristics: ADS42B49 table .................................................. 6
•
Deleted DNL and INL rows from Electrical Characteristics: ADS42B49 table ..................................................................... 6
•
Changed Analog Inputs, VID parameter typical specification in Electrical Characteristics: General table ............................ 6
•
Deleted Analog Inputs, Analog input common-mode current row from Electrical Characteristics: General table ................ 6
•
Changed DC Accuracy, Offset error parameter typical specification in Electrical Characteristics: General table ............... 6
•
Changed Power Supply, IDRVDD parameter CMOS interface row in Electrical Characteristics: General table ................. 6
•
Changed Power Supply, Digital power, CMOS interface parameter typical specification in Electrical Characteristics:
General table ........................................................................................................................................................................ 6
•
Changed tJ parameter typical specification in Timing Requirements table .......................................................................... 8
•
Deleted Wakeup time maximum specifications in Timing Requirements table .................................................................... 8
•
Changed footnote 1 in Timing Requirements table .............................................................................................................. 8
•
Changed ADC latency, default after reset typical specification in Timing Requirements table ............................................ 8
•
Changed ADC latency parameter typical specification in Timing Requirements table ......................................................... 8
•
Added tPDI specifications to Timing Requirements table ....................................................................................................... 8
•
Updated Figure 4 ................................................................................................................................................................ 11
•
Updated Figure 5 ................................................................................................................................................................ 12
•
Changed CTRL1, CTRL2, and CTRL3 control mode description in Table 4 ..................................................................... 18
•
Changed first column of (5 / 8) AVDD row in Table 6 ........................................................................................................ 19
•
Changed sixth row in Table 7 ............................................................................................................................................. 19
•
Changed third paragraph in the Serial Register Readout section ...................................................................................... 22
•
Changed Register Address 06h in Description of Serial Registers section ........................................................................ 35
•
Filled in TBD in Theory of Operation section ...................................................................................................................... 45
•
Added Analog Input section ................................................................................................................................................ 45
•
Added Figure 49 to Drive Circuit Requirements section ..................................................................................................... 46
•
Changed description of Driving Circuit section ................................................................................................................... 47
•
Changed description of Multiplexed Mode of Operation section ........................................................................................ 56
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Product Folder Links: ADS42B49
61
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS42B49IRGC25
ACTIVE
VQFN
RGC
64
25
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
ADS42B49IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
AZ42B49I
ADS42B49IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
AZ42B49I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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