ATMEL ATWILC1000B-MUT Ieee 802.11 b/g/n link controller soc Datasheet

ATWILC1000B-MUT
IEEE 802.11 b/g/n Link Controller SoC
DATASHEET
Description
Atmel® ATWILC1000B is a single chip IEEE® 802.11b/g/n Radio/Baseband/MAC
link controller optimized for low-power mobile applications. ATWILC1000B
supports single stream 1x1 802.11n mode providing up to 72Mbps PHY rate. The
ATWILC1000B features fully integrated Power Amplifier, LNA, Switch, and Power
Management. Implemented in 65nm CMOS technology, the ATWILC1000B
offers very low power consumption while simultaneously providing high
performance and minimal bill of materials.
The ATWILC1000B supports 2- and 3-wire Bluetooth® coexistence protocols. The
ATWILC1000B provides multiple peripheral interfaces including UART, SPI, I2C,
and SDIO. The only external clock source needed for the ATWILC1000B is a
high-speed crystal or oscillator with a wide range of reference clock frequencies
supported (12-40MHz). The ATWILC1000B is available in both QFN and Wafer
Level Chip Scale Package (WLCSP) packaging.
Features
 IEEE 802.1 b/g/n 20MHz (1x1) solution
 Single spatial stream in 2.4GHz ISM band
 Integrated PA and T/R Switch
 Superior Sensitivity and Range via advanced PHY signal processing
 Advanced Equalization and Channel Estimation
 Advanced Carrier and Timing Synchronization
 Wi-Fi Direct and Soft-AP support
 Supports IEEE 802.11 WEP, WPA, and WPA2 Security
 Supports China WAPI security
 Superior MAC throughput via hardware accelerated two-level A-MSDU/AMPDU frame aggregation and block acknowledgement
 On-chip memory management engine to reduce host load
 SPI, SDIO, UART, and I2C host interfaces
 2- or 3-wire Bluetooth coexistence interface
 Operating temperature range of -40°C to +85°C
 Power save modes:
– <1µA Power Down mode typical @3.3V I/O
– 380µA Doze mode with chip settings preserved (used for beacon monitoring)
– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or host I/O transaction
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Ta bl e of Conte nts
1
Ordering Information and IC Marking ........................................................................ 4
2
Block Diagram ............................................................................................................. 4
3
Pinout and Package Information ................................................................................ 4
3.1
3.2
4
Electrical Specifications ........................................................................................... 11
4.1
4.2
4.3
5
7.3
Features ................................................................................................................................. 16
Description.............................................................................................................................. 16
.............................................................................................................................................. 17
Features ................................................................................................................................. 17
Description.............................................................................................................................. 17
.............................................................................................................................................. 17
Receiver Performance ............................................................................................................ 17
Transmitter Performance ........................................................................................................ 19
I2C Slave Interface .............................................................................................................................. 20
I2C Master Interface ............................................................................................................................ 21
SPI Slave Interface.............................................................................................................................. 22
SPI Master Interface............................................................................................................................ 24
SDIO Slave Interface........................................................................................................................... 25
UART .............................................................................................................................................. 27
Wi-Fi/Bluetooth Coexistence ............................................................................................................... 28
GPIOs .............................................................................................................................................. 28
Power Management ................................................................................................... 29
9.1
9.2
9.3
9.4
2
7.1.1
7.1.2
PHY
7.2.1
7.2.2
Radio
7.3.1
7.3.2
External Interfaces .................................................................................................... 20
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
Processor ............................................................................................................................................ 15
Memory Subsystem............................................................................................................................. 15
Non-volatile Memory (eFuse) .............................................................................................................. 15
WLAN Subsystem ...................................................................................................... 16
7.2
8
Crystal Oscillator ................................................................................................................................. 13
Low-Power Oscillator .......................................................................................................................... 14
CPU and Memory Subsystems ................................................................................. 15
6.1
6.2
6.3
7
Absolute Ratings ................................................................................................................................. 11
Recommended Operating Conditions ................................................................................................. 11
DC Electrical Characteristics ............................................................................................................... 12
Clocking ................................................................................................................... 13
5.1
5.2
6
Pin Description ...................................................................................................................................... 4
Package Description ............................................................................................................................. 7
Power Architecture .............................................................................................................................. 29
Power Consumption ............................................................................................................................ 30
9.2.1 Description of Device States................................................................................................... 30
9.2.2 Current Consumption in Various Device States...................................................................... 30
9.2.3 Restrictions for Power States ................................................................................................. 31
Power-Up/Down Sequence ................................................................................................................. 31
Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 32
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10 Reference Design ...................................................................................................... 33
11 Reflow Profile Information ........................................................................................ 34
11.1 Storage Condition................................................................................................................................ 34
11.1.1 Moisture Barrier Bag Before Opened ..................................................................................... 34
11.1.2 Moisture Barrier Bag Open ..................................................................................................... 34
11.2 Stencil Design ..................................................................................................................................... 34
11.3 Baking Conditions ............................................................................................................................... 34
11.4 Soldering and Reflow Condition .......................................................................................................... 34
11.4.1 Reflow Oven ........................................................................................................................... 34
12 Reference Documentation and Support................................................................... 36
12.1 Reference Documents......................................................................................................................... 36
13 Revision History ........................................................................................................ 37
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1
Ordering Information and IC Marking
Table 1-1.
Ordering Details
Atmel official part number (for ordering)
2
Package type
IC marking
ATWILC1000B-MU-T
5x5 QFN in Tape and Reel
ATWILC1000B
ATWILC1000B-UU-T
3.25x3.25 WLCSP in Tape and Reel
ATWILC1000B
Block Diagram
Figure 2-1.
ATWILC1000B Block Diagram
Vbatt
SDIO
SPI
UART
x2
2
IC
Bluetooth
Coexistance
RTC
Clock
PMU
XO
GPIO
WILC1000B
Host Interface
802.11bgn
Forward
Error
Correction
Microcontroller
802.11bgn
OFDM
Channel
Estimation /
Equalization
Rx
Digital
Core
802.11bgn
MAC
PLL
RAM
802.11bgn
Coding
802.11bgn
iFFT
Pinout and Package Information
3.1
Pin Description
~
Tx
Digital
Core
DPD
3
X
ADC
DAC
X
ATWILC1000B is offered in an exposed pad 40-pin QFN package. This package has an exposed paddle that
must be connected to the system board ground. The QFN package pin assignment is shown in Figure 3-1. The
color shading is used to indicate the pin type as follows:

Green – power

Red – analog

Blue – digital I/O

Yellow – digital input

Grey – unconnected or reserved
The ATWILC1000B pins are described in Table 3-1.
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Figure 3-1.
Pin Assignment
Table 3-1.
Pin Description
Pin #
Pin Name
Pin Type
Description
1
TP_P
Analog
Test Pin/Customer No Connect
2
VDD_RF_RX
Power
Tuner RF Supply (see Section 9.1)
3
VDD_AMS
Power
Tuner BB Supply (see Section 9.1)
4
VDD_RF_TX
Power
Tuner RF Supply (see Section 9.1)
5
VDD_BATT_PPA
Power
PA 1st Stage Supply (see Section 9.1)
6
VDD_BATT_PA
Power
PA 2nd Stage Supply (see Section 9.1)
7
RFIOP
Analog
Pos. RF Differential I/O (see Table 9-3)
8
RFION
Analog
Neg. RF Differential I/O (see Table 9-3)
9
SDIO_SPI_CFG
Digital Input
Tie to 1 for SPI, 0 for SDIO
10
GPIO0/HOST_WAKE
Digital I/O, Programmable Pull-Up
GPIO0/SLEEP Mode Control
11
GPIO2/IRQN
Digital I/O, Programmable Pull-Up
GPIO2/Device Interrupt
12
SD_DAT3
Digital I/O, Programmable Pull-Up
SDIO Data3
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Pin #
Pin Name
Pin Type
13
SD_DAT2/SPI_RXD
Digital I/O, Programmable Pull-Up
SDIO Data2/SPI Data RX
14
VDDC
Power
Digital Core Power Supply (see Section 9.1)
15
VDDIO
Power
Digital I/O Power Supply (see Section 9.1)
16
SD_DAT1/SPI_SSN
Digital I/O, Programmable Pull-Up
SDIO Data1/SPI Slave Select
17
SD_DAT0/SPI_TXD
Digital I/O, Programmable Pull-Up
SDIO Data0/SPI Data TX
18
SD_CMD/SPI_SCK
Digital I/O, Programmable Pull-Up
SDIO Command/SPI Clock
19
SD_CLK
Digital I/O, Programmable Pull-Up
SDIO Clock
20
VBATT_BUCK
Power
Battery Supply for DC/DC Converter (see Section 9.1)
21
VSW
Power
Switching output of DC/DC Converter (see
Section 9.1)
22
VREG_BUCK
Power
Core Power from DC/DC Converter (see Section 9.1)
23
CHIP_EN
Analog
PMU Enable
24
GPIO1/RTC_CLK
Digital I/O, Programmable Pull-Up
GPIO1/32kHz Clock Input
25
TEST_MODE
Digital Input
Test Mode – Customer Tie to GND
26
VDDIO
Power
Digital I/O Power Supply (see Section 9.1)
27
VDDC
Power
Digital Core Power Supply (see Section 9.1)
28
GPIO3
Digital I/O, Programmable Pull-Up
GPIO3/SPI_SCK_Flash
29
GPIO4
Digital I/O, Programmable Pull-Up
GPIO4/SPI_SSN_Flash
30
GPIO5
Digital I/O, Programmable Pull-Up
GPIO5/SPI_TXD_Flash
31
GPIO6
Digital I/O, Programmable Pull-Up
GPIO6/SPI_RXD_Flash
32
I2C_SCL
Digital I/O, Programmable Pull-Up
I2C Slave Clock (high-drive pad, see Table 43)
33
I2C_SDA
Digital I/O, Programmable Pull-Up
I2C Slave Data (high-drive pad, see Table 4-3)
34
RESETN
Digital Input
Active-Low Hard Reset
35
XO_N
Analog
Crystal Oscillator N
36
XO_P
Analog
Crystal Oscillator P
37
VDD_SXDIG
Power
SX Power Supply (see Section 9.1)
38
VDD_VCO
Power
VCO Power Supply (see Section 9.1)
39
VDDIO_A
Power
Tuner VDDIO Power Supply (see Section 9.1)
40
TPN
Analog
Test Pin/Customer No Connect
41(1)
PADDLE VSS
Power
Connect to System Board Ground
Notes: 1.
6
Applies to QFN package only.
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Description
3.2
Package Description
The ATWILC1000B QFN package information is provided in Table 3-2.
Table 3-2.
QFN Package Information
Parameter
Value
Units
Tolerance
Package Size
5x5
mm
±0.1mm
QFN Pad Count
40
Total Thickness
0.85
QFN Pad Pitch
0.40
Pad Width
0.20
±0.05mm
mm
Exposed Pad size
3.7x3.7
The ATWILC1000B 40L QFN package view is shown in Figure 3-2.
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Figure 3-2.
QFN Package
The QFN package is a qualified Green Package.
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Figure 3-3.
WLCSP Package
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Figure 3-4.
10
WLCSP WILC1000B UU
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Electrical Specifications
4.1
Absolute Ratings
Table 4-1.
Absolute Maximum Ratings
Characteristic
Symbol
Min.
Max.
Unit
Core Supply Voltage
VDDC
-0.3
1.5
I/O Supply Voltage
VDDIO
-0.3
5.0
Battery Supply Voltage
VBATT
-0.3
5.0
Digital Input Voltage
VIN
-0.3
VDDIO
Analog Input Voltage
VAIN
-0.3
1.5
ESD Human Body Model
VESDHBM
-1000, -2000
(see notes below)
+1000, +2000
(see notes below)
Storage Temperature
TA
-65
150
V
ºC
Junction Temperature
125
RF input power max
23
Notes:
1.
2.
3.
4.2
dBm
VIN corresponds to all the digital pins.
VAIN corresponds to the following analog pins: VDD_RF_RX, VDD_RF_TX, VDD_AMS, RFIOP, RFION,
XO_N, XO_P, VDD_SXDIG, VDD_VCO.
For VESDHBM, each pin is classified as Class 1, or Class 2, or both:

The Class 1 pins include all the pins (both analog and digital)

The Class 2 pins are all digital pins only

VESDHBM is ±1kV for Class1 pins. VESDHBM is ±2kV for Class2 pins
Recommended Operating Conditions
Table 4-2.
Recommended Operating Conditions
Characteristic
Symbol
Min.
Typ.
Max.
I/O Supply Voltage Low Range
VDDIOL
1.62
1.80
2.00
I/O Supply Voltage Mid-Range
VDDIOM
2.00
2.50
3.00
I/O Supply Voltage High Range
VDDIOH
3.00
3.30
3.60
Battery Supply Voltage
VBATT
2.5A
3.60
4.20
Unit
V
Operating Temperature
Notes:
1.
2.
3.
4.
-40
85
ºC
ATWILC1000B is functional across this range of voltages; however, optimal RF performance is guaranteed
for VBATT in the range 3.0V < VBATT < 4.2V.
I/O supply voltage is applied to the following pins: VDDIO_A, VDDIO.
Battery supply voltage is applied to following pins: VDD_BATT_PPA, VDD_BATT_PA, VBATT_BUCK.
Refer to Section 9.1 and Table 9-3 for the details of power connections.
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4.3
DC Electrical Characteristics
Table 4-3 provides the DC characteristics for the ATWILC1000B digital pads.
Table 4-3.
DC Electrical Characteristics
VDDIO
condition
Characteristic
Min.
Typ.
Max.
Input Low Voltage VIL
-0.30
0.60
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
Unit
VDDIOL
Output Low Voltage VOL
Output High Voltage VOH
0.45
VDDIO-0.50
Input Low Voltage VIL
-0.30
0.63
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
VDDIOM
Output Low Voltage VOL
Output High Voltage VOH
0.45
VDDIO-0.50
Input Low Voltage VIL
-0.30
0.65
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
(up to 3.60)
VDDIOH
Output Low Voltage VOL
Output High Voltage VOH
V
0.45
VDDIO-0.50
All
Output Loading
20
All
Digital Input Load
6
VDDIOL
Pad Drive Strength (regular pads (1))
1.7
2.4
VDDIOM
Pad Drive Strength (regular pads (1))
3.4
6.5
VDDIOH
Pad Drive Strength (regular pads (1))
10.6
13.5
VDDIOL
Pad Drive Strength (high-drive pads (1))
3.4
4.8
VDDIOM
Pad Drive Strength (high-drive pads (1))
6.8
13
VDDIOH
Pad Drive Strength (high-drive pads (1))
21.2
27
pF
Note:
12
1.
mA
The following are high-drive pads: I2C_SCL, I2C_SDA; all other pads are regular.
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5
Clocking
5.1
Crystal Oscillator
Table 5-1.
Crystal Oscillator Parameters
Parameter
Crystal Resonant Frequency
Min.
Typ.
Max.
Unit
12
26
40
MHz
50
150
Ω
Crystal Equivalent Series Resistance
Stability – Initial Offset (1)
-100
100
Stability - Temperature and Aging
-25
25
ppm
Note:
1.
Initial offset must be calibrated to maintain ±25ppm in all operating conditions. This calibration is performed
during final production testing.
The block diagram in Figure 5-1(a) shows how the internal Crystal Oscillator (XO) is connected to the external
crystal. The XO has 5pF internal capacitance on each terminal XO_P and XO_N. To bypass the crystal
oscillator with an external reference, an external signal capable of driving 5pF can be applied to the XO_N
terminal as shown Figure 5-1(b).
Figure 5-1.
XO Connections
External Clock
XO_N
XO_P
XO_N
XO_P
ATWILC1000B
ATWILC1000B
(a)
(b)
(a) Crystal Oscillator is Used
b) Crystal Oscillator is Bypassed
Table 5-2 specifies the electrical and performance requirements for the external clock.
Table 5-2.
Bypass Clock Specification
Parameter
Min.
Max.
Unit
Comments
Oscillation frequency
12
32
MHz
Must be able to drive 5pF load @ desired frequency
Voltage swing
0.5
1.2
Vpp
Must be AC coupled
Stability – Temperature and Aging
-25
+25
ppm
Phase Noise
-130
dBc/Hz
Jitter (RMS)
<1psec
At 10kHz offset
Based on integrated phase noise spectrum from
1kHz to 1MHz
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5.2
Low-Power Oscillator
ATWILC1000B has an internally-generated 32kHz clock to provide timing information for various sleep
functions. Alternatively, ATWILC1000B allows for an external 32kHz clock to be used for this purpose, which is
provided through Pin 24 (RTC_CLK). Software selects whether the internal clock or external clock is used.
The internal low-power clock is ring-oscillator based and has accuracy within 10,000ppm. When using the
internal low-power clock, the advance wakeup time in beacon monitoring mode has to be increased by about
1% of the sleep time to compensate for the oscillator inaccuracy. For example, for the DTIM interval value of 1,
wakeup time has to be increased by 1ms.
For any application targeting very low power consumption, an external 32kHz RTC clock should be used.
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6
CPU and Memory Subsystems
6.1
Processor
ATWILC1000B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as STA and AP modes.
6.2
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data
RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows
the APS3 core to perform various data management tasks on the TX and RX data packets.
Non-volatile Memory (eFuse)
ATWILC1000B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This
non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such
as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other
software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the
same bit map, which is shown in Figure 6-1. The purpose of the first 80 bits in each bank is fixed, and the
remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank
can be programmed independently, this allows for several updates of the device parameters following the initial
programming e.g., updating MAC address. Refer to ATWILC1000B Programming Guide for the eFuse
programming instructions.
Flags
8
Bank 0
F
48
MAC ADDR
7
8
G
15
Used
1
Freq.
Offset
1
TX
Gain
Correc
tion
1
Used
4
MAC ADDR
Used
3
Reserved
1
Invalid
1
eFuse Bit Map
Version
Figure 6-1.
Used
6.3
16
FO
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
128 Bits
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7
WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
7.1.1
Features
The ATWILC1000B IEEE802.11 MAC supports the following functions:

IEEE 802.11b/g/n

IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling

Advanced IEEE 802.11n features:

7.1.2
–
Transmission and reception of aggregated MPDUs (A-MPDU)
–
Transmission and reception of aggregated MSDUs (A-MSDU)
–
Immediate Block Acknowledgement
–
Reduced Interframe Spacing (RIFS)
Support for IEEE 802.11i and WFA security with key management
–
WEP 64/128
–
WPA-TKIP
–
128-bit WPA2 CCMP (AES)

Support for WAPI security

Advanced power management
–
Standard 802.11 Power Save Mode
–
Wi-Fi Alliance WMM-PS (U-APSD)

RTS-CTS and CTS-self support

Supports either STA or AP mode in the infrastructure basic service set mode

Supports independent basic service set (IBSS)
Description
The ATWILC1000B MAC is designed to operate at low power while providing high data throughput. The IEEE
802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a
programmable processor provides optimal power efficiency and real-time response while providing the
flexibility to accommodate evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement data path functions with heavy computational
requirements. For example, a FCS engine checks the CRC of the transmitting and receiving packets, and a
cipher engine performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2
CCMP-AES, and WAPI security requirements.
Control functions which have real-time requirements are implemented using hardwired control logic modules.
These logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX
control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module, aggregation/deaggregation module, block ACK controller (implements the protocol requirements for burst block
communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher
engine, and the DMA interface to the TX/RX FIFOs).
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The MAC functions implemented solely in software on the microprocessor have the following characteristics:

Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing.

Functions with low computational load or without critical real-time requirements. Examples are
authentication and association.

Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling.
7.2
PHY
7.2.1
Features
The ATWILC1000B IEEE802.11 PHY supports the following functions:
7.2.2

Single antenna 1x1 stream in 20MHz channels

Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps

Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps

Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0,
14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps

IEEE 802.11n mixed mode operation

Per packet TX power control

Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and
frame detection
Description
The ATWILC1000B WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication environment
with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC
(Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier
sensing and clear channel assessment, as well as the automatic gain control.
7.3
Radio
7.3.1
Receiver Performance
Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C.
Table 7-1.
Receiver Performance
Parameter
Description
Frequency
Sensitivity
802.11b
Sensitivity
802.11g
Min.
Typ.
2,412
1Mbps DSS
-98
2Mbps DSS
-94
5.5Mbps DSS
-92
11Mbps DSS
-88
6Mbps OFDM
-90
9Mbps OFDM
-89
Max.
Unit
2,484
MHz
dBm
dBm
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Parameter
Sensitivity
802.11n
(BW=20MHz)
Maximum Receive
Signal Level
Adjacent Channel
Rejection
Cellular Blocker
Immunity
18
Description
Min.
Typ.
12Mbps OFDM
-88
18Mbps OFDM
-85
24Mbps OFDM
-83
36Mbps OFDM
-80
48Mbps OFDM
-76
54Mbps OFDM
-74
MCS 0
-89
MCS 1
-87
MCS 2
-85
MCS 3
-82
MCS 4
-77
MCS 5
-74
MCS 6
-72
MCS 7
-70.5
Max.
Unit
dBm
1-11Mbps DSS
-10
0
6-54Mbps OFDM
-10
0
MCS 0 – 7
-10
0
1Mbps DSS (30MHz offset)
50
11Mbps DSS (25MHz offset)
43
6Mbps OFDM (25MHz offset)
40
54Mbps OFDM (25MHz offset)
25
MCS 0 – 20MHz BW (25MHz offset)
40
MCS 7 – 20MHz BW (25MHz offset)
20
776-794MHz CDMA
-14
824-849MHz GSM
-10
880-915MHz GSM
-10
1710-1785MHz GSM
-15
1850-1910MHz GSM
-15
1850-1910MHz WCDMA
-24
1920-1980MHz WCDMA
-24
dBm
dB
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dBm
7.3.2
Transmitter Performance
Radio Performance under Typical Conditions: VBATT=3.6V; VDDIO=3.3V; temp.: 25°C.
Table 7-2.
Transmitter Performance
Parameter
Description
Frequency
Min.
Typ.
2,412
Output Power (1), ON_Transmit
802.11b 1Mbps
19.5
802.11b 11Mbps
20.5
802.11g 6Mbps
19.5
802.11g 54Mbps
17.5
802.11n MCS 0
18.0
802.11n MCS 7
15.5
Max.
Unit
2,484
MHz
dBm
TX Power Accuracy
±1.5 (2)
dB
Carrier Suppression
30.0
dBc
2nd
-33
3rd
-38
Harmonic Output Power
Notes:
1.
2.
dBm/MHz
Measured at 802.11 spec compliant EVM/Spectral Mask.
Measured at RF Pin assuming 50Ω differential.
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8
External Interfaces
ATWILC1000B external interfaces include:

I2C Slave for control

SPI Slave and SDIO Slave for control and data transfer

SPI Master for external Flash

I2C Master for external EEPROM

Two UARTs for debug, control, and data transfer

General Purpose Input/Output (GPIO) pins

Wi-Fi/Bluetooth coexistence interface
With the exception of the SPI Slave and SDIO Slave host interfaces, which are selected using the dedicated
SDIO_SPI_CFG pin, the other interfaces can be assigned to various pins by programming the corresponding
pin MUXing control register for each pin to a specific value between 0 and 6.The default values of these
registers are 0, which is GPIO mode. The summary of the available interfaces and their corresponding pin
MUX settings is shown in Table 8-1. For specific programming instructions, refer to ATWILC1000B
Programming Guide.
Table 8-1.
8.1
Pin-MUX Matrix of External Interfaces
I2C Slave Interface
The I2C Slave interface, used primarily for control by the host processor, is a two-wire serial interface
consisting of a serial data line (SDA, Pin 33) and a serial clock (SCL, Pin 32). It responds to the seven bit
address value 0x60. The ATWILC1000B I2C supports I2C bus Version 2.1 - 2000 and can operate in standard
mode (with data rates up to 100Kb/s) and fast mode (with data rates up to 400Kb/s).
The I2C Slave is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while
the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to
perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”.
The I2C Slave timing is provided in Figure 8-1 and Table 8-2.
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Figure 8-1.
I2C Slave Timing Diagram
tPR
tSUDAT
tHDDAT
tBUF
tSUSTO
SDA
tHL
tLH
tWL
SCL
tLH
tHDSTA
tHL
tWH
tPR
tPR
fSCL
Table 8-2.
tSUSTA
I2C Slave Timing Parameters
Parameter
Symbol
Min.
Max.
Units
400
kHz
SCL Clock Frequency
fSCL
0
SCL Low Pulse Width
tWL
1.3
SCL High Pulse Width
tWH
0.6
SCL, SDA Fall Time
tHL
300
SCL, SDA Rise Time
tLH
300
START Setup Time
tSUSTA
0.6
START Hold Time
tHDSTA
0.6
SDA Setup Time
tSUDAT
100
Remarks
µs
ns
This is dictated by external
components
µs
ns
0
SDA Hold Time
tHDDAT
Master Programming
Option
40
STOP Setup time
tSUSTO
0.6
Bus Free Time Between STOP and START
tBUF
1.3
Glitch Pulse Reject
tPR
0
Slave and Master Default
µs
8.2
50
ns
I2C Master Interface
ATWILC1000B provides an I2C bus master, which is intended primarily for accessing an external EEPROM
memory through a software-defined protocol. The I2C Master is a two-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA can be configured on one of the following pins: SD_CLK (pin
19), GPIO1 (pin 24), GPIO6 (pin 31), or I2C_SDA (pin 33). SCL can be configured on one of the following pins:
GPIO0 (pin 10), SD_DAT3 (pin 12), GPIO4 (pin 29), or I2C_SCL (pin 32). For more specific instructions refer
to ATWILC1000B Programming Guide.
The I2C Master interface supports three speeds:

Standard mode (100kb/s)

Fast mode (400kb/s)

High-speed mode (3.4Mb/s)
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The timing diagram of the I2C Master interface is the same as that of the I2C Slave interface (see Figure 8-1).
The timing parameters of I2C Master are shown in Table 8-3.
Table 8-3.
I2C Master Timing Parameters
Standard Mode
Parameter
Fast Mode
High-Speed Mode
Symbol
Units
Min.
Max.
100
Min.
0
Max.
400
Min.
0
Max.
SCL Clock Frequency
fSCL
0
3400
SCL Low Pulse Width
tWL
4.7
1.3
0.16
SCL High Pulse Width
tWH
4
0.6
0.06
SCL Fall Time
tHLSCL
300
300
10
40
SDA Fall Time
tHLSDA
300
300
10
80
SCL Rise Time
tLHSCL
1000
300
10
40
SDA Rise Time
tLHSDA
1000
300
10
80
START Setup Time
tSUSTA
4.7
0.6
0.16
START Hold Time
tHDSTA
4
0.6
0.16
SDA Setup Time
tSUDAT
250
100
10
SDA Hold Time
tHDDAT
5
40
0
STOP Setup time
tSUSTO
4
0.6
0.16
Bus Free Time Between
STOP and START
tBUF
4.7
1.3
Glitch Pulse Reject
tPR
kHz
µs
ns
ns
µs
ns
8.3
0
70
µs
50
SPI Slave Interface
ATWILC1000B provides a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI Slave
interface can be used for control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in
Table 8-4. The RXD pin is same as Master Output, Slave Input (MOSI), and the TXD pin is same as Master
Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is available
immediately following reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO.
Table 8-4.
SPI Slave Interface Pin Mapping
Pin #
SPI Function
9
CFG: Must be tied to VDDIO
16
SSN: Active Low Slave Select
18
SCK: Serial Clock
13
RXD: Serial Data Receive (MOSI)
17
TXD: Serial Data Transmit (MISO)
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buffered, resulting in a high impedance drive onto the serial master receive line.
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The SPI Slave interface responds to a protocol that allows an external host to read or write any register in the
chip as well as initiate DMA transfers. For the details of the SPI protocol and more specific instructions refer to
ATWILC1000B Programming Guide.
The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock
Phase (CPHA) settings. These modes are illustrated in Table 8-5 and Figure 8-2. The red lines in Figure 8-2
correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.
Table 8-5.
SPI Slave Modes
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
Figure 8-2.
SPI Slave Clock Polarity and Clock Phase Timing
CPOL = 0
SCK
CPOL = 1
SSN
CPHA = 0
RXD/TXD
(MOSI/MISO)
CPHA = 1
z
1
z
2
1
3
2
4
3
5
4
6
5
7
6
8
7
z
8
z
The SPI Slave timing is provided in Figure 8-3 and Table 8-6.
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Figure 8-3.
SPI Slave Timing Diagram
Table 8-6.
SPI Slave Timing Parameters
Parameter
8.4
Symbol
Min.
Max.
Units
48
MHz
Clock Input Frequency
fSCK
Clock Low Pulse Width
tWL
5
Clock High Pulse Width
tWH
5
Clock Rise Time
tLH
5
Clock Fall Time
tHL
5
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
Slave Select Setup Time
tSUSSN
5
Slave Select Hold Time
tHDSSN
5
ns
20
SPI Master Interface
ATWILC1000B provides a SPI Master interface for accessing external Flash memory. The SPI Master pins are
mapped as shown in Table 8-7. The TXD pin is same as Master Output, Slave Input (MOSI), and the RXD pin
is same as Master Input, Slave Output (MISO). The SPI Master interface supports all four standard modes of
clock polarity and clock phase shown in Table 8-5. External SPI Flash memory is accessed by a processor
programming commands to the SPI Master interface, which in turn initiates a SPI master access to the Flash.
For more specific instructions refer to ATWILC1000B Programming Guide.
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Table 8-7.
SPI Master Interface Pin Mapping
Pin #
Pin Name
SPI Function
28
GPIO3
SCK: Serial Clock Output
29
GPIO4
SCK: Active Low Slave Select Output
30
GPIO5
TXD: Serial Data Transmit Output (MOSI)
31
GPIO6
RXD: Serial Data Receive Input (MISO)
The SPI Master timing is provided in Figure 8-4 and Table 8-8.
Figure 8-4.
SPI Master Timing Diagram
fSCK
tLH
tWH
tWL
SCK
tHL
SSN,
TXD
tODLY
tISU
tIHD
RXD
Table 8-8.
SPI Master Timing Parameters
Parameter
8.5
Symbol
Min.
Max.
Units
48
MHz
Clock Output Frequency
fSCK
Clock Low Pulse Width
tWL
5
Clock High Pulse Width
tWH
5
Clock Rise Time
tLH
5
Clock Fall Time
tHL
5
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
ns
5
SDIO Slave Interface
The ATWILC1000B SDIO Slave is a full speed interface. The interface supports the 1-bit/4-bit SD transfer
mode at the clock range of 0-50MHz. The Host can use this interface to read and write from any register within
the chip as well as configure the ATWILC1000B for data DMA. To use this interface, pin 9 (SDIO_SPI_CFG)
must be grounded. The SDIO Slave pins are mapped as shown in Table 8-9.
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Table 8-9.
SDIO Interface Pin Mapping
Pin #
SPI function
9
CFG: Must be tied to ground
12
DAT3: Data 3
13
DAT2: Data 2
16
DAT1: Data 1
17
DAT0: Data 0
18
CMD: Command
19
CLK: Clock
When the SDIO card is inserted into an SDIO aware host, the detection of the card will be via the means
described in SDIO specification. During the normal initialization and interrogation of the card by the host, the
card will identify itself as an SDIO device. The host software will obtain the card information in a tuple (linked
list) format and determine if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it will
be allowed to power up fully and start the I/O function(s) built into it.
The SD memory card communication is based on an advanced 9-pin interface (Clock, Command, four Data,
and three Power lines) designed to operate at maximum operating frequency of 50MHz.
The SDIO Slave interface has the following features:

Meets SDIO card specification version 2.0

Host clock rate variable between 0 and 50MHz

1 bit/4-bit SD bus modes supported

Allows card to interrupt host

Responds to Direct read/write (IO52) and Extended read/write (IO53) transactions

Supports Suspend/Resume operation
The SDIO Slave interface timing is provided in Figure 8-5 and Table 8-10.
Figure 8-5.
SDIO Slave Timing Diagram
fpp
tWL
SD_CLK
tWH
tHL
tLH
tISU
tIH
Inputs
tODLY(MAX)
tODLY(MIN)
Outputs
Table 8-10.
SDIO Slave Timing Parameters
Parameter
26
Symbol
Min.
Max.
Units
50
MHz
Clock Input Frequency
fPP
0
Clock Low Pulse Width
tWL
10
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ns
Parameter
8.6
Symbol
Min.
Max.
Clock High Pulse Width
tWH
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIH
5
Output Delay
tODLY
0
Units
10
14
UART
ATWILC1000B has two Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial
communication: UART1 and UART2. The UARTs are compatible with the RS-232 standard, where
ATWILC1000B operates as Data Terminal Equipment (DTE).
UART1 has a 2-pin interface without flow control (RXD/TXD), where RXD (received data) can be enabled on
one of five alternative pins and TXD (transmitted data) can be enabled on one of seven alternative pins by
programming their corresponding pin MUX control registers (see Table 8-1). UART2 has a 4-pin interface with
flow control (RXD/TXD/CTS/RTS), where RXD (received data) can be enabled on one of two alternative pins,
TXD (transmitted data) can be enabled on one of two alternative pins, CTS (clear to send) can be enabled on
one of two alternative pins, and RTS (request to send) can be enabled on one of two alternative pins by
programming their corresponding pin MUX control registers (see Table 8-1).
The RTS and CTS are used for hardware flow control; they MUST be connected to
the host MCU UART and enabled for the UART interface to be functional.
Both UARTs feature programmable baud rate generation with fractional clock division, which allows
transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is
selectable between XO×2, XO, XO÷2, and XO÷4, which corresponds to 52MHz, 26MHz, 13MHz, and 6.5MHz
for the typical XO frequency (26MHz). The clock divider value is programmable as 13 integer bits and 3
fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the
maximum baud rate of 52MHz/8.0 = 6.5MBd for typical XO frequency.
Both UARTs can be configured for seven or eight bit operation, with or without parity, with four different parity
types (odd, even, mark, or space), and with one or two stop bits. They also have RX and TX FIFOs, which
ensure reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both RX
and TX direction. The UARTs also have status registers showing the number of received characters available
in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits.
UART2 supports standard flow control using CTS and RTS signals – UART2 can be programmed to enable or
disable flow control. CTS is an active low input. When it is asserted (low) UART2 will transmit data; when it
becomes de-asserted (high) UART2 will finish transmitting the current byte (if it is in progress) and will not
resume transmitting until CTS becomes asserted again. RTS is an active low output. It becomes asserted (low)
when the RX FIFO in UART2 has space; it becomes de-asserted (high) when there is not enough space in the
RX FIFO.
An example of UART receiving or transmitting a single packet is shown in Figure 8-6. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
For more specific instructions refer to ATWILC1000B Programming Guide.
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Figure 8-6.
8.7
Example of UART RX or TX Packet
Wi-Fi/Bluetooth Coexistence
ATWILC1000B supports 2-wire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE
802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2 or 3 wire) is chosen to be
compatible with the specific Bluetooth device used in a given application. Coexistence interface can be
enabled on several alternative pins by programming their corresponding pin MUX control register to 6 (see
Table 8-1, where any pin marked “IO_COE” in the “Mux6” column can be configured for any function of the
coexistence interface). Table 8-11 shows a usage example of the 2-wire interface using the GPIO3 and GPIO4
pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5 pins; for more specific instructions on configuring
Coexistence refer to ATWILC1000B Programming Guide.
Table 8-11.
Pin name
8.8
Coexistence Pin Assignment Example
Pin #
Function
Target
2-wire
3-wire
GPIO3
28
BT_Req
BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot
Used
Used
GPIO4
29
WL_Act
Device response to the BT request.
High - BT_req is denied and BT slot blocked.
Used
Used
GPIO5
30
BT_Pri
Priority of the BT packets in the requested slot.
High to indicate high priority and low for normal.
Not Used
Used
GPIO6
31
Ant_SW
Direct control on Antenna (coex bypass)
Optional
Optional
GPIOs
Nine General Purpose Input/Output (GPIO) pins, labeled GPIO 0-8, are available to allow for application
specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read by the host
or internal processor) or as an output (the output values can be programmed by the host or internal processor),
where the default mode after power-up is input. GPIOs 7 and 8 are only available when the host does not use
the SDIO interface, which shares two of its pins with these GPIOs. Therefore, for SDIO-based applications,
seven GPIOs (0-6) are available. For more specific usage instructions refer to ATWILC1000B Programming
Guide.
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9
Power Management
9.1
Power Architecture
ATWILC1000B uses an innovative power architecture to eliminate the need for external regulators and reduce
the number of off-chip components. This architecture is shown in Figure 9-1. The Power Management Unit
(PMU) has a DC/DC Converter that converts VBATT to the core supply used by the digital and RF/AMS blocks.
Table 9-1 shows the typical values for the digital and RF/AMS core voltages. The PA and eFuse are supplied
by dedicated LDOs, and the VCO is supplied by a separate LDO structure.
Figure 9-1.
Power Architecture
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Table 9-1.
PMU Output Voltages
Parameter
Typical
RF/AMS Core Voltage (VREG_BUCK)
1.35V
Digital Core Voltage (VDDC)
1.10V
The power connections in Figure 9-1 provide a conceptual framework for understanding the ATWILC1000B
power architecture. Refer to the reference design for an example of power supply connections, including
proper isolation of the supplies used by the digital and RF/AMS blocks.
9.2
Power Consumption
9.2.1
Description of Device States
ATWILC1000B has several Devices States:

ON_Transmit – Device is actively transmitting an 802.11 signal. Highest output power and nominal
current consumption

ON_Receive – Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal current
consumption

ON_Doze – Device is on but is neither transmitting nor receiving

Power_Down – Device core supply off (Leakage)
The following pins are used to switch between the ON and Power_Down states:

CHIP_EN – Device pin (pin #23) used to enable DC/DC Converter

VDDIO – I/O supply voltage from external supply
In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between the ON
states and Power_Down state CHIP_EN has to change between high and low (GND) voltage. When VDDIO is
off and CHIP_EN is low, the chip is powered off with no leakage (also see Section 9.2.3).
9.2.2
Current Consumption in Various Device States
Table 9-2.
Current Consumption
Device State
Code Rate
Output
Power, dBm
Current Consumption (1)
IVBATT
IVDDIO
802.11b 1Mbps
19.5
294mA
22mA
802.11b 11Mbps
20.5
290mA
22mA
802.11g 6Mbps
19.5
292mA
22mA
802.11g 54Mbps
17.5
250mA
22mA
802.11n MCS 0
18.0
289mA
22mA
802.11n MCS 7
15.5
244mA
22mA
802.11b 1Mbps
N/A
52.5mA
22mA
802.11b 11Mbps
N/A
52.5mA
22mA
802.11g 6Mbps
N/A
55.0mA
22mA
802.11g 54Mbps
N/A
57.5mA
22mA
802.11n MCS 0
N/A
54.0mA
22mA
ON_Transmit
ON_Receive
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Device State
Output
Power, dBm
Current Consumption (1)
IVBATT
IVDDIO
802.11n MCS 7
N/A
58.5mA
22mA
ON_Doze
N/A
N/A
380µA
<10µA
Power_Down
N/A
N/A
<0.5µA
<0.2µA
Note:
9.2.3
Code Rate
1.
Conditions: VBATT @3.6v, VDDIO @2.8V, 25°C
Restrictions for Power States
When no power supplied to the device, for example, the DC/DC Converter output and VDDIO are both off (at
ground potential), a voltage cannot be applied to the device pins because each pin contains an ESD diode
from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must
be on, so the SLEEP or Power_Down state must be used.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
9.3
Power-Up/Down Sequence
The power-up/down sequence for ATWILC1000B is shown in Figure 9-2. The timing parameters are provided
in Table 9-3.
Figure 9-2.
Power Up/Down Sequence
VBATT
tA
t A'
VDDIO
tB
t B'
CHIP_EN
tC
t C'
RESETN
XO Clock
Table 9-3.
Power-Up/Down Sequence Timing
Parameter
Min.
tA
0
Max.
Unit
Description
Notes
VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously
or can be tied together. VDDIO must not rise
before VBATT.
VDDIO rise to CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not left
floating.
ms
tB
0
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9.4
Parameter
Min.
Max.
Unit
Description
Notes
tC
5
CHIP_EN rise to RESETN
rise
This delay is needed because XO clock must
stabilize before RESETN removal. RESETN
must be driven high or low, not left floating.
tA
0
VDDIO fall to VBATT fall
VBATT and VDDIO can fall simultaneously or
can be tied together. VBATT must not fall before VDDIO.
tB
0
CHIP_EN fall to VDDIO fall
VDDIO must not fall before CHIP_EN.
CHIP_EN and RESETN can fall simultaneously.
tC
0
RESETN fall to VDDIO fall
VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously.
Digital I/O Pin Behavior during Power-Up Sequences
The following table represents digital I/O Pin states corresponding to device power modes.
Table 9-4.
Digital I/O Pin Behavior in Different Device States
Device State
CHIP_EN
RESETN
Output Driver
Input Driver
Pull Up/Down
Resistor (96kΩ)
Power_Down:
core supply off
High
Low
Low
Disabled (HiZ)
Disabled
Disabled
Power-On Reset:
core supply on, hard
reset on
High
High
Low
Disabled (HiZ)
Disabled
Enabled
Power-On Default:
core supply on, device out
of reset but not
programmed yet
High
High
High
Disabled (HiZ)
Enabled
Enabled
High
Programmed
by firmware
for each pin:
Enabled or
Disabled
Opposite of
Output
Driver state
Programmed by
firmware for
each pin:
Enabled or
Disabled
On_Doze/
On_Transmit/
On_Receive:
core supply on, device programmed by firmware
32
VDDIO
High
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High
DNI
C22
0
Antenna Matching
Network. Place
right next to antenna
DNI
C21
L2
E1
ANTENNA
Low Pass Filter
For Harmonics
0.5pF
R2
L3
DNI
R3
2.0nH
L9
C17
L8
C32
3.3nH
7
8
6.8pF
Y1
26MHz
Values Shown are initial v alues
f or cry stal CL=8pF
but must be adjusted f or each
board design.
C16
C15
35
36
9
25
VDDIO
0.7pF
C33
6.8pF
6.8pF
6.8pF
24
C24
C23
1
40
External 32.768KHz clock may
be used instead of on chip sleep
clock. (Use RTC pin).
3.3nH
1.0pF
1.0pF
0.01uF
C1
FB2
BLM03AG121SN1
2
C2 2.2uF
2
4
3
37
38
ATWILC1000
XO_N
XO_P
RTC_MUX
SDIO_SPI_CFG
TEST_MODE
RFIOP
RFION
TPP
TPN
U1
Place C1 next to pins 2 & 4.
Place C19 next to pin 38.
1
C11 2.2uF
VDDIO
VDDC
2
1
FB3
VBAT
C4 0.1uF
C7 1.0uF
VREG_BUCK
VSW
CHIP_EN
RESETN
Wake
GPIO_6
GPIO_5
GPIO_4
GPIO_3
SD_DAT3
SD_DAT2_SPI_RXD
SD_DAT1_SPI_SSN
SD_DAT0_SPI_TXD
SD_CMD_SPI_SCK
SD_CLK
IRQN
I2C_SCL
I2C_SDA
2.2uF
6.3V
C3
BLM03AG121SN1
22
21 L5
23
34
10
31
30
29
28
12
13
16
17
18
19
11
32
33
VDDIO
Place C4, C5 and C6
next to pins 15, 26 & 39
R20
4.7K
15nH L1
0
0
0
0
0
0
0
0
0
0
VDDC
RxD
TxD
1uH
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SD_CMD
SD_CLK
IRQN
I2C_SCL
I2C_SDA
Place C8 & C12
next to pins 14 & 27
L5 = 15nH is required in
series with L1 = 1uH to
reduce switching noise
RF interf erence.
R16
R17
R18
R19
4.7K
VDDIO
R12
R6
R8
R5
R13
R14
R11
C5 0.1uF
Place C2 next to pin 3.
Place C11 next to pin 37.
C6 0.1uF
FB1
BLM03AG121SN1
2
1
C8 2.2uF
1P3V
C19 0.1uF
VDDRF_RX
VDD_RF_TX
VDD_AMS
VDD_SXDIG
VDD_VCO
39
15
26
VDDIO_A
VDDIO_0
VDDIO_1
VSS
27
14
VDDC2
VDDC1
5
6
VBAT_PPA
VBAT_PA
20
VBat_buck
VDDIO
VBAT
2.2uF
6.3V
C10
1P3V
WLAN_Wake required
if UART is the only
host interf ace used.
If SPI or SDIO is used,
Wake pin is not required
and should be lef t
unconnected.
Chip_En
Reset_n
WLAN_Wake
Connect Chip_En and
Resetn to host GPIO
pins that def ault low or
high impedance with a
pull down resistor
at power on.
0 Ohm resistors are
placeholders in case
f ilter resistors are required
to reduce RF noise.
VDDIO
VBAT
Figure 10-1.
41
C12 2.2uF
10
Reference Design
The ATWILC1000B reference design schematic is shown in Figure 10-1.
ATWILC1000B Reference Schematic
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11
Reflow Profile Information
This section provides guidelines for reflow processes in getting the Atmel module soldered to the customer’s
design.
11.1
Storage Condition
11.1.1 Moisture Barrier Bag Before Opened
A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product shall be 12 months from the date the bag is sealed.
11.1.2 Moisture Barrier Bag Open
Humidity indicator cards must be blue, <30%.
11.2
Stencil Design
The recommended stencil is laser-cut, stainless-steel type with thickness of 100µm to 130µm and
approximately a 1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taper with
bottom opening 25µm larger than the top can be utilized. Local manufacturing experience may find other
combinations of stencil thickness and aperture size to get good results.
11.3
Baking Conditions
This module is rated at MSL level 3. After sealed bag is opened, no baking is required within 168 hours so long
as the devices are held at ≤30oC/60% RH or stored at <10% RH.
The module will require baking before mounting if:
11.4

The sealed bag has been open for >168 hours

Humidity Indicator Card reads >10%

SIPs need to be baked for 8 hours at 125°C
Soldering and Reflow Condition
11.4.1 Reflow Oven
It is strongly recommended that a reflow oven equipped with more heating zones and Nitrogen atmosphere be
used for lead-free assembly. Nitrogen atmosphere has shown to improve the wet-ability and reduce
temperature gradient across the board. It can also enhance the appearance of the solder joints by reducing the
effects of oxidation.
The following bullet items should also be observed in the reflow process:
34

Some recommended pastes include NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5
Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, no clean paste

Allowable reflow soldering times: 2 times based on the following reflow soldering profile (see Figure 111)

Temperature profile: Reflow soldering shall be done according to the following temperature profile (see
Figure 11-1)

Peak temp: 250°C
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Figure 11-1.
Solder Reflow Profile
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12
Reference Documentation and Support
12.1
Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
The following list of documents available on Atmel web or integrated into development tools.
To enable fast development contact your local FAE or visit the http://www.atmel.com/.
Title
Content
Datasheet
This Document
Design Files Package
User Guide, Schematic, PCB layout, Gerber, BOM & System notes on: RF/Radio Full
Test Report, radiation pattern, design guide-lines, temperature performance, ESD.
Platform Getting started
Guide
How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick
start guidelines.
HW Design Guide
Best practices and recommendations to design a board with the product, Including:
Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance
matching, using a power amplifier, etc.), SPI/UART protocol between Wi-Fi SoC and the
Host MCU.
SW Design Guide
Integration guide with clear description of: High level Arch, overview on how to write a
networking application, list all API, parameters and structures.
Features of the device, SPI/handshake protocol between device and host MCU, flow/sequence/state diagram and timing.
SW Programmer Guide
Explain in details the flow chart and how to use each API to implement all generic use
cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample App
note.
For a complete listing of development-support tools and documentation, visit http://www.atmel.com/, or contact
the nearest Atmel field representative.
36
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13
Revision History
Doc Rev.
42491B
42491A
Date
Comments
03/2016
1.
2.
3.
4.
5.
6.
Update package drawings in figures Figure 3-2 and Figure 3-3.
Clarified the datapath description in Section 7.1.2.
Revise Transmit Power table values in Table 7-2.
Updated power consumption table values in Table 9-2.
Updated Schematic figure to Rev 2 in Figure 10-1.
Include Reflow Profile data in Chapter 11.
07/2015
DS update to RevB offering
Changes from WILC1000A (42351C) to WILC1000B:
1. Added second UART, increased UART data rates
2. Increased instruction RAM size from 128KB to 160KB
3. Updated pin MUX table: added new options for various interfaces
4. Improved description of Coexistence interface
5. Added VDD_VCO switch and connection in the power architecture
6. Updated power consumption numbers
7. Updated reference schematic
8. Changed RTC_CLK pad definition from pull-down to pull-up
9. Modified sections 9.2.1 and 9.2.2 to add high-power and low-power modes and current consumption numbers
10. Updated radio performance in Table 7-1 and Table 7-2
11. Fixed typos for SPI Slave interface timing in Table 8-6
12. Fixed typos for battery supply name: changed from VBAT to VBATT
13. Corrected Table 8-11
14. Corrected Doze mode current in Table 9-2 and in feature list
15. Corrected Table 4-3 and added high-drive pads reference in Table 3-1
16. Miscellaneous minor updates and corrections
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