AD ADSP-BF504F Blackfin embedded processor Datasheet

Blackfin
Embedded Processor
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
FEATURES
PERIPHERALS
Up to 400 MHz high-performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a range of supply voltages for internal and I/O operations. See Processor — Operating Conditions on Page 25
Internal 32M bit flash (available on ADSP-BF504F and
ADSP-BF506F processors)
Internal ADC (available on ADSP-BF506F processor)
Off-chip voltage regulator interface
88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504
and ADSP-BF504F processors
120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F
processor
Two 32-bit up/down counters with rotary support
Eight 32-bit timers/counters with PWM support
Two three-phase 16-bit center-based PWM units
Two dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
Two Serial Peripheral Interface (SPI) compatible ports
Two UARTs with IrDA® support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
Internal ADC with 12 channels, 12 bits, and up to 2 MSPS
ADC controller module (ACM), providing a glue-less interface
between Blackfin processor and internal or external ADC
Controller Area Network (CAN) controller
Two-wire interface (TWI) controller
12 peripheral DMAs
Two memory-to-memory DMA channels
Event handler with 52 interrupt inputs
35 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
68K bytes of L1 SRAM (processor core-accessible) memory:
(See Table 1 on Page 3 for L1 and L3 memory size details)
External (interface-accessible) memory controller with glueless support for internal 32M bit flash and boot ROM
Flexible booting options from internal flash and SPI memory
or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
COUNTER1–0
WATCHDOG TIMER
VOLTAGE REGULATOR INTERFACE
JTAG TEST AND EMULATION
B
PERIPHERAL
PWM 1–0
ACCESS BUS
SPORT1–0
INTERRUPT
CONTROLLER
SPI1–0
PORT G
UART1–0
L1 DATA
MEMORY
DMA
CONTROLLER
16
DCB
PPI
DMA
ACCESS
BUS
DEB
32M BIT
FLASH
PORT F
PORT H
L1 INSTRUCTION
MEMORY
EAB
GPIO
TIMER7–0
MEMORY PORT
FLASH CONTROL
RSI
ACM
ADC
CAN
BOOT
ROM
TWI
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2010 Analog Devices, Inc. All rights reserved.
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
TABLE OF CONTENTS
Features ................................................................. 1
ADC and ACM Interface ....................................... 18
Memory ................................................................ 1
Internal ADC ..................................................... 19
Peripherals ............................................................. 1
ADC Application Hints ........................................ 20
Table Of Contents .................................................... 2
Related Documents .............................................. 20
Revision History ...................................................... 2
Signal Descriptions ................................................. 21
General Description ................................................. 3
Processor — Specifications ....................................... 25
Portable Low-Power Architecture ............................. 3
Processor — Operating Conditions .......................... 25
System Integration ................................................ 3
Processor — Electrical Characteristics ...................... 27
Processor Peripherals ............................................. 3
Processor — Absolute Maximum Ratings .................. 30
Blackfin Processor Core .......................................... 4
ESD Sensitivity ................................................... 30
Memory Architecture ............................................ 5
Package Information ............................................ 30
Flash Memory ...................................................... 9
Processor — Timing Specifications .......................... 31
DMA Controllers .................................................. 9
Processor — Output Drive Currents ........................ 49
Watchdog Timer .................................................. 9
Processor — Test Conditions ................................. 50
Timers ............................................................... 9
Processor — Environmental Conditions ................... 52
Up/Down Counters and Thumbwheel Interfaces ........ 10
Flash Program and Erase Times and Endurance Cycles .... 53
3-phase PWM Units ............................................ 10
Flash – Absolute Maximum Ratings ............................ 53
Serial Ports ........................................................ 10
ADC — Specifications ............................................. 54
Serial Peripheral Interface (SPI) Ports ...................... 11
ADC — Timing Specifications ................................ 56
UART Ports (UARTs) .......................................... 11
ADC — Absolute Maximum Ratings ........................ 57
Parallel Peripheral Interface (PPI) ........................... 11
ADC — Typical Performance Characteristics ............. 57
RSI Interface ...................................................... 12
ADC — Terminology ........................................... 60
Controller Area Network (CAN) Interface ................ 12
ADC — Theory of Operation ................................. 61
TWI Controller Interface ...................................... 13
ADC — Modes of Operation .................................. 67
Ports ................................................................ 13
ADC — Serial Interface ........................................ 70
Dynamic Power Management ................................ 13
120-Lead LQFP Lead assignment ............................... 72
ADSP-BF50x Voltage Regulation ............................ 15
88-Lead LFCSP Lead assignment ................................ 75
Clock Signals ..................................................... 15
Outline Dimensions ................................................ 78
Booting Modes ................................................... 16
Surface Mount Design .......................................... 79
Instruction Set Description ................................... 17
Ordering Guide ..................................................... 79
Development Tools ............................................. 17
Designing an Emulator-Compatible
Processor Board (Target) ................................... 17
REVISION HISTORY
Updated specifications (reference PCN 09_0173) in the Clock
and Reset Timing section to accurately describe processor coldstartup/reset timing ..................................................31
1/10—Rev. PrB to Rev. PrC
Numerous small corrections and additions to document.
Major changes/additions include:
Revised all timing diagrams for clarity/consistency in Processor
— Timing Specifications .......................................... 31
Rev. PrC
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor's product page
on the www.analog.com website and use the View PCN link.
| Page 2 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
GENERAL DESCRIPTION
The ADSP-BF50x processors are members of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The ADSP-BF50x processors are completely code compatible
with other Blackfin processors. ADSP-BF50x processors offer
performance up to 400 MHz and reduced static power consumption. Differences with respect to peripheral combinations
are shown in Table 1.
Table 1. Processor Comparison
Memory (bytes)
ADSPFeature
BF504
Up/Down/Rotary Counters
2
Timer/Counters with PWM
8
3-Phase PWM Units
2
SPORTs
2
SPIs
2
UARTs
2
Parallel Peripheral Interface
1
Removable Storage Interface
1
CAN
1
TWI
1
Internal 32M Bit Flash
–
ADC Control Module (ACM)
1
Internal ADC
–
GPIOs
35
L1 Instruction SRAM
16K
L1 Instruction SRAM/Cache
16K
L1 Data SRAM
16K
L1 Data SRAM/Cache
16K
L1 Scratchpad
4K
L3 Boot ROM
4K
Maximum Speed Grade1
Maximum System Clock Speed
Package Options
88-Lead
LFCSP
1
ADSPADSPBF504F BF506F
2
2
8
8
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
–
1
35
35
16K
16K
16K
16K
16K
16K
16K
16K
4K
4K
4K
4K
400 MHz
100 MHz
88-Lead 120-Lead
LFCSP
LQFP
Maximum speed grade is not available with every possible SCLK selection.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. PrC
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low-power and
low-voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF50x processors are highly integrated system-on-achip solutions for the next generation of embedded industrial,
instrumentation, and power/motion control applications. By
combining industry-standard interfaces with a high-performance signal processing core, cost-effective applications can be
developed quickly, without the need for costly external components. The system peripherals include a watchdog timer; two
32-bit up/down counters with rotary support; eight 32-bit timers/counters with PWM support; six pairs of three-phase 16-bit
center-based PWM units; two dual-channel, full-duplex synchronous serial ports (SPORTs); two serial peripheral interface
(SPI) compatible ports; two UARTs with IrDA support; a parallel peripheral interface (PPI); a removable storage interface
(RSI) controller; an internal ADC with 12 channels, 12 bits, up
to 2 MSPS, and ACM controller; a controller area network
(CAN) controller; a two-wire interface (TWI) controller; and an
internal 32M bit flash.
PROCESSOR PERIPHERALS
The ADSP-BF50x processors contain a rich set of peripherals
connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall
system performance (see the block diagram on Page 1). These
Blackfin processors contain high-speed serial and parallel ports,
an interrupt controller for flexible management of interrupts
from the on-chip peripherals or external sources, and power
management control functions to tailor the performance and
power characteristics of the processor and system to many
application scenarios.
The SPORT, SPI, UART, PPI, and RSI peripherals are supported by a flexible DMA structure. There are also separate
memory DMA channels dedicated to data transfers between the
processor’s various memory spaces, including boot ROM and
internal 32M bit synchronous burst flash. Multiple on-chip
buses running at up to 100 MHz provide enough bandwidth to
keep the processor core running along with activity on all of the
on-chip and external peripherals.
The ADSP-BF50x processors include an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
| Page 3 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
BLACKFIN PROCESSOR CORE
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
40
A0
32
40
A1
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. PrC
| Page 4 of 80 | January 2010
LOOP BUFFER
CONTROL
UNIT
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The second core-accessible memory block is the L1 data memory, consisting of 32K bytes of SRAM, of which 16K bytes may
be configured as cache. This memory block is accessed at full
processor speed.
The third memory block is 4K bytes of scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
0xFFFF FFFF
CORE MEMORY MAPPED REGISTERS
0xFFE0 0000
SYSTEM MEMORY MAPPED REGISTERS
0xFFC0 0000
RESERVED
0xFFB0 1000
INTERNAL SCRATCHPAD RAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000
RESERVED
0xFFA0 8000
L1 INSTRUCTION SRAM/CACHE (16K BYTES)
0xFFA0 4000
L1 INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF80 8000
L1 DATA BANK A SRAM/CACHE (16K BYTES)
0xFF80 4000
L1 DATA BANK A SRAM (16K BYTES)
0xFF80 0000
RESERVED
0xEF00 1000
BOOT ROM (4K BYTES)
0xEF00 0000
RESERVED
0x2040 0000
SYNC FLASH (32M BITS) *
0x2000 0000
MEMORY ARCHITECTURE
RESERVED
0x0000 0000
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency core-accessible memory
as cache or SRAM, and larger, lower-cost and performance
interface-accessible memory systems. See Figure 3.
The core-accessible L1 memory system is the highest-performance memory available to the Blackfin processor. The
interface-accessible memory system, accessed through the
external bus interface unit (EBIU), provides access to the internal flash memory and boot ROM.
The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory, providing high-bandwidth access to the core.
Rev. PrC
INTERNAL
(CORE-ACCESSIBLE)
MEMORY MAP
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
EXTERNAL
(INTERFACE-ACCESSIBLE)
MEMORY MAP
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The data memory holds data,
and a dedicated scratchpad data memory stores stack and local
variable information.
* AVAILABLE ON PARTS WITH SYNC FLASH (F)
Figure 3. Internal/External Memory Map
External (Interface-Accessible) Memory
External memory is accessed via the EBIU memory port. This
16-bit interface provides a glueless connection to the internal
flash memory and boot ROM. Internal flash memory ships from
the factory in an erased state except for block 0 of the parameter
bank. Block 0 of the Flash memory parameter bank ships from
the factory in an unknown state. An erase operation should be
performed prior to programming this block.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor and emulation
modes and appear as reserved space to on-chip peripherals.
| Page 5 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Booting
Table 2. Core Event Controller (CEC)
The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 16.
Event Handling
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated either by the software watchdog timer, by the
NMI input signal to the processor, or by software. The
NMI event is frequently used as a power-down indicator to
initiate an orderly shutdown of the system.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
registers (SIC_IARx). Table 3 describes the inputs into the SIC
and the default mappings into the CEC.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, an interrupt service routine (ISR) must
save the state of the processor to the supervisor stack.
The processor event controller consists of two stages: the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. Table 2
describes the inputs to the CEC, identifies their names in the
event vector table (EVT), and lists their priorities.
Rev. PrC
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
| Page 6 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Source
General Purpose
Interrupt (at Reset)
Peripheral Interrupt ID
Default Core
Interrupt ID
SIC Registers
PLL Wakeup Interrupt
IVG7
0
0
IAR0
IMASK0, ISR0, IWR0
DMA Error (generic)
IVG7
1
0
IAR0
IMASK0, ISR0, IWR0
PPI Status
IVG7
2
0
IAR0
IMASK0, ISR0, IWR0
SPORT0 Status
IVG7
3
0
IAR0
IMASK0, ISR0, IWR0
SPORT1 Status
IVG7
4
0
IAR0
IMASK0, ISR0, IWR0
UART0 Status
IVG7
5
0
IAR0
IMASK0, ISR0, IWR0
UART1 Status
IVG7
6
0
IAR0
IMASK0, ISR0, IWR0
SPI0 Status
IVG7
7
0
IAR0
IMASK0, ISR0, IWR0
SPI1 Status
IVG7
8
0
IAR1
IMASK0, ISR0, IWR0
CAN Status
IVG7
9
0
IAR1
IMASK0, ISR0, IWR0
RSI Mask 0 Interrupt
IVG7
10
0
IAR1
IMASK0, ISR0, IWR0
–
11
–
IAR1
IMASK0, ISR0, IWR0
CNT0 Interrupt
IVG8
12
1
IAR1
IMASK0, ISR0, IWR0
CNT1 Interrupt
IVG8
13
1
IAR1
IMASK0, ISR0, IWR0
DMA Channel 0 (PPI Rx/Tx)
IVG9
14
2
IAR1
IMASK0, ISR0, IWR0
DMA Channel 1 (RSI Rx/Tx)
IVG9
15
2
IAR1
IMASK0, ISR0, IWR0
Reserved
DMA Channel 2 (SPORT0 Rx)
IVG9
16
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 3 (SPORT0 Tx)
IVG9
17
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 4 (SPORT1 Rx)
IVG9
18
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 5 (SPORT1 Tx)
IVG9
19
2
IAR2
IMASK0, ISR0, IWR0
DMA Channel 6 (SPI0 Rx/Tx)
IVG10
20
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 7 (SPI1 Rx/Tx)
IVG10
21
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 8 (UART0 Rx)
IVG10
22
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 9 (UART0 Tx)
IVG10
23
3
IAR2
IMASK0, ISR0, IWR0
DMA Channel 10 (UART1 Rx)
IVG10
24
3
IAR3
IMASK0, ISR0, IWR0
DMA Channel 11 (UART1 Tx)
IVG10
25
3
IAR3
IMASK0, ISR0, IWR0
CAN Receive
IVG11
26
4
IAR3
IMASK0, ISR0, IWR0
CAN Transmit
IVG11
27
4
IAR3
IMASK0, ISR0, IWR0
TWI
IVG11
28
4
IAR3
IMASK0, ISR0, IWR0
Port F Interrupt A
IVG11
29
4
IAR3
IMASK0, ISR0, IWR0
Port F Interrupt B
IVG11
30
4
IAR3
IMASK0, ISR0, IWR0
–
31
–
IAR3
IMASK0, ISR0, IWR0
Timer 0
IVG12
32
5
IAR4
IMASK1, ISR1, IWR1
Timer 1
IVG12
33
5
IAR4
IMASK1, ISR1, IWR1
Timer 2
IVG12
34
5
IAR4
IMASK1, ISR1, IWR1
Timer 3
IVG12
35
5
IAR4
IMASK1, ISR1, IWR1
Timer 4
IVG12
36
5
IAR4
IMASK1, ISR1, IWR1
Timer 5
IVG12
37
5
IAR4
IMASK1, ISR1, IWR1
Timer 6
IVG12
38
5
IAR4
IMASK1, ISR1, IWR1
Timer 7
IVG12
39
5
IAR4
IMASK1, ISR1, IWR1
Port G Interrupt A
IVG12
40
5
IAR5
IMASK1, ISR1, IWR1
Reserved
Rev. PrC
| Page 7 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 3. System Interrupt Controller (SIC) (Continued)
General Purpose
Interrupt (at Reset)
Peripheral Interrupt ID
Default Core
Interrupt ID
Port G Interrupt B
IVG12
41
5
IAR5
IMASK1, ISR1, IWR1
MDMA Stream 0
IVG13
42
6
IAR5
IMASK1, ISR1, IWR1
Peripheral Interrupt Source
SIC Registers
MDMA Stream 1
IVG13
43
6
IAR5
IMASK1, ISR1, IWR1
Software Watchdog Timer
IVG13
44
6
IAR5
IMASK1, ISR1, IWR1
Port H Interrupt A
IVG13
45
6
IAR5
IMASK1, ISR1, IWR1
Port H Interrupt B
IVG13
46
6
IAR5
IMASK1, ISR1, IWR1
ACM Status Interrupt
IVG7
47
0
IAR5
IMASK1, ISR1, IWR1
ACM Interrupt
IVG10
48
3
IAR6
IMASK1, ISR1, IWR1
Reserved
–
49
–
IAR6
IMASK1, ISR1, IWR1
Reserved
–
50
–
IAR6
IMASK1, ISR1, IWR1
PWM0 Trip Interrupt
IVG10
51
3
IAR6
IMASK1, ISR1, IWR1
PWM0 Sync Interrupt
IVG10
52
3
IAR6
IMASK1, ISR1, IWR1
PWM1 Trip Interrupt
IVG10
53
3
IAR6
IMASK1, ISR1, IWR1
PWM1 Sync Interrupt
IVG10
54
3
IAR6
IMASK1, ISR1, IWR1
RSI Mask 1 Interrupt
IVG10
55
3
IAR6
IMASK1, ISR1, IWR1
–
56 through 63
–
–
IMASK1, ISR1, IWR1
Reserved
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
• CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and is cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each of the peripheral
interrupt events shown in Table 3 on Page 7.
Rev. PrC
• SIC interrupt mask registers (SIC_IMASKx) – Control the
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, the corresponding
peripheral event is unmasked and is forwarded to the CEC
when asserted. A cleared bit in these registers masks the
corresponding peripheral event, preventing the event from
propagating to the CEC.
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indicates that the peripheral is not asserting the event.
• SIC interrupt wakeup enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
For more information, see Dynamic Power Management
on Page 13.
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the
| Page 8 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
general-purpose interrupt to the IPEND output asserted is three
core clock cycles; however, the latency can be much higher,
depending on the activity within and the state of the processor.
FLASH MEMORY
The ADSP-BF504F and ADSP-BF506F processors include an
on-chip 32M bit (×16, multiple bank, burst) Flash memory. The
features of this memory include:
• Synchronous/asynchronous read
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
Examples of DMA types supported by the processor DMA controller include:
• Synchronous burst read mode: 50 MHz
• A single, linear buffer that stops upon completion
• Asynchronous/synchronous read mode
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• Random access times: 70 ns
• 1-D or 2-D DMA using a linked list of descriptors
• Synchronous burst read suspend
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
• Memory blocks
• Multiple bank memory array: 4 Mbit banks
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
• Parameter blocks (top location)
• Dual operations
• Program erase in one bank while read in others
• No delay between read and write operations
• Block locking
WATCHDOG TIMER
• All blocks locked at power-up
• Any combination of blocks can be locked or locked
down
• Security
• 128-bit user programmable OTP cells
• 64-bit unique device number
• Common Flash interface (CFI)
• 100 000 program/erase cycles per block
Flash memory ships from the factory in an erased state except
for block 0 of the parameter bank. Block 0 of the Flash memory
parameter bank ships from the factory in an unknown state. An
erase operation should be performed prior to programming this
block.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMAcapable peripherals include the SPORTs, SPI ports, UARTs,
RSI, and PPI. Each individual DMA-capable peripheral has at
least one dedicated DMA channel.
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
Rev. PrC
The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a core and system reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the
timer expires before being reset by software. The programmer
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a reset, the watchdog timer resets both
the core and the processor peripherals. After a reset, software
can determine whether the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are nine general-purpose programmable timer units in
the processors. Eight timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized: to an external clock input to the
several other associated PF pins, to an external clock input to
the PPI_CLK input pin, or to the internal SCLK.
| Page 9 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
switching patterns for control of the electronically commutated
motor (ECM) or brushless dc motor (BDCM). Software can
enable a special mode for switched reluctance motors (SRM).
The six PWM output signals (per PWM unit) consist of three
high-side drive signals (PWMx_AH, PWMx_BH, and
PWMx_CH) and three low-side drive signals (PWMx_AL,
PWMx_BL, and PWMx_CL). The polarity of the generated
PWM signal can be set with software, so that either active HI or
active LO PWM patterns can be produced.
Two 32-bit up/down counters are provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumbwheels. The counters can also operate
in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input pin or by two
edge detectors.
The switching frequency of the generated PWM pattern is programmable using the 16-bit PWM_TM register. The PWM
generator can operate in single update mode or double update
mode. In single update mode, the duty cycle values are programmable only once per PWM period, so that the resultant
PWM patterns are symmetrical about the midpoint of the PWM
period. In the double update mode, a second updating of the
PWM registers is implemented at the midpoint of the PWM
period. In this mode, it is possible to produce asymmetrical
PWM patterns that produce lower harmonic distortion in
3-phase PWM inverters.
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumb wheels. All three pins have a programmable debouncing
circuit.
Pulses synchronous to the switching frequency can be generated
internally and output on the PWMx_SYNC pin. The PWM unit
can also accept externally generated synchronization pulses
through PWMx_SYNC.
Internal signals forwarded to each timer unit enable these timers to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
Each PWM unit features a dedicated asynchronous shutdown
pin, PWMx_TRIP, which (when brought low) instantaneously
places all six PWM outputs in the OFF state.
3-PHASE PWM UNITS
The processors incorporate two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following
features:
UP/DOWN COUNTERS AND
THUMBWHEEL INTERFACES
The two/dual 3-phase PWM generation units each feature:
• 16-bit center-based PWM generation unit
SERIAL PORTS
• Programmable PWM pulse width
• I2S capable operation.
• Single/double update modes
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
transition to full ON and full OFF states
• Possibility to synchronize the PWM generation to either
externally-generated or internally-generated synchronization pulses
• Special provisions for BDCM operation (crossover and
output enable functions)
• Wide variety of special switched reluctance (SR) operating
modes
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
Each PWM block integrates a flexible and programmable
3-phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction motor (ACIM) or
permanent magnet synchronous motor (PMSM) control. In
addition, the PWM block contains special functions that considerably simplify the generation of the required PWM
Rev. PrC
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
| Page 10 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF50x processors have two SPI-compatible ports
that enable the processor to communicate with multiple SPIcompatible devices.
The SPI interface uses three pins for transferring data: two data
pins MOSI (Master Output-Slave Input) and MISO (Master
Input-Slave Output) and a clock pin, serial clock (SCK). An SPI
chip select input pin (SPIx_SS) lets other SPI devices select the
processor, and three SPI chip select output pins (SPIx_SEL3–1)
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel,
configurable to support transmit or receive data streams. The
SPI’s DMA channel can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
f SCLK
SPI Clock Rate = -----------------------------------2 × SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF50x Blackfin processors provide two full-duplex
universal asynchronous receiver/transmitter (UART) ports.
Each UART port provides a simplified UART interface to other
peripherals or hosts, enabling full-duplex, DMA-supported,
asynchronous transfers of serial data. A UART port includes
Rev. PrC
support for five to eight data bits, one or two stop bits, and
none, even, or odd parity. Each UART port supports two modes
of operation:
• PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access). The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexible interrupt timing options are available on the transmit
side.
Each UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK) bits per second.
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as
f SCLK
UART Clock Rate = -----------------------------------------------------------------------( 1 – EDBO )
16
× UART_Divisor
Where the 16-bit UART divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant eight bits), and the EDBO is a bit in the
UARTx_GCTL register.
In conjunction with the general-purpose timer functions, autobaud detection is supported.
The UARTs feature a pair of UAx_RTS (request to send) and
UAx_CTS (clear to send) signals for hardware flow purposes.
The transmitter hardware is automatically prevented from
sending further data when the UAx_CTS input is de-asserted.
The receiver can automatically de-assert its
UAx_RTS output when the enhanced receive FIFO exceeds a
certain high-water level. The capabilities of the UARTs are further extended with support for the Infrared Data Association
(IrDA®) Serial Infrared Physical Layer Link Specification (SIR)
protocol.
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
| Page 11 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
General-Purpose Mode Descriptions
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input mode – Frame syncs and data are inputs into the PPI.
• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
• Output mode – Frame syncs and data are outputs from the
PPI.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit and 10-bit
through 16-bit data, programmable in the PPI_CONTROL
register.
Vertical Blanking Interval Mode
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
RSI INTERFACE
The removable storage interface (RSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), secure digital input/output cards (SDIO), and CEATA hard disk drives. The following list describes the main features of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CEATA hard disk drive
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit, and 8-bit MMC modes
Frame Capture Mode
• Support for 4-bit and 8-bit CE-ATA hard disk drives
Frame capture mode allows the video source(s) to act as a slave
(for frame capture for example). The ADSP-BF50x processors
control when to read from the video source(s). PPI_FS1 is an
HSYNC output and PPI_FS2 is a VSYNC output.
• A ten-signal external interface with clock, command, and
up to eight data lines
Output Mode
• Card interface clock generation from SCLK
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
• SDIO interrupt and read wait features
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
Active Video Mode
Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
Rev. PrC
• Card detection using one of the data signals
• CE-ATA command completion signal recognition and
disable
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF50x processors provide a CAN controller that is a
communication controller implementing the Controller Area
Network (CAN) V2.0B protocol. This protocol is an asynchronous communications protocol used in both industrial and
automotive control systems. CAN is well suited for control
applications due to its capability to communicate reliably over a
network since the protocol incorporates CRC checking, message
error tracking, and fault node confinement.
The CAN controller is based on a 32-entry mailbox RAM and
supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification,
revision 2.0, part B.
| Page 12 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the network. If the identifier in the transmitted message matches an
identifier in one of its mailboxes, the module knows that the
message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the processor from sleep mode
upon generation of a wake-up event, such that the processor can
be maintained in a low-power mode during idle conditions.
Additionally, a CAN wake-up event can wake up the on-chip
internal voltage regulator from the powered-down
hibernate state.
The electrical characteristics of each network connection are
very stringent. Therefore, the CAN interface is typically divided
into two parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks.
The ADSP-BF50x CAN module represents the controller part of
the interface. This module’s network I/O is a single transmit
output and a single receive input, which connect to a line
transceiver.
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
TWI CONTROLLER INTERFACE
The processors include a two-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is compatible with the widely used
I2C® bus standard. The TWI module offers the capabilities of
simultaneous master and slave operation, support for both 7-bit
addressing and multimedia data arbitration. The TWI interface
utilizes two pins for transferring clock (SCL) and data (SDA)
and supports the protocol at speeds up to 400K bits/sec. The
TWI interface pins are compatible with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
PORTS
Because of the rich set of peripherals, the processor groups the
many peripheral signals to three ports—Port F, Port G, and
Port H. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 35 bidirectional, general-purpose I/O (GPIO)
pins allocated across three separate GPIO modules—PORTFIO,
PORTGIO, and PORTHIO, associated with Port F, Port G, and
Port H, respectively. Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme;
however, the GPIO functionality is the default state of the device
upon power-up. Neither GPIO output nor input drivers are
Rev. PrC
active by default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and
interrupt registers:
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
DYNAMIC POWER MANAGEMENT
The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissipation. When configured for a 0 volt core supply voltage, the
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 4 for a summary of the power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
| Page 13 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). If disabled, the PLL
control input must be re-enabled before transitioning to the
full-on or sleep modes.
Table 4. Power Settings
Core
PLL
Clock
Mode/State PLL
Bypassed (CCLK)
Full On
Enabled No
Enabled
Active
Enabled/ Yes
Enabled
Disabled
Sleep
Enabled —
Disabled
Deep Sleep Disabled —
Disabled
Hibernate
Disabled —
Disabled
System
Clock
(SCLK)
Enabled
Enabled
Core
Power
On
On
Enabled On
Disabled On
Disabled Off
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF50x Blackfin Processor Hardware Reference.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically, an external event wakes up the processor. When in the
sleep mode, asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in
the PLL control register (PLL_CTL). If BYPASS is disabled, the
processor transitions to the full on mode. If BYPASS is enabled,
the processor transitions to the active mode.
Writing 0 to the HIBERNATE bit causes EXT_WAKE to transition low, which can be used to signal an external voltage
regulator to shut down.
Since VDDEXT can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.
The processor can be woken up by asserting the RESET pin. All
hibernate wakeup events initiate the hardware reset sequence.
Individual sources are enabled by the VR_CTL register. The
EXT_WAKE signal indicates the occurrence of a wakeup event.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state.
Power Savings
As shown in Table 5, the processor supports three different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advantage of dynamic power management without affecting the other
I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered
according to the appropriate Processor — Specifications table
for processor operating conditions; even if the feature/peripheral is not used.
Table 5. Power Domains
Power Domain
All internal logic, except Memory
Flash Memory
All other I/O
ADC digital supply1 (Logic, I/O)
ADC analog supply1
DMA accesses to L1 memory are not supported in sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
may still be running but cannot access internal resources or
external memory. This powered-down mode can only be exited
by assertion of the reset pin (RESET). Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the peripherals (SCLK). This setting sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (for
example, memory contents, register contents, and other information) must be written to a non-volatile storage device prior to
removing power if the processor state is to be preserved.
Rev. PrC
1
Power Supply
VDDINT
VDDFLASH
VDDEXT
DVDD, VDRIVE
AVDD
On ADSP-BF506F processor only.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Power Savings Factor
T RED
f CCLKRED
V DDINTRED 2
= -------------------------- ×  -------------------------------- ×  --------------- 



f CCLKNOM
V DDINTNOM
T NOM 
| Page 14 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
% Power Savings = ( 1 – Power Savings Factor ) × 100%
where the variables in the equations are:
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
ADSP-BF50X VOLTAGE REGULATION
The ADSP-BF50x processors require an external voltage regulator to power the VDDINT domain. To reduce standby power
consumption, the external voltage regulator can be signaled
through EXT_WAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.
While in the hibernate state, all external supplies (VDDEXT,
VDDFLASH) can still be applied, eliminating the need for external
buffers. The external voltage regulator can be activated from
this power down state by asserting the RESET pin, which then
initiates a boot sequence. EXT_WAKE indicates a wakeup to
the external voltage regulator.
The power good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the power good
functionality, refer to the ADSP-BF50x Blackfin Processor Hardware Reference.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable multiplication factor
(bounded by specified minimum and maximum VCO frequencies). The default multiplier is 6×, but it can be modified by a
software instruction sequence.
BLACKFIN
CLKOUT (SCLK)
CLKBUF
TO PLL CIRCUITRY
EN
EN
SELECT
560 ⍀
EXTCLK
330 ⍀*
CLOCK SIGNALS
18 pF *
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins. The onchip resistance between CLKIN and the XTAL pin is in the
500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in
Figure 4 fine tune phase and amplitude of the sine frequency.
FOR OVERTONE
OPERATION ONLY:
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.
Figure 4. External Crystal Connections
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and
SCLK rates depend on the applied voltages VDDINT and VDDEXT;
the VCO is always permitted to run up to the CCLK frequency
specified by the part’s speed grade. The EXTCLK pin can be
configured to output either the SCLK frequency or the input
buffered CLKIN frequency, called CLKBUF. When configured
to output SCLK (CLKOUT), the EXTCLK pin acts as a reference signal in many timing specifications. While active by
default, it can be disabled using the EBIU_AMGCTL register.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
Rev. PrC
XTAL
CLKIN
| Page 15 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
PLL
0.5u to 64u
CLKIN
Preliminary Technical Data
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CCLK
÷ 1 to 15
SCLK
VCO
BOOTING MODES
The processor has several mechanisms (listed in Table 8) for
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedicated to this purpose. There are two categories of boot modes.
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.
Table 8. Booting Modes
SCLK d CCLK
BMODE2–0
000
001
010
011
100
101
110
111
Figure 5. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Example Frequency Ratios
(MHz)
VCO
SCLK
50
50
300
50
400
40
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Example Frequency Ratios
(MHz)
Divider Ratio
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
The maximum CCLK frequency both depends on the part’s
speed grade (see Page 79) and depends on the applied VDDINT
voltage. See Table 14 for details. The maximal system clock rate
(SCLK) depends on the applied VDDINT and VDDEXT voltages (see
Table 16).
Rev. PrC
1
Description
Idle/No Boot
Boot from internal parallel flash in async mode1
Boot from internal parallel flash in sync mode1
Boot through SPI0 master from SPI memory
Boot through SPI0 slave from host device
Boot through PPI from host
Reserved
Boot through UART0 slave from host device
This boot mode supported on ADSP-BF504F and ADSP-BF506F processor only.
The boot modes listed in Table 8 provide a number of mechanisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
Some boot modes require a boot host wait (HWAIT) signal,
which is a GPIO output signal that is driven and toggled by the
boot kernel at boot time. If pulled high through an external pullup resistor, the HWAIT signal behaves active high and will be
driven low when the processor is ready for data. Conversely,
when pulled low, HWAIT is driven high when the processor is
ready for data. When the boot sequence completes, the HWAIT
pin can be used for other purposes. The BMODE pins of the
reset configuration register, sampled during power-on resets
and software-initiated resets, implement the modes shown in
Table 8.
• IDLE State / No Boot (BMODE = 0x0) — In this mode, the
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recovery, debug, or other functions.
• Boot from stacked parallel flash in 16-bit asynchronous
mode (BMODE = 0x1) — In this mode, the boot kernel
starts booting from address 0x2000 0000.
• Boot from stacked parallel flash in 16-bit synchronous
mode (BMODE = 0x2) — In this mode, the boot kernel
loads the first block header from address 0x2000 0000. Boot
kernel operation from this point is TBD.
• Boot from serial SPI memory, EEPROM or flash
(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable
devices are supported. The processor uses the PF13 GPIO
pin to select a single SPI EEPROM/flash device (connected
to the SPI0 interface) and submits a read command and
successive address bytes (0x00) until a valid 8-, 16-, 24-, or
| Page 16 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
32-bit addressable device is detected. Pull-up resistors are
required on the SPI0_SEL1 and MISO pins. By default, a
value of 0x85 is written to the SPI_BAUD register.
• Boot from SPI host device (BMODE = 0x4) — The processor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
The HWAIT signal must be interrogated by the host before
every transmitted byte. A pull-up resistor is required on the
SPI0_SS input. A pull-down on the serial clock (SCK) may
improve signal quality and booting robustness.
• Boot from PPI host device (BMODE = 0x5) — The processor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
• Boot from UART0 host on Port G (BMODE = 0x7) —
Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host
selects a bit rate within the UART clocking capabilities.
When performing the autobaud detection, the UART
expects an “@” (0x40) character (eight bits data, one start
bit, one stop bit, no parity bit) on the UA0_RX pin to determine the bit rate. The UART then replies with an
acknowledgement composed of 4 bytes (0xBF, the value of
UART0_DLL, the value of UART0_DLH, then 0x00). The
host can then download the boot stream. The processor
deasserts the UA0_RTS output to hold off the host;
UA0_CTS functionality is not enabled at boot time.
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass the pre-boot routine and/or boot
kernel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, wait states, or
serial bit rates.
The boot ROM also features C-callable function that can be
called by the user application at run time. This enables secondstage boot or boot management schemes to be implemented
with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
Rev. PrC
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
DEVELOPMENT TOOLS
The processor is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF50x processors.
EZ-KIT Lite® Evaluation Board
For evaluation of ADSP-BF50x processors, use the EZ-KIT Lite
boards soon to be available from Analog Devices. When these
evaluation kits are available, order using part number
ADZS-BF506-EZLITE. The boards come with on-chip emulation capabilities and is equipped to enable software
development. Multiple daughter cards will be available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
| Page 17 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see (EE-68) Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
The ADC is integrated into the ADSP-BF506F product. Figure 7
shows how to connect the internal ADC to the ACM and to one
of the two SPORTs on the ADSP-BF506F processor.
ADSP-BF506F
DRxSEC
SPORTx
DRxPRI
RCLKx
RFSx
ADC AND ACM INTERFACE
This section describes the ADC and ACM interface. System
designers should also consult the ADSP-BF50x Blackfin Processor Hardware Reference for additional information.
ACLK
ACM
ACM_A[2:0]
ACM_SGLDIFF
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processor and the internal analog-to-digital converter (ADC) module. The ACM is
available on the ADSP-BF504, ADSP-BF504F, and
ADSP-BF506F processors, and the ADC is available on the
ADSP-BF506F processor only. The analog-to-digital conversions are initiated by the processor, based on external or
internal events.
ACM_RANGE
RANGE
SGL/DIFF
A[2:0]
ADC
CS
(INTERNAL) ADSCLK
DOUTA
DOUTB
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
The ACM synchronizes the ADC conversion process; generating the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by the SPORT peripherals.
The serial interface on the ADC allows the part to be directly
connected to the ADSP-BF504, ADSP-BF504F, and
ADSP-BF506F processors using serial interface protocols.
Figure 6 shows how to connect an external ADC to the ACM
and one of the two SPORTs on the ADSP-BF504 or
ADSP-BF504F processors.
ADSP-BF504/ADSP-BF504F
SPORTx
DRxSEC
DRxPRI
RCLKx
RFSx
ACLK
CS
ACM_A[2:0]
ACM_SGLDIFF
ACM_RANGE
Figure 7. ADC (Internal), ACM, and SPORT Connections
The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F processors interface directly to the ADC without any glue logic
required. The availability of secondary receive registers on the
serial ports of the Blackfin processors means only one serial port
is necessary to read from both DOUT pins simultaneously.
Figure 7 (ADC (Internal), ACM, and SPORT Connections)
shows both DOUTA and DOUTB of the ADC connected to one of
the processor’s serial ports. The SPORTx Receive Configuration
1 register and SPORTx Receive Configuration 2 register should
be set up as outlined in Table 9 (The SPORTx Receive Configuration 1 Register (SPORTx_RCR1)) and Table 10 (The SPORTx
Receive Configuration 2 Register (SPORTx_RCR2)).
Table 9. The SPORTx Receive Configuration 1 Register
(SPORTx_RCR1)
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 0
RLSBIT = 0
RDTYPE = 00
IRCLK = 0
RSPEN = 1
TFSR = RFSR = 1
SPORT
SELECT
MUX
ACM
RANGE
SGL/DIFF
A[2:0]
ADC
(EXTERNAL)
CS
SPORT
SELECT
MUX
CS
ADSCLK
DOUTA
DOUTB
Figure 6. ADC (External), ACM, and SPORT Connections
Rev. PrC
| Page 18 of 80 | January 2010
Description
Sample data with rising edge of RSCLK
Active low frame signal
Frame every word
External RFS used
Receive MSB first
Zero fill
External receive clock
Receive enabled
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
NOTE: The SPORT must be enabled with the following settings: external clock, external frame sync, and active low frame
sync.
Table 10. The SPORTx Receive Configuration 2 Register
(SPORTx_RCR2)
Setting
RXSE = 1
SLEN = 1111
Description
Secondary side enabled
16-bit data-word (or may be set to 1101 for
14-bit data-word)
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
ADC is available to download at www.analog.com.
INTERNAL ADC
REF SELECT
The internal ADC is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to
5.25 V power supply and features throughput rates up to
2 MSPS. The device contains two ADCs, each preceded by a
3-channel multiplexer, and a low noise, wide bandwidth trackand-hold amplifier that can handle input frequencies in excess
of 30 MHz.
Figure 8 shows the functional block diagram of the internal
ADC. The ADC features include:
• Dual 12-bit, 3-channel ADC
• Throughput rate: up to 2 MSPS
REF
BUF
MUX
T/H
AVDD
DVDD
ADC
VA1
VA2
VA3
VA4
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
VA5
CONTROL
LOGIC
VB1
VB2
VB4
DOUTA
ADSCLK
CS
RANGE
SGL/DIFF
A0
A1
A2
VA6
VB3
An ADC is integrated into the ADSP-BF506F product. All ADC
signals are connected out to package pins to enable maximum
interconnect flexibility in mixed signal applications.
DCAPA
VDRIVE
MUX
T/H
VB5
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
DOUTB
VB6
BUF
AGND AGND AGND DCAPB
DGND
DGND
Figure 8. ADC (Internal) Functional Block Diagram
The internal ADC uses advanced design techniques to achieve
very low power dissipation at high throughput rates. The part
also offers flexible power/ throughput rate management when
operating in normal mode as the quiescent current consumption is so low.
The analog input range for the part can be selected to be a 0 V to
VREF (or 2 × VREF) range, with either straight binary or twos
complement output coding. The internal ADC has an on-chip
2.5 V reference that can be overdriven when an external reference is preferred.
• Specified for DVDD and AVDD of 2.7 V to 5.25 V
• Pin-configurable analog inputs
• 12-channel single-ended inputs
Additional highlights of the internal ADC include:
or
• 6-channel fully differential inputs
or
• 6-channel pseudo differential inputs
• Accurate on-chip voltage reference: 2.5 V
• Dual conversion with read 437.5 ns, 32 MHz ADSCLK
• High speed serial interface
• High Throughput with Low Power Consumption
• SPI®-/QSPITM-/MICROWIRETM-/DSP-compatible
• The internal ADC offers both a standard 0 V to VREF input
range and a 2 × VREF input range.
• Low power shutdown mode
The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is
determined by the ADSCLK frequency. There are no pipelined
delays associated with the part.
Rev. PrC
• Two Complete ADC Functions Allow Simultaneous Sampling and Conversion of Two Channels — Each ADC has
three fully/pseudo differential pairs, or six single-ended
channels, as programmed. The conversion result of both
channels is simultaneously available on separate data lines,
or in succession on one data line if only one serial connection is available.
• No Pipeline Delay — The part features two standard successive approximation ADCs with accurate control of the
sampling instant via a CS input and once off conversion
control.
| Page 19 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
ADC APPLICATION HINTS
The following sections provide application hints for using the
ADC.
Grounding and Layout Considerations
The analog and digital supplies to the ADC are independent and
separately pinned out to minimize coupling between the analog
and digital sections of the device. The printed circuit board
(PCB) that houses the ADC should be designed so that the analog and digital sections are separated and confined to certain
areas of the board. This design facilitates the use of ground
planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins should be sunk
in the AGND plane. Digital and analog ground planes should be
joined in only one place. If the ADC is in a system where multiple devices require an AGND to DGND connection, the
connection should still be made at one point only, a star ground
point that should be established as close as possible to the
ground pins on the ADC.
Avoid running digital lines under the device as this couples
noise onto the die. Avoid running digital lines in the area of the
AGND pad as this couples noise onto the ADC die and into the
AGND plane. The power supply lines to the ADC should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board, fast
switching signals, such as clocks, should be shielded with digital
ground, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feed through within the board, traces on opposite
sides of the board should run at right angles to each other.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with 0.1
μF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as possible
to the device, ideally right up against the device. The 0.1 μF
capacitors should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types or surface-mount types. These low ESR and ESI capacitors
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF50x processors (and related processors) can be ordered from any
Analog Devices sales office or accessed electronically on our
website:
• Getting Started With Blackfin Processors
• ADSP-BF50x Blackfin Processor Hardware Reference (volumes 1 and 2)
• Blackfin Processor Programming Reference
• ADSP-BF50x Blackfin Processor Anomaly List
Rev. PrC
| Page 20 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF50x processors are listed in
Table 11. All pins for the ADC (ADSP-BF506F processor only)
are listed in Table 12.
hibernate, all signals are three-stated with the following exceptions: EXT_WAKE is driven low and XTAL is driven to a solid
logic level.
In order to maintain maximum function and reduce package
size and pin count, some pins have multiple, multiplexed functions. In cases where pin function is reconfigurable, the default
state is shown in plain text, while the alternate functions are
shown in italics.
During and immediately after reset, all I/O pins have their input
buffers disabled until enabled by user software with the exception of the pins that need pull-ups or pull-downs, as noted in
Table 11.
During and immediately after reset, all processor signals (not
ADC signals) are three-stated with the following exceptions:
EXT_WAKE is driven high and XTAL is driven in conjunction
with CLKIN to create a crystal oscillator circuit. During
Adding a parallel termination to CLKOUT may prove useful in
further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual
hardware.
Table 11. Processor — Signal Descriptions
Signal Name
Port F: GPIO and Multiplexed Peripherals
PF0/TSCLK0/UA0_RX/TMR6/CUD0
PF1/RSCLK0/UA0_TX/TMR5/CDG0
PF2/DT0PRI/PWM0_BH/PPI_D8/CZM0
PF3/TFS0/PWM0_BL/PPI_D9/CDG0
PF4/RFS0/PWM0_CH/PPI_D10/TACLK0
PF5/DR0PRI/PWM0_CL/PPI_D11/TACLK1
PF6/UA1_TX/PWM0_TRIP/PPI_D12
PF7/UA1_RX/PWM0_SYNC/PPI_D13/TACI3
PF8/UA1_RTS/DT0SEC/PPI_D7
PF9/UA1_CTS/DR0SEC/PPI_D6/CZM0
PF10/SPI0_SCK/TMR2/PPI_D5
PF11/SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2
PF12/SPI0_MOSI/PWM0_SYNC/PPI_D3
PF13/SPI0_SEL1/TMR3/PPI_D2/SPI0_SS
PF14/SPI0_SEL2/PWM0_AH/PPI_D1
PF15/SPI0_SEL3/PWM0_AL/PPI_D0
Port G: GPIO and Multiplexed Peripherals
PG0/SPI1_SEL3/TMRCLK/PPI_CLK/UA1_RX/TACI4
PG1/SPI1_SEL2/PPI_FS3/CAN_RX/TACI5
PG2/SPI1_SEL1/TMR4/CAN_TX/SPI1_SS
PG3/HWAIT/SPI1_SCK/DT1SEC/UA1_TX
PG4/SPI1_MOSI/DR1SEC/PWM1_SYNC/TACLK6
PG5/SPI1_MISO/TMR7/PWM1_TRIP
PG6/ACM_SGLDIFF/SD_D3/PWM1_AH
PG7/ACM_RANGE/SD_D2/PWM1_AL
PG8/DR1SEC/SD_D1/PWM1_BH
PG9/DR1PRI/SD_D0/PWM1_BL
PG10/RFS1/SD_CMD/PWM1_CH/TACI6
PG11/RSCLK1/SD_CLK/PWM1_CL/TACLK7
PG12/UA0_RX/SD_D4/PPI_D15/TACI2
PG13/UA0_TX/SD_D5/PPI_D14/CZM1
Type Function
Driver
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT0 TX Serial CLK/UART0 RX/Timer6/Count Up Dir 0
GPIO/SPORT0 RX Serial CLK/UART0 TX/Timer5/Count Down Dir 0
GPIO/SPORT0 TX Pri Data/PWM0 Drive B Hi/PPI Data 8/Counter Zero Marker 0
GPIO/SPORT0 TX Frame Sync/PWM0 Drive B Lo/PPI Data 9/Count Down Dir 0
GPIO/SPORT0 RX Frame Sync/PWM0 Drive C Hi/PPI Data 10/Alt Timer CLK 0
GPIO/SPORT0 Pri RX Data/PWM0 Drive C Lo/PPI Data 11/Alt Timer CLK 1
GPIO/UART1 TX/PWM0 TRIP/PPI Data 12
GPIO/UART1 RX/PWM0 SYNC/PPI Data 13/Alt Capture In 3
GPIO/UART1 RTS/SPORT0 TX Sec Data/PPI Data 7
GPIO/UART1 CTS/SPORT0 Sec RX Data/PPI Data 6/Counter Zero Marker 0
GPIO/SPI0 SCK/Timer2/PPI Data 5
GPIO/SPI0 MISO/PWM0 TRIP/PPI Data 4/Alt Timer CLK 2
GPIO/SPI0 MOSI/PWM0 SYNC/PPI Data 3
GPIO/SPI0 Slave Select 1/Timer3/PPI Data 2/SPI0 Slave Select In
GPIO/SPI0 Slave Select 2/PWM0 AH/PPI Data 1
GPIO/SPI0 Slave Select 3/PWM0 AL/PPI Data 0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPI1 Slave Select 3/Timer CLK/PPI Clock/UART1 RX/Alt Capture In 4
GPIO/SPI1 Slave Select 2/PPI FS3/CAN RX/Alt Capture In 5
GPIO/SPI1 Slave Select 1/Timer4/CAN TX/SPI1 Slave Select In
GPIO/HWAIT/SPI1 SCK/SPORT1 TX Sec Data/UART1 TX
GPIO/SPI1 MOSI/SPORT1 Sec RX Data/PWM1 SYNC/Alt Timer CLK 6
GPIO/SPI1 MISO/Timer7/PWM1 TRIP
GPIO/ADC CM SGL DIFF/SD Data 3/PWM1 Drive A Hi
GPIO/ADC CM RANGE/SD Data 2/PWM1 Drive A Lo
GPIO/SPORT1 Sec RX Data/SD Data 1/PWM1 Drive B Hi
GPIO/SPORT1 Pri RX Data/SD Data 0/PWM1 Drive B Lo
GPIO/SPORT1 RX Frame Sync/SD CMD/PWM1 Drive C Hi/Alt Capture In 6
GPIO/SPORT1 RX Serial CLK/SD CLK/PWM1 Drive C Lo/Alt Timer CLK 7
GPIO/UART0 RX/SD Data 4/PPI Data 15/Alt Capture In 2
GPIO/UART0 TX/SD Data 5/PPI Data 14/Counter Zero Marker 1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Rev. PrC
| Page 21 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 11. Processor — Signal Descriptions (Continued)
Signal Name
PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1
PG15/UA0_CTS/SD_D7/TMR1/PPI_FS2/CDG1
Port H: GPIO and Multiplexed Peripherals
PH0/ACM_A2/DT1PRI/SPI0_SEL3/WAKEUP
PH1/ACM_A1/TFS1/SPI1_SEL3/TACLK3
PH2/ACM_A0/TSCLK1/SPI1_SEL2/TACI7
TWI (Two-Wire Interface) Port
SCL
SDA
JTAG Port
TCK
TDO
TDI
TMS
TRST
Type Function
I/O GPIO/UART0 RTS/SD Data 6/Timer0/PPI FS1/Count Up Dir 1
I/O GPIO/UART0 CTS/SD Data 7/Timer1/PPI FS2/Count Down Dir 1
I/O GPIO/ADC CM A2/SPORT1 TX Pri Data/SPI0 Slave Select 3/Wake-up Input
I/O GPIO/ADC CM A1/SPORT1 TX Frame Sync/SPI1 Slave Select 3/Alt Timer CLK 3
I/O GPIO/ADC CM A0/SPORT1 TX Serial CLK/SPI1 Slave Select 2/Alt Capture In 7
I/O
5V
I/O
5V
EMU
Clock
CLKIN
XTAL
EXTCLK
Mode Controls
RESET
NMI
O
JTAG CLK
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
(This signal should be pulled low if the JTAG port is not used.)
Emulation Output
I
O
O
CLK/Crystal In
Crystal Output
Clock Output
I
I
BMODE2–0
ADSP-BF50x Voltage Regulation I/F
EXT_WAKE
PG
Power Supplies
I
Reset
Nonmaskable Interrupt
(This signal should be pulled high when not used.)
Boot Mode Strap 2-0
VDDEXT
VDDINT
VDDFLASH
GND
I
O
I
I
I
TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
O
I
P
P
P
G
Wake up Indication
Power Good
ALL SUPPLIES MUST BE POWERED
See Processor — Operating Conditions on Page 25.
I/O Power Supply
Internal Power Supply
Flash Memory Power Supply
Ground for All Supplies
Rev. PrC
| Page 22 of 80 | January 2010
Driver
Type
TBD
TBD
TBD
TBD
TBD
TBD
TBD
C
C
B
C
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Table 12. ADC — Signal Descriptions (ADSP-BF506F Processor Only)
Signal Name
DGND
REF SELECT
AVDD
DCAPA, DCAPB (VREF)
AGND
VA1 to VA6
VB1 to VB6
RANGE
SGL/DIFF
A0 to A2
CS
ADSCLK
Type Function
G Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND
pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be
at the same potential and must not be more than 0.3 V apart, even on a transient basis.
I Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be
tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be
supplied to the internal ADC through the DCAPA and/or DCAPB pins.
P Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
internal ADC. The AVDD and DVDD voltages should ideally be at the same potential and must not be more
than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.
I Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins
to decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip
reference can be taken from these pins and applied externally to the rest of a system. The range of the
external reference is dependent on the analog input range selected.
G Analog Ground. Ground reference point for all analog circuitry on the internal ADC. All analog input
signals and any external reference signal should be referred to this AGND voltage. All three of these
AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should
be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
I Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 51 (Analog Input Type and Channel Selection).
I Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 51 (Analog Input Type and Channel Selection).
I Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the
analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is
tied to a logic high when CS goes low, the analog input range is 2 × VREF. For details, see Table 51 (Analog
Input Type and Channel Selection).
I Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single
ended. A logic low selects differential operation while a logic high selects single-ended operation. For
details, see Table 51 (Analog Input Type and Channel Selection).
I Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B,
and so on. The pair of channels selected may be two single-ended channels or two differential pairs.
The logic states of these pins need to be set up prior to the acquisition time and subsequent falling
edge of CS to correctly set up the multiplexer for that conversion. For further details, see Table 51
(Analog Input Type and Channel Selection).
I Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the internal ADC and framing the serial data transfer. When connecting CS to a processor signal that is
three-stated during reset and/or hibernate, adding a pull-up resistor may prove useful to avoid random
ADC operation.
I Serial Clock. Logic input. A serial clock input provides the ADSCLK for accessing the data from the
internal ADC. This clock is also used as the clock source for the conversion process.
Rev. PrC
| Page 23 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 12. ADC — Signal Descriptions (ADSP-BF506F Processor Only) (Continued)
Signal Name
DOUTA, DOUTB
VDRIVE
DVDD
Type Function
O Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked
out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first.
If CS is held low for 16 ADSCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits
of data. If CS is held low for a further 16 ADSCLK cycles on either DOUTA or DOUTB, the data from the other
ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be
gathered in serial format on either DOUTA or DOUTB using only one serial port. For more information, see
the ADC — Serial Interface section.
P Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the digital I/O
interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than
that at AVDD and DVDD but should never exceed either by more than 0.3 V.
P Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the internal
ADC. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than
0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
Rev. PrC
| Page 24 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
PROCESSOR — SPECIFICATIONS
Specifications are subject to change without notice.
PROCESSOR — OPERATING CONDITIONS
Parameter
VDDINT1
Internal Supply Voltage
VDDEXT2
External Supply Voltage
2
VDDEXT
External Supply Voltage
VDDFLASH2,3 Flash Memory Supply Voltage
VIH
High Level Input Voltage4, 5
VIH
High Level Input Voltage4, 5
VIH
High Level Input Voltage4, 5
VIHTWI
High Level Input Voltage6
VIL
Low Level Input Voltage4, 5
Low Level Input Voltage4, 5
VIL
VIL
Low Level Input Voltage4, 5
VILTWI
Low Level Input Voltage6
TJ
Junction Temperature
TJ
Junction Temperature
Conditions
ADSP-BF504
ADSP-BF504F, ADSP-BF506F
VDDEXT = 1.90 V
VDDEXT = 2.75 V
VDDEXT = 3.6 V
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT = 1.7 V
VDDEXT = 2.25 V
VDDEXT = 3.0 V
VDDEXT = minimum
88-Lead LFCSP @ TAMBIENT = –40°C to +85°C
120-Lead LQFP @ TAMBIENT = –40°C to +85°C
Min
TBD
1.7
2.7
1.7
1.1
1.7
2.0
0.7 × VBUSTWI7, 8
–0.3
–0.3
–0.3
–0.3
–40
–40
Nominal
TBD
1.8/2.5/3.3
3.3
1.8
Max
TBD
3.6
3.6
2.0
3.6
3.6
3.6
VBUSTWI7, 8
0.6
0.7
0.8
0.3 × VBUSTWI8
+105
+105
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
The expected nominal value is 1.4 V ±5%, and initial customer designs should design with a programmable regulator that can be adjusted from 0.95 V to 1.5 V in 50 mV steps.
Must remain powered (even if the associated function is not used).
3
For ADSP-BF504, VDDFLASH pins should be connected to GND.
4
Bidirectional pins (PF15–0, PG15–0, PH2–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF50x processors are 3.3 V tolerant
(always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
5
Parameter value applies to all input and bidirectional pins, except SDA and SCL.
6
Parameter applies to SDA and SCL.
7
The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 13.
8
SDA and SCL are pulled up to VBUSTWI. See Table 13.
1
2
Table 13 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Table 13. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
VDDEXT Nominal
3.3
1.8
2.5
1.8
3.3
1.8
2.5
–
VBUSTWI Minimum
2.97
1.7
2.97
2.97
4.5
2.25
2.25
–
Rev. PrC
VBUSTWI Nominal
3.3
1.8
3.3
3.3
5
2.5
2.5
–
| Page 25 of 80 | January 2010
VBUSTWI Maximum
3.63
1.98
3.63
3.63
5.5
2.75
2.75
–
Unit
V
V
V
V
V
V
V
–
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
ADSP-BF50x Clock Related Operating Conditions
Table 14 describes the core clock timing requirements for the
ADSP-BF50x processors. Take care in selecting MSEL, SSEL,
and CSEL ratios so as not to exceed the maximum core clock
and system clock (see Table 16). Table 15 describes phaselocked loop operating conditions.
Table 14. Core Clock (CCLK) Requirements—ADSP-BF50x Processors—All Speed Grades1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Core Clock Frequency (VDDINT =tbd V Minimum)
Core Clock Frequency (VDDINT =tbd V Minimum)
Core Clock Frequency (VDDINT = tbd V Minimum)
Core Clock Frequency (VDDINT = tbd V Minimum)
Core Clock Frequency (VDDINT = tbd V Minimum)
Maximum
400
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
Maximum
Speed Grade1
Unit
MHz
See the Ordering Guide on Page 79.
Table 15. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Voltage Controlled Oscillator (VCO) Frequency
Minimum
72
See the Ordering Guide on Page 79.
Table 16. Maximum SCLK Conditions for ADSP-BF50x Processors
Parameter
fSCLK
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ tbd V)
CLKOUT/SCLK Frequency (VDDINT < tbd V)
Rev. PrC
| Page 26 of 80 | January 2010
VDDEXT = 1.8 V/2.5 V/3.3 V Nominal Unit
100
MHz
TBD
MHz
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
PROCESSOR — ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
1.35
Typical
Max
Unit
VOH
High Level Output Voltage
VDDEXT = 1.7 V, IOH = –0.5 mA
VOH
High Level Output Voltage
VDDEXT = 2.25 V, IOH = –0.5 mA 2.0
V
VOH
High Level Output Voltage
VDDEXT = 3.0 V, IOH = –0.5 mA
V
VOL
Low Level Output Voltage
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
0.4
V
VOLTWI
Low Level Output Voltage
VDDEXT = 1.7 V/2.25 V/3.0 V,
IOL = 2.0 mA
TBD
V
V
IIH
High Level Input Current1
VDDEXT =3.6 V, VIN = 3.6 V
10.0
μA
1
V
2.4
IIL
Low Level Input Current
VDDEXT =3.6 V, VIN = 0 V
10.0
μA
IIHP
High Level Input Current JTAG2
VDDEXT = 3.6 V, VIN = 3.6 V
75.0
μA
IOZH
Three-State Leakage Current3
VDDEXT = 3.6 V, VIN = 3.6 V
10.0
μA
4
VDDEXT =3.0 V, VIN = 5.5 V
10.0
μA
VDDEXT = 3.6 V, VIN = 0 V
10.0
μA
IOZHTWI
Three-State Leakage Current
IOZL
Three-State Leakage Current3
5
fIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V
TBD
VDDINT Current in Deep Sleep Mode
VDDINT = TBD V, fCCLK = 0 MHz,
fSCLK = 0 MHz, TJ = 25°C,
ASF = 0.00
TBD
mA
IDDSLEEP
VDDINT Current in Sleep Mode
VDDINT = TBD V, fSCLK = 25 MHz,
TJ = 25°C
TBD
mA
IDD-IDLE
VDDINT Current in Idle
VDDINT = TBD V, fCCLK = 50 MHz,
TJ = 25°C, ASF = TBD
TBD
mA
IDD-TYP
VDDINT Current
VDDINT = TBD V, fCCLK = 400 MHz,
TJ = 25°C, ASF = 1.00
TBD
mA
IDDHIBERNATE8
Hibernate State Current
VDDEXT = 3.30 V,
VDDFLASH =1.8 V, TJ = 25°C,
CLKIN = 0 MHz (VDDINT = 0 V)
TBD
μA
IDDSLEEP9
VDDINIT Current in Sleep Mode
fCCLK = 0 MHz, fSCLK > 0 MHz
mA10
Table 18 +
(TBD × VDDINT ×
fSCLK)
IDDDEEPSLEEP9
VDDINT Current in Deep Sleep Mode
fCCLK = 0 MHz, fSCLK = 0 MHz
Table 18
VDDINT Current
fCCLK > 0 MHz, fSCLK ≥ 0 MHz
mA
Table 18 +
(Table 19 ×
ASF) +
(TBD × VDDINT ×
fSCLK)
CIN
Input Capacitance
IDDDEEPSLEEP7
IDDINT
9
IDDFLASH1
TBD
6
pF
mA
Flash Memory Supply Current 1
— Asynchronous Read (5 MHz NORCLK11)
10
20
mA
4 Word
Flash Memory Supply Current 1
— Synchronous Read (50 MHz NORCLK11) 8 Word
18
20
mA
20
22
mA
16 Word
25
27
mA
Continuous
28
30
mA
IDDFLASH2
Flash Memory Supply Current 2
— Reset/Powerdown
15
50
μA
IDDFLASH3
Flash Memory Supply Current 3
— Standby
15
50
μA
Rev. PrC
| Page 27 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Parameter
Test Conditions
Min
Typical
Max
Unit
IDDFLASH4
Flash Memory Supply Current 4
— Automatic Standby
15
50
μA
IDDFLASH5
Flash Memory Supply Current 5
— Program
15
40
mA
Flash Memory Supply Current 5
— Erase
15
40
mA
Program/Erase in one bank,
asynchronous read in
another bank
25
60
mA
Program/Erase in one bank,
synchronous read in another
bank
43
70
mA
15
50
μA
IDDFLASH6
IDDFLASH7
Flash Memory Supply Current 6
— Dual Operations
Flash Memory Supply Current 7
— Program/Erase Suspended (Standby)
1
Applies to input pins.
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
3
Applies to three-statable pins.
4
Applies to bidirectional pins SCL and SDA.
5
Applies to all signal pins.
6
Guaranteed, but not tested.
7
See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8
Applies to VDDEXT supply only. Clock inputs are tied high or low.
9
Guaranteed maximum specifications.
10
Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder.
11
See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of NORCLK.
2
Rev. PrC
| Page 28 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Total Power Dissipation
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 19 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Processor — Electrical Characteristics on
Page 27 shows the current dissipation for internal circuitry
(VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 18), and
IDDINT specifies the total power specification for the listed test
conditions, including the dynamic component as a function of
voltage (VDDINT) and frequency (Table 19).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 17).
Table 17. Activity Scaling Factors (ASF)1
IDDINT Power Vector
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
1
Activity Scaling Factor (ASF)
TBD
TBD
TBD
TBD
TBD
TBD
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF50x
processors.
Table 18. Preliminary ADSP-BF50x Static Current — IDD-DEEPSLEEP (mA)
1
TJ (°C)
–40
–20
0
25
40
55
70
85
100
105
1
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Voltage (VDDINT)1
TBD V
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
Valid temperature and voltage ranges are model-specific. See Processor — Operating Conditions on Page 25.
Table 19. Preliminary ADSP-BF50x Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
fCCLK
(MHz)2
400
300
200
100
1
2
TBD V
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
Voltage (VDDINT)2
TBD V
TBD V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD V
TBD
TBD
TBD
TBD
The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Processor — Electrical Characteristics
on Page 27.
Valid frequency and voltage ranges are model-specific. See Processor — Operating Conditions on Page 25.
Rev. PrC
| Page 29 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
PROCESSOR — ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses greater than those listed in Table 20 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
The information presented in Figure 9 and Table 22 provides
details about the package branding for the ADSP-BF50x processors. For a complete listing of product availability, see Ordering
Guide on Page 79.
a
ADSP-BF50x
Table 20.
tppZccc
Parameter
Internal Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage1, 2
Input Voltage1, 2, 3
Output Voltage Swing
Storage Temperature Range
Junction Temperature While Biased
Rating
–0.3 V to +1.5 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
–0.5 V to
VDDEXT +0.5 V
–65°C to +150°C
+110°C
vvvvvv.x n.n
#yyww country_of_origin
B
Figure 9. Product Information on Package
Table 22. Package Brand Information
Brand Key
ADSP-BF50x
t
pp
Z
ccc
vvvvvv.x
n.n
#
yyww
1
Applies to 100% transient duty cycle. For other duty cycles see Table 21.
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 Volts.
3
Applies to pins SCL and SDA.
2
Table 21. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)
–0.50
–0.70
–0.80
–0.90
–1.00
1
VIN Max (V)
+3.80
+4.00
+4.10
+4.20
+4.30
Maximum Duty Cycle
100 %
40%
25%
15%
10%
1
See product names in the Ordering Guide on Page 79.
Applies to all signal pins with the exception of CLKIN, XTAL, EXT_WAKE.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. PrC
Field Description
Product Name1
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliance Designator
Date Code
| Page 30 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
PROCESSOR — TIMING SPECIFICATIONS
Clock and Reset Timing
Table 23 and Figure 10 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 14 to
Table 16, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
speed grade.
Table 23. Clock and Reset Timing
Parameter
Timing Requirements
CLKIN Frequency1, 2, 3, 4
fCKIN
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulse Width Low5
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF Delay
Min
Max
Unit
12
10
10
11 × tCKIN
50
MHz
ns
ns
ns
10
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 14 on Page 26 through
Table 16 on Page 26.
3
The tCKIN period (see Figure 10) equals 1/fCKIN.
4
If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz.
5
Applies after power-up sequence is complete. See Table 24 and Figure 11 for power-up reset timing.
tCKIN
CLKIN
tCKINL
tBUFDLAY
tCKINH
CLKBUF
tWRST
RESET
Figure 10. Clock and Reset Timing
Rev. PrC
| Page 31 of 80 | January 2010
tBUFDLAY
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 24. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RESET Deasserted after the VDDINT, VDDEXT, VDDFLASH, and CLKIN Pins are Stable and
Within Specification
tRST_IN_PWR
RESET
V
,V
DDINT
CLKIN
,V
DDFLASH
DDEXT
Figure 11. Power-Up Reset Timing
Rev. PrC
| Page 32 of 80 | January 2010
3500 × tCKIN
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Parallel Peripheral Interface Timing
Table 25 and Figure 12 on Page 33, Figure 18 on Page 39, and
Figure 20 on Page 40 describe parallel peripheral interface
operations.
Table 25. Parallel Peripheral Interface Timing
Min
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width1
tPCLK
PPI_CLK Period1
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
VDDEXT = 1.8 V
Max
Min
6.4
20
ns
ns
6.7
6.7
ns
1.0
3.5
1.5
1.0
3.5
1.5
ns
ns
ns
8.8
1.7
1.7
9.8
8.8
1.8
1.8
PPI_CLK frequency cannot exceed fSCLK/2
DATA1 IS
SAMPLED
PPI_CLK
POLC = 0
tPCLKW
PPI_CLK
POLC = 1
tSFSPE
tHFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE
tHDRPE
PPI_DATA
Figure 12. PPI GP Rx Mode with External Frame Sync Timing
Rev. PrC
Unit
6.4
20
9.8
DATA0 IS
SAMPLED
VDDEXT = 2.5/3.3 V
Max
| Page 33 of 80 | January 2010
tPCLK
ns
ns
ns
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
DATA DRIVING/
FRAME SYNC
SAMPLING EDGE
DATA DRIVING/
FRAME SYNC
SAMPLING EDGE
PPI_CLK
POLC = 0
tPCLKW
PPI_CLK
POLC = 1
tSFSPE
tHFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
tHDTPE
PPI_DATA
Figure 13. PPI GP Tx Mode with External Frame Sync Timing
FRAME
SYNC IS
DRIVEN
OUT
DATA0 IS
SAMPLED
PPI_CLK
POLC = 0
tPCLKW
tPCLK
PPI_CLK
POLC = 1
tHOFSPE
tDFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE
tHDRPE
PPI_DATA
Figure 14. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrC
| Page 34 of 80 | January 2010
tPCLK
Preliminary Technical Data
FRAME
SYNC IS
DRIVEN
OUT
ADSP-BF504/F,ADSP-BF506F
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
tPCLKW
PPI_CLK
POLC = 1
tHOFSPE
tDFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
tHDTPE
DATA0
PPI_DATA
Figure 15. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrC
| Page 35 of 80 | January 2010
tPCLK
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
RSI Controller Timing
Table 26 and Figure 16 describe RSI Controller Timing.
Table 27 and Figure 17 describe RSI controller (high speed)
timing.
Table 26. RSI Controller Timing
Parameter
Timing Requirements
Input Setup Time
tISU
Input Hold Time
tIH
Switching Characteristics
Clock Frequency Data Transfer Mode
fPP1
Clock Frequency Identification Mode
fOD
tWL
Clock Low Time
Clock High Time
tWH
Clock Rise Time
tTLH
tTHL
Clock Fall Time
Output Delay Time During Data Transfer Mode
tODLY
Output Delay Time During Identification Mode
tODLY
1
2
Min
Max
5.6
2
ns
ns
0
1002
15
15
25
400
10
10
14
50
tPP = 1/fPP
Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
tPP
SD_CLK
VOH (MIN)
tTHL
tISU
tTLH
tWL
tIH
tWH
INPUT
tODLY
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 16. RSI Controller Timing
Rev. PrC
| Page 36 of 80 | January 2010
Unit
VOL (MAX)
MHz
kHz
ns
ns
ns
ns
ns
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Table 27. RSI Controller Timing (High Speed Mode)
Parameter
Timing Requirements
Input Setup Time
tISU
Input Hold Time
tIH
Switching Characteristics
Clock Frequency Data Transfer Mode
fPP1
Clock Low Time
tWL
Clock High Time
tWH
tTLH
Clock Rise Time
Clock Fall Time
tTHL
Output Delay Time During Data Transfer Mode
tODLY
tOH
Output Hold Time
1
Min
Max
5.6
2
ns
ns
0
9.5
9.5
50
3
3
TBD
2.5
tPP = 1/fPP
tPP
SD_CLK
VOH (MIN)
tTHL
tISU
tTLH
tWL
tIH
tWH
INPUT
tODLY
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 17. RSI Controller Timing (High-Speed Mode)
Rev. PrC
| Page 37 of 80 | January 2010
Unit
tOH
VOL (MAX)
MHz
ns
ns
ns
ns
ns
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Serial Ports
Table 28 through Table 31 on Page 40 and Figure 18 on Page 39
through Figure 20 on Page 40 describe serial port operations.
Table 28. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE
Receive Data Setup Before RSCLKx1,2
Receive Data Hold After RSCLKx1,2
tHDRE
tSCLKEW
TSCLKx/RSCLKx Width
tSCLKE
TSCLKx/RSCLKx Period
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tDDTE
Transmit Data Delay After TSCLKx3
tHDTE
Transmit Data Hold After TSCLKx3
Min
VDDEXT = 1.8 V
Max
3.0
3.0
3.0
3.6
5.4
18.0
VDDEXT = 2.5/3.3 V
Min
Max
Unit
3.0
3.0
3.0
3.6
5.4
18.0
ns
ns
ns
ns
ns
ns
12.5
0.0
12.0
0.0
12.5
0.0
ns
ns
12.0
0.0
ns
ns
1
Referenced to sample edge.
When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 39 (ACM Timing).
3
Referenced to drive edge.
2
Table 29. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx1
Receive Data Setup Before RSCLKx1,2
tSDRI
tHDRI
Receive Data Hold After RSCLKx1,2
Switching Characteristics
tSCLKIW
TSCLKx/RSCLKx Width
tSCLKI
TSCLKx/RSCLKx Period
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
tDDTI
Transmit Data Delay After TSCLKx3
tHDTI
Transmit Data Hold After TSCLKx3
Min
VDDEXT = 1.8 V
Max
VDDEXT = 2.5/3.3 V
Max
Unit
12.4
–1.5
12.4
–1.5
11.3
–1.5
11.3
–1.5
ns
ns
ns
ns
5.4
18.0
5.4
18.0
ns
ns
ns
3.0
–4.0
3.0
–4.0
3.0
–1.8
1
Referenced to sample edge.
When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 39 (ACM Timing).
3
Referenced to drive edge.
2
Rev. PrC
Min
| Page 38 of 80 | January 2010
ns
3.0
–1.8
ns
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKEW
tSCLKIW
RSCLKx
RSCLKx
tDFSE
tDFSI
tHOFSI
tHFSI
tSFSI
RFSx
tSFSE
tHOFSE
tHFSE
RFSx
tSDRE
tHDRI
tSDRI
DRx
tHDRE
DRx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
SAMPLE EDGE
t SCLKEW
TSCLKx
tSCLKE
TSCLKx
tDFSI
tHOFSI
tDFSE
tSFSI
tHOFSE
tHFSI
TFSx
tSFSE
tHFSE
TFSx
tDDTE
tDDTI
tHDTI
tHDTE
DTx
DTx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 18. Serial Ports
Table 30. Serial Ports—Enable and Three-State
Min
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1
tDTENI
Data Enable Delay from Internal TSCLKx1
tDDTTI
Data Disable Delay from Internal TSCLKx1
1
VDDEXT=1.8 V
Max
0.0
–2.0
DRIVE
TSCLKx
tDTENE/I
tDDTTE/I
DTx
Figure 19. Serial Ports — Enable and Three-State
| Page 39 of 80 | January 2010
10.0
–2.0
3.0
DRIVE
VDDEXT=2.5/3.3 V
Max
0.0
10.0
Referenced to drive edge.
Rev. PrC
Min
3.0
Unit
ns
ns
ns
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 31. Serial Ports — External Late Frame Sync
Min
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx
or External RFSx in Multi-channel Mode With MFD = 01, 2
tDTENLFSE
Data Enable from External RFSx in Multi-channel Mode With 0.0
MFD = 01, 2
1
2
VDDEXT=1.8 V
Max
11.2
EXTERNAL RFSx IN MULTI-CHANNEL MODE WITH MCE = 1
SAMPLE
DRIVE
RSCLKx
tSFSE/I
tHOFSE/I
RFSx
tDDTLFSE
tDTENLFSE
1ST BIT
DTx
LATE EXTERNAL TFSx
SAMPLE
DRIVE
DRIVE
TSCLKx
tSFSE/I
tHOFSE/I
TFSx
tDDTLFSE
1ST BIT
DTx
Figure 20. Serial Ports — External Late Frame Sync
Rev. PrC
| Page 40 of 80 | January 2010
VDDEXT=2.5/3.3 V
Max
10.0
0.0
When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
DRIVE
Min
Unit
ns
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Serial Peripheral Interface (SPI) Port—Master Timing
Table 32 and Figure 21 describe SPI port master operations.
Table 32. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
tHSPIDM
Switching Characteristics
tSDSCIM
SPISELx low to First SCK Edge
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
Last SCK Edge to SPISELx High
tHDSM
tSPITDM
Sequential Transfer Delay
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
Min
VDDEXT = 1.8 V
Max
Min
VDDEXT = 2.5/3.3 V
Max
12.0
–1.5
11.6
–1.5
ns
ns
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
ns
ns
ns
ns
ns
ns
ns
6
6
–1.0
–1.0
SPISELx
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tHDSPIDM
MOSI
(OUTPUT)
tDDSPIDM
LSB
MSB
tSSPIDM
CPHA = 1
tHSPIDM
MSB
VALID
MISO
(INPUT)
LSB VALID
tHDSPIDM
MOSI
(OUTPUT)
CPHA = 0
MISO
(INPUT)
tDDSPIDM
MSB
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrC
Unit
| Page 41 of 80 | January 2010
tSPITDM
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 33 and Figure 22 describe SPI port slave operations.
Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
Serial Clock Low Period
tSPICLS
tSPICLK
Serial Clock Period
tHDS
Last SCK Edge to SPISS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
tHSPID
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
tDSDHI
SPISS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Min
VDDEXT = 1.8 V
Max
Min
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
1.6
0
0
VDDEXT = 2.5/3.3 V
Max
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
1.6
12.0
8.5
10
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
12.0
8.5
10
0
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
SCKx
(CPOL = 0)
(INPUT)
tSPICLS
tSDSCI
tSPICHS
SCKx
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
MISOx
(OUTPUT)
tSSPID
MOSIx
(INPUT)
tDSDHI
LSB
tHSPID
MSB VALID
tDSOE
LSB VALID
tHDSPID
tDDSPID
tDSDHI
MSB
LSB
CPHA = 0
MOSIx
(INPUT)
tDDSPID
MSB
CPHA = 1
MISOx
(OUTPUT)
tHDSPID
tHSPID
tSSPID
MSB VALID
LSB VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrC
| Page 42 of 80 | January 2010
Unit
tSPITDS
ns
ns
ns
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF50x Hardware Reference Manual.
General-Purpose Port Timing
Table 34 and Figure 23 describe general-purpose
port operations.
Table 34. General-Purpose Port Timing
Min
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
tSCLK + 1
Switching Characteristic
tGPOD
General-Purpose Port Pin Output Delay from CLKOUT High 0
VDDEXT = 1.8 V
Max
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 23. General-Purpose Port Timing
Rev. PrC
| Page 43 of 80 | January 2010
Min
VDDEXT = 2.5/3.3 V
Max
tSCLK + 1
9.66
0
Unit
ns
9.66
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Timer Cycle Timing
Table 35 and Figure 24 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 35. Timer Cycle Timing
Min
Parameter
Timing Requirements
tWL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High
(Measured In SCLK Cycles)1
tTIS
Timer Input Setup Time Before CLKOUT Low2
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
VDDEXT = 1.8 V
Max
Min
VDDEXT = 2.5/3.3 V
Max
Unit
1 × tSCLK
1 × tSCLK
ns
1 × tSCLK
1 × tSCLK
ns
5
–2
5
–2
ns
ns
1 × tSCLK
(232–1)tSCLK
8.1
1
1 × tSCLK
(232–1)tSCLK
ns
8.1
ns
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
TMRx INPUT
tWH,tWL
Figure 24. Timer Cycle Timing
Rev. PrC
| Page 44 of 80 | January 2010
tHTO
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Timer Clock Timing
Table 36 and Figure 25 describe timer clock timing.
Table 36. Timer Clock Timing
Min
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
VDDEXT = 1.8 V
Max
Min
VDDEXT = 2.5/3.3 V
Max
12.0
12.0
Unit
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 25. Timer Clock Timing
Up/Down Counter/Rotary Encoder Timing
Table 37. Up/Down Counter/Rotary Encoder Timing
Parameter
Timing Requirements
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
tCIS
Counter Input Setup Time Before CLKOUT High1
tCIH
Counter Input Hold Time After CLKOUT High1
1
Min
VDDEXT = 1.8 V
Max
tSCLK + 1
5.5
4.0
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLKOUT
tCIS
tCIH
CUD/CDG/CZM
tWCOUNT
Figure 26. Up/Down Counter/Rotary Encoder Timing
Rev. PrC
| Page 45 of 80 | January 2010
Min
VDDEXT = 2.5/3.3 V
Max
tSCLK + 1
4.0
4.0
Unit
ns
ns
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Pulse Width Modulator (PWM) Timing
Table 38 and Figure 27 describe PWM operations.
Table 38. PWM Timing
VDDEXT = 1.8 V
Parameter
Min
Max
VDDEXT = 2.5/3.3 V
Min
Max
Unit
Timing Requirements
tES
External Sync Pulse Width
2 × tSCLK + 1
2 × tSCLK + 1
ns
Switching Characteristics
tDODIS
Output1 Inactive (OFF) After Trip Input
1
TBD
2
tDOE
Output Delay After External Sync
tOD
Output1 Delay After Falling Edge of CLKOUT
1
2
3 × tSCLK + tOD
5 × tSCLK + tOD
3 × tSCLK + tOD
TBD
TBD
ns
5 × tSCLK + tOD
ns
TBD
ns
PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
When the external sync signal is synchronous to the peripheral clock, it takes 3 cycles for the output to appear. When the external sync signal is asynchronous to the peripheral
clock, it takes 5 cycles for the output to appear.
CLKOUT
PWMx_SYNC
(AS INPUT)
tES
tOD
tDOE
OUTPUT
tDODIS
PWMx_TRIP
Figure 27. PWM Timing
Rev. PrC
| Page 46 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
ADC Controller Module (ACM) Timing
Table 39 and Figure 28 describe ACM operations.
f SCLK
f ACLK = -------------------------------------------------------( 2 × ACMCKDIV ) + 2
Note that the ACM clock (ACLK) frequency in MHz is set by
the following equation (in which ACMCKDIV ranges from
0 to 255).
1
t ACLK = -------------f ACLK
Table 39. ACM Timing
VDDEXT = 1.8 V
Min
Parameter
Max
VDDEXT = 2.5/3.3 V
Min
Max
Units
Timing Requirements
tSDR
SPORT DRxPRI/DRxSEC Setup Before ACLK
7
7
ns
tHDR
SPORT DRxPRI/DRxSEC Hold After ACLK
0
0
ns
Switching Characteristics
tDO
ACM Controls (ACM_A[2:0], ACM_RANGE, ACM_SGLDIFF) Delay
After Falling Edge of CLKOUT
8.4
8.4
ns
tDACLK
ACLK Delay After Falling Edge of CLKOUT
8.4
8.4
ns
tDCS
CS Active Edge Delay After Falling Edge of CLKOUT
5.3
ns
tDCSACLK The Delay Between the Active Edge of CS and the First Edge of
ACLK
5.3
tACLK
tACLK
CLKOUT
tDCS
CS
tDACLK
tDCSACLK
ACLK
tDO
ACM
CONTROLS
tSDR
tHDR
DRxPRI/
DRxSEC
Figure 28. ACM Timing
Rev. PrC
| Page 47 of 80 | January 2010
ns
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 40 and Figure 29 describe JTAG port operations.
Table 40. JTAG Port Timing
Min
Parameter
Timing Requirements
tTCK
TCK Period
TDI, TMS Setup Before TCK High
tSTAP
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
VDDEXT = 1.8 V
Max
20
4
4
4
5
4
System Inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, NMI, BMODE3–0, RESET, PG.
50 MHz Maximum
3
System Outputs = EXTCLK, SCL, SDA, PF15–0, PG15–0, PH2–0.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 29. JTAG Port Timing
Rev. PrC
| Page 48 of 80 | January 2010
VDDEXT = 2.5/3.3 V
Max
20
4
4
4
5
4
10
12.6
1
Min
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
PROCESSOR — OUTPUT DRIVE CURRENTS
DA
TA
TB
D
DA
TA
TB
D
Figure 30 through Figure 44 show typical current-voltage characteristics for the output drivers of the ADSP-BF50x processors.
Figure 34. Driver Type B Current (2.5V VDDEXT)
DA
TA
TB
D
DA
TA
TB
D
Figure 30. Driver Type A Current (3.3V VDDEXT)
Figure 35. Driver Type B Current (1.8V VDDEXT)
DA
TA
TB
D
DA
TA
TB
D
Figure 31. Driver Type A Current (2.5V VDDEXT)
Figure 36. Driver Type C Current (3.3V VDDEXT)
Figure 32. Driver Type A Current (1.8V VDDEXT)
DA
TA
TB
D
The curves represent the current drive capability of the output
drivers. See Table 11 on Page 21 for information about which
driver type corresponds to a particular pin.
DA
TA
TB
D
Figure 37. Drive Type C Current (2.5V VDDEXT)
Figure 33. Driver Type B Current (3.3V VDDEXT)
Rev. PrC
| Page 49 of 80 | January 2010
Preliminary Technical Data
DA
TA
DA
TA
TB
D
TB
D
ADSP-BF504/F,ADSP-BF506F
Figure 42. Driver Type E Current (3.3V VDDEXT)
DA
TA
DA
TA
TB
TB
D
D
Figure 38. Driver Type C Current (1.8V VDDEXT)
Figure 43. Driver Type E Current (2.5V VDDEXT)
DA
TA
DA
TA
TB
D
TB
D
Figure 39. Driver Type D Current (3.3V VDDEXT)
Figure 40. Driver Type D Current (2.5V VDDEXT)
Figure 44. Driver Type E Current (1.8V VDDEXT)
PROCESSOR — TEST CONDITIONS
DA
TA
TB
D
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 45
shows the measurement point for AC measurements (except
output enable/disable). The measurement point VMEAS is VDDEXT/2
for VDDEXT (nominal) = 1.8 V/2.5 V/3.3 V.
INPUT
OR
OUTPUT
VMEAS
Figure 41. Driver Type D Current (1.8V VDDEXT)
Figure 45. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Rev. PrC
| Page 50 of 80 | January 2010
VMEAS
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 46.
REFERENCE
SIGNAL
tDIS_MEASURED
tDIS
tENA_MEASURED
VOL
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
tDECAY
OUTPUT STOPS DRIVING
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be
tDECAY plus the various output disable times as specified in the
Processor — Timing Specifications on Page 31.
Capacitive Loading
tENA
VOH
(MEASURED)
The time tDIS_MEASURED is the interval from when the reference signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
tTRIP
OUTPUT STARTS DRIVING
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 47). VLOAD is equal
to (VDDEXT) /2. The graphs of Figure 48 through Figure 55 show
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
HIGH IMPEDANCE STATE
TESTER PIN ELECTRONICS
Figure 46. Output Enable/Disable
50:
VLOAD
The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or
VTRIP(low). For VDDEXT (nominal) = 1.8V, VTRIP (high) is 1.05V,
and VTRIP (low) is 0.75V. For VDDEXT (nominal) = 2.5V, VTRIP
(high) is 1.5V and VTRIP (low) is 1.0V. For VDDEXT (nominal) =
3.3V, VTRIP (high) is 1.9V, and VTRIP (low) is 1.4V. Time tTRIP is
the interval from when the output starts driving to when the
output reaches the VTRIP(high) or VTRIP(low) trip voltage.
T1
45:
DUT
OUTPUT
70:
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
0.5pF
4pF
2pF
400:
Time tENA is calculated as shown in the equation:
t ENA = t ENA_MEASURED – t TRIP
If multiple pins are enabled, the measurement value is that of
the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left side
of Figure 46.
t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay time
can be approximated by the equation:
t DECAY = ( C L ΔV ) ⁄ I L
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 47. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
T
TA
A
D
Figure 48. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver A at VDDEXT = Min
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for VDDEXT (nominal) = 2.5 V/3.3 V and 0.15 V
for VDDEXT (nominal) = 1.8V.
Rev. PrC
BD
| Page 51 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
TCASE = Case temperature (°C) measured by customer at top
center of package.
D
TB
A
T
DA
ΨJT = From Table 41 and Table 42.
Figure 49. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver A at VDDEXT = Max
PD = Power dissipation (see Total Power Dissipation on Page 29
for the method to calculate PD).
Table 41. Thermal Characteristics (88-Lead LFCSP)
D
TB
A
T
DA
Figure 50. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver B at VDDEXT = Min
D
TB
A
T
DA
Figure 51. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver B at VDDEXT = Max
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
26.2
23.7
22.9
16.0
9.8
0.21
0.36
0.43
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 42. Thermal Characteristics (120-Lead LQFP)
D
TB
A
T
DA
Figure 52. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver C at VDDEXT = Min
D
TB
A
T
DA
Figure 53. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver C at VDDEXT = Max
D
TB
A
T
DA
Parameter
θJA
θJMA
θJMA
θJB
θJC
ΨJT
ΨJT
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
26.9
24.2
23.3
16.4
12.7
0.50
0.77
1.02
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
Figure 54. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver D at VDDEXT = Min
where:
TA = Ambient temperature (°C)
D
TB
A
T
DA
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Figure 55. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver D at VDDEXT = Max
Values of θJB are provided for package comparison and printed
circuit board design considerations.
PROCESSOR — ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
In Table 41 and Table 42, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6, and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883 (Method
1012.1). All measurements use a 2S2P JEDEC test board.
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature (°C).
Rev. PrC
| Page 52 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The program and erase times and the number of program/ erase
cycles per block are shown in Table 43. Exact erase times may
change depending on the memory array condition. The best
case is when all the bits in the block or bank are at ‘0’ (pre pro-
grammed). The worst case is when all the bits in the block or
bank are at ‘1’ (not pre programmed). Usually, the system overhead is negligible with respect to the erase time.
Table 43. Program/Erase Times and Endurance Cycles
Parameter
Condition
Typ
Erase
Parameter Block (4K word)1
Main Block (32K word)
Pre Programmed
Not Pre Programmed
Word
Parameter Block (4K word)
Main Block (32K word)
Program
Erase
Main Blocks
Parameter Blocks
0.3
Program2
Suspend Latency
Program/Erase
Cycles (per Block)
1
2
0.8
1
12
40
300
5
5
Typ after 100 k
W/E cycles
1
3
12
The difference between pre programmed and not pre programmed is not significant (< 30 ms).
Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).
FLASH – ABSOLUTE MAXIMUM RATINGS
Table 44 shows the ADC absolute maximum ratings.
Table 44. Flash Absolute Maximum Ratings
Parameter
Junction Temperature While Biased
Rating
See Table 20 on
Page 30
Storage Temperature Range
–65°C to +150°C
Flash Memory Supply Voltage (VDDFLASH) –0.2 V to +2.45 V
Rev. PrC
| Page 53 of 80 | January 2010
Max
Unit
2.5
s
4
4
100
s
s
μs
ms
ms
μs
μs
Cycles
Cycles
10
20
100,000
100,000
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
ADC — SPECIFICATIONS
ADC — OPERATING CONDITIONS
Parameter
VDD1 (AVDD, DVDD, VDRIVE)
Conditions
fADSCLK = 24 MHz, fS up to 1.5 MSPS, internal or
external reference = 2.5 V ± 1% unless
otherwise noted
VDD (AVDD, DVDD, VDRIVE)
fADSCLK = 32 MHz, fS up to 2.0 MSPS, internal or
external reference = 2.5 V ± 1% unless
otherwise noted
TJ Junction Temperature 120-Lead LQFP @ TAMBIENT = –40°C to +85°C
1
Min
2.7
Nominal
Max
3.6
Unit
V
4.75 (AVDD, DVDD)
2.7 (VDRIVE)
5.25 (AVDD, DVDD)
5.25 (VDRIVE)
V
V
–40
+105
°C
Throughout this datasheet, VDD refers to both AVDD and DVDD.
Table 45. Operating Conditions (Analog, Voltage Reference, and Logic I/O)
Parameter
ANALOG INPUT1
Single-Ended Input Range
Pseudo Differential Input Range: VIN+ – VIN–2
Fully Differential Input Range: VIN+ and VIN–
DC Leakage Current
Input Capacitance4
INTERNAL VOLTAGE REFERENCE (OUTPUT)5
Reference Output Voltage
Long-Term Stability
Output Voltage Hysteresis6
DCAPA, DCAPB Output Impedance
Reference Temperature Coefficient
VREF Noise
EXTERNAL VOLTAGE REFERENCE (INPUT)5
Reference Input Voltage Range7
DC Leakage Current7
Input Capacitance
DIGITAL LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
Specification
Unit
Test Conditions/Comments
0 V to VREF
0 V to 2 × VREF
0 to VREF
2 × VREF
VCM ± VREF/2
VCM ± VREF
±1
45
10
V
V
V
V
V
V
μA max
pF typ
pF typ
RANGE= low
RANGE = high
RANGE = low
RANGE = high
VCM = common-mode voltage3 = VREF/2, RANGE = low
VCM = VREF, RANGE = high
VA1 to VA6, VB1 to VB6
When in track
When in hold
2.5 ± 0.2%
150
50
10
20
20
V
@ 25°C, AVDD = 2.7 V to 5.25 V
ppm typ
For 1000 hours
ppm typ
Ω typ
ppm/°C max 10ppm/°C typ
μV rms typ
0.1/AVDD
±2
25
V min/V max See ADC — Typical Performance Characteristics
μA max
External reference applied to Pin DCAPA/Pin DCAPB
pF typ
2.8
0.4
±15
5
V min
V max
nA typ
pF typ
Rev. PrC
VIN = 0 V or VDRIVE
| Page 54 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Table 45. Operating Conditions (Analog, Voltage Reference, and Logic I/O) (Continued)
Parameter
DIGITAL LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance4
Output Coding8
Specification
Unit
Test Conditions/Comments
VDRIVE – 0.2
0.4
±1
7
Straight (natural) binary
Twos complement
V min
V max
μA max
pF typ
no DC load (IOH = 0 mA)
no DC load (IOL = 0 mA)
VIN = 0V or VDRIVE
SGL/DIFF = 1
SGL/DIFF = 0; SGL/DIFF = 1
1
VIN– or VIN+ must remain within GND/VDD.
VIN– = 0V for specified performance. For full input range on VIN– pin, see Figure 80 and Figure 81.
3
For full common-mode range, see Figure 76 and Figure 77.
4
Sample tested during initial release to ensure compliance.
5
Relates to Pin DCAPA or Pin DCAPB.
6
See ADC — Terminology on Page 60.
7
External voltage reference applied to Pins DCAPA, Pin DCAPB (VREF)
8
See Table 50 and Table 51.
2
Table 46. Operating Conditions (ADC Performance/Accuracy)
Parameter
DYNAMIC PERFORMANCE
Specification
Unit
Test Conditions/Comments
Signal-to-Noise Ratio (SNR)
71
69
dB min
dB min
fIN = 50 kHz sine wave; differential mode
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
fIN = 50 kHz sine wave; differential mode
Signal-to-(Noise + Distortion) Ratio (SINAD)1 70
dB min
68
dB min
Total Harmonic Distortion (THD)1
–77
–73
dB max
dB max
Spurious-Free Dynamic Range (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
SAMPLE AND HOLD
Aperture Delay2
Aperture Jitter2
Aperture Delay Matching2
Full Power Bandwidth
–75
dB max
–88
–88
–88
dB typ
dB typ
dB typ
11
50
200
33/26
3.5/3
ns max
ps typ
ps max
MHz typ
MHz typ
Rev. PrC
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
fIN = 50 kHz sine wave; differential mode
fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
fIN = 50 kHz sine wave
fa = 30 kHz, fb = 50 kHz
@ 3 dB, AVDD, DVDD = 5 V/AVDD, DVDD = 3 V
@ 0.1 dB, AVDD, DVDD = 5 V/AVDD, DVDD = 3 V
| Page 55 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 46. Operating Conditions (ADC Performance/Accuracy) (Continued)
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1, 3
Straight Natural Binary Output Coding
Offset Error1
Offset Error Match1
Gain Error1
Gain Error Match1
Twos Complement Output Coding
Positive Gain Error1
Positive Gain Error Match1
Zero Code Error1
Zero Code Error Match1
Negative Gain Error1
Negative Gain Error Match1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
Specification
Unit
Test Conditions/Comments
12
±1
±1.5
Bits
LSB max
LSB max
±0.99
–0.99/+1.5
LSB max
LSB max
TBD
TBD
TBD
TBD
LSB max
LSB typ
LSB max
LSB typ
TBD
TBD
TBD
LSB max
LSB typ
LSB max
TBD
TBD
TBD
LSB typ
LSB max
LSB typ
14
90
110
2
ADSCLK cycles 437.5 ns with ADSCLK = 32 MHz
ns max
Full-scale step input; AVDD, DVDD = 5 V
ns max
Full-scale step input; AVDD, DVDD = 3 V
MSPS max
±0.7 LSB typ; differential mode
±0.9 LSB typ; single-ended and pseudo
differential modes
Differential mode
Single-ended and pseudo differential modes
1
See ADC — Terminology on Page 60.
Sample tested during initial release to ensure compliance.
3
Guaranteed no missed codes to 12 bits.
2
Table 47. Operating Conditions (Power1)
Parameter
POWER SUPPLY REQUIREMENTS
VDD
VDRIVE
IDD
Normal Mode (Static)
Operational
fS = 2 MSPS
fS = 1.5 MSPS
Partial Power-Down Mode
Full Power-Down Mode (VDD)
POWER DISSIPATION
Normal Mode (Operational)
Partial Power-Down (Static)
Full Power-Down (Static)
1
Specification
Unit
Test Conditions/Comments
2.7/5.25
2.7/5.25
V min/V max
V min/V max
2.3
mA max
6.4
4
500
2.8
mA max
mA max
μA max
μA max
VDD = 5.25 V; 5.7 mA typ
VDD = 3.6 V; 3.4 mA typ
Static
33.6
2.625
14.7
mW max
mW max
μW max
VDD = 5.25 V
VDD = 5.25 V
VDD = 5.25 V
Digital Logic Inputs = 0 V or VDRIVE
VDD = 5.25 V
In this table, VDD refers to both AVDD and DVDD.
Rev. PrC
| Page 56 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
ADC — TIMING SPECIFICATIONS
Table 48. Serial Data Interface1
Parameter
fADSCLK2
tCONVERT
tQUIET
t2
t3
t4 3
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
4/32
14 × tADSCLK
437.5
583.3
30
20/30
15
27/36
0.45 tADSCLK
0.45 tADSCLK
5/10
15
30
5/35
Unit
MHz min/max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min/max
Description/Conditions
tADSCLK = 1/fADSCLK
fADSCLK = 32 MHz, fSAMPLE = 2 MSPS; AVDD, DVDD = 5 V
fADSCLK = 24 MHz, fSAMPLE = 1.5 MSPS; AVDD, DVDD = 3 V
Minimum time between end of serial read and next falling edge of CS
CS to ADSCLK setup time; VDRIVE = 5 V/3 V
Delay from CS until DOUTA and DOUTB are three-state disabled
Data access time after ADSCLK falling edge, VDRIVE = 5 V/3 V
ADSCLK low pulse width
ADSCLK high pulse width
ADSCLK to data valid hold time, VDRIVE = 5 V/3 V
CS rising edge to DOUTA, DOUTB, high impedance
CS rising edge to falling edge pulse width
ADSCLK falling edge to DOUTA, DOUTB, high impedance
1
See also Figure 93 on Page 71 and Figure 94 on Page 71.
Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
2
ADC — ABSOLUTE MAXIMUM RATINGS
Stresses above those listed in Table 49 may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 49. Absolute Maximum Ratings
Parameter
AVDD, DVDD to AGND
DVDD to DGND
VDRIVE to DGND
VDRIVE to AGND
AVDD to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
VREF to AGND
Input Current to Any ADC Pin
Except Supplies1
Storage Temperature Range
Junction Temperature Under Bias
1
Rating
–0.3 V to +7 V
–0.3 V to +7 V
–0.3 V to DVDD
–0.3 V to AVDD
–0.3 V to +0.3 V
–0.3 V to +0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to +7 V
–0.3 V to VDRIVE + 0.3 V
–0.3 V to AVDD + 0.3 V
±10 mA
–65°C to +150°C
+110°C
Transient currents of up to 100 mA will not cause latch up.
Rev. PrC
| Page 57 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
ADC — TYPICAL PERFORMANCE
CHARACTERISTICS
4096 POINT FFT
VDD = 5V, VDRIVE = 3V
FSAMPLE = 2MSPS
FIN = 52kHz
SINAD = 71.4dB
THD = –84.42dB
DIFFERENTIAL MODE
–10
TA = 25°C, unless otherwise noted.
–30
–60
INTERNAL REFERENCE
(dB)
–50
–70
–70
PSRR (dB)
–80
EXTERNAL REFERENCE
–90
–90
–110
–100
–110
–120
200
100
200
300
400 500 600 700
FREQUENCY (kHz)
800
900
1000
Figure 59. FFT
100mV p-p SINE WAVE ON AVDD
NO DECOUPLING
SINGLE-ENDED MODE
0
0
1.0
400 600 800 1000 1200 1400 1600 1800 2000
SUPPLY RIPPLE FREQUENCY (kHz)
VDD = 5V, VDRIVE = 3V
DIFFERENTIAL MODE
0.8
0.6
Figure 56. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
–50
DNL ERROR (LSB)
0.4
VDD = 5V
–55
–60
ISOLATION (dB)
–65
0.2
0
–0.2
–0.4
–70
–0.6
–75
–0.8
–80
–1.0
–85
0
500
–90
1000
1500
2000 2500
CODE
3000
3500
4000
Figure 60. Typical DNL
–95
–100
0
100
200
300 400 500 600 700
NOISE FREQUENCY (kHz)
800
900
1.0
1000
VDD = 5V, VDRIVE = 3V
DIFFERENTIAL MODE
0.8
0.6
Figure 57. Channel-to-Channel Isolation
74
VDD = 5V
DIFFERENTIAL MODE
INL ERROR (LSB)
0.4
RANGE = 0 TO VREF
72
VDD = 3V
DIFFERENTIAL MODE
SINAD (dB)
70
0.2
0
–0.2
–0.4
–0.6
68
–0.8
66
–1.0
0
64
1000
1500
2000 2500
CODE
Figure 61. Typical INL
62
60
500
0
500
1000
1500
2000
INPUT FREQUENCY (kHz)
2500
3000
Figure 58. SINAD vs. Analog Input Frequency for Various Supply Voltages
Rev. PrC
| Page 58 of 80 | January 2010
3000
3500
4000
Preliminary Technical Data
1.0
10000
VDD = 3V/5V
DIFFERENTIAL MODE
0.8
9000
POSITIVE DNL
0.4
POSITIVE INL
0.2
0
–0.2
NEGATIVE INL
–0.4
–0.6
7000
6000
5000
4000
3000
1000
0
0.5
1.0
1.5
2.0
0
2046
2.5
2047
2048
Figure 62. Linearity Error vs. VREF
2050
Figure 65. Histogram of Codes for 10k Samples in Differential Mode
12.0
10000
11.5
9000
11.0
INTERNAL
REFERENCE
SINGLE-ENDED
MODE
9984
CODES
8000
NO. OF OCCURRENCES
VDD = 5V
SINGLE-ENDED MODE
10.5
10.0
VDD = 3V
SINGLE-ENDED MODE
9.5
9.0
VDD = 3V
DIFFERENTIAL MODE
8.5
VDD = 5V
DIFFERENTIAL MODE
8.0
7000
6000
5000
4000
3000
2000
7.5
7.0
2049
CODE
VREF (V)
EFFECTIVE NUMBER OF BITS
DIFFERENTIAL
MODE
10000
CODES
2000
NEGATIVE DNL
–0.8
–1.0
INTERNAL
REFERENCE
8000
NO. OF OCCURRENCES
0.6
LINEARITY ERROR (LSB)
ADSP-BF504/F,ADSP-BF506F
1000
0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
3.5
4.0
4.5
0
2046
5.0
5 CODES
2047
11 CODES
2048
2049
2050
CODE
Figure 66. Histogram of Codes for 10k Samples in Single-Ended Mode
Figure 63. Effective Number of Bits vs. VREF
2.5010
–60
DIFFERENTIAL MODE
VDD = 3V/5V
–65
2.5005
–70
2.5000
VREF (V)
CMRR (dB)
–75
2.4995
2.4990
–80
–85
–90
2.4985
2.4980
–95
0
20
40
60
80
100 120 140
CURRENT LOAD (PA)
160
180
Figure 64. VREF vs. Reference Output Current Drive
Rev. PrC
200
–100
0
200
400
600
800
RIPPLE FREQUENCY (kHz)
1000
Figure 67. CMRR vs. Common-Mode Ripple Frequency
| Page 59 of 80 | January 2010
1200
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
ADC — TERMINOLOGY
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent
codes in the ADC.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation from a
straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero
scale with a single (1) LSB point below the first code transition, and full scale with a 1 LSB point above the last code
transition.
Offset Error
Offset error applies to straight binary output coding. It is the
deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal (AGND + 1 LSB).
Offset Error Match
Offset error match is the difference in offset error across all 12
channels.
Gain Error
Gain error applies to straight binary output coding. It is the
deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (VREF 1 LSB) after the offset error
is adjusted out. Gain error does not include reference error.
Negative Gain Error Match
This is the difference in negative gain error across all 12
channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
end of conversion. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier
to reach its final value, within ±1/2 LSB, after the end of
conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2),
excluding dc. The ratio is dependent on the number of quantization levels in the digitalization process; the more levels,
the smaller the quantization noise. The theoretical signal-to(noise + distortion) ratio for an ideal N-bit converter with a
sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, theoretical SINAD is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the ADC, it is defined as
Gain Error Match
Gain error match is the difference in gain error across all 12
channels.
Positive Gain Error
This applies when using twos complement output coding
with, for example, the 2 × VREF input range as –VREF to +VREF
biased about the VREF point. It is the deviation of the last code
transition (011…110) to (011…111) from the ideal (+VREF
1 LSB) after the zero code error is adjusted out.
Positive Gain Error Match
This is the difference in positive gain error across all 12
channels.
Zero Code Error
Zero code error applies when using twos complement output
coding with, for example, the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
mid-scale transition (all 0s to all 1s) from the ideal VIN voltage
(VREF).
Zero Code Error Match
Zero code error match refers to the difference in zero code
error across all 12 channels.
Negative Gain Error
This applies when using twos complement output coding
option, in particular the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
first code transition (100…000) to (100…001) from the ideal
(that is, –VREF + 1 LSB) after the zero code error is adjusted
out.
Rev. PrC
THD(dB) = 20 log
V22 + V32 + V4 2 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Effective Number of Bits (ENOB)
This is a figure of merit which characterizes the dynamic performance of the ADC at a specified input frequency and
sampling rate. ENOB is expressed in bits. For a full scale sinusoidal input, ENOB is defined as:
ENOB = (SINAD – 1.76)/6.02.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic, or spurious noise, is defined as the ratio of
the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale (2 × VREF when VDD = 5 V, VREF when VDD = 3 V),
10 kHz sine wave signal to all un-selected input channels and
| Page 60 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
determining how much that signal is attenuated in the
selected channel with a 50 kHz signal (0 V to VREF). The result
obtained is the worst-case across all 12 channels for the ADC.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with non-linearities create distortion
products at sum, and difference frequencies of mfa ± nfb
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n are equal to zero.
For example, the second-order terms include (fa + fb) and
(fa fb), while the third-order terms include (2fa + fb),
(2fa fb), (fa + 2fb), and (fa 2fb).
The ADC is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are specified separately. The calculation of the inter-modulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the
rms amplitude of the sum of the fundamentals expressed in
dBs.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN of
frequency fS as
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
where:
VREF (25°C) is VREF at 25°C.
VREF (T_HYS) is the maximum change of VREF at
T_HYS+ or T_HYS.
ADC — THEORY OF OPERATION
The following sections describe the ADC theory of operation.
Circuit Information
The ADC is a fast, micro-power, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When operated from a 5 V supply, the ADC is capable of throughput rates
of up to 2 MSPS when provided with a 32 MHz clock, and a
throughput rate of up to 1.5 MSPS at 3 V.
The ADC contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins.
The serial clock input accesses data from the part but also provides the clock source for each successive approximation ADC.
The analog input range for the part can be selected to be a 0 V to
VREF input or a 2 × VREF input, configured with either singleended or differential analog inputs. The ADC has an on-chip
2.5 V reference that can be overdriven when an external reference is preferred. If the internal reference is to be used elsewhere
in a system, then the output needs to buffered first.
The ADC also features power-down options to allow power saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the ADC — Modes of Operation section.
Converter Operation
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 56 (PSRR vs. Supply Ripple Frequency Without Supply Decoupling).
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum
change of reference output voltage after the device is cycled
through temperature from either
The ADC has two successive approximation ADCs, each based
around two capacitive DACs. Figure 68 (ADC Acquisition
Phase) and Figure 69 (ADC Conversion Phase) show simplified
schematics of one of these ADCs in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In Figure 68 (ADC Acquisition
Phase) (the acquisition phase), SW3 is closed, SW1 and SW2 are
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays acquire the differential signal
on the input.
T_HYS+ = +25°C to TMAX to +25°C
or
CAPACITIVE
DAC
T_HYS = +25°C to TMIN to +25°C
VHYS ( ppm) =
CS
B
It is expressed in ppm by
VIN+
VREF (25°C) − VREF (T _ HYS)
× 10 6
VREF (25°C)
VIN–
A SW1
A
SW2
CS
COMPARATOR
CONTROL
LOGIC
SW3
B
VREF
CAPACITIVE
DAC
Figure 68. ADC Acquisition Phase
Rev. PrC
| Page 61 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
When the ADC starts a conversion (see Figure 69 (ADC Conversion Phase)), SW3 opens and SW1 and SW2 move to
Position B, causing the comparator to become unbalanced. Both
inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
The output impedances of the sources driving the VIN+ and VIN–
pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors.
CAPACITIVE
DAC
VIN–
COMPARATOR
CS
B
VIN+
A SW1
A
SW2
B
VREF
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47 Ω and 10 pF. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and may necessitate the use of an input buffer amplifier. The
choice of the op amp is a function of the particular application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated.
CONTROL
LOGIC
SW3
CS
The C1 capacitors in Figure 70 (Equivalent Analog Input Circuit, Conversion Phase—Switches Open, Track Phase—
Switches Closed) are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components
made up of the on resistance of the switches. The value of these
resistors is typically about 100 Ω. The C2 capacitors are the
ADC’s sampling capacitors with a capacitance of 45 pF typically.
CAPACITIVE
DAC
Figure 69. ADC Conversion Phase
Analog Input Structure
Figure 70 (Equivalent Analog Input Circuit, Conversion
Phase—Switches Open, Track Phase—Switches Closed) shows
the equivalent circuit of the analog input structure of the ADC
in differential/pseudo differential mode. In single-ended mode,
VIN is internally tied to AGND. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV. This causes these diodes to become forward-biased and starts conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part.
The THD increases as the source impedance increases and performance degrades. Figure 71 (THD vs. Analog Input
Frequency for Various Source Impedances, Single-Ended Mode
shows a graph of the THD vs. the analog input signal frequency
for different source impedances in single-ended mode, while
Figure 72 (THD vs. Analog Input Frequency for Various Source
Impedances, Differential Mode) shows the THD vs. the analog
input signal frequency for different source impedances in differential mode.
Figure 73 (THD vs. Analog Input Frequency for Various Supply
Voltages) shows a graph of the THD vs. the analog input frequency for various supplies while sampling at 2 MSPS. In this
case, the source impedance is 47 Ω.
–50
FSAMPLE = 1.5MSPS
VDD = 3V
–55 RANGE = 0V TO VREF
RSOURCE = 300Ÿ
–60
VDD
R1 C2
VIN+
C1
THD (dB)
–65
D
D
VDD
D
VIN–
C1
RSOURCE = 0Ÿ
–70
RSOURCE = 100Ÿ
–75
RSOURCE = 47Ÿ
–80
RSOURCE = 10Ÿ
–85
R1 C2
–90
D
Figure 70. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
Rev. PrC
0
100
200
300
400
INPUT FREQUENCY (kHz)
500
600
Figure 71. THD vs. Analog Input Frequency for Various
Source Impedances, Single-Ended Mode
| Page 62 of 80 | January 2010
Preliminary Technical Data
–60
FSAMPLE = 1.5MSPS
VDD = 3V
RANGE = 0V TO VREF
–65
RSOURCE = 0Ÿ
THD (dB)
–70
ADSP-BF504/F,ADSP-BF506F
+2.5V
RSOURCE = 300Ÿ
R
+1.25V
0V
VIN
VA1
3R
–1.25V
RSOURCE = 100Ÿ
ADC1
VREF
R
VB6 (DCAPA/DCAPB)
–75
0.47μF
–80
RSOURCE = 47Ÿ
–85
1ADDITIONAL PINS OMITTED FOR CLARITY.
RSOURCE = 10Ÿ
–90
0
100
200
300 400 500 600 700
INPUT FREQUENCY (kHz)
800
900
1000
Figure 74. Single-Ended Mode Connection Diagram
Differential Mode
Figure 72. THD vs. Analog Input Frequency for
Various Source Impedances, Differential Mode
The ADC can have a total of six differential analog input pairs.
Differential signals have some benefits over single-ended signals, including noise immunity based on the device’s commonmode rejection and improvements in distortion performance.
Figure 75 (Differential Input Definition) defines the fully differential analog input of the ADC.
–50
FSAMPLE = 1.5MSPS/2MSPS
VDD = 3V/5V
–55 RANGE = 0 TO VREF
VDD = 3V
SINGLE-ENDED MODE
–60
–65
THD (dB)
0V
R
VREF p-p
–70
VDD = 3V
DIFFERENTIAL MODE
COMMON
MODE
VOLTAGE
–75
VIN+
ADC1
VREF p-p
VIN–
–80
–85
–90
VDD = 5V
SINGLE-ENDED MODE
0
100
200
1ADDITIONAL
VDD = 5V
DIFFERENTIAL MODE
300 400 500 600 700
INPUT FREQUENCY (kHz)
PINS OMITTED FOR CLARITY.
Figure 75. Differential Input Definition
800
900
1000
Figure 73. THD vs. Analog Input Frequency for Various Supply Voltages
Analog Inputs
The ADC has a total of 12 analog inputs. Each on-board ADC
has six analog inputs that can be configured as six single-ended
channels, three pseudo differential channels, or three fully differential channels. These may be selected as described in the
Analog Input Selection section.
Single-Ended Mode
The ADC can have a total of 12 single-ended analog input channels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input
before applying it to the ADC. The analog input range can be
programmed to be either 0 to VREF or 0 to 2 × VREF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this signal to make it correctly formatted for the ADC. Figure 74 shows
a typical connection diagram when operating the ADC in single-ended mode.
Rev. PrC
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– pins in each differential
pair (VIN+ VIN–). VIN+ and VIN– should be simultaneously driven
by two signals each of amplitude VREF (or 2 × VREF, depending
on the range chosen) that are 180° out of phase. The amplitude
of the differential signal is, therefore (assuming the 0 to VREF
range is selected) –VREF to +VREF peak-to-peak (2 × VREF),
regardless of the common mode (CM).
The common mode is the average of the two signals
(VIN+ + VIN–)/2
and is, therefore, the voltage on which the two inputs are
centered.
This results in the span of each input being CM ± VREF/2. This
voltage has to be set up externally and its range varies with the
reference value, VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an
amplifier, the actual common-mode range is determined by the
amplifier’s output voltage swing.
Figure 76 (Input Common-Mode Range vs. VREF (0 to VREF
Range, VDD = 5 V)) and Figure 77 (Input Common-Mode
Range vs. VREF (2 × VREF Range, VDD = 5 V)) show how the
common-mode range typically varies with VREF for a 5 V power
| Page 63 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
supply using the 0 to VREF range or 2 × VREF range, respectively.
The common mode must be in this range to guarantee the functionality of the ADC.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude –VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the 2 ×
VREF range is used, then the input signal amplitude extends from
– 2 VREF to +2 VREF after conversion.
3.5
TA = 25°C
COMMON-MODE RANGE (V)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
3.5
4.0
4.5
5.0
Figure 76. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
5.0
An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the ADC. The circuit
configurations illustrated in Figure 78 (Dual Op Amp Circuit to
Convert a Single-Ended Unipolar Signal into a Differential Signal) and Figure 79 (Dual Op Amp Circuit to Convert a SingleEnded Bipolar Signal into a Differential Unipolar Signal) show
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a suitable dual op amp that can be used in this configuration to
provide differential drive to the ADC.
3.0
0
Using an Op Amp Pair
TA = 25°C
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 78 (Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal)
and Figure 79 (Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal) are optimized
for dc coupling applications requiring best distortion
performance.
The circuit configuration shown in Figure 78 (Dual Op Amp
Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal) converts a unipolar, single-ended signal into a
differential signal.
4.5
2 × VREF p–p
COMMON-MODE RANGE (V)
4.0
3.5
VREF
3.0
GND
220Ÿ
440Ÿ
V+
220Ÿ
220Ÿ
2.0
V+
1.5
A
1.0
0.5
0
0.5
1.0
1.5
2.0
VIN+
ADC1
V–
2.5
0
27Ÿ
3.75V
2.5V
1.25V
V–
27Ÿ
10kŸ
3.75V
2.5V
1.25V
VREF
VIN–
(DCAPA/DCAPB)
0.47μF
2.5
VREF (V)
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 77. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Figure 78. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
Driving Differential Inputs
Differential operation requires that VIN+ and VIN– be simultaneously driven with two equal signals that are 180° out of phase.
The common mode must be set up externally. The commonmode range is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Because
not all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-differential conversion.
Rev. PrC
The differential op amp driver circuit shown in Figure 79 (Dual
Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a
Differential Unipolar Signal) is configured to convert and level
shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC.
Pseudo Differential Mode
The ADC can have a total of six pseudo differential pairs. In this
mode, VIN+ is connected to the signal source that must have an
amplitude of VREF (or 2 × VREF, depending on the range chosen)
| Page 64 of 80 | January 2010
Preliminary Technical Data
2 × VREF p–p
440Ÿ
GND
3.75V
220Ÿ
V+
ADSP-BF504/F,ADSP-BF506F
2.5
2.5V
1.25V
27Ÿ
VIN+
ADC
1
TA = 25°C
2.0
V–
220Ÿ
220Ÿ
V+
A
V–
1.5
3.75V
2.5V
VREF
1.25V
27Ÿ
VIN– (DCAPA/DCAPB)
VIN– (V)
220kŸ
1.0
0.5
10kŸ
0.47μF
20kŸ
0
1ADDITIONAL PINS OMITTED FOR CLARITY.
–0.5
0
Figure 79. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
to make use of the full dynamic range of the part. A dc input is
applied to the VIN– pin. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+
input. The benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled.
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
3.5
4.0
4.5
5.0
Figure 81. VIN– Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 5 V
VREF
p–p
The typical voltage range for the VIN– pin, while in pseudo differential mode, is shown in Figure 80 (VIN– Input Voltage Range
vs. VREF in Pseudo Differential Mode with VDD = 3 V) and
Figure 81 (VIN– Input Voltage Range vs. VREF in Pseudo Differential Mode with VDD = 5 V). Figure 82 (Pseudo Differential
Mode Connection Diagram) shows a connection diagram for
pseudo differential mode.
VIN+
DC INPUT
VOLTAGE
ADC1
VIN–
VREF (DCAPA/DCAPB)
0.47μF
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 82. Pseudo Differential Mode Connection Diagram
1.0
TA = 25°C
Analog Input Selection
0.8
VIN– (V)
0.6
0.4
0.2
0
–0.2
–0.4
0
0.5
1.0
1.5
VREF (V)
2.0
2.5
Figure 80. VIN- Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 3 V
3.0
The analog inputs of the ADC can be configured as singleended or true differential via the SGL/DIFF logic pin, as shown
in Figure 83 (Selecting Differential or Single-Ended Configuration). If this pin is tied to a logic low, the analog input channels
to each on-chip ADC are set up as three true differential pairs. If
this pin is at logic high, the analog input channels to each onchip ADC are set up as six single-ended analog inputs. The
required logic level on this pin needs to be established prior to
the acquisition time and remain unchanged during the conversion time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13th rising edge of
ADSCLK after the CS falling edge (see Figure 93 (Serial Interface Timing Diagram)). If the level on this pin is changed, it will
be recognized by the ADC; therefore, it is necessary to keep the
same logic level during acquisition and conversion to avoid corrupting the conversion in progress.
For example, in Figure 83 (Selecting Differential or SingleEnded Configuration) the SGL/DIFF pin is set at logic high for
the duration of both the acquisition and conversion times so the
analog inputs are configured as single ended for that conversion
(Sampling Point A). The logic level of the SGL/DIFF changed to
low after the track-and-hold returned to track and prior to the
Rev. PrC
| Page 65 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
required acquisition time for the next sampling instant at Point
B; therefore, the analog inputs are configured as differential for
that conversion.
A
1
The analog input range of the ADC can be selected as 0 V to
VREF or 0 V to 2 × VREF via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by setting
the logic state of the RANGE pin a time tacq prior to the falling
edge of CS. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of ADSCLK. If this pin is tied
to a logic low, the analog input range selected is 0 V to VREF. If
this pin is tied to a logic high, the analog input range selected is
0 V to 2 × VREF.
B
tACQ
CS
14
1
acquisition time would start again from this point. The selected
input channels are decoded as shown in Table 51 (Analog Input
Type and Channel Selection).
14
ADSCLK
SGL/DIFF
Figure 83. Selecting Differential or Single-Ended Configuration
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time
provided the mode is not changed. If the mode is changed from
fully differential to pseudo differential, for example, then the
Output Coding
The ADC output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 50 (ADC Output Coding)
shows which output coding scheme is used for each possible
analog input configuration.
Table 50. ADC Output Coding
SGL/DIFF
0
0
1
1
0
0
(Differential Input)
(Differential Input)
(Single-Ended Input)
(Single-Ended Input)
(Pseudo-Differential Input)
(Pseudo-Differential Input)
RANGE
0
1
0
1
0
1
(0 V to VREF)
(0 V to 2 × VREF)
(0 V to VREF)
(0 V to2 × VREF)
(0 V to VREF)
(0 V to 2 × VREF)
Output Coding
Twos complement
Twos complement
Straight binary
Twos complement
Straight binary
Twos complement
Table 51. Analog Input Type and Channel Selection
SGL/DIFF
1
1
1
1
1
1
0
0
0
0
0
0
A2
0
0
0
0
1
1
0
0
0
0
1
1
A1
0
0
1
1
0
0
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
ADC A
VIN+
VA1
VA2
VA3
VA4
VA5
VA6
VA1
VA1
VA3
VA3
VA5
VA5
VIN–
AGND
AGND
AGND
AGND
AGND
AGND
VA2
VA2
VA4
VA4
VA6
VA6
ADC B
VIN+
VB1
VB2
VB3
VB4
VB5
VB6
VB1
VB1
VB3
VB3
VB5
VB5
VIN–
AGND
AGND
AGND
AGND
AGND
AGND
VB2
VB2
VB4
VB4
VB6
VB6
Comment
Single ended
Single ended
Single ended
Single ended
Single ended
Single ended
Fully differential
Pseudo differential
Fully differential
Pseudo differential
Fully differential
Pseudo differential
Transfer Functions
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB
size is VREF/4096 when the 0 V to VREF range is used, and the LSB
size is 2 × VREF/4096 when the 0 V to 2 × VREF range is used. In
differential mode, the LSB size is 2 × VREF /4096 when the 0 V to
VREF range is used, and the LSB size is 4 × VREF/4096 when the 0
V to 2 × VREF range is used. The ideal transfer characteristic for
Rev. PrC
the ADC when straight binary coding is output is shown in
Figure 84 (Straight Binary Transfer Characteristic), and the
ideal transfer characteristic for the ADC when twos complement coding is output is shown in Figure 85 (Twos
Complement Transfer Characteristic with VREF ± VREF Input
Range) (this is shown with the 2 × VREF range).
| Page 66 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
agement options. These options can be chosen to optimize the
power dissipation/throughput rate ratio for differing application requirements.
111...111
ADC CODE
111...110
Normal Mode
This mode is intended for applications needing fastest throughput rates because the user does not have to worry about any
power-up times with the ADC remaining fully powered at all
times. Figure 86 (Normal Mode Operation) shows the general
diagram of the operation of the ADC in this mode.
111...000
1LSB = VREF/4096
011...111
000...010
000...001
000...000
VREF – 1LSB
0V 1LSB
CS
ANALOG INPUT
1
NOTE
1. VREF IS EITHER VREF OR 2 × VREF.
DOUTA
DOUTB
Figure 84. Straight Binary Transfer Characteristic
011...111
011...110
ADC CODE
14
LEADING ZEROS + CONVERSION RESULT
Figure 86. Normal Mode Operation
1LSB = 2 u VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF + 1LSB VREF – 1LSB
10
ADSCLK
+VREF – 1 LSB
ANALOG INPUT
Figure 85. Twos Complement Transfer Characteristic with
VREF ± VREF Input Range
Serial Interface Voltage Drive
The ADC also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the ADC was operated with a AVDD/DVDD of 5 V, the VDRIVE pin
could be powered from a 3 V supply, best ADC performance
low voltage digital processors. Therefore, the ADC could be
used with the 2 × VREF input range, with a AVDD/DVDD of 5 V
while still being able to serial interface to 3 V digital I/O parts.
ADC — MODES OF OPERATION
The mode of operation of the ADC is selected by controlling the
(logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. After a conversion is
initiated, the point at which CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode, CS can control whether the device
returns to normal operation or remains in power-down. These
modes of operation are designed to provide flexible power man-
Rev. PrC
The conversion is initiated on the falling edge of CS, as
described in the ADC — Serial Interface section. To ensure that
the part remains fully powered up at all times, CS must remain
low until at least 10 ADSCLK falling edges have elapsed after the
falling edge of CS. If CS is brought high any time after the 10th
ADSCLK falling edge but before the 14th ADSCLK falling edge,
the part remains powered up, but the conversion is terminated
and DOUTA and DOUTB go back into three-state. Fourteen serial
clock cycles are required to complete the conversion and access
the conversion result. The DOUT line does not return to threestate after 14 ADSCLK cycles have elapsed, but instead does so
when CS is brought high again. If CS is left low for another 2
ADSCLK cycles (for example, if only a 16 ADSCLK burst is
available), two trailing zeros are clocked out after the data. If CS
is left low for a further 14 (or16) ADSCLK cycles, the result
from the other ADC on board is also accessed on the same DOUT
line, as shown in Figure 94 (Reading Data from Both ADCs on
One DOUT Line with 32 ADSCLKs). See the ADC — Serial
Interface section.
Once 32 ADSCLK cycles have elapsed, the DOUT line returns to
three-state on the 32nd ADSCLK falling edge. If CS is brought
high prior to this, the DOUT line returns to three-state at that
point. Therefore, CS may idle low after 32 ADSCLK cycles until
it is brought high again sometime prior to the next conversion
(effectively idling CS low), if so desired, because the bus still
returns to three-state upon completion of the dual result read.
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time is allowed).
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be performed at a high throughput rate, and the ADC is then powered
| Page 67 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
down for a relatively long duration between these bursts of several conversions. When the ADC is in partial power-down, all
analog circuitry is powered down except for the on-chip reference and reference buffer.
again on the rising edge of CS. If the ADC is already in partial
power-down mode and CS is brought high between the second
and 10th falling edges of ADSCLK, the device enters full powerdown mode.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the second falling edge of ADSCLK and before the 10th falling edge of
ADSCLK, as shown in Figure 87 (Entering Partial Power-Down
Mode). Once CS is brought high in this window of ADSCLKs,
the part enters partial power-down, the conversion that was initiated by the falling edge of CS is terminated, and DOUTA and
DOUTB go back into three-state. If CS is brought high before the
second ADSCLK falling edge, the part remains in normal mode
and does not power down. This avoids accidental power-down
due to glitches on the CS line.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substantially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the ADC
is in full power-down, all analog circuitry is powered down. Full
power-down is entered in a similar way as partial power-down,
except the timing sequence shown in Figure 87 (Entering Partial
Power-Down Mode) must be executed twice. The conversion
process must be interrupted in a similar fashion by bringing CS
high anywhere after the second falling edge of ADSCLK and
before the 10th falling edge of ADSCLK. The device enters partial power-down at this point. To reach full power-down, the
next conversion cycle must be interrupted in the same way, as
shown in Figure 89 (Entering Full Power-Down Mode). Once
CS is brought high in this window of ADSCLKs, the part completely powers down.
CS
1
2
10
14
ADSCLK
DOUTA
DOUTB
THREE-STATE
Figure 87. Entering Partial Power-Down Mode
Note that it is not necessary to complete the 14 ADSCLKs once
CS is brought high to enter a power-down mode.
To exit this mode of operation and power up the ADC again, a
dummy conversion is performed. On the falling edge of CS, the
device begins to power up and continues to power up as long as
CS is held low until after the falling edge of the 10th ADSCLK.
The device is fully powered up after approximately 1 μs has
elapsed, and valid data results from the next conversion, as
shown in Figure 88 (Exiting Partial Power-Down Mode). If CS
is brought high before the second falling edge of ADSCLK, the
ADC again goes into partial power-down. This avoids accidental power-up due to glitches on the CS line. Although the device
may begin to power up on the falling edge of CS, it powers down
THE PART BEGINS
TO POWER UP.
To exit full power-down and power up the ADC, a dummy conversion is performed, as when powering up from partial powerdown. On the falling edge of CS, the device begins to power up
and continues to power up, as long as CS is held low until after
the falling edge of the 10th ADSCLK. The required power-up
time must elapse before a conversion can be initiated, as shown
in Figure 90 (Exiting Full Power-Down Mode). See the PowerUp Times section for the power-up times associated with the
ADC.
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
tPOWER-UP1
CS
ADSCLK
DOUTA
DOUTB
1
10
14
INVALID DATA
14
VALID DATA
Figure 88. Exiting Partial Power-Down Mode
Rev. PrC
1
| Page 68 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
THE PART ENTERS
PARTIAL POWER DOWN.
THE PART BEGINS
TO POWER UP.
THE PART ENTERS
FULL POWER DOWN.
CS
ADSCLK
1
2
DOUTA
DOUTB
10
14
1
2
THREE-STATE
INVALID DATA
10
INVALID DATA
14
THREE-STATE
Figure 89. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
ADSCLK
DOUTA
DOUTB
14
10
1
14
1
INVALID DATA
VALID DATA
Figure 90. Exiting Full Power-Down Mode
Power-Up Times
As described in detail, the ADC has two power-down modes,
partial power-down and full power-down. This section deals
with the power-up time required when coming out of either of
these modes. It should be noted that the power-up times, as
explained in this section, apply with the recommended capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down, approximately 1.5 ms
should be allowed from the falling edge of CS, shown as
tPOWER-UP2 in Figure 90 (Exiting Full Power-Down Mode). Powering up from partial power-down requires much less time. The
power-up time from partial power-down is typically 1 μs; however, if using the internal reference, then the ADC must be in
partial power-down for at least 67 μs in order for this power-up
time to apply.
When power supplies are first applied to the ADC, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure the part is fully powered up before attempting a valid
conversion. Likewise, if it is intended to keep the part in the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th ADSCLK
falling edge (see Figure 86 (Normal Mode Operation)); in the
second cycle, CS must be brought high before the 10th ADSCLK
edge but after the second ADSCLK falling edge (see Figure 87
(Entering Partial Power-Down Mode)). Alternatively, if it is
intended to place the part in full power-down mode when the
supplies are applied, then three dummy cycles must be initiated.
Rev. PrC
The first dummy cycle must hold CS low until after the 10th
ADSCLK falling edge (see Figure 86 (Normal Mode Operation)); the second and third dummy cycles place the part in full
power-down (see Figure 89 (Entering Full Power-Down
Mode)).
Once supplies are applied to the ADC, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final
values.
Power vs. Throughput Rate
The power consumption of the ADC varies with the throughput
rate. When using very slow throughput rates and as fast an
ADSCLK frequency as possible, the various power-down
options can be used to make significant power savings. However, the ADC quiescent current is low enough that even
without using the power-down options, there is a noticeable
variation in power consumption with sampling rate. This is true
whether a fixed ADSCLK value is used or if it is scaled with the
sampling rate. Figure 91 (Power vs. Throughput in Normal
Mode with VDD = 3 V) and Figure 92 (Power vs. Throughput
in Normal Mode with VDD = 5 V) show plots of power vs. the
throughput rate when operating in normal mode for a fixed
| Page 69 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
maximum ADSCLK frequency and an ADSCLK frequency that
scales with the sampling rate with VDD = 3 V and VDD = 5 V,
respectively. In all cases, the internal reference was used.
10.0
Likewise, if CS is held low for a further 14 (or 16) ADSCLK
cycles on DOUTB, the data from Conversion A is output on
DOUTB.
TA = 25°C
9.5
This is illustrated in Figure 94 (Reading Data from Both ADCs
on One DOUT Line with 32 ADSCLKs) where the case for
DOUTA is shown. In this case, the DOUT line in use goes back into
three-state on the 32nd ADSCLK falling edge or the rising edge
of CS, whichever occurs first.
9.0
POWER (mW)
8.5
VARIABLE ADSCLK
8.0
7.5
7.0
24MHz ADSCLK
6.5
6.0
5.5
5.0
0
200
400
600
800
1000
THROUGHPUT (kSPS)
1200
1400
Figure 91. Power vs. Throughput in Normal Mode with VDD = 3 V
30
TA = 25°C
28
26
POWER (mW)
24
VARIABLE ADSCLK
22
20
32MHz ADSCLK
18
16
14
12
10
0
200
400
not brought high but is instead held low for a further 14 (or 16)
ADSCLK cycles on DOUTA, the data from Conversion B is output on DOUTA (followed by two trailing zeros).
600 800 1000 1200 1400 1600 1800 2000
THROUGHPUT (kSPS)
A minimum of 14 serial clock cycles are required to perform the
conversion process and to access data from one conversion on
either data line of the ADC. CS going low provides the leading
zero to be read in by the microcontroller or DSP. The remaining
data is then clocked out by subsequent ADSCLK falling edges,
beginning with a second leading zero. Thus, the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the second leading zero. The 12-bit result then
follows with the final bit in the data transfer valid on the 14th
falling edge, having being clocked out on the previous (13th) falling edge. In applications with a slower ADSCLK, it may be
possible to read in data on each ADSCLK rising edge depending
on the ADSCLK frequency. The first rising edge of ADSCLK
after the CS falling edge would have the second leading zero
provided, and the 13th rising ADSCLK edge would have DB0
provided.
Note that with fast ADSCLK values, and thus short ADSCLK
periods, in order to allow adequately for t2, an ADSCLK rising
edge may occur before the first ADSCLK falling edge. This rising edge of ADSCLK may be ignored for the purposes of the
timing descriptions in this section. If a falling edge of ADSCLK
is coincident with the falling edge of CS, then this falling edge of
ADSCLK is not acknowledged by the ADC, and the next falling
edge of ADSCLK will be the first registered after the falling edge
of CS.
Figure 92. Power vs. Throughput in Normal Mode with VDD = 5 V
ADC — SERIAL INTERFACE
Figure 93 (Serial Interface Timing Diagram) shows the detailed
timing diagram for serial interfacing to the ADC. The serial
clock provides the conversion clock and controls the transfer of
information from the ADC during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 ADSCLKs to complete. Once 13
ADSCLK falling edges have elapsed, the track-and-hold goes
back into track on the next ADSCLK rising edge, as shown in
Figure 93 (Serial Interface Timing Diagram) at Point B. If a 16
ADSCLK transfer is used, then two trailing zeros appear after
the final LSB. On the rising edge of CS, the conversion is terminated and DOUTA and DOUTB go back into three-state. If CS is
Rev. PrC
| Page 70 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
CS
t9
t2
ADSCLK
t6
1
3
2
5
t3
DOUTA
0
DB11
0
DOUTB THREESTATE
2 LEADING ZEROS
B
4
t4
DB10
13
t5
t7
DB9
DB2
DB8
tQUIET
t8
DB1
DB0
THREE-STATE
Figure 93. Serial Interface Timing Diagram
CS
t6
t2
ADSCLK
3
2
1
t3
DOUTA
4
5
t4
0 ZERO DB11A
THREESTATE 2 LEADING
ZEROS
DB10A
t5
DB9A
14
16
15
17
32
t10
t7
ZERO
ZERO
ZERO
ZERO
DB11B
2 TRAILING ZEROS
2 LEADING ZEROS
Figure 94. Reading Data from Both ADCs on One DOUT Line with 32 ADSCLKs
Rev. PrC
| Page 71 of 80 | January 2010
ZERO
ZERO
2 TRAILING ZEROS
THREESTATE
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
120-LEAD LQFP LEAD ASSIGNMENT
Table 52 lists the LQFP leads by signal mnemonic.
Table 53 on Page 73 lists the LQFP leads by lead number.
Table 52. 120-Lead LQFP Lead Assignment (Alphabetically by Signal)
Signal
A0
A1
A2
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
BMODE0
BMODE1
BMODE2
CLKIN
CS
DCAPA
DCAPB
DGND
DGND
DOUTA
DOUTB
DVDD
EMU
EXT_WAKE
EXTCLK
GND
GND
GND
GND
NC
No.
100
98
97
73
78
79
82
93
99
76
58
57
56
110
101
77
94
74
104
105
103
107
68
70
120
13
17
108
109
60
Signal
NC
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
No.
72
11
118
119
2
4
3
5
7
8
9
10
14
16
18
19
21
22
71
27
28
29
31
32
38
39
40
43
44
45
Signal
No.
VB5
88
VB6
87
VDDEXT
1
VDDEXT
6
VDDEXT
15
20
VDDEXT
VDDEXT
23
VDDEXT
26
VDDEXT
30
VDDEXT
41
VDDEXT
51
59
VDDEXT
VDDEXT
62
VDDEXT
64
VDDEXT
66
VDDEXT
67
VDDEXT
112
116
VDDEXT
VDDFLASH
25
VDDFLASH
63
VDDFLASH
69
VDDINT
24
VDDINT
42
VDDINT
52
VDDINT
53
VDDINT
61
VDDINT
65
VDDINT
117
VDRIVE
106
XTAL
111
GND
121*
AGND
122**
* Pin no. 121 is the GND supply (see Figure 95 and Figure 96) for the processor (4.6mm × 6.17mm); this pad must connect to GND.
** Pin no. 122 is the AGND supply (see Figure 95 and Figure 96) for the ADC (2.81mm × 2.81mm); this pad must connect to AGND.
Rev. PrC
Signal
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
RANGE
REF_SELECT
RESET
SCL
ADSCLK
SDA
SGL/DIFF
TCK
TDI
TDO
TMS
TRST
VA1
VA2
VA3
VA4
VA5
VA6
VB1
VB2
VB3
VB4
No.
46
47
48
49
50
113
115
114
95
75
12
55
102
54
96
34
33
36
35
37
80
81
83
84
85
86
92
91
90
89
| Page 72 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Table 53. 120-Lead LQFP Lead Assignment (Numerically by Lead Number)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal
VDDEXT
PF2
PF4
PF3
PF5
VDDEXT
PF6
PF7
PF8
PF9
NMI
RESET
GND
PF10
VDDEXT
PF11
GND
PF12
PF13
VDDEXT
PF14
PF15
VDDEXT
VDDINT
VDDFLASH
VDDEXT
PG0
PG1
PG2
VDDEXT
No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Signal
PG3
PG4
TDI
TCK
TMS
TDO
TRST
PG5
PG6
PG7
VDDEXT
VDDINT
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
VDDEXT
VDDINT
VDDINT
SDA
SCL
BMODE2
BMODE1
BMODE0
VDDEXT
NC
No.
Signal
91
VB2
92
VB1
93
AGND
94
DCAPB
95
RANGE
96
SGL/DIFF
97
A2
98
A1
99
AGND
100
A0
101
CS
102
ADSCLK
103
DOUTB
104
DGND
105
DOUTA
106
VDRIVE
107
DVDD
108
GND
109
GND
110
CLKIN
111
XTAL
112
VDDEXT
113
PH0
114
PH2
115
PH1
116
VDDEXT
117
VDDINT
118
PF0
119
PF1
120
EXTCLK
121*
GND
122**
AGND
* Pin no. 121 is the GND supply (see Figure 95 and Figure 96) for the processor (4.6mm × 6.17mm); this pad must connect to GND.
** Pin no. 122 is the AGND supply (see Figure 95 and Figure 96) for the ADC (2.81mm × 2.81mm); this pad must connect to AGND.
Rev. PrC
No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Signal
VDDINT
VDDEXT
VDDFLASH
VDDEXT
VDDINT
VDDEXT
VDDEXT
EMU
VDDFLASH
EXT_WAKE
PG
NC
AGND
DGND
REF_SELECT
AVDD
DCAPA
AGND
AGND
VA1
VA2
AGND
VA3
VA4
VA5
VA6
VB6
VB5
VB4
VB3
| Page 73 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Figure 95 shows the top view of the 120-lead LQFP package lead
configuration. Figure 96 shows the bottom view of the 120-lead
LQFP package lead configuration.
PIN 120
PIN 91
PIN 1
PIN 90
PIN 1 INDICATOR
ADSP-BF50X
120-LEAD LQFP
TOP VIEW
PIN 30
PIN 61
PIN 31
PIN 60
Figure 95. 120-Lead LQFP Package Lead Configuration (Top View)
PIN 31
PIN 60
PIN 30
PIN 61
GND
PAD
(PIN 121)
ADSP-BF50X
120-LEAD
LQFP
BOTTOM VIEW
AGND
PAD
(PIN 122)
PIN 1
PIN 90
PIN 120
PIN 91
Figure 96. 120-Lead LQFP Package Lead Configuration (Bottom View)
Rev. PrC
| Page 74 of 80 | January 2010
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
88-LEAD LFCSP LEAD ASSIGNMENT
Table 54 lists the LFCSP leads by signal mnemonic.
Table 55 on Page 76 lists the LFCSP by lead number.
Table 54. 88-Lead LFCSP Lead Assignment (Alphabetically by Signal)
Signal
BMODE0
BMODE1
BMODE2
CLKIN
EMU
EXT_WAKE
EXTCLK
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NMI
PF0
PF1
PF2
PF3
Lead
No.
51
50
49
68
60
62
78
3
7
67
45
46
47
48
64
65
66
1
76
77
80
81
Signal
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
Lead
No.
82
83
85
86
87
88
4
6
8
9
11
12
63
17
18
19
21
22
28
29
30
33
Signal
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
RESET
SCL
SDA
TCK
TDI
TDO
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
Lead
No.
34
35
36
37
38
39
40
71
72
73
2
44
43
24
23
27
25
26
5
10
13
16
* Pin no. 89 is the GND supply (see Figure 98) for the processor; this pad must connect to GND.
Rev. PrC
| Page 75 of 80 | January 2010
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDFLASH
VDDFLASH
VDDFLASH
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
XTAL
GND
Lead
No.
20
31
41
52
54
56
58
59
70
74
79
84
15
55
61
14
32
42
53
57
75
69
89*
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Table 55. 88-Lead LFCSP Lead Assignment (Numerically by Lead Number)
Lead
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Signal
NMI
RESET
GND
PF10
VDDEXT
PF11
GND
PF12
PF13
VDDEXT
PF14
PF15
VDDEXT
VDDINT
VDDFLASH
VDDEXT
PG0
PG1
PG2
VDDEXT
PG3
PG4
Lead
No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
TDI
TCK
TMS
TRST
TDO
PG5
PG6
PG7
VDDEXT
VDDINT
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
VDDEXT
VDDINT
SDA
SCL
Lead
No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Signal
NC
NC
NC
NC
BMODE2
BMODE1
BMODE0
VDDEXT
VDDINT
VDDEXT
VDDFLASH
VDDEXT
VDDINT
VDDEXT
VDDEXT
EMU
VDDFLASH
EXT_WAKE
PG
NC
NC
NC
* Pin no. 89 is the GND supply (see Figure 98) for the processor; this pad must connect to GND.
Rev. PrC
| Page 76 of 80 | January 2010
Lead
No.
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89*
Signal
GND
CLKIN
XTAL
VDDEXT
PH0
PH1
PH2
VDDEXT
VDDINT
PF0
PF1
EXTCLK
VDDEXT
PF2
PF3
PF4
PF5
VDDEXT
PF6
PF7
PF8
PF9
GND
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
Figure 97 shows the top view of the LFCSP pin configuration.
Figure 98 shows the bottom view of the LFCSP lead
configuration.
PIN 88
PIN 67
PIN 1
PIN 66
PIN 1 INDICATOR
ADSP-BF50X
88-LEAD LFCSP
TOP VIEW
PIN 22
PIN 45
PIN 23
PIN 44
Figure 97. 88-Lead LFCSP Lead Configuration (Top View)
PIN 67
PIN 88
PIN 66
PIN 1
ADSP-BF50X
88-LEAD
LFCSP
BOTTOM VIEW
GND PAD
(PIN 89)
PIN 1 INDICATOR
PIN 45
PIN 22
PIN 46
PIN 23
Figure 98. 88-Lead LFCSP Lead Configuration (Bottom View)
Rev. PrC
| Page 77 of 80 | January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions in Figure 99 (for the 120-lead LQFP) and in
Figure 100 (for the 88-lead LFCSP) are shown in millimeters.
16.20
16.00 SQ
15.80
14.10
14.00 SQ
13.90
91
120
1
1.60
MAX
0.75
0.60
0.45
0.23
0.18
0.13
PIN 1
1.00 REF
VIEW A
12°
1.45
1.40
1.35
0.15
0.10
0.05
90
SEATING
PLANE
0.20
0.15
0.09
7°
0°
0.40
BSC
LEAD
PITCH
TOP VIEW
(PINS DOWN)
30
61
31
0.08 MAX
COPLANARITY
60
4.60 REF
VIEW A
0.77 REF
1.53
31
60
61
30
6.17
REF
1.915
EXPOSED PAD
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
90
1
91
120
BOTTOM VIEW
(PINS UP)
COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD
Figure 99. 120-Lead LQFP (SQ-120-2)
Rev. PrC
2.945
REF
SQ
| Page 78 of 80 | January 2010
2.81
REF
SQ
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
12.10
12.00 SQ
11.90
0.60
MAX
0.60 MAX
88
67
66
PIN 1
INDICATOR
1
PIN 1
INDICATOR
11.85
11.75 SQ
11.65
0.50
BSC
0.50
0.40
0.30
45
44
SEATING
PLANE
22
10.50
REF
0.70
0.65
0.60
12° MAX
23
BOTTOM VIEW
TOP VIEW
0.85
0.80
0.75
6.70
REF SQ
EXPOSED PAD
0.30
0.23
0.18
0.045
0.025
0.005
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.138~0.194 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VRRD.
Figure 100. 88-Lead LFCSP (BC-CP-1)
SURFACE MOUNT DESIGN
Table 56 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 56. Surface Mount Design Supplement
Package
120-Lead LQFP
88-Lead LFCSP
Ball Attach Type
Solder Mask Defined
Solder Mask Defined
Solder Mask Opening
TBD mm diameter
TBD mm diameter
Lead Pad Size
TBD mm diameter
TBD mm diameter
ORDERING GUIDE
Table 57. ADSP-BF50x Processors1
Model
ADSPBF504BCPZ-ENG
ADSPBF504FBCPZ-ENG
ADSPBF506FBSWZ-ENG
1
2
Temperature
Range2
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
Processor Instruction
Rate (Max)
400 MHz
400 MHz
400 MHz
Package Description
88-Lead LFCSP
88-Lead LFCSP
120-Lead LQFP
For feature comparison between ADSP-BF504, ADSP-BF504F, and ADSP-BF506F processors, see the Processor Comparison in Table 1 on Page 3.
Referenced temperature is ambient temperature.
Rev. PrC
| Page 79 of 80 | January 2010
Package
Option
BC-CP-1
BC-CP-1
SQ-120-2
Preliminary Technical Data
ADSP-BF504/F,ADSP-BF506F
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08560-0-1/10(PrC)
Rev. PrC
| Page 80 of 80 | January 2010