CS5231-3 CS5231-3 500mA, 3.3V Linear Regulator with Auxiliary Control Features Description The CS5231-3 combines a threeterminal linear regulator with circuitry to control an external PFET transistor with the intent of managing two input supplies. A 5V supply powers the regulator while an auxiliary 3.3V supply is controlled by the IC. The design has been optimized to provide a “glitch-free” transition between the two supplies. The CS5231-3 linear regulator provides a fixed 3.3V output @ 500mA with an overall accuracy of ± 2%. The NPN-PNP composite pass transistor provides a low dropout voltage and requires less supply current than PNP designs. Full protection including current limit and thermal shutdown is provided. Also designed for low reverse current, the IC prevents excessive cur- rent from flowing from the output to ground if the regulator input voltage is lower than the output voltage. The CS5231-3 also controls an auxiliary supply that can provide power to the regulator output when input voltage for the regulator is not available. The AuxDrv auxiliary output is normally pulled up to the regulator input voltage and drives low whenever the input voltage drops below 4.4V (nominal). It is typically used to control a PFET switch that connects a 3.3V auxiliary supply to the regulator output. The CS5231-3 is available in a 5-lead D2PAK (TO-263) package. Applications include Network Interface Cards (NICs), modem cards and power supplies with multiple input sources. Linear Regulator ■ 3.3V ± 2% Output Voltage ■ 3mA Quiescent Current @ 500mA ■ Fast Transient Response ■ Current Limit ■ Thermal Shutdown with Hysteresis ■ 450µA Reverse Output Current ■ Fast Transient Response System Power Management ■ Auxiliary Supply Control Package Options Block Diagram 5 Lead D2PAK VOUT VIN 50kΩ Internal Bias AuxDrv Current Limit − VIN UV Comparator Error Amp + − Bandgap Reference 1 1. No Connect Shutdown 2. VIN + 10kΩ VREF 3. Gnd 4. VOUT 5. AuxDrv Gnd Thermal Shutdown Tab = Gnd Consult factory for other package options. Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 3/31/99 1 A ® Company CS5231-3 Absolute Maximum Ratings Maximum Operating Junction Temperature ..........................................................................................................................150°C Storage Temperature Range .....................................................................................................................................-65°C to +150°C Lead Temperature Soldering Reflow (SMD styles only) ...........................................................................................60 sec. max above 183°C, 230°C peak ESD Damage Threshold (Human Body Model)....................................................................................................................2kV PIN SYMBOL PIN NAME VMAX VMIN ISOURCE ISINK VIN IC Power Input 14V -0.3V 100mA Internally Limited VOUT Output Voltage 6V -0.3V Internally Limited 100mA Auxiliary Drive Output 14V -0.3V 10mA 50mA IC Ground N/A N/A N/A N/A AuxDrv Gnd Electrical Characteristics: 0°C < TA < 70°C, 0°C < TJ < 125°C, 4.75V ≤ VCC < 6V, COUT ≥ 10µF with ESR < 1Ω, IOUT = 10mA, unless otherwise specified. PARAMETER ■ Linear Regulator Output Voltage Line Regulation Load Regulation Ground Current Reverse Current Current Limit Thermal Shutdown Thermal Shutdown Hysteresis ■ Auxiliary Drive Upper VIN Threshold Lower VIN Threshold VIN Threshold Hysteresis Output Low Voltage Output Low Peak Voltage AuxDrv Current Limit Response Time Pull-Up/Down Resistance TEST CONDITIONS 10mA < IOUT < 500mA IOUT = 10mA, VIN = 4.75V to 6V VIN = 5V, IOUT = 10mA to 500mA IOUT = 10mA IOUT = 500mA VIN = 0V, VOUT = 3.3V 0V < VOUT < 3.2V Note 1 Note 1 MIN TYP 3.234 -2% 3.300 3.366 +2% V 1 5 mV 5 15 mV 2 3 0.45 0.85 180 25 3 6 1 1.2 210 mA mA mA A °C °C 0.55 150 MAX UNIT Increase VIN until regulator turns on and AuxDrv drives high 4.35 4.5 4.65 V Decrease VIN until regulator turns off and AuxDrv drives low 4.25 4.4 4.55 V 75 100 0.1 125 0.4 mV V 0.65 0.9 V 6 25 mA 1 10 µs 10 25 kΩ IAuxDrv = 100µA, 1V < VIN < 4.5V Increase VIN from 0V to 1V. Record peak AuxDrv output voltage VAuxDrv = 1V, VIN = 4.0V Step VIN from 5V to 4V, measure time for VAuxDrv to drive low. Note 1 VIN = 0V and VIN > 4.7V 0.5 5 Note 1: Guaranteed by design, not 100% production tested. Thermal shutdown is 100% functionally tested at wafer probe. 2 CS5231-3 Package Pin Description PACKAGE PIN # 5Lead D2 PIN SYMBOL FUNCTION PAK 1 N/C No connection. 2 VIN Input voltage. 3 Gnd Ground and IC substrate connection (case). 4 VOUT Regulated output voltage. 5 AuxDrv Output used to control an auxiliary supply voltage. This lead is driven low if VIN is less than 4.5V, and is otherwise pulled up to VIN through an internal 10kΩ resistor. Typical Performance Characteristics 80 IOUT = 10mA 3.302 4.75V <VIN < 6V Line Regulation (µV) Output Voltage (V) 70 3.300 IOUT = 500mA 3.298 3.296 60 125°C 50 27°C 40 0°C 0 20 40 60 80 100 0.0 120 0.2 0.4 IOUT (A) Junction Temperature (°C) Line Regulation vs. IOUT Over Temperature Output Voltage vs. Junction Temperature 1.2 125°C Reverse Current (µA) Load Regulation (mV) 1.0 0.8 0.6 0.4 27°C 390 380 370 0.2 360 0°C 0.0 0.0 0.2 0 0.4 20 40 60 80 Junction Temperature (°C) IOUT (A) Load Regulation vs. IOUT Over Temperature Reverse Current vs. Junction Temperature 3 100 120 CS5231-3 Typical Performance Characteristics: continued 4.520 125°C 3 4.500 VIN Turn-on Threshold 4.480 VIN Threshold Voltage (V) VOUT (V) 27°C 2 0°C 1 4.460 4.440 4.420 VIN Turn-on Threshold 4.400 0 4.380 0.0 0.2 0.4 0.6 0.8 40 20 0 1.0 IOUT (A) VOUT vs. IOUT Over Temperature 80 100 120 140 6.0 7.0 VIN Thresholds vs. Junction Temperature 1000 2.6 2.4 TJ = 0°C IGnd @ 0°C 2.2 Capacitance (µF) Ground Current (mA) 60 Junction Temperature (C) TJ = 27°C IGnd @ 27°C 2.0 1.8 100 TJ = 125°C IGnd @ 125°C 1.6 10 0.0 0.2 0.0 0.4 1.0 2.0 3.0 4.0 5.0 Capacitance ESR(Ω) Load Current (A) Ground Current vs. Load Current Region of Stable Operation 5.000 3.400 Current Limit (mA) VOUT 4.800 3.300 CIN = 33µF COUT = 33µF VIN = 5.00V 4.600 3.200 4.400 4.200 IOUT 500mA 4.000 0 20 40 60 80 Temperature (C) 100 120 140 AuxDrv Current Limit vs. Junction Temperature 10mA Transient Response 4 Time, 5µs per division CS5231-3 Application Circuit +5V PCI C1 33µF VOUT VIN CS5231-3 Gnd AuxDrv M1 ASIC VDD +3.3V VAUX C3 33µF C1 33µF *indicates PFET body diode Application Information external compensation capacitor is required for the linear regulator to be stable, and this capacitance also serves as a charge reservoir to minimize any “glitching” that might result during the supply changeover. Hysteresis is present in the AuxDrv circuitry, requiring VIN to drop by 100mV (typical) after the linear regulator is providing power to the load before the AuxDrv circuitry can be re-enabled. Theory of Operation The CS5231-3 is a fixed 3.3V linear regulator that contains an auxiliary drive control feature. When VIN is greater than the typical 4.5V threshold, the IC functions as a linear regulator. It provides up to 500mA of current to a load through a composite PNP-NPN pass transistor. An output capacitor greater than 10µF with equivalent series resistance less than 1Ω is required for compensation. More information is provided in the Stability Considerations section. The CS5231-3 provides an auxiliary drive feature that allows a load to remain powered even if the VIN supply for the IC is absent. An external p-channel FET is the only additional component required to implement this function if an auxiliary power supply is available. The PFET gate is connected to the AuxDrv lead. The PFET drain is connected to the auxiliary power supply, and the PFET source is connected to the load. The polarity of this connection is very important, since the PFET body diode will be connected between the load and the auxiliary supply. If the PFET is connected with its drain to the load and its source to the supply, the body diode will be forward-biased if the auxiliary supply is turned off. This will result in the linear regulator providing current to everything on the auxiliary supply rail. The AuxDrv lead is internally connected to a 10kΩ resistor and to a saturating NPN transistor that acts as a switch. If the VIN supply is off, the AuxDrv output will connect the PFET gate to ground through the 10kΩ resistor, and the PFET will conduct current to the load. As the VIN supply begins to rise, the AuxDrv lead will also rise until it reaches a typical voltage of about 650mV. The NPN transistor connected to the AuxDrv lead will saturate at this point, and the gate of the PFET will be pulled down to a typical voltage of about 100mV. The PFET will continues to conduct current to the load. The VIN supply voltage will continue to rise, but the linear regulator output is disabled until VIN reaches a typical threshold of 4.5V. During this time, the load continues to be powered by the auxiliary driver. Once the 4.5V VIN threshold is reached, the saturating NPN connected to the AuxDrv lead turns off. The on-chip 10kΩ pull-up resistor will pull the PFET gate up to VIN, thus turning the PFET off. The linear regulator turns on at the same time. An VIN VOUT VAUXDRV IOUT = STARTUP 375mA Figure 1. Initial power-up, VAUX not present ROUT = 8.8Ω. VIN VOUT VAUXDRV IOUT = 375mA VAUX = 3.30V Figure 2a. Power-up, VAUX = 3.30V. Note the “oscillatory performance” as the linear regulator charges the VOUT node. IOUT × RDS(ON) ≈ 130mV 5 CS5231-3 Application Information: continued VIN VIN VOUT VOUT VAUXDRV VAUXDRV IOUT = 375mA VAUX = 3.465 IOUT = 375mA VAUX = 3.30 Figure 4a. Power-up, VAUX = 3.465V. IOUT × RDS(ON) is compensated by the higher value of VAUX Figure 2b. Power-down, VAUX = 3.30V. Again, note ∆V = IOUT RDS(ON) ≈ 130mV. VIN VIN VOUT VOUT VAUXDRV VAUXDRV IOUT = 375mA VAUX = 3.465 IOUT = 375mA VAUX = 3.135V Figure 3a. Power-up, VAUX = 3.135V. The “oscillatory performance” mode lasts longer because the difference between VAUX and 3.30 is greater. Figure 4b. Power-down, VAUX = 3.465V. Stability Considerations The output capacitor helps determine three main characteristics of a linear regulator: startup, transient response and stability. Startup is affected because the output capacitor must be charged. At initial startup, the VIN supply may not be present, and the output capacitor will be charged through the PFET. The PFET will initially provide current to the load through its body diode. The diode will act as a voltage follower until sufficient voltage is present to turn the FET on. Since most commercial power supplies have a fairly low ramp rate, charging through the body diode should effectively limit in-rush current to the capacitor. During normal operation, transient load current requirements will be satisfied from the charge stored in the output capacitor until either the linear regulator or the auxiliary supply can respond. Larger values of capacitance will improve transient response, but will also cost more. A linear regulator will respond within microseconds, where an external power supply may take milliseconds to react. The output capacitance will provide the difference in current until this occurs. The result will be an instantaneous voltage change at the output. This change is the product of the current change and the capacitor ESR: VIN VOUT VAUXDRV IOUT = 375mA VAUX = 3.135 Figure 3b. Power-down, VAUX = 3.135V. The difference in voltage is now IOUT × RDS(ON) plus the difference in supply voltages (3.30 -VAUX). 6 ∆VOUT = (∆ILOAD) (ESR) If required, using a few capacitors in parallel to increase the bulk charge storage and reduce the ESR should give better performance than using a single input capacitor. Short, straight connections between the power supply and VIN lead along with careful layout of the PC board ground plane will reduce parasitic inductance effects. Wide VIN and VOUT traces will reduce resistive voltage drops. This limitation directly affects load regulation. Capacitor ESR must be minimized if output voltage must be maintained within tight tolerances. In such a case, it is often advisable to use a parallel network of different types of capacitors. For example, electrolytic capacitors provide high charge storage capacity in a small size, while tantalum capacitors have low ESR. The parallel combination will result in a high capacity, low ESR network. It is also important to physically locate the capacitance network close to the load, and to connect the network to the load with wide PC board traces to minimize the metal resistance. The CS5231-3 has been carefully designed to be stable for output capacitances greater than 10µF with equivalent series resistance less than 1Ω. While careful board layout is important, the user should have a stable system if these constraints are met. A graph showing the region of stability for the CS5231-3 is included in the “Typical Performance Characteristics” section of this data sheet. Choosing the PFET Switch The choice of the external PFET switch is based on two main considerations. First, the PFET should have a very low turn-on threshold. Choosing a switch transistor with VGS(ON) ≈ 1V ensures the PFET will be fully enhanced with only 3.3V of gate drive voltage. Second, the switch transistor should be chosen to have a low RDS(ON) to minimize the voltage drop due to current flow in the switch. The formula for calculating the maximum allowable on-resistance is RDS(ON)(MAX) = Input Capacitors and the VIN Thresholds VAUX(MIN) − VOUT(MIN) 1.5 × IOUT(MAX) where VAUX(MIN) is the minimum value of the auxiliary supply voltage, VOUT(MIN) is the minimum allowable output voltage, IOUT(MAX) is the maximum output current and 1.5 is a “fudge factor” to account for increases in RDS(ON) due to temperature. A capacitor placed on the VIN pin will help to improve transient response. During a load transient, the input capacitor serves as a charge “reservoir”, providing the needed extra current until the external power supply can respond. One of the consequences of providing this current is an instantaneous voltage drop at VIN due to capacitor ESR. The magnitude of the voltage change is again the product of the current change and the capacitor ESR. It is very important to consider the maximum current step that can exist in the system. If the change in current is large enough, it is possible that the instantaneous voltage drop on VIN will exceed the VIN threshold hysteresis, and the IC will enter a mode of operation resembling an oscillation. As the part turns on, the output current IOUT will increase, reaching current limit during initial charging. Increasing IOUT results in a drop at VIN such that the shutdown threshold is reached. The part will turn off, and the load current will decrease. As IOUT decreases, VIN will rise and the part will turn on, starting the cycle all over again. This oscillatory operation is most likely at initial startup when the output capacitance is not charged, and in cases where the ramp-up of the VIN supply is slow. It may also occur during the power transition when the linear regulator turns on and the PFET turns off. a 15µs delay exists between turn-on of the regulator and the AUXDRV pin pulling the gate of the PFET high. This delay prevents “chatter” during the power transitions. During this interval, the linear regulator will attempt to regulate the output voltage as 3.3V. If the output voltage is significantly below 3.3V, the IC will go into current limit while trying to raise VOUT. It is a short-lived phenomenon and is mentioned here to alert the user that the condition can exist. It is typically not a problem in applications. Careful choice of the PFET switch with respect to RDS(ON) will minimize the voltage drop which the output must charge through to return to a regulated state. More information is provided in the section on choosing the PFET switch. Output Voltage Sensing It is not possible to remotely sense the output voltage of the CS5231-3 since the feedback path to the error amplifier is not externally available. It is important to minimize voltage drops due to metal resistance of high current PC board traces. Such voltage drops can occur in both the supply traces and the return traces. The following board layout practices will help to minimize output voltage errors: • Always place the linear regulator as close to both load and output capacitors as possible. • Always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. • Connect the load to ground through the widest possible traces. • Connect the IC ground to the load ground trace at the point where it connects to the load. Current Limit The CS5231-3 has internal current limit protection. Output current is limited to a typical value of 850mA, even under output short circuit conditions. If the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition. The IC does not contain circuitry to report this fault. Thermal Shutdown The CS5231-3 has internal temperature monitoring circuitry. The output is disabled if junction temperature of the IC reaches a typical value of 180°C. Thermal hysteresis is typi7 CS5231-3 Application Information: continued and heatsink-to-air thermal resistance (θSA). The resulting equation for junction-to-air thermal resistance is cally 25°C and allows the IC to recover from a thermal fault without the need for an external reset signal. The monitoring circuitry is located near the composite PNPNPN output transistor, since this transistor is responsible for most of the on-chip power dissipation. The combination of current limit and thermal shutdown will protect the IC from nearly any fault condition. θJA = θJC + θCS + θSA The value of θJC for the CS5231-3 is provided in the Packaging Information section of this data sheet. θCS can be considered zero, since heat is conducted out of the package by the IC leads and the tab of the D2PAK package, and since the IC leads and tab are soldered directly to the PC board. Modification of θSA is the primary means of thermal management. For surface mount components, this means modifying the amount of trace metal that connects to the IC. The thermal capacity of PC board traces is dependent on how much copper area is used, whether or not the IC is in direct contact with the metal, whether or not the metal surface is coated with some type of sealant, and whether or not there is airflow across the PC board. The chart provided below shows heatsinking capability of a square, single sided copper PC board trace. The area is given in square millimeters. It is assumed there is no airflow across the PC board. Reverse Current Protection During normal system operation, the auxiliary drive circuitry will maintain voltage on the VOUT pin when VIN is absent. IC reliability and system efficiency are improved by limiting the amount of reverse current that flows from VOUT to ground and from VOUT to VIN. Current flows from VOUT to ground through the feedback resistor divider that sets up the output voltage. This resistor can range in value from 6kΩ to about 10kΩ, and roughly 500µA will flow in the typical case. Current flow from VOUT to VIN will be limited to leakage current after the IC shuts down. On-chip RC time constants are such that the output transistor should be turned off well before VIN drops below the VOUT voltage. 70 Calculating Power Dissipation and Heatsink Requirements Thermal Resistance, °C/W CS5231-3 Application Information: continued Most linear regulators operate under conditions that result in high on-chip power dissipation. This results in high junction temperatures. Since the IC has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. Some heatsinking will usually be required. Thermal characteristics of an IC depend on four parameters: ambient temperature (TA in °C), power dissipation (PD in watts), thermal resistance from the die to the ambient air (θJA in °C per watt) and junction temperature (TJ in °C). The maximum junction temperature is calculated from the formula below: 60 50 40 30 20 10 0 0 2000 4000 6000 PC Board Trace Area (mm2) Figure 5: Thermal Resistance Capability of Copper PC Board Metal Traces TJ(MAX) = TA(MAX) + (θJA) (PD(MAX)) Typical D2PAK PC Board Heatsink Design Maximum ambient temperature and power dissipation are determined by the design, while θJA is dependent on the package manufacturer. The maximum junction temperature for operation of the CS5231-3 within specification is 150°C. The maximum power dissipation of a linear regulator is given as A typical design of the PC board surface area needed for the D2PAK package is shown below. Calculations were made assuming VIN(MAX) =5.25V, VOUT(MIN) = 3.266V, IOUT(MAX) = 500mA, IGnd(MAX) = 5mA and TA = 70°C. PD = (5.25V − 3.266V) (0.5A) + (5.25V) (0.005A) = 1018mW PD(MAX) = (Vin(MAX) − VOUT(MIN)) (ILOAD(MAX)) + (VIN (MAX)) (IGnd(MAX)) Maximum temperature rise ∆T = TJ(MAX) − TA = 150°C − 70°C = 80°C. where IGnd(MAX) is the IC bias current. It is possible to change the effective value of θJA by adding a heatsink to the design. A heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. Each material in the path of heat flow has its own characteristic thermal resistance, all measured in °C per watt. The thermal resistances are summed to determine the total thermal resistance between the die junction and air. There are three components of interest: junction-to-case thermal resistance (θJC), case-to-heatsink thermal resistance (θCS) θJA (worst case) = ∆T/PD = 80°C/1.018W = 78.56°C/W First, we determine the need for heatsinking. If we assume the maximum θJA = 50°C/W for the D2PAK, the maximum temperature rise is found to be ∆T = (PD) (θJA) = (1.018W) (50°C/W) = 50.9°C This is less than the maximum specified operating junction temperature of 125°C, and no heatsinking is required. Since the D2PAK has a large tab, mounting this part to the 8 PC board by soldering both tab and leads will provide superior performance with no PC board area penalty. The VOUT Connection The VOUT connection is tied to the VOUT lead of the CS5231-3 and the PFET source. This point provides a convenient point at which some type of lead may be applied. Description The CS5231-3 application circuit has been implemented as shown in the following pages. The schematic, bill of materials and printed circuit board artwork can be used to build the circuit. The design is very simple and consists of two capacitors, a p-channel FET and the CS5231-3. Five turret pins are provided for connection of supplies, meters, oscilloscope probes and loads. The CS5231-3 power supply management solution is implemented in an area less than 1.5 square inches. Due to the simplicity of the design, output current must be derated if the CS5231-3 is operated at VIN voltages greater than 7V. Figure 15 provides the derating curve on a maximum power dissipation if heatsink is added. Operating at higher power dissipation without heatsink may result in a thermal shutdown condition. VIN TP1 VIN U1 VOUT TP5 CS5231-3 GND AUXDRV C1 GND TP2 TP3 TP6 AUXDRV Q1 TP4 +3.3V VAUX C2 Application Circuit Schematic PC Board Layout Artwork 600 The PC board is a single layer copper design. The layout artwork is reproduced at actual size below. IOUT (mA) 500 400 300 2" 200 100 0 5 6 7 8 9 10 VIN(VOLTS) 11 12 13 14 1.5" Figure 6: Demo Board Output Current Derating vs VIN The VIN Connection The VIN connection is denoted as such on the PC board. The maximum input voltage to the IC is 14V before damage to the IC is possible. However, the specification range for the IC is 4.75V < VIN < 6V. Top Copper Layer The Gnd Connection The Gnd connection ties the IC power return to two turret pins. The extra turret pin provides for connection of multiple instrument grounds to the demonstration board. 2" VIN 5V AUX.DRV AUX3.3V The AuxDrv Connection The AuxDrv lead of the CS5231-3 is connected to the gate of the external PFET. This connection is also brought to a turret pin to allow easy connection of an oscilloscope probe for viewing the AuxDrv waveforms. 1.5" VOUT 3.3V GND GND The VAUX Connection The VAUX turret pin provides a connection point between an external 3.3V supply and the PFET drain. Top Silk Screen Layer 9 CS5231-3 Application Circuit Characteristics Test Descriptions The startup and supply transition waveforms shown in figures 1 through 4b were obtained using the application circuit board with a resistive load of 8.8Ω. This provides a DC load of 375mA when the regulated output voltage is 3.3V. A standard 2A bench supply was used to provide power to the application circuit. The transient response waveforms shown in the Typical Performance Characteristics section were obtained by switching a 6.3Ω resistor across the output. The graph provided below show typical RDS(ON) performance for the PFET. The data is provided as VDS vs IOUT for different values of VAUX. 160 VAUX = 3.135V 140 VAUX = 3.300V 120 100 VAUX = 3.465V 80 Vds (mV) Temperature Performance The graph below shows thermal performance for the CS5231-3 across the normal operating output current range. 60 40 20 0 0 55 100 200 300 400 IOUT (mA) 50 Package Temperature (C) CS5231-3 Application Circuit Characteristics: continued Figure 8: PFET Vds vs IOUT 45 40 35 30 25 20 0 50 100 150 200 250 300 350 Load Current (mA) 400 450 500 Figure 7: Package Temperature vs Load Current (VIN = 5V, TA =23 C°) PFET RDS(ON) Performance Application Circuit Bill of Materials Refdes Description Part Number Manufacturer Contact Information C1, C2 33µF, 16V tantalum capacitors TAJ336K016 AVX Corp www.avxcorp.com 1-843-448-9411 Q1 p-channel FET transistor MGSF1P02ELT1 Motorola www.mot-sps.com U1 Linear regulator with auxiliary CS5231-3DPS Cherry Semiconductor www.cherry-sem.com 1-800-272-3601 T1-T6 Turret pins 40F6023 Newark Electronics www.newark.com 1-800-463-9275 10 500 CS5231-3 Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) Thermal Data RΘJC RΘJA typ typ 5Lead D2PAK 2.5 10-50* ˚C/W ˚C/W *Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA 5 Lead D2PAK (DP) 10.31 (.406) 10.05 (.396) 1.40 (.055) 1.14 (.045) 1.68 (.066) 1.40 (.055) 8.53 (.336) 8.28 (.326) 15.75 (.620) 14.73 (.580) 2.74(.108) 2.49(.098) 0.91 (.036) 0.66 (.026) 2.79 (.110) 2.29 (.090) 1.70 (.067) REF .254 (.010) REF 0.10 (.004) 0.00 (.000) 4.57 (.180) 4.31 (.170) Ordering Information Part Number CS5231-3GDP5 CS5231-3GDPR5 Rev. 3/31/99 Description 5 Lead D2PAK 5 Lead D2PAK (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 11 © 1999 Cherry Semiconductor Corporation