TI CSD17313Q2Q1 30v n-channel nexfet power mosfet Datasheet

CSD17313Q2Q1
www.ti.com
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
30V N-Channel NexFET™ Power MOSFET
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Optimized for 5V Gate Drive
Ultra Low Qg and Qgd
Low Thermal Resistance
Pb Free
RoHS Compliant
Halogen Free
SON 2-mm × 2-mm Plastic Package
Drain to Source Voltage
30
V
Qg
Gate Charge Total (4.5V)
2.1
nC
Qgd
Gate Charge Gate to Drain
0.4
RDS(on)
Drain to Source On Resistance
VGS(th)
nC
VGS = 3V
31
mΩ
VGS = 4.5V
26
mΩ
VGS = 8V
24
mΩ
Threshold Voltage
1.3
V
ORDERING INFORMATION
APPLICATIONS
•
•
VDS
Device
Package
Media
CSD17313Q2Q1
SON 2-mm × 2-mm
Plastic Package
13-Inch
Reel
DC-DC Converters
Battery and Load Management Applications
Qty
Ship
3000
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
DESCRIPTION
VDS
Drain to Source Voltage
30
V
The NexFET power MOSFET has been designed to
minimize losses in power conversion applications and
optimized for 5V gate drive applications. The 2-mm ×
2-mm SON offers excellent thermal performance for
the size of the package.
VGS
Gate to Source Voltage
+10 / –8
V
Continuous Drain Current, TC = 25°C
5
A
Continuous Drain Current(1)
5
A
IDM
Pulsed Drain Current, TA = 25°C(2)
20
A
PD
Power Dissipation
2.3
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, Single Pulse,
ID = 19A, L = 0.1mH, RG = 25Ω
18
mJ
Top View
D
1
6
D
5
D
4
S
(1) Package Limited
(2) Pulse duration ≤300μs, duty cycle ≤2%
D
D
2
G
3
S
ID
P0108-01
Text For Spacing
RDS(on) vs VGS
Text For Spacing
GATE CHARGE
8
ID = 4A
70
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
80
60
T C = 125°C
50
40
30
20
T C = 25°C
10
ID = 4A
VDS = 15V
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
0
0.5
1
1.5
2
2.5
Qg - Gate Charge - nC
3
3.5
4
G003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CSD17313Q2Q1
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
IDSS
Drain to Source Leakage
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage
VDS = 0V, VGS = +10 / -8V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250μA
RDS(on)
gfs
Drain to Source On Resistance
Transconductance
30
0.9
V
1
μA
100
nA
1.3
1.8
V
VGS = 3V, ID = 4A
31
42
mΩ
VGS = 4.5V, ID = 4A
26
32
mΩ
VGS = 8V, ID = 4A
24
30
mΩ
VDS = 15V, ID = 4A
16
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
260
340
pF
140
180
Crss
pF
Reverse Transfer Capacitance
13
17
pF
RG
Series Gate Resistance
1.3
2.6
Ω
Qg
Gate Charge Total (4.5V)
2.1
2.7
nC
Qgd
Gate Charge – Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VDS = 15V,
f = 1MHz
VDS = 15V,
ID = 4A
VDS = 13.5V, VGS = 0V
VDS = 15V, VGS = 4.5V,
ID = 4A, RG = 2Ω
0.4
nC
0.7
nC
0.3
nC
3.8
nC
2.8
ns
3.9
ns
4.2
ns
1.3
ns
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 4A, VGS = 0V
0.85
VDD= 13.5V, IF = 4A,
di/dt = 300A/μs
1
V
6.4
nC
12.9
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
TYP MAX
UNIT
RθJC
Thermal Resistance Junction to Case (1)
PARAMETER
7.4
°C/W
RθJA
Thermal Resistance Junction to Ambient (1) (2)
67
°C/W
(1)
(2)
2
MIN
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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Copyright © 2012–2013, Texas Instruments Incorporated
CSD17313Q2Q1
www.ti.com
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
Max RθJA = 67°C/W
when mounted on
1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick)
Cu.
G1 D1
S1
Max RθJA = 228°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
G1 S1 D1
M0179-01
M0180-01
Text Added For Spacing
Text Added For Spacing
Text Added For Spacing
Text Added For Spacing
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
ZqJA - Normalized Thermal Impedance
10
1
0.5
0.3
0.1
Duty Cycle = t1/t2
0.1
0.05
P
0.02
0.01
t1
0.01
t2
Typical RqJA = 182°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
Single Pulse
0.001
0.0001
0.001
0.01
0.1
1
tp - Pulse Duration - s
10
100
1k
G012
Figure 1. Transient Thermal Impedance
Copyright © 2012–2013, Texas Instruments Incorporated
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SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
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TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
10
9
9
8
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
TEXT ADDED FOR SPACING
10
VGS = 8V
7
VGS = 4.5V
6
VGS = 3.5V
5
4
VGS = 3V
3
VGS = 2.5V
2
TEXT ADDED FOR SPACING
VDS = 5V
8
7
T C = 125°C
6
5
T C = 25°C
4
3
T C = -55°C
2
1
1
0
0
0
0.2
0.4
0.6
0.8
VDS - Drain-to-Source Voltage - V
1
1
1.2
1.4
G001
Figure 2. Saturation Characteristics
C - Capacitance - nF
VGS - Gate-to-Source Voltage - V
6
5
4
3
2
0.5
Coss = Cds + Cgd
0.4
Ciss = Cgd + Cgs
0.3
0.2
Crss = Cgd
0.1
1
0
0
0.5
1
1.5
2
2.5
Qg - Gate Charge - nC
3
3.5
4
0
5
10
15
20
VDS - Drain-to-Source Voltage - V
G003
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
RDS(on) - On-State Resistance - mΩ
1.2
1
0.8
0.6
0.4
0.2
0
-75
30
G004
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
80
ID = 250µA
1.4
25
Figure 5. Capacitance
1.6
VGS(th) - Threshold Voltage - V
G002
f = 1MHz
VGS = 0V
0.6
0
ID = 4A
70
60
T C = 125°C
50
40
30
20
T C = 25°C
10
0
-25
25
75
T C - Case Temperature - °C
125
175
Figure 6. Threshold Voltage vs. Temperature
4
3
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
0.7
ID = 4A
VDS = 15V
7
2.8
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
8
1.6 1.8
2
2.2 2.4 2.6
VGS - Gate-to-Source Voltage - V
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G005
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
Copyright © 2012–2013, Texas Instruments Incorporated
CSD17313Q2Q1
www.ti.com
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
ID = 4A
VGS = 8V
1.4
ISD - Source-to-Drain Current - A
Normalized On-State Resistance
1.6
1.2
1
0.8
0.6
0.4
0.2
-75
1
T C = 125°C
0.1
T C = 25°C
0.01
0.001
0.0001
-25
25
75
T C - Case Temperature - °C
125
175
0
0.2
G007
Figure 8. Normalized On-State Resistance vs. Temperature
1
G008
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
100
1ms
10ms
100ms
1s
DC
I(AV) - Peak Avalanche Current - A
IDS - Drain-to-Source Current - A
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
100
10
1
0.1
Single Pulse
Typical RthetaJA =182ºC/W(min Cu)
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage - V
50
G001
Figure 10. Maximum Safe Operating Area
T C = 25°C
10
T C = 125°C
1
0.01
0.1
1
t(AV) - Time in Avalanche - ms
10
G010
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
IDS - Drain-to-Source Current - A
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100 125
T C - Case Temperature - °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2012–2013, Texas Instruments Incorporated
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CSD17313Q2Q1
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
www.ti.com
MECHANICAL DATA
Q2 Package Dimensions
D2
D
K3
K1
K
K2
4
4
5
6
8
K4
E
7
E1
E2
5
E3
6
Pin 1 Dot
2
3
3
L
1
Top View
2
1
Pin 1 ID
e
b
D1
Pinout
A
A1
C
Bottom View
Source
4, 7
Gate
3
Drain
1, 2, 5, 6, 8
Front View
M0175-02
DIM
MILLIMETERS
MIN
NOM
MAX
MIN
NOM
MAX
A
0.700
0.750
0.800
0.028
0.030
0.032
A1
0.000
0.050
0.000
b
0.250
0.350
0.010
0.300
C
0.203 TYP
D
2.000 TYP
D1
0.900
0.950
D2
0.300 TYP
E
2.000 TYP
E1
0.900
1.000
0.002
0.012
0.080 TYP
1.000
0.036
0.038
0.080 TYP
1.100
0.036
0.040
0.280 TYP
0.0112 TYP
0.470 TYP
0.0188 TYP
e
0.650 BSC
0.026 TYP
K
0.280 TYP
0.0112 TYP
K1
0.350 TYP
0.014 TYP
K2
0.200 TYP
0.008 TYP
K3
0.200 TYP
0.008 TYP
0.470 TYP
0.200
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0.25
0.040
0.012 TYP
E3
L
0.014
0.008 TYP
E2
K4
6
INCHES
0.044
0.0188 TYP
0.300
0.008
0.010
0.012
Copyright © 2012–2013, Texas Instruments Incorporated
CSD17313Q2Q1
www.ti.com
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing through
PCB Layout Techniques.
Recommended Stencil Pattern
Note:
All dimensions are in mm, unless otherwise specified.
Copyright © 2012–2013, Texas Instruments Incorporated
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CSD17313Q2Q1
SLPS427C – OCTOBER 2012 – REVISED MARCH 2013
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Q2 Tape and Reel Information
4.00 ±0.10
Ø 1.50 ±0.10
4.00 ±0.10
Ø 1.00 ±0.25
1.00 ±0.05
2.30 ±0.05
10° Max
3.50 ±0.05
8.00
+0.30
–0.10
1.75 ±0.10
2.00 ±0.05
0.254 ±0.02
2.30 ±0.05
10° Max
M0168-01
Notes: 1. Measured from centerline of sprocket hole to centerline of pocket
2. Cumulative tolerance of 10 sprocket holes is ±0.20
3. Other material available
4. Typical SR of form tape Max 108 OHM/SQ
5. All dimensions are in mm, unless otherwise specified.
REVISION HISTORY
Changes from Original (October 2012) to Revision A
•
Page
Changed the device number From: CSD17313Q2-Q1 To: CSD17313Q2Q1 ...................................................................... 1
Changes from Revision A (November 2012) to Revision B
Page
•
Changed the Recommended PCB Pattern ........................................................................................................................... 7
•
Added the Recommended Stencil Pattern ............................................................................................................................ 7
Changes from Revision B (January 2013) to Revision C
•
8
Page
Changed Figure 10, Maximum Safe Operating Area ........................................................................................................... 5
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Copyright © 2012–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD17313Q2Q1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SON
DQK
6
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU SN
Level-1-260C-UNLIM
(4)
-50 to 150
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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