CAT4109, CAV4109 3-Channel Constant-Current RGB LED Driver with Individual PWM Dimming Description The CAT4109/CAV4109 is a 3−channel constant−current LED driver, requiring no inductor. LED channel currents up to 175 mA are programmed independently via separate external resistors. Low output voltage operation of 0.4 V at 175 mA allows for more power efficient designs across wider supply voltage range. The three LED pins are compatible with high voltage up to 25 V supporting applications with long strings of LEDs. Three independent control inputs PWM1, PWM2, PWM3, control respectively LED1, LED2, LED3 channels. The device also includes an output enable (OE) control pin to disable all three channels independently of the PWMx input states. Thermal shutdown protection is incorporated in the device to disable the LED outputs whenever the die temperature exceeds 150°C. The device is available in a 16−lead SOIC package. Features • • • • • • • • • • • 3 Independent Current Sinks up to 175 mA rated 25 V LED Current Set by External Low Power Control Resistors Individual PWM Control per Channel Low Dropout Current Source (0.4 V at 175 mA) Output Enable Input for Dimming “Zero” Current Shutdown Mode 3 V to 5.5 V Logic Supply Thermal Shutdown Protection 16−lead SOIC Package CAV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Application • Multi−color LED, Architectural Lighting • LED Signs and Displays • LCD Backlight www.onsemi.com SOIC−16 V SUFFIX CASE 751BG PIN CONNECTIONS PGND 1 VDD GND OE PWM3 NC PWM2 NC PWM1 NC RSET3 LED1 RSET2 LED2 RSET1 LED3 (Top View) MARKING DIAGRAM L3A CAT4109VB YMXXXX L = Assembly Location 3 = PB Free A = Product Revision (Fixed as “A”) CAT4109V = Device Code B = Leave Blank Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXXX = Last Four Digits of Assembly Lot Number ORDERING INFORMATION Device Package Shipping CAT4109V−GT2 (Note 1) SOIC−16 (Pb−Free) 2,000/ Tape & Reel CAV4109V−GT2 (Note 1) SOIC−16 (Pb−Free) 2,000/ Tape & Reel 1. Lead Finish Pb−Free © Semiconductor Components Industries, LLC, 2015 May, 2015 − Rev. 6 1 Publication Order Number: CAT4109/D CAT4109, CAV4109 VIN 5 V to 25 V VDD 3 V to 5.5 V C1 1 mF VDD OE PWM1 PWM2 PWM3 CONTROLLER RSET1 RSET2 RSET3 R1 R2 RED GREEN BLUE LED1 LED2 LED3 CAT4109/CAV4109 GND PGND R3 Figure 1. Typical Application Circuit Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units 6 V −0.3 V to 6 V V LED1, LED2, LED3 Voltage 25 V DC Output Current on LED1 to LED3 200 mA Storage Temperature Range −55 to +160 °C Junction Temperature Range −40 to +150 °C 300 °C VDD Voltage Input Voltage Range (OE, PWM1, PWM2, PWM3) Lead Soldering Temperature (10 sec.) ESD RATING Human Body Model (Note 2) LV pins (non LEDn pins # 3, 4, 5, 6, 7, 8, 15 and 16) HV pins( LEDn pins #9, 10 and 11) 1500 500 Machine Model (Note 3) LV pins (non LEDn pins # 3, 4, 5, 6, 7, 8, 15 and 16) HV pins ( LEDn pins #9, 10 and 11) 200 175 Charged Device Model (Note 4) 1000 V V V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JESD22−A114C 3. JESD625−A 4. JESD22−C101E Table 2. RECOMMENDED OPERATING CONDITIONS Range Units VDD Parameter 3.0 to 5.5 V Voltage applied to LED1 to LED3, outputs off up to 25 V Voltage applied to LED1 to LED3, outputs on up to 6 (Note 5) V 2 to 175 mA −40 to +85 −40 to +105 °C °C Output Current on LED1 to LED3 Ambient Temperature Range CAT4109 CAV4109 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. Keeping LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package. www.onsemi.com 2 CAT4109, CAV4109 Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over recommended operating conditions unless specified otherwise. Typical values are at VDD = 5.0 V, TAMB = 25°C.) Name Symbol Conditions Min Typ Max Units DC CHARACTERISTICS IDD1 Supply Current Outputs Off VLED = 5 V, RSET = 24.9 kW 2 5 mA IDD2 Supply Current Outputs Off VLED = 5 V, RSET = 5.23 kW 4 10 mA IDD3 Supply Current Outputs On VLED = 0.5 V, RSET = 24.9 kW 2 5 mA IDD4 Supply Current Outputs On VLED = 0.5 V, RSET = 5.23 kW 4 10 mA Shutdown Current VOE = 0 V 1 mA ILKG LED Output Leakage VLED = 5 V, Outputs Off 1 mA ROE OE Pull−down Resistance 140 250 kW OE Logic High Level OE Logic Low Level 1.3 ISHDN VOE_IH VOE_IL VPWM_IH VPWM_IL IIL VRSETx −1 PWMx Logic High Level PWMx Logic Low Level Logic Input Leakage Current (PWMx) 190 0.4 0.7 x VDD VPWMx = VDD or GND RSETx Regulated Voltage 0.3 x VDD V V −5 0 5 mA 1.17 1.2 1.23 V TSD Thermal Shutdown 150 °C THYS Thermal Hysteresis 20 °C ILED/IRSET VUVLO RSET to LED Current Gain Ratio 100 mA LED Current 400 Undervoltage Lockout (UVLO) Threshold 1.8 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. RECOMMENDED TIMING (Min and Max values are over recommended operating conditions unless specified otherwise. Typical values are at VDD = 5.0 V, TAMB = 25°C.) Name Symbol Conditions Min Typ Max Units tPS Turn−On time, OE rising to ILED from Shutdown ILED = 100 mA 1.4 ms tP1 Turn−On time, OE or PWMx rising to ILED ILED = 100 mA 600 ns tP2 Turn−Off time, OE or PWMx falling to ILED ILED = 100 mA 300 ns tR LED rise time ILED = 100 mA 300 ns tF LED fall time ILED = 100 mA 300 ns tLO OE low time 1 ms tHI OE high time 5 ms tPWRDWN OE low time to shutdown delay 4 www.onsemi.com 3 8 ms CAT4109, CAV4109 tPWRDWN tHI tLO Output Enable SHUTDOWN SHUTDOWN 0 mA tP2 tPS LED Current SHUTDOWN 0 mA tF tP1 tR ILED = (1.2 V/RSET) x 400 90% 50% 50% 0 mA 10% VIN Quiescent Current SHUTDOWN 0 mA SHUTDOWN 0 mA Figure 2. CAT4109/CAV4109 OE Timing OE Operation Accurate linear dimming on OE is compatible with PWM frequencies from 100 Hz to 5 kHz for PWM duty cycle down to 1%. PWM frequencies up to 50 kHz can be supported for duty cycles greater than 10%. When performing a combination of low frequencies and small duty cycles, the device may enter shutdown mode. This has no effect on the dimming accuracy, because the turn−on time tPS is very short, in the range of 1 ms. To ensure that PWM pulses are recognized, pulse width low time tLO should be longer than 1 ms. The driver enters a “zero current” shutdown mode after a 4 ms delay (typical) when OE is held low. The Output Enable (OE) pin has two primary functions. When the OE input goes from high to low, all three LED channels are turned off. If OE remains low for longer than tPWRDWN, the device enters shutdown mode drawing “zero current” from the supply. The OE input can be used to adjust the contrast of the RGB LED by applying an external PWM signal. The device has a very fast turn−on time (from OE rising to LED on) allowing “instant on” when dimming LEDs. When applying PWM signals to the three PWMx inputs and using the OE pin for dimming, the OE PWM frequency should be much lower to preserve the color mixing. www.onsemi.com 4 CAT4109, CAV4109 TYPICAL PERFORMANCE CHARACTERISTICS (VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25°C unless otherwise specified.) 8.0 No Load QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 3.0 3.5 4.0 4.5 5.0 2.0 100 200 300 400 RSET CURRENT (mA) Figure 3. Quiescent Current vs. Input Voltage (ILED = 0 mA) Figure 4. Quiescent Current vs. RSET Current 200 Full Load 160 LED CURRENT (mA) 5.5 5.0 4.5 120 80 40 3.0 3.5 4.0 4.5 5.0 0 5.5 0 0.2 0.4 0.6 0.8 INPUT VOLTAGE (V) LED PIN VOLTAGE (V) Figure 5. Quiescent Current vs. Input Voltage (ILED = 175 mA) Figure 6. LED Current vs. LED Pin Voltage 200 200 160 160 120 80 40 0 0 INPUT VOLTAGE (V) LED CURRENT (mA) QUIESCENT CURRENT (mA) LED CURRENT (mA) 4.0 0 5.5 6.0 4.0 6.0 1.0 120 80 40 3.0 3.5 4.0 4.5 5.0 0 5.5 −40 0 40 80 INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 7. LED Current Change vs. Input Voltage Figure 8. LED Current Change vs. Temperature www.onsemi.com 5 120 CAT4109, CAV4109 TYPICAL PERFORMANCE CHARACTERISTICS 1.30 1.30 1.25 1.25 RSET VOLTAGE (V) RSET VOLTAGE (V) (VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25°C unless otherwise specified.) 1.20 1.15 1.10 3.0 3.5 4.0 4.5 5.0 1.20 1.15 1.10 −40 5.5 0 40 80 INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 9. RSET Pin Voltage vs. Input Voltage Figure 10. RSET Pin Voltage vs. Temperature 200 LED CURRENT (mA) 160 120 80 40 0 0 120 15 30 45 60 RSET (kW) Figure 11. LED Current vs. RSET Resistor Figure 12. OE Transient Response at 1 kHz Figure 13. PWMx Transient Response www.onsemi.com 6 CAT4109, CAV4109 Table 5. PIN DESCRIPTIONS Name Pin Number Function PGND 1 Power Ground. GND 2 Ground Reference. PWM3 3 PWM control input for LED3 PWM2 4 PWM control input for LED2 PWM1 5 PWM control input for LED1 RSET3 6 LED current set pin for LED3 RSET2 7 LED current set pin for LED2 RSET1 8 LED current set pin for LED1 LED3 9 LED channel 3 cathode terminal LED2 10 LED channel 2 cathode terminal LED1 11 LED channel 1 cathode terminal NC 12 Not connected inside package NC 13 Not connected inside package NC 14 Not connected inside package OE 15 Output Enable input pin VDD 16 Device Supply pin Pin Function PGND is the power ground reference pin for the device. This pin must be connected to the GND pin and to the ground plane on the PCB. GND is the ground reference pin for the entire device. This pin must be connected to the ground plane on the PCB. PWM1 to PWM3 are the control inputs respectively for LED1, LED2 and LED3 channels. When PWMx are low, the associated LED channels are turned off. When PWMx are high, the corresponding channels are turned on, assuming the OE input is also high. PWMx pins can not be left open and must be set either to logic high or low. RSET1 to RSET3 are the LED current set inputs. The current pulled out of these pins will be mirrored in the corresponding LED channel with a gain of 400. LED1 to LED3 are the LED current sink inputs. These pins are connected to the bottom cathodes of the LED strings. The current sinks bias the LEDs with a current equal to 400 times the corresponding RSETx pin current. For the LED sink to operate correctly the voltage on the LED pin must be above 0.4 V. Each LED channel can withstand voltages up to 25 V. OE is the output enable input. When high, all LED channels are enabled according to the state of their corresponding PWMx control inputs. When low, all LED channels are turned off. This pin can be used to turn all the LEDs off independently of the state of the PWMx inputs. If the OE stays low for a duration longer than tPWRDWN, the device enters shutdown mode. VDD is the positive supply pin voltage for the entire device. A small 1 mF bypass ceramic capacitor is recommended between VDD pin and ground near the device. www.onsemi.com 7 CAT4109, CAV4109 BLOCK Diagram LED1 LED2 LED3 1.2 V Ref + VDD RSET3 Current Setting RSET2 Current Setting RSET1 Current Setting CURRENT SINKS OE PWM1 PWM2 PWM3 PGND GND Figure 14. CAT4109/CAV4109 Functional Block Diagram Basic Operation Tight current regulation for all channels is possible over a wide range of input and LED voltages due to independent current sensing circuitry on each channel. The LED channels have a low dropout of 0.4 V or less for all current ranges and supply voltages. This helps improve heat dissipation and efficiency. Upon power−up, an under−voltage lockout circuit sets all outputs to off. Once the VDD supply voltage is greater than the under−voltage lockout threshold, the device channel can be turned on. The on/off state of each channel LED1, LED2 and LED3 is independently controlled respectively by PWM1, PWM2, PWM3. When a PWMx is high, the associated LEDx channel is turned on. The CAT4109/CAV4109 uses 3 independent current sinks to accurately regulate the current in each LED channel to 400 times the current sink from the corresponding RSET pin. Each of the resistors tied to the RSET1, RSET2, RSET3 pins set the current respectively in the LED1, LED2, and LED3 channels. Table 6 shows standard resistor values for RSET and the corresponding LED current. Table 6. RSET RESISTOR SETTINGS LED Current [mA] RSET [kW] 20 24.9 60 8.45 100 5.23 175 3.01 www.onsemi.com 8 CAT4109, CAV4109 Application Information Power Dissipation Recommended Layout The power dissipation (PD) of the CAT4109/CAV4109 can be calculated as follows: Bypass capacitor C1 should be placed as close to the IC as possible. RSET resistors should be directly connected to the GND pin of the device. For better thermal dissipation, multiple via can be used to connect the GND pad to a large ground plane. It is also recommended to use large pads and traces on the PCB wherever possible to spread out the heat. The LEDs for this layout are driven from a separate supply (VLED+), but they can also be driven from the same supply connected to VDD. P D + ǒV DD I DDǓ ) SǒV LEDN I LEDNǓ where VLEDN is the voltage at the LED pin, and ILEDN is the associated LED current. Combinations of high VLED voltage or high ambient temperature can cause the CAT4109/CAV4109 to enter thermal shutdown. In applications where VLEDN is high, a resistor can be inserted in series with the LED string to lower PD. Thermal dissipation of the junction heat consists primarily of two paths in series. The first path is the junction to the case (qJC) thermal resistance which is defined by the package style, and the second path is the case to ambient (qCA) thermal resistance, which is dependent on board layout. The overall junction to ambient (qJA) thermal resistance is equal to: q JA + q JC ) q CA For a given package style and board layout, the operating junction temperature TJ is a function of the power dissipation PD, and the ambient temperature, resulting in the following equation: T J + T AMB ) P D (q JC ) q CA) + T AMB ) P D q JA When mounted on a double−sided printed circuit board with two square inches of copper allocated for “heat spreading”, the resulting qJA is about 74°C/W. For example, at 60°C ambient temperature, the maximum power dissipation is calculated as follow: P Dmax + Figure 15. Recommended Layout (T Jmax * T AMB) (150 * 60) + + 1.2 W q JA 74 www.onsemi.com 9 CAT4109, CAV4109 PACKAGE DIMENSIONS SOIC−16, 150 mils CASE 751BG−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 MAX c 0.19 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 0.25 3.90 4.00 1.27 BSC e PIN#1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 q 0º 8º TOP VIEW D h q A e b A1 c L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAT4109/D